[ARM] Remove redundant TARGET_VFP

	* arm.h (TARGET_VFP): Delete.
	(TARGET_VFPD32): Remove references to TARGET_VFP.
	(TARGET_VFP3, TARGET_VFP5): Likewise.
	(TARGET_VFP_SINGLE, TARGET_VFP_DOUBLE): Likewise.
	(TARGET_NEON_FP16): Likewise.
	(TARGET_FMA): Likewise.
	(TARGET_CRYPTO): Likewise.
	(TARGET_NEON): Likewise.
	(SECONDARY_OUTPUT_RELOAD_CLASS): Likewise.
	(FUNCTION_ARG_REGNO_P): Likewise.
	* arm.c (arm_option_check_internal): Likewise.
	(arm_option_override): Likewise.
	(use_return_insn): Likewise.
	(arm_function_value_regno_p): Likewise.
	(arm_apply_result_size): Likewise.
	(use_vfp_abi): Likewise.
	(arm_legitimate_address_outer_p): Likewise.
	(thumb2_legitimate_address_p): Likewise.
	(arm_legitimate_index_p): Likewise.
	(thumb2_legitimate_index_p): Likewise.
	(arm_legitimate_address): Likewise.
	(arm_get_vfp_saved_size): Likewise.
	(arm_emit_vfp_multi_reg_pop): Likewise.
	(arm_get_frame_offsets): Likewise.
	(arm_save_coproc_regs): Likewise.
	(arm_hard_regno_mode_ok): Likewise.
	(arm_expand_epilogue_apcs_frame): Likewise.
	(arm_expand_epilogue): Likewise.
	(arm_file_start): Likewise.
	(arm_conditional_register_usage): Likewise.
	(arm_validize_comparison): Use vfp_compare_operand directly.
	* arm-builtins.c (arm_init_builtins): Remove references to TARGET_VFP.
	(arm_expand_vfp_builtin): Use TARGET_HARD_FLOAT for detecting
	unsupported usage.
	(arm_atomic_assign_expand_fenv): Likewise.
	* arm.md (divsf3): Likewise.
	(arm_negsi2): Likewise.
	(absdf2): Likewise.
	(arm_movdi): Likewise.
	(arm_movt): Likewise.
	(cbranchsf4): Change predicate to vfp_compare_operand.
	(cbranchdf4): Change predicate to vfp_compare_operand.
	(cstorehf4): Change predicate to vfp_compare_operand.
	(cstoresf4): Change predicate to vfp_compare_operand.
	(cstoredf4): Change predicate to vfp_compare_operand.
	(vfp_pop_multiple_with_writeback): Remove references to TARGET_VFP.
	(movhi_insn_arch4, movhi_bytes): Likewise.
	* constraints.md (Dt): Likewise.
	(Dp): Likewise.
	* iterators.md (SDF): Likewise.
	* predicates.md (arm_float_compare_operand): Delete.
	(const_double_vcvt_power_of_two_reciprocal): Remove references to
	TARGET_VFP.
	(const_double_vcvt_power_of_two): Likewise.
	* thumb2.md thumb2_movsi_insn): Likewise.
	* vfp.md (arm_movhi_vfp, thumb2_movhi_vfp): Likewise.
	(movhf_vfp): Likewise.
	(arm_movsi_vfp, thumb2_movsi_vfp): Likewise.
	(movdi_vfp, movdi_vfp_cortexa8): Likewise.
	(movsf_vfp, thumb2_movsf_vfp): Likewise.
	(movdf_vfp, thumb2_movdf_vfp): Likewise.
	(movsfcc_vfp, abssf2_vfp, negsf2_vfp, addsf3_vfp): Likewise.
	(subsf3_vfp, divsf3_vfp): Likewise.
	(mulsf3_vfp, mulsf3negsf_vfp, negmulsf3_vfp): Likewise.
	(mulsf3addsf_vfp, (mulsf3subsf_vfp, mulsf3negsfaddsf_vfp): Likewise.
	(mulsf3negsfsubsf_vfp): Likewise.
	(truncsisf2_vfp, fixuns_truncsfsi2, floatsisf2_vfp): Likewise.
	(floatunssisf2, sqrtsf2_vfp): Likewise.
	(movcc_vfp): Likewise.
	(cmpsf_split_vfp, cmpsf_trap_split_vfp): Likewise.
	(cmpsf_vfp, cmpsf_trap_vfp): Likewise.
	(push_multi_vfp): Likewise.
	(set_fpscr, get_fpscr): Likewise.
	* arm-c.c (arm_cpu_builtins): Unconditionally define __VFP_FP__.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241118 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 16 insertions, 21 deletions

diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 7c4ea85c405..8a076ba3d8e 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -134,8 +134,6 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
 #define TARGET_HARD_FLOAT		(arm_float_abi != ARM_FLOAT_ABI_SOFT)
 /* Use hardware floating point calling convention.  */
 #define TARGET_HARD_FLOAT_ABI		(arm_float_abi == ARM_FLOAT_ABI_HARD)
-/* We only support the VFP model these days.  */
-#define TARGET_VFP		        (1)
 #define TARGET_IWMMXT			(arm_arch_iwmmxt)
 #define TARGET_IWMMXT2			(arm_arch_iwmmxt2)
 #define TARGET_REALLY_IWMMXT		(TARGET_IWMMXT && TARGET_32BIT)
@@ -173,46 +171,45 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
    to be more careful with TARGET_NEON as noted below.  */
 
 /* FPU is has the full VFPv3/NEON register file of 32 D registers.  */
-#define TARGET_VFPD32 (TARGET_VFP && TARGET_FPU_REGS == VFP_REG_D32)
+#define TARGET_VFPD32 (TARGET_FPU_REGS == VFP_REG_D32)
 
 /* FPU supports VFPv3 instructions.  */
-#define TARGET_VFP3 (TARGET_VFP && TARGET_FPU_REV >= 3)
+#define TARGET_VFP3 (TARGET_FPU_REV >= 3)
 
 /* FPU supports FPv5 instructions.  */
-#define TARGET_VFP5 (TARGET_VFP && TARGET_FPU_REV >= 5)
+#define TARGET_VFP5 (TARGET_FPU_REV >= 5)
 
 /* FPU only supports VFP single-precision instructions.  */
-#define TARGET_VFP_SINGLE (TARGET_VFP && TARGET_FPU_REGS == VFP_REG_SINGLE)
+#define TARGET_VFP_SINGLE (TARGET_FPU_REGS == VFP_REG_SINGLE)
 
 /* FPU supports VFP double-precision instructions.  */
-#define TARGET_VFP_DOUBLE (TARGET_VFP && TARGET_FPU_REGS != VFP_REG_SINGLE)
+#define TARGET_VFP_DOUBLE (TARGET_FPU_REGS != VFP_REG_SINGLE)
 
 /* FPU supports half-precision floating-point with NEON element load/store.  */
-#define TARGET_NEON_FP16						\
-  (TARGET_VFP								\
-   && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_NEON)		\
+#define TARGET_NEON_FP16					\
+  (ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_NEON)		\
    && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_FP16))
 
 /* FPU supports VFP half-precision floating-point.  */
 #define TARGET_FP16							\
-  (TARGET_VFP && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_FP16))
+  (ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_FP16))
 
 /* FPU supports fused-multiply-add operations.  */
-#define TARGET_FMA (TARGET_VFP && TARGET_FPU_REV >= 4)
+#define TARGET_FMA (TARGET_FPU_REV >= 4)
 
 /* FPU is ARMv8 compatible.  */
-#define TARGET_FPU_ARMV8 (TARGET_VFP && TARGET_FPU_REV >= 8)
+#define TARGET_FPU_ARMV8 (TARGET_FPU_REV >= 8)
 
 /* FPU supports Crypto extensions.  */
 #define TARGET_CRYPTO							\
-  (TARGET_VFP && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_CRYPTO))
+  (ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_CRYPTO))
 
 /* FPU supports Neon instructions.  The setting of this macro gets
    revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
    and TARGET_HARD_FLOAT to ensure that NEON instructions are
    available.  */
 #define TARGET_NEON							\
-  (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP			\
+  (TARGET_32BIT && TARGET_HARD_FLOAT					\
    && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_NEON))
 
 /* FPU supports ARMv8.1 Adv.SIMD extensions.  */
@@ -1216,7 +1213,7 @@ enum reg_class
    the data layout happens to be consistent for big-endian, so we explicitly allow
    that case.  */
 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS)		\
-  (TARGET_VFP && TARGET_BIG_END					\
+  (TARGET_BIG_END						\
    && !(GET_MODE_SIZE (FROM) == 16 && GET_MODE_SIZE (TO) == 8)	\
    && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD			\
        || GET_MODE_SIZE (TO) > UNITS_PER_WORD)			\
@@ -1267,8 +1264,7 @@ enum reg_class
    NO_REGS is returned.  */
 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X)		\
   /* Restrict which direct reloads are allowed for VFP/iWMMXt regs.  */ \
-  ((TARGET_VFP && TARGET_HARD_FLOAT				\
-    && IS_VFP_CLASS (CLASS))					\
+  ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS))			\
    ? coproc_secondary_reload_class (MODE, X, FALSE)		\
    : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS)			\
    ? coproc_secondary_reload_class (MODE, X, TRUE)		\
@@ -1280,8 +1276,7 @@ enum reg_class
 /* If we need to load shorts byte-at-a-time, then we need a scratch.  */
 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X)		\
   /* Restrict which direct reloads are allowed for VFP/iWMMXt regs.  */ \
-  ((TARGET_VFP && TARGET_HARD_FLOAT				\
-    && IS_VFP_CLASS (CLASS))					\
+  ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS))			\
     ? coproc_secondary_reload_class (MODE, X, FALSE) :		\
     (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ?			\
     coproc_secondary_reload_class (MODE, X, TRUE) :		\
@@ -1541,7 +1536,7 @@ typedef struct
    On the ARM, r0-r3 are used to pass args.  */
 #define FUNCTION_ARG_REGNO_P(REGNO)					\
    (IN_RANGE ((REGNO), 0, 3)						\
-    || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT		\
+    || (TARGET_AAPCS_BASED && TARGET_HARD_FLOAT				\
 	&& IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15))	\
     || (TARGET_IWMMXT_ABI						\
 	&& IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))