diff options
| author | thopre01 <thopre01@138bc75d-0d04-0410-961f-82ee72b054a4> | 2016-07-14 17:21:21 +0000 |
|---|---|---|
| committer | thopre01 <thopre01@138bc75d-0d04-0410-961f-82ee72b054a4> | 2016-07-14 17:21:21 +0000 |
| commit | 7c039c4473e2ecb85bc5a9b6a22e1ed609ad5b74 (patch) | |
| tree | aaf7626d7ddb7f1de47ac2aca1163eec1e0ace05 /gcc/config/arm/arm.h | |
| parent | 80c5e533604fa199b6b38e7ed37ff07d86429f7f (diff) | |
| download | gcc-7c039c4473e2ecb85bc5a9b6a22e1ed609ad5b74.tar.gz | |
2016-07-14 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* config/arm/arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M Mainline.
(TARGET_HAVE_LDACQD): New macro.
* config/arm/sync.md (atomic_loaddi): Use TARGET_HAVE_LDACQD rather
than TARGET_HAVE_LDACQ.
(arm_load_acquire_exclusivedi): Likewise.
(arm_store_release_exclusivedi): Likewise.
libgcc/
* gcc.target/arm/atomic-comp-swap-release-acquire.c: Rename into ...
* gcc.target/arm/atomic-comp-swap-release-acquire-1.c: This.
* gcc.target/arm/atomic-op-acq_rel.c: Rename into ...
* gcc.target/arm/atomic-op-acq_rel-1.c: This.
* gcc.target/arm/atomic-op-acquire.c: Rename into ...
* gcc.target/arm/atomic-op-acquire-1.c: This.
* gcc.target/arm/atomic-op-char.c: Rename into ...
* gcc.target/arm/atomic-op-char-1.c: This.
* gcc.target/arm/atomic-op-consume.c: Rename into ...
* gcc.target/arm/atomic-op-consume-1.c: This.
* gcc.target/arm/atomic-op-int.c: Rename into ...
* gcc.target/arm/atomic-op-int-1.c: This.
* gcc.target/arm/atomic-op-relaxed.c: Rename into ...
* gcc.target/arm/atomic-op-relaxed-1.c: This.
* gcc.target/arm/atomic-op-release.c: Rename into ...
* gcc.target/arm/atomic-op-release-1.c: This.
* gcc.target/arm/atomic-op-seq_cst.c: Rename into ...
* gcc.target/arm/atomic-op-seq_cst-1.c: This.
* gcc.target/arm/atomic-op-short.c: Rename into ...
* gcc.target/arm/atomic-op-short-1.c: This.
* gcc.target/arm/atomic-comp-swap-release-acquire-2.c: New test.
* gcc.target/arm/atomic-op-acq_rel-2.c: Likewise.
* gcc.target/arm/atomic-op-acquire-2.c: Likewise.
* gcc.target/arm/atomic-op-char-2.c: Likewise.
* gcc.target/arm/atomic-op-consume-2.c: Likewise.
* gcc.target/arm/atomic-op-int-2.c: Likewise.
* gcc.target/arm/atomic-op-relaxed-2.c: Likewise.
* gcc.target/arm/atomic-op-release-2.c: Likewise.
* gcc.target/arm/atomic-op-seq_cst-2.c: Likewise.
* gcc.target/arm/atomic-op-short-2.c: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@238348 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/arm/arm.h')
| -rw-r--r-- | gcc/config/arm/arm.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 317885cf719..c7149d1f497 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -261,7 +261,12 @@ extern void (*arm_lang_output_object_attributes_hook)(void); || arm_arch7) && arm_arch_notm) /* Nonzero if this chip supports load-acquire and store-release. */ -#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && arm_arch_notm) +#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && TARGET_32BIT) + +/* Nonzero if this chip supports LDAEXD and STLEXD. */ +#define TARGET_HAVE_LDACQEXD (TARGET_ARM_ARCH >= 8 \ + && TARGET_32BIT \ + && arm_arch_notm) /* Nonzero if this chip provides the MOVW and MOVT instructions. */ #define TARGET_HAVE_MOVT (arm_arch_thumb2 || arm_arch8) |