[ARC] Cleanup, fix and set LRA default.

LP_COUNT register cannot be freely allocated by the compiler as it
size, and/or content may change depending on the ARC hardware
configuration. Thus, make this register fixed.

Remove register classes and unused constraint letters.

Cleanup the implementation of conditional_register_usage hook by using
macros instead of magic constants and removing all references to
reg_class_contents which are bringing so much grief when lra is enabled.

gcc/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.h (reg_class): Reorder registers classes, remove
	unused register classes.
	(REG_CLASS_NAMES): Likewise.
	(REG_CLASS_CONTENTS): Likewise.
	(FIXED_REGISTERS): Make lp_count fixed.
	(BASE_REG_CLASS): Remove ACC16_BASE_REGS reference.
	(PROGRAM_COUNTER_REGNO): Remove.
	* config/arc/arc.c (arc_conditional_register_usage): Remove unused
	register classes, use constants for register numbers, remove
	reg_class_contents references.
	(arc_process_double_reg_moves): Add asserts.
	(arc_secondary_reload): Remove LPCOUNT_REG reference, use
	lra_in_progress predicate.
	(arc_init_reg_tables): Remove unused register classes.
	(arc_register_move_cost): Likewise.
	(arc_preferred_reload_class): Likewise.
	(hwloop_optimize): Update rtx patterns involving lp_count
	register.
	(arc_return_address_register): Rename ILINK1, INLINK2 regnums
	macros.
	* config/arc/constraints.md ("c"): Choose between GENERAL_REGS and
	CHEAP_CORE_REGS.  Former one will be used for LRA.
	("Rac"): Choose between GENERAL_REGS and ALL_CORE_REGS.  Former
	one will be used for LRA.
	("w"): Choose between GENERAL_REGS and WRITABLE_CORE_REGS.  Former
	one will be used for LRA.
	("W"): Choose between GENERAL_REGS and MPY_WRITABLE_CORE_REGS.
	Former one will be used for LRA.
	("f"): Delete constraint.
	("k"): Likewise.
	("e"): Likewise.
	("l"): Change it from register constraint to constraint.
	* config/arc/arc.md (movqi_insn): Remove unsed lp_count constraints.
	(movhi_insn): Likewise.
	(movsi_insn): Update pattern.
	(arc_lp): Likewise.
	(dbnz): Likewise.
	(stack_tie): Remove 'b' constraint letter.
	(R4_REG): Define.
	(R9_REG, R15_REG, R16_REG, R25_REG): Likewise.
	(R32_REG, R40_REG, R41_REG, R42_REG, R43_REG, R44_REG): Likewise.
	(R57_REG, R59_REG, PCL_REG): Likewise.
	(ILINK1_REGNUM): Renamed to ILINK1_REG.
	(ILINK2_REGNUM): Renamed to ILINK2_REG.
	(Rgp): Remove.
	(SP_REGS): Likewise.
	(Rcw): Remove unused reg classes.
	* config/arc/predicates.md (dest_reg_operand): Just default on
	register_operand predicate.
	(mpy_dest_reg_operand): Likewise.
	(move_dest_operand): Use macros instead of constants.

From-SVN: r266100

1 files changed, 4 insertions, 24 deletions

diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md
index efa3650e1fa..c4be56f766e 100644
--- a/gcc/config/arc/predicates.md
+++ b/gcc/config/arc/predicates.md
@@ -20,33 +20,12 @@
 (define_predicate "dest_reg_operand"
   (match_code "reg,subreg")
 {
-  rtx op0 = op;
-
-  if (GET_CODE (op0) == SUBREG)
-    op0 = SUBREG_REG (op0);
-  if (REG_P (op0) && REGNO (op0) < FIRST_PSEUDO_REGISTER
-      && TEST_HARD_REG_BIT (reg_class_contents[ALL_CORE_REGS],
-			    REGNO (op0))
-      && !TEST_HARD_REG_BIT (reg_class_contents[WRITABLE_CORE_REGS],
-			    REGNO (op0)))
-    return 0;
   return register_operand (op, mode);
 })
 
 (define_predicate "mpy_dest_reg_operand"
   (match_code "reg,subreg")
 {
-  rtx op0 = op;
-
-  if (GET_CODE (op0) == SUBREG)
-    op0 = SUBREG_REG (op0);
-  if (REG_P (op0) && REGNO (op0) < FIRST_PSEUDO_REGISTER
-      && TEST_HARD_REG_BIT (reg_class_contents[ALL_CORE_REGS],
-			    REGNO (op0))
-      /* Make sure the destination register is not LP_COUNT.  */
-      && !TEST_HARD_REG_BIT (reg_class_contents[MPY_WRITABLE_CORE_REGS],
-			    REGNO (op0)))
-    return 0;
   return register_operand (op, mode);
 })
 
@@ -358,13 +337,14 @@
     case REG :
      /* Program Counter register cannot be the target of a move.  It is
 	 a readonly register.  */
-      if (REGNO (op) == PROGRAM_COUNTER_REGNO)
+      if (REGNO (op) == PCL_REG)
 	return 0;
       else if (TARGET_MULMAC_32BY16_SET
-	       && (REGNO (op) == 56 || REGNO(op) == 57))
+	       && (REGNO (op) == MUL32x16_REG || REGNO (op) == R57_REG))
 	return 0;
       else if (TARGET_MUL64_SET
-	       && (REGNO (op) == 57 || REGNO(op) == 58 || REGNO(op) == 59 ))
+	       && (REGNO (op) == R57_REG || REGNO (op) == MUL64_OUT_REG
+		   || REGNO (op) == R59_REG))
 	return 0;
       else if (REGNO (op) == LP_COUNT)
         return 1;