Remove enum before machine_mode

r216834 did a mass removal of "enum" before "machine_mode".  This patch
removes some new uses that have been added since then.

2017-07-05  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* combine.c (simplify_if_then_else): Remove "enum" before
	"machine_mode".
	* compare-elim.c (can_eliminate_compare): Likewise.
	* config/aarch64/aarch64-builtins.c (aarch64_simd_builtin_std_type):
	Likewise.
	(aarch64_lookup_simd_builtin_type): Likewise.
	(aarch64_simd_builtin_type): Likewise.
	(aarch64_init_simd_builtin_types): Likewise.
	(aarch64_simd_expand_args): Likewise.
	* config/aarch64/aarch64-protos.h (aarch64_simd_attr_length_rglist):
	Likewise.
	(aarch64_reverse_mask): Likewise.
	(aarch64_simd_emit_reg_reg_move): Likewise.
	(aarch64_gen_adjusted_ldpstp): Likewise.
	(aarch64_ccmp_mode_to_code): Likewise.
	(aarch64_operands_ok_for_ldpstp): Likewise.
	(aarch64_operands_adjust_ok_for_ldpstp): Likewise.
	* config/aarch64/aarch64.c (aarch64_ira_change_pseudo_allocno_class):
	Likewise.
	(aarch64_min_divisions_for_recip_mul): Likewise.
	(aarch64_reassociation_width): Likewise.
	(aarch64_get_condition_code_1): Likewise.
	(aarch64_simd_emit_reg_reg_move): Likewise.
	(aarch64_simd_attr_length_rglist): Likewise.
	(aarch64_reverse_mask): Likewise.
	(aarch64_operands_ok_for_ldpstp): Likewise.
	(aarch64_operands_adjust_ok_for_ldpstp): Likewise.
	(aarch64_gen_adjusted_ldpstp): Likewise.
	* config/aarch64/cortex-a57-fma-steering.c (fma_node::rename):
	Likewise.
	* config/arc/arc.c (legitimate_offset_address_p): Likewise.
	* config/arm/arm-builtins.c (arm_simd_builtin_std_type): Likewise.
	(arm_lookup_simd_builtin_type): Likewise.
	(arm_simd_builtin_type): Likewise.
	(arm_init_simd_builtin_types): Likewise.
	(arm_expand_builtin_args): Likewise.
	* config/arm/arm-protos.h (arm_expand_builtin): Likewise.
	* config/ft32/ft32.c (ft32_libcall_value): Likewise.
	(ft32_setup_incoming_varargs): Likewise.
	(ft32_function_arg): Likewise.
	(ft32_function_arg_advance): Likewise.
	(ft32_pass_by_reference): Likewise.
	(ft32_arg_partial_bytes): Likewise.
	(ft32_valid_pointer_mode): Likewise.
	(ft32_addr_space_pointer_mode): Likewise.
	(ft32_addr_space_legitimate_address_p): Likewise.
	* config/i386/i386-protos.h (ix86_operands_ok_for_move_multiple):
	Likewise.
	* config/i386/i386.c (ix86_setup_incoming_vararg_bounds): Likewise.
	(ix86_emit_outlined_ms2sysv_restore): Likewise.
	(iamcu_alignment): Likewise.
	(canonicalize_vector_int_perm): Likewise.
	(ix86_noce_conversion_profitable_p): Likewise.
	(ix86_mpx_bound_mode): Likewise.
	(ix86_operands_ok_for_move_multiple): Likewise.
	* config/microblaze/microblaze-protos.h
	(microblaze_expand_conditional_branch_reg): Likewise.
	* config/microblaze/microblaze.c
	(microblaze_expand_conditional_branch_reg): Likewise.
	* config/powerpcspe/powerpcspe.c (rs6000_init_hard_regno_mode_ok):
	Likewise.
	(rs6000_reassociation_width): Likewise.
	(rs6000_invalid_binary_op): Likewise.
	(fusion_p9_p): Likewise.
	(emit_fusion_p9_load): Likewise.
	(emit_fusion_p9_store): Likewise.
	* config/riscv/riscv-protos.h (riscv_regno_mode_ok_for_base_p):
	Likewise.
	(riscv_hard_regno_mode_ok_p): Likewise.
	(riscv_address_insns): Likewise.
	(riscv_split_symbol): Likewise.
	(riscv_legitimize_move): Likewise.
	(riscv_function_value): Likewise.
	(riscv_hard_regno_nregs): Likewise.
	(riscv_expand_builtin): Likewise.
	* config/riscv/riscv.c (riscv_build_integer_1): Likewise.
	(riscv_build_integer): Likewise.
	(riscv_split_integer): Likewise.
	(riscv_legitimate_constant_p): Likewise.
	(riscv_cannot_force_const_mem): Likewise.
	(riscv_regno_mode_ok_for_base_p): Likewise.
	(riscv_valid_base_register_p): Likewise.
	(riscv_valid_offset_p): Likewise.
	(riscv_valid_lo_sum_p): Likewise.
	(riscv_classify_address): Likewise.
	(riscv_legitimate_address_p): Likewise.
	(riscv_address_insns): Likewise.
	(riscv_load_store_insns): Likewise.
	(riscv_force_binary): Likewise.
	(riscv_split_symbol): Likewise.
	(riscv_force_address): Likewise.
	(riscv_legitimize_address): Likewise.
	(riscv_move_integer): Likewise.
	(riscv_legitimize_const_move): Likewise.
	(riscv_legitimize_move): Likewise.
	(riscv_address_cost): Likewise.
	(riscv_subword): Likewise.
	(riscv_output_move): Likewise.
	(riscv_canonicalize_int_order_test): Likewise.
	(riscv_emit_int_order_test): Likewise.
	(riscv_function_arg_boundary): Likewise.
	(riscv_pass_mode_in_fpr_p): Likewise.
	(riscv_pass_fpr_single): Likewise.
	(riscv_pass_fpr_pair): Likewise.
	(riscv_get_arg_info): Likewise.
	(riscv_function_arg): Likewise.
	(riscv_function_arg_advance): Likewise.
	(riscv_arg_partial_bytes): Likewise.
	(riscv_function_value): Likewise.
	(riscv_pass_by_reference): Likewise.
	(riscv_setup_incoming_varargs): Likewise.
	(riscv_print_operand): Likewise.
	(riscv_elf_select_rtx_section): Likewise.
	(riscv_save_restore_reg): Likewise.
	(riscv_for_each_saved_reg): Likewise.
	(riscv_register_move_cost): Likewise.
	(riscv_hard_regno_mode_ok_p): Likewise.
	(riscv_hard_regno_nregs): Likewise.
	(riscv_class_max_nregs): Likewise.
	(riscv_memory_move_cost): Likewise.
	* config/rl78/rl78-protos.h (rl78_split_movsi): Likewise.
	* config/rl78/rl78.c (rl78_split_movsi): Likewise.
	(rl78_addr_space_address_mode): Likewise.
	* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
	Likewise.
	* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Likewise.
	(rs6000_reassociation_width): Likewise.
	(rs6000_invalid_binary_op): Likewise.
	(fusion_p9_p): Likewise.
	(emit_fusion_p9_load): Likewise.
	(emit_fusion_p9_store): Likewise.
	* config/visium/visium-protos.h (prepare_move_operands): Likewise.
	(ok_for_simple_move_operands): Likewise.
	(ok_for_simple_move_strict_operands): Likewise.
	(ok_for_simple_arith_logic_operands): Likewise.
	(visium_legitimize_reload_address): Likewise.
	(visium_select_cc_mode): Likewise.
	(output_cbranch): Likewise.
	(visium_split_double_move): Likewise.
	(visium_expand_copysign): Likewise.
	(visium_expand_int_cstore): Likewise.
	(visium_expand_fp_cstore): Likewise.
	* config/visium/visium.c (visium_pass_by_reference): Likewise.
	(visium_function_arg): Likewise.
	(visium_function_arg_advance): Likewise.
	(visium_libcall_value): Likewise.
	(visium_setup_incoming_varargs): Likewise.
	(visium_legitimate_constant_p): Likewise.
	(visium_legitimate_address_p): Likewise.
	(visium_legitimize_address): Likewise.
	(visium_secondary_reload): Likewise.
	(visium_register_move_cost): Likewise.
	(visium_memory_move_cost): Likewise.
	(prepare_move_operands): Likewise.
	(ok_for_simple_move_operands): Likewise.
	(ok_for_simple_move_strict_operands): Likewise.
	(ok_for_simple_arith_logic_operands): Likewise.
	(visium_function_value_1): Likewise.
	(rtx_ok_for_offset_p): Likewise.
	(visium_legitimize_reload_address): Likewise.
	(visium_split_double_move): Likewise.
	(visium_expand_copysign): Likewise.
	(visium_expand_int_cstore): Likewise.
	(visium_expand_fp_cstore): Likewise.
	(visium_split_cstore): Likewise.
	(visium_select_cc_mode): Likewise.
	(visium_split_cbranch): Likewise.
	(output_cbranch): Likewise.
	(visium_print_operand_address): Likewise.
	* expmed.c (flip_storage_order): Likewise.
	* expmed.h (emit_cstore): Likewise.
	(flip_storage_order): Likewise.
	* genrecog.c (validate_pattern): Likewise.
	* hsa-gen.c (gen_hsa_addr): Likewise.
	* internal-fn.c (expand_arith_overflow): Likewise.
	* ira-color.c (allocno_copy_cost_saving): Likewise.
	* lra-assigns.c (find_hard_regno_for_1): Likewise.
	* lra-constraints.c (prohibited_class_reg_set_mode_p): Likewise.
	(process_invariant_for_inheritance): Likewise.
	* lra-eliminations.c (move_plus_up): Likewise.
	* omp-low.c (lower_oacc_reductions): Likewise.
	* simplify-rtx.c (simplify_subreg): Likewise.
	* target.def (TARGET_SETUP_INCOMING_VARARG_BOUNDS): Likewise.
	(TARGET_CHKP_BOUND_MODE): Likewise..
	* targhooks.c (default_chkp_bound_mode): Likewise.
	(default_setup_incoming_vararg_bounds): Likewise.
	* targhooks.h (default_chkp_bound_mode): Likewise.
	(default_setup_incoming_vararg_bounds): Likewise.
	* tree-ssa-math-opts.c (divmod_candidate_p): Likewise.
	* tree-vect-loop.c (calc_vec_perm_mask_for_shift): Likewise.
	(have_whole_vector_shift): Likewise.
	* tree-vect-stmts.c (vectorizable_load): Likewise.
	* doc/tm.texi: Regenerate.

gcc/brig/
	* brig-c.h (brig_type_for_mode): Remove "enum" before "machine_mode".
	* brig-lang.c (brig_langhook_type_for_mode): Likewise.

gcc/jit/
	* dummy-frontend.c (jit_langhook_type_for_mode): Remove "enum" before
	"machine_mode".


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@250003 138bc75d-0d04-0410-961f-82ee72b054a4

4 files changed, 25 insertions, 25 deletions

diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c
index f09399f4c15..d30009ba441 100644
--- a/gcc/config/aarch64/aarch64-builtins.c
+++ b/gcc/config/aarch64/aarch64-builtins.c
@@ -530,7 +530,7 @@ aarch64_mangle_builtin_type (const_tree type)
 }
 
 static tree
-aarch64_simd_builtin_std_type (enum machine_mode mode,
+aarch64_simd_builtin_std_type (machine_mode mode,
 			       enum aarch64_type_qualifiers q)
 {
 #define QUAL_TYPE(M)  \
@@ -566,7 +566,7 @@ aarch64_simd_builtin_std_type (enum machine_mode mode,
 }
 
 static tree
-aarch64_lookup_simd_builtin_type (enum machine_mode mode,
+aarch64_lookup_simd_builtin_type (machine_mode mode,
 				  enum aarch64_type_qualifiers q)
 {
   int i;
@@ -585,7 +585,7 @@ aarch64_lookup_simd_builtin_type (enum machine_mode mode,
 }
 
 static tree
-aarch64_simd_builtin_type (enum machine_mode mode,
+aarch64_simd_builtin_type (machine_mode mode,
 			   bool unsigned_p, bool poly_p)
 {
   if (poly_p)
@@ -649,7 +649,7 @@ aarch64_init_simd_builtin_types (void)
   for (i = 0; i < nelts; i++)
     {
       tree eltype = aarch64_simd_types[i].eltype;
-      enum machine_mode mode = aarch64_simd_types[i].mode;
+      machine_mode mode = aarch64_simd_types[i].mode;
 
       if (aarch64_simd_types[i].itype == NULL)
 	{
@@ -1015,7 +1015,7 @@ typedef enum
 static rtx
 aarch64_simd_expand_args (rtx target, int icode, int have_retval,
 			  tree exp, builtin_simd_arg *args,
-			  enum machine_mode builtin_mode)
+			  machine_mode builtin_mode)
 {
   rtx pat;
   rtx op[SIMD_MAX_BUILTIN_ARGS + 1]; /* First element for result operand.  */
@@ -1040,7 +1040,7 @@ aarch64_simd_expand_args (rtx target, int icode, int have_retval,
       else
 	{
 	  tree arg = CALL_EXPR_ARG (exp, opc - have_retval);
-	  enum machine_mode mode = insn_data[icode].operand[opc].mode;
+	  machine_mode mode = insn_data[icode].operand[opc].mode;
 	  op[opc] = expand_normal (arg);
 
 	  switch (thisarg)
diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
index bfe44a75e12..e397ff4afa7 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -342,8 +342,8 @@ bool aarch64_modes_tieable_p (machine_mode mode1,
 bool aarch64_zero_extend_const_eq (machine_mode, rtx, machine_mode, rtx);
 bool aarch64_move_imm (HOST_WIDE_INT, machine_mode);
 bool aarch64_mov_operand_p (rtx, machine_mode);
-int aarch64_simd_attr_length_rglist (enum machine_mode);
-rtx aarch64_reverse_mask (enum machine_mode);
+int aarch64_simd_attr_length_rglist (machine_mode);
+rtx aarch64_reverse_mask (machine_mode);
 bool aarch64_offset_7bit_signed_scaled_p (machine_mode, HOST_WIDE_INT);
 char *aarch64_output_scalar_simd_mov_immediate (rtx, machine_mode);
 char *aarch64_output_simd_mov_immediate (rtx, machine_mode, unsigned);
@@ -411,7 +411,7 @@ void aarch64_save_restore_target_globals (tree);
 /* Initialize builtins for SIMD intrinsics.  */
 void init_aarch64_simd_builtins (void);
 
-void aarch64_simd_emit_reg_reg_move (rtx *, enum machine_mode, unsigned int);
+void aarch64_simd_emit_reg_reg_move (rtx *, machine_mode, unsigned int);
 
 /* Expand builtins for SIMD intrinsics.  */
 rtx aarch64_simd_expand_builtin (int, tree, rtx);
@@ -444,7 +444,7 @@ bool aarch64_atomic_ldop_supported_p (enum rtx_code);
 void aarch64_gen_atomic_ldop (enum rtx_code, rtx, rtx, rtx, rtx, rtx);
 void aarch64_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx);
 
-bool aarch64_gen_adjusted_ldpstp (rtx *, bool, enum machine_mode, RTX_CODE);
+bool aarch64_gen_adjusted_ldpstp (rtx *, bool, machine_mode, RTX_CODE);
 #endif /* RTX_CODE */
 
 void aarch64_init_builtins (void);
@@ -468,11 +468,11 @@ extern void aarch64_final_prescan_insn (rtx_insn *);
 extern bool
 aarch64_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel);
 void aarch64_atomic_assign_expand_fenv (tree *, tree *, tree *);
-int aarch64_ccmp_mode_to_code (enum machine_mode mode);
+int aarch64_ccmp_mode_to_code (machine_mode mode);
 
 bool extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset);
-bool aarch64_operands_ok_for_ldpstp (rtx *, bool, enum machine_mode);
-bool aarch64_operands_adjust_ok_for_ldpstp (rtx *, bool, enum machine_mode);
+bool aarch64_operands_ok_for_ldpstp (rtx *, bool, machine_mode);
+bool aarch64_operands_adjust_ok_for_ldpstp (rtx *, bool, machine_mode);
 
 extern void aarch64_asm_output_pool_epilogue (FILE *, const char *,
 					      tree, HOST_WIDE_INT);
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 037339d431d..ef1b5a8e215 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -1032,7 +1032,7 @@ static reg_class_t
 aarch64_ira_change_pseudo_allocno_class (int regno, reg_class_t allocno_class,
 					 reg_class_t best_class)
 {
-  enum machine_mode mode;
+  machine_mode mode;
 
   if (allocno_class != ALL_REGS)
     return allocno_class;
@@ -1045,7 +1045,7 @@ aarch64_ira_change_pseudo_allocno_class (int regno, reg_class_t allocno_class,
 }
 
 static unsigned int
-aarch64_min_divisions_for_recip_mul (enum machine_mode mode)
+aarch64_min_divisions_for_recip_mul (machine_mode mode)
 {
   if (GET_MODE_UNIT_SIZE (mode) == 4)
     return aarch64_tune_params.min_div_recip_mul_sf;
@@ -1054,7 +1054,7 @@ aarch64_min_divisions_for_recip_mul (enum machine_mode mode)
 
 static int
 aarch64_reassociation_width (unsigned opc ATTRIBUTE_UNUSED,
-			     enum machine_mode mode)
+			     machine_mode mode)
 {
   if (VECTOR_MODE_P (mode))
     return aarch64_tune_params.vec_reassoc_width;
@@ -4887,7 +4887,7 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
 }
 
 static int
-aarch64_get_condition_code_1 (enum machine_mode, enum rtx_code);
+aarch64_get_condition_code_1 (machine_mode, enum rtx_code);
 
 int
 aarch64_get_condition_code (rtx x)
@@ -4901,7 +4901,7 @@ aarch64_get_condition_code (rtx x)
 }
 
 static int
-aarch64_get_condition_code_1 (enum machine_mode mode, enum rtx_code comp_code)
+aarch64_get_condition_code_1 (machine_mode mode, enum rtx_code comp_code)
 {
   switch (mode)
     {
@@ -11693,7 +11693,7 @@ aarch64_simd_mem_operand_p (rtx op)
    COUNT is the number of components into which the copy needs to be
    decomposed.  */
 void
-aarch64_simd_emit_reg_reg_move (rtx *operands, enum machine_mode mode,
+aarch64_simd_emit_reg_reg_move (rtx *operands, machine_mode mode,
 				unsigned int count)
 {
   unsigned int i;
@@ -11714,7 +11714,7 @@ aarch64_simd_emit_reg_reg_move (rtx *operands, enum machine_mode mode,
 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
    one of VSTRUCT modes: OI, CI, or XI.  */
 int
-aarch64_simd_attr_length_rglist (enum machine_mode mode)
+aarch64_simd_attr_length_rglist (machine_mode mode)
 {
   return (GET_MODE_SIZE (mode) / UNITS_PER_VREG) * 4;
 }
@@ -13705,7 +13705,7 @@ aarch64_vectorize_vec_perm_const_ok (machine_mode vmode,
 }
 
 rtx
-aarch64_reverse_mask (enum machine_mode mode)
+aarch64_reverse_mask (machine_mode mode)
 {
   /* We have to reverse each vector because we dont have
      a permuted load that can reverse-load according to ABI rules.  */
@@ -14548,7 +14548,7 @@ aarch64_sched_adjust_priority (rtx_insn *insn, int priority)
 
 bool
 aarch64_operands_ok_for_ldpstp (rtx *operands, bool load,
-				enum machine_mode mode)
+				machine_mode mode)
 {
   HOST_WIDE_INT offval_1, offval_2, msize;
   enum reg_class rclass_1, rclass_2;
@@ -14655,7 +14655,7 @@ aarch64_operands_ok_for_ldpstp (rtx *operands, bool load,
 
 bool
 aarch64_operands_adjust_ok_for_ldpstp (rtx *operands, bool load,
-				       enum machine_mode mode)
+				       machine_mode mode)
 {
   enum reg_class rclass_1, rclass_2, rclass_3, rclass_4;
   HOST_WIDE_INT offval_1, offval_2, offval_3, offval_4, msize;
@@ -14789,7 +14789,7 @@ aarch64_operands_adjust_ok_for_ldpstp (rtx *operands, bool load,
 
 bool
 aarch64_gen_adjusted_ldpstp (rtx *operands, bool load,
-			     enum machine_mode mode, RTX_CODE code)
+			     machine_mode mode, RTX_CODE code)
 {
   rtx base, offset, t1, t2;
   rtx mem_1, mem_2, mem_3, mem_4;
diff --git a/gcc/config/aarch64/cortex-a57-fma-steering.c b/gcc/config/aarch64/cortex-a57-fma-steering.c
index 94d7f9c5869..6d90acdd4a2 100644
--- a/gcc/config/aarch64/cortex-a57-fma-steering.c
+++ b/gcc/config/aarch64/cortex-a57-fma-steering.c
@@ -603,7 +603,7 @@ fma_node::rename (fma_forest *forest)
     {
       rtx_insn *insn = this->m_insn;
       HARD_REG_SET unavailable;
-      enum machine_mode mode;
+      machine_mode mode;
       int reg;
 
       if (dump_file)