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| author | ktkachov <ktkachov@138bc75d-0d04-0410-961f-82ee72b054a4> | 2017-06-05 08:52:02 +0000 |
|---|---|---|
| committer | ktkachov <ktkachov@138bc75d-0d04-0410-961f-82ee72b054a4> | 2017-06-05 08:52:02 +0000 |
| commit | 38a4c04c16d3c915d8dd37c967fbe1e56dbd92aa (patch) | |
| tree | cfc8ea9bf517102b09175cd4e621302b1fa41679 /gcc/config/aarch64 | |
| parent | 25236514370ae7e0881c57529a83d5ce7745b0f5 (diff) | |
| download | gcc-38a4c04c16d3c915d8dd37c967fbe1e56dbd92aa.tar.gz | |
[AArch64] Add combine pattern for storing lane zero of a vector
* config/aarch64/aarch64-simd.md (aarch64_store_lane0<mode>):
New pattern.
* gcc.target/aarch64/store_lane0_str_1.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@248871 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/aarch64')
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 693b476788e..c5a86ff6f71 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -153,6 +153,19 @@ (set_attr "length" "4,4,4,8,8,8,4")] ) +;; When storing lane zero we can use the normal STR and its more permissive +;; addressing modes. + +(define_insn "aarch64_store_lane0<mode>" + [(set (match_operand:<VEL> 0 "memory_operand" "=m") + (vec_select:<VEL> (match_operand:VALL_F16 1 "register_operand" "w") + (parallel [(match_operand 2 "const_int_operand" "n")])))] + "TARGET_SIMD + && ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])) == 0" + "str\\t%<Vetype>1, %0" + [(set_attr "type" "neon_store1_1reg<q>")] +) + (define_insn "load_pair<mode>" [(set (match_operand:VD 0 "register_operand" "=w") (match_operand:VD 1 "aarch64_mem_pair_operand" "Ump")) |