diff options
| author | Wilco Dijkstra <wdijkstr@arm.com> | 2015-09-20 16:43:28 +0000 |
|---|---|---|
| committer | Jiong Wang <jiwang@gcc.gnu.org> | 2015-09-20 16:43:28 +0000 |
| commit | feca59ff1144d0657b03da31bfcc79948a9b3c2c (patch) | |
| tree | b37097c720244ac97240842b8acb1cbe9bb1c0eb /gcc/config/aarch64/aarch64.c | |
| parent | 8fcbb4e328b3d7146160b33a8b4a396252127b4e (diff) | |
| download | gcc-feca59ff1144d0657b03da31bfcc79948a9b3c2c.tar.gz | |
[AArch64][4/5] Remove redundant code
2015-09-20 Wilco Dijkstra <wdijkstr@arm.com>
* config/aarch64/aarch64.c (aarch64_internal_mov_immediate): Remove
redundant immediate generation code.
From-SVN: r227949
Diffstat (limited to 'gcc/config/aarch64/aarch64.c')
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 60 |
1 files changed, 0 insertions, 60 deletions
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index ca9fdbde9cc..af8ec3ccae0 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -1437,8 +1437,6 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate, int i; bool first; unsigned HOST_WIDE_INT val, val2; - bool subtargets; - rtx subtarget; int one_match, zero_match, first_not_ffff_match; int num_insns = 0; @@ -1468,7 +1466,6 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate, /* Remaining cases are all for DImode. */ val = INTVAL (imm); - subtargets = optimize && can_create_pseudo_p (); one_match = 0; zero_match = 0; @@ -1506,63 +1503,6 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate, if (zero_match == 2) goto simple_sequence; - mask = 0x0ffff0000UL; - for (i = 16; i < 64; i += 16, mask <<= 16) - { - HOST_WIDE_INT comp = mask & ~(mask - 1); - - if (aarch64_uimm12_shift (val - (val & mask))) - { - if (generate) - { - subtarget = subtargets ? gen_reg_rtx (DImode) : dest; - emit_insn (gen_rtx_SET (subtarget, GEN_INT (val & mask))); - emit_insn (gen_adddi3 (dest, subtarget, - GEN_INT (val - (val & mask)))); - } - num_insns += 2; - return num_insns; - } - else if (aarch64_uimm12_shift (-(val - ((val + comp) & mask)))) - { - if (generate) - { - subtarget = subtargets ? gen_reg_rtx (DImode) : dest; - emit_insn (gen_rtx_SET (subtarget, - GEN_INT ((val + comp) & mask))); - emit_insn (gen_adddi3 (dest, subtarget, - GEN_INT (val - ((val + comp) & mask)))); - } - num_insns += 2; - return num_insns; - } - else if (aarch64_uimm12_shift (val - ((val - comp) | ~mask))) - { - if (generate) - { - subtarget = subtargets ? gen_reg_rtx (DImode) : dest; - emit_insn (gen_rtx_SET (subtarget, - GEN_INT ((val - comp) | ~mask))); - emit_insn (gen_adddi3 (dest, subtarget, - GEN_INT (val - ((val - comp) | ~mask)))); - } - num_insns += 2; - return num_insns; - } - else if (aarch64_uimm12_shift (-(val - (val | ~mask)))) - { - if (generate) - { - subtarget = subtargets ? gen_reg_rtx (DImode) : dest; - emit_insn (gen_rtx_SET (subtarget, GEN_INT (val | ~mask))); - emit_insn (gen_adddi3 (dest, subtarget, - GEN_INT (val - (val | ~mask)))); - } - num_insns += 2; - return num_insns; - } - } - if (zero_match != 2 && one_match != 2) { /* Try emitting a bitmask immediate with a movk replacing 16 bits. |