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| author | tbsaunde <tbsaunde@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-07-09 02:49:51 +0000 |
|---|---|---|
| committer | tbsaunde <tbsaunde@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-07-09 02:49:51 +0000 |
| commit | 5fe18e785a87cd6fa3bef8df8c83adf50274f42d (patch) | |
| tree | e4dc3a562a1e0900ee3ab1384aba87e00500bcef /gcc/combine.c | |
| parent | bddd01c17102927f2cab4b73704474ad913278c2 (diff) | |
| download | gcc-5fe18e785a87cd6fa3bef8df8c83adf50274f42d.tar.gz | |
reduce conditional compilation for LOAD_EXTEND_OP
Provide a default in files where that is possible, so that everything
else there can be unconditionally compiled. However rtlanal.c and
reload.c do tricky things that break providing a global default, so we
can't do that yet.
gcc/ChangeLog:
2015-07-08 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* combine.c (try_combine): Don't check if LOAD_EXTEND_OP is
defined.
(simplify_set): Likewise.
* cse.c (cse_insn): Likewise.
* fold-const.c (fold_single_bit_test): Likewise.
(fold_unary_loc): Likewise.
* postreload.c (reload_cse_simplify_set): Likewise.
(reload_cse_simplify_operands): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@225591 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/combine.c')
| -rw-r--r-- | gcc/combine.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/gcc/combine.c b/gcc/combine.c index 9be230a51e2..11cee8559c1 100644 --- a/gcc/combine.c +++ b/gcc/combine.c @@ -113,6 +113,10 @@ along with GCC; see the file COPYING3. If not see #include "obstack.h" #include "rtl-iter.h" +#ifndef LOAD_EXTEND_OP +#define LOAD_EXTEND_OP(M) UNKNOWN +#endif + /* Number of attempts to combine instructions in this function. */ static int combine_attempts; @@ -3744,7 +3748,6 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0, be written as a ZERO_EXTEND. */ if (split_code == SUBREG && MEM_P (SUBREG_REG (*split))) { -#ifdef LOAD_EXTEND_OP /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's what it really is. */ if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split))) @@ -3752,7 +3755,6 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0, SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode, SUBREG_REG (*split))); else -#endif SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode, SUBREG_REG (*split))); } @@ -6772,7 +6774,6 @@ simplify_set (rtx x) } } -#ifdef LOAD_EXTEND_OP /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this would require a paradoxical subreg. Replace the subreg with a zero_extend to avoid the reload that would otherwise be required. */ @@ -6790,7 +6791,6 @@ simplify_set (rtx x) src = SET_SRC (x); } -#endif /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we are comparing an item known to be 0 or -1 against 0, use a logical |