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authorwilco <wilco@138bc75d-0d04-0410-961f-82ee72b054a4>2016-05-16 11:01:36 +0000
committerwilco <wilco@138bc75d-0d04-0410-961f-82ee72b054a4>2016-05-16 11:01:36 +0000
commitd156d6edc8c69c3202a07f18d58c7347197de8c0 (patch)
treee84132de7f1aaa6bdec02d372ef377a9142f64f4 /gcc/ada/exp_ch10.ads
parent59f08ba6e23a827e9d07c7a14ec44492d650673e (diff)
downloadgcc-d156d6edc8c69c3202a07f18d58c7347197de8c0.tar.gz
This patch fixes the attributes of integer immediate shifts which were
incorrectly modelled as register controlled shifts. Also change EXTR attribute to being a rotate. * gcc/config/aarch64/aarch64.md (aarch64_ashl_sisd_or_int_<mode>3): Split integer shifts into shift_reg and bfm. (aarch64_lshr_sisd_or_int_<mode>3): Likewise. (aarch64_ashr_sisd_or_int_<mode>3): Likewise. (ror<mode>3_insn): Likewise. (<optab>si3_insn_uxtw): Likewise. (<optab><mode>3_insn): Change to rotate_imm. (extr<mode>5_insn_alt): Likewise. (extrsi5_insn_uxtw): Likewise. (extrsi5_insn_uxtw_alt): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@236278 138bc75d-0d04-0410-961f-82ee72b054a4
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