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| author | meissner <meissner@138bc75d-0d04-0410-961f-82ee72b054a4> | 2016-08-01 23:27:38 +0000 |
|---|---|---|
| committer | meissner <meissner@138bc75d-0d04-0410-961f-82ee72b054a4> | 2016-08-01 23:27:38 +0000 |
| commit | c79d3723c59f7cfc697a096d8ad63fb950332e4a (patch) | |
| tree | be32d404c0080a73c0b9158ff5d20a1437865f28 /gcc/ChangeLog | |
| parent | c6b4d6c105b46ecde17a3c6d39585400565eca95 (diff) | |
| download | gcc-c79d3723c59f7cfc697a096d8ad63fb950332e4a.tar.gz | |
[gcc]
2016-08-01 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
Add support for vec_extract on vector float, vector int, vector
short, and vector char vector types.
* config/rs6000/rs6000.c (rs6000_expand_vector_extract): Add
vector float, vector int, vector short, and vector char
optimizations on 64-bit ISA 2.07 systems for both constant and
variable element numbers.
(rs6000_split_vec_extract_var): Likewise.
* config/rs6000/vsx.md (vsx_xscvspdp_scalar2): Allow SFmode to be
Altivec registers on ISA 2.07 and above.
(vsx_extract_v4sf): Delete alternative that hard coded element 0,
which never was matched due to the split occuring before register
allocation (and the code would not have worked on little endian
systems if it did match). Allow extracts to go to the Altivec
registers if ISA 2.07 (power8). Change from using "" around the
C++ code to using {}'s.
(vsx_extract_v4sf_<mode>_load): New insn to optimize vector float
vec_extracts when the vector is in memory.
(vsx_extract_v4sf_var): New insn to optimize vector float
vec_extracts when the element number is variable on 64-bit ISA
2.07 systems.
(vsx_extract_<mode>, VSX_EXTRACT_I iterator): Add optimizations
for 64-bit ISA 2.07 as well as ISA 3.0.
(vsx_extract_<mode>_p9, VSX_EXTRACT_I iterator): Likewise.
(vsx_extract_<mode>_p8, VSX_EXTRACT_I iterator): Likewise.
(vsx_extract_<mode>_load, VSX_EXTRACT_I iterator): New insn to
optimize vector int, vector short, and vector char vec_extracts
when the vector is in memory.
(vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): New insn to
optimize vector int, vector short, and vector char vec_extracts
when the element number is variable.
[gcc/testsuite]
2016-08-01 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/vec-extract-5.c: New tests to test
vec_extract for vector float, vector int, vector short, and vector
char.
* gcc.target/powerpc/vec-extract-6.c: Likewise.
* gcc.target/powerpc/vec-extract-7.c: Likewise.
* gcc.target/powerpc/vec-extract-8.c: Likewise.
* gcc.target/powerpc/vec-extract-9.c: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@238971 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/ChangeLog')
| -rw-r--r-- | gcc/ChangeLog | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 795f1c7eee2..fa109062803 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,37 @@ +2016-08-01 Michael Meissner <meissner@linux.vnet.ibm.com> + + * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): + Add support for vec_extract on vector float, vector int, vector + short, and vector char vector types. + * config/rs6000/rs6000.c (rs6000_expand_vector_extract): Add + vector float, vector int, vector short, and vector char + optimizations on 64-bit ISA 2.07 systems for both constant and + variable element numbers. + (rs6000_split_vec_extract_var): Likewise. + * config/rs6000/vsx.md (vsx_xscvspdp_scalar2): Allow SFmode to be + Altivec registers on ISA 2.07 and above. + (vsx_extract_v4sf): Delete alternative that hard coded element 0, + which never was matched due to the split occuring before register + allocation (and the code would not have worked on little endian + systems if it did match). Allow extracts to go to the Altivec + registers if ISA 2.07 (power8). Change from using "" around the + C++ code to using {}'s. + (vsx_extract_v4sf_<mode>_load): New insn to optimize vector float + vec_extracts when the vector is in memory. + (vsx_extract_v4sf_var): New insn to optimize vector float + vec_extracts when the element number is variable on 64-bit ISA + 2.07 systems. + (vsx_extract_<mode>, VSX_EXTRACT_I iterator): Add optimizations + for 64-bit ISA 2.07 as well as ISA 3.0. + (vsx_extract_<mode>_p9, VSX_EXTRACT_I iterator): Likewise. + (vsx_extract_<mode>_p8, VSX_EXTRACT_I iterator): Likewise. + (vsx_extract_<mode>_load, VSX_EXTRACT_I iterator): New insn to + optimize vector int, vector short, and vector char vec_extracts + when the vector is in memory. + (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): New insn to + optimize vector int, vector short, and vector char vec_extracts + when the element number is variable. + 2016-08-01 Georg-Johann Lay <avr@gjlay.de> PR target/71948 |