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| author | uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4> | 2008-03-13 18:00:22 +0000 |
|---|---|---|
| committer | uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4> | 2008-03-13 18:00:22 +0000 |
| commit | 5b2ddfe1ac6ede4c1403b88c056836a14e29576a (patch) | |
| tree | c6429056dd73cc8c9fed28097d65446aeba8eadf | |
| parent | c9f96750c9b58b580ce78eb19da6e3100304ea45 (diff) | |
| download | gcc-5b2ddfe1ac6ede4c1403b88c056836a14e29576a.tar.gz | |
* doc/extend.texi (X86 Built-in Functions): Missed fragment from
my previous commit commit.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@133178 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 3 | ||||
| -rw-r--r-- | gcc/doc/extend.texi | 2 |
2 files changed, 3 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ade053e53c4..7eb3e89ad00 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -4,7 +4,8 @@ __builtin_ia32_psrl?, __builtin_ia32_psra?, __builtin_ia32_psll?i, __builtin_ia32_psrl?i, __builtin_ia32_psra?i, __builtin_ia32_psll?128, __builtin_ia32_psrl?128, __builtin_ia32_psra?128]: Fix the mode of - input arguments and the mode of return value. + input arguments and the mode of return value. Built-in functions + that operate on whole 64-bit MMX register now use V1DI mode. 2008-03-13 Alon Dayan <alond@il.ibm.com> Olga Golovanevsky <olga@il.ibm.com> diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 69d38688db2..53ec6efa617 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -7406,7 +7406,7 @@ The following machine modes are available for use with MMX built-in functions (@pxref{Vector Extensions}): @code{V2SI} for a vector of two 32-bit integers, @code{V4HI} for a vector of four 16-bit integers, and @code{V8QI} for a vector of eight 8-bit integers. Some of the built-in functions operate on -MMX registers as a whole 64-bit entity, these use @code{DI} as their mode. +MMX registers as a whole 64-bit entity, these use @code{V1DI} as their mode. If 3Dnow extensions are enabled, @code{V2SF} is used as a mode for a vector of two 32-bit floating point values. |