diff options
author | yufeng <yufeng@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-07-23 12:23:05 +0000 |
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committer | yufeng <yufeng@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-07-23 12:23:05 +0000 |
commit | 0000f7ab2f65114c34afed41139d2581cd3e79a7 (patch) | |
tree | 9e93446b0e9c98412a7696116abfd3b0a7ca514e | |
parent | 011aed183cf78e157edcfaf04fa3120b0fed656b (diff) | |
download | gcc-0000f7ab2f65114c34afed41139d2581cd3e79a7.tar.gz |
[AArch64, ILP32] 3/6 Change tests to be ILP32-friendly.
gcc/testsuite/
* gcc.dg/20020219-1.c: Skip the test on aarch64*-*-* in ilp32.
* gcc.target/aarch64/aapcs64/test_18.c (struct y): Change the field
type from long to long long.
* gcc.target/aarch64/atomic-op-long.c: Update dg-final directives
to have effective-target keywords of lp64 and ilp32.
* gcc.target/aarch64/fcvt_double_int.c: Likewise.
* gcc.target/aarch64/fcvt_double_long.c: Likewise.
* gcc.target/aarch64/fcvt_double_uint.c: Likewise.
* gcc.target/aarch64/fcvt_double_ulong.c: Likewise.
* gcc.target/aarch64/fcvt_float_int.c: Likewise.
* gcc.target/aarch64/fcvt_float_long.c: Likewise.
* gcc.target/aarch64/fcvt_float_uint.c: Likewise.
* gcc.target/aarch64/fcvt_float_ulong.c: Likewise.
* gcc.target/aarch64/vect_smlal_1.c: Replace 'long' with 'long long'.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@201166 138bc75d-0d04-0410-961f-82ee72b054a4
-rw-r--r-- | gcc/testsuite/ChangeLog | 17 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/20020219-1.c | 1 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c | 8 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/atomic-op-long.c | 6 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/fcvt_double_int.c | 10 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c | 12 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/fcvt_double_uint.c | 6 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c | 18 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c | 10 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c | 12 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c | 6 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c | 18 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c | 6 |
13 files changed, 89 insertions, 41 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 4cd3d0f62b2..e715ca564fd 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,20 @@ +2013-07-23 Yufeng Zhang <yufeng.zhang@arm.com> + + * gcc.dg/20020219-1.c: Skip the test on aarch64*-*-* in ilp32. + * gcc.target/aarch64/aapcs64/test_18.c (struct y): Change the field + type from long to long long. + * gcc.target/aarch64/atomic-op-long.c: Update dg-final directives + to have effective-target keywords of lp64 and ilp32. + * gcc.target/aarch64/fcvt_double_int.c: Likewise. + * gcc.target/aarch64/fcvt_double_long.c: Likewise. + * gcc.target/aarch64/fcvt_double_uint.c: Likewise. + * gcc.target/aarch64/fcvt_double_ulong.c: Likewise. + * gcc.target/aarch64/fcvt_float_int.c: Likewise. + * gcc.target/aarch64/fcvt_float_long.c: Likewise. + * gcc.target/aarch64/fcvt_float_uint.c: Likewise. + * gcc.target/aarch64/fcvt_float_ulong.c: Likewise. + * gcc.target/aarch64/vect_smlal_1.c: Replace 'long' with 'long long'. + 2013-07-23 Tom Tromey <tromey@redhat.com> Joseph Myers <joseph@codesourcery.com> diff --git a/gcc/testsuite/gcc.dg/20020219-1.c b/gcc/testsuite/gcc.dg/20020219-1.c index ffdf19a43c1..d2ba755f50f 100644 --- a/gcc/testsuite/gcc.dg/20020219-1.c +++ b/gcc/testsuite/gcc.dg/20020219-1.c @@ -13,6 +13,7 @@ /* { dg-do run } */ /* { dg-options "-O2" } */ /* { dg-options "-O2 -mdisable-indexing" { target hppa*-*-hpux* } } */ +/* { dg-skip-if "" { aarch64*-*-* && ilp32 } { "*" } { "" } } */ /* { dg-skip-if "" { "ia64-*-hpux*" } "*" "-mlp64" } */ /* { dg-skip-if "" { { i?86-*-* x86_64-*-* } && x32 } { "*" } { "" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c b/gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c index b611e9b27fa..2ebecee63e5 100644 --- a/gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c +++ b/gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c @@ -9,10 +9,10 @@ struct y { - long p; - long q; - long r; - long s; + long long p; + long long q; + long long r; + long long s; } v = { 1, 2, 3, 4 }; struct z diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c index 9468ef44524..0672d48b66a 100644 --- a/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c @@ -39,5 +39,7 @@ atomic_fetch_or_RELAXED (long a) return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); } -/* { dg-final { scan-assembler-times "ldxr\tx\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ -/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, x\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "ldxr\tx\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target lp64} } } */ +/* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target ilp32} } } */ +/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, x\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target lp64} } } */ +/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target ilp32} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_double_int.c b/gcc/testsuite/gcc.target/aarch64/fcvt_double_int.c index 697aab1c478..e5399099b71 100644 --- a/gcc/testsuite/gcc.target/aarch64/fcvt_double_int.c +++ b/gcc/testsuite/gcc.target/aarch64/fcvt_double_int.c @@ -8,8 +8,10 @@ #include "fcvt.x" /* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *d\[0-9\]" 2 } } */ -/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 } } */ -/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 2 } } */ -/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 } } */ -/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 2 } } */ +/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */ +/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */ /* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *d\[0-9\]" 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c b/gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c index edf640bda4b..5eb36ff6ddd 100644 --- a/gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c +++ b/gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c @@ -7,7 +7,11 @@ #include "fcvt.x" -/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, *d\[0-9\]" 2 } } */ -/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 3 } } */ -/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 3 } } */ -/* { dg-final { scan-assembler-times "fcvtas\tx\[0-9\]+, *d\[0-9\]" 2 } } */ +/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */ +/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 3 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */ +/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 3 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */ +/* { dg-final { scan-assembler-times "fcvtas\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_double_uint.c b/gcc/testsuite/gcc.target/aarch64/fcvt_double_uint.c index a1fae764fdb..59be47512cf 100644 --- a/gcc/testsuite/gcc.target/aarch64/fcvt_double_uint.c +++ b/gcc/testsuite/gcc.target/aarch64/fcvt_double_uint.c @@ -8,8 +8,10 @@ #include "fcvt.x" /* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *d\[0-9\]" 2 } } */ -/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 } } */ +/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */ /* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *d\[0-9\]" 2 } } */ -/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 } } */ +/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */ /* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *d\[0-9\]" 2 } } */ /* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *d\[0-9\]" 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c b/gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c index f95fe55c674..55723cf9063 100644 --- a/gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c +++ b/gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c @@ -7,9 +7,15 @@ #include "fcvt.x" -/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\]+, *d\[0-9\]" 2 } } */ -/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 } } */ -/* { dg-final { scan-assembler-times "fcvtpu\tx\[0-9\]+, *d\[0-9\]" 2 } } */ -/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 } } */ -/* { dg-final { scan-assembler-times "fcvtmu\tx\[0-9\]+, *d\[0-9\]" 2 } } */ -/* { dg-final { scan-assembler-times "fcvtau\tx\[0-9\]+, *d\[0-9\]" 2 } } */ +/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */ +/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */ +/* { dg-final { scan-assembler-times "fcvtpu\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */ +/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */ +/* { dg-final { scan-assembler-times "fcvtmu\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */ +/* { dg-final { scan-assembler-times "fcvtau\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c b/gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c index ac1509857c4..2e10e2dec9d 100644 --- a/gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c +++ b/gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c @@ -8,8 +8,10 @@ #include "fcvt.x" /* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *s\[0-9\]" 2 } } */ -/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 } } */ -/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 2 } } */ -/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 } } */ -/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 2 } } */ +/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */ +/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */ /* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *s\[0-9\]" 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c b/gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c index 928ac52f7bc..1debf710f56 100644 --- a/gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c +++ b/gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c @@ -7,7 +7,11 @@ #include "fcvt.x" -/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, *s\[0-9\]" 2 } } */ -/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 3 } } */ -/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 3 } } */ -/* { dg-final { scan-assembler-times "fcvtas\tx\[0-9\]+, *s\[0-9\]" 2 } } */ +/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */ +/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 3 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */ +/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 3 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */ +/* { dg-final { scan-assembler-times "fcvtas\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c b/gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c index a7d1868ba73..c0b0c693a2b 100644 --- a/gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c +++ b/gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c @@ -8,8 +8,10 @@ #include "fcvt.x" /* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *s\[0-9\]" 2 } } */ -/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 } } */ +/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */ /* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *s\[0-9\]" 2 } } */ -/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 } } */ +/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */ /* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *s\[0-9\]" 2 } } */ /* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *s\[0-9\]" 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c b/gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c index ab6f46e7134..07309e2c884 100644 --- a/gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c +++ b/gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c @@ -7,9 +7,15 @@ #include "fcvt.x" -/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\]+, *s\[0-9\]" 2 } } */ -/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 } } */ -/* { dg-final { scan-assembler-times "fcvtpu\tx\[0-9\]+, *s\[0-9\]" 2 } } */ -/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 } } */ -/* { dg-final { scan-assembler-times "fcvtmu\tx\[0-9\]+, *s\[0-9\]" 2 } } */ -/* { dg-final { scan-assembler-times "fcvtau\tx\[0-9\]+, *s\[0-9\]" 2 } } */ +/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */ +/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */ +/* { dg-final { scan-assembler-times "fcvtpu\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */ +/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */ +/* { dg-final { scan-assembler-times "fcvtmu\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */ +/* { dg-final { scan-assembler-times "fcvtau\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */ +/* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c b/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c index 1f86eaeeb6e..f8cfeccf334 100644 --- a/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c +++ b/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c @@ -4,11 +4,11 @@ typedef signed char S8_t; typedef signed short S16_t; typedef signed int S32_t; -typedef signed long S64_t; +typedef signed long long S64_t; typedef signed char *__restrict__ pS8_t; typedef signed short *__restrict__ pS16_t; typedef signed int *__restrict__ pS32_t; -typedef signed long *__restrict__ pS64_t; +typedef signed long long *__restrict__ pS64_t; typedef unsigned char U8_t; typedef unsigned short U16_t; typedef unsigned int U32_t; @@ -16,7 +16,7 @@ typedef unsigned long U64_t; typedef unsigned char *__restrict__ pU8_t; typedef unsigned short *__restrict__ pU16_t; typedef unsigned int *__restrict__ pU32_t; -typedef unsigned long *__restrict__ pU64_t; +typedef unsigned long long *__restrict__ pU64_t; extern void abort (); |