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| author | uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4> | 2017-03-25 18:10:37 +0000 |
|---|---|---|
| committer | Roland McGrath <mcgrathr@google.com> | 2018-02-27 11:21:28 -0800 |
| commit | b824b5a2484202f6eabbe118b1cf7682ce77b76e (patch) | |
| tree | 3498b57e0363417502af7377b7c4bb9ff83666a3 | |
| parent | 2a1ebe0b1d58adcd16d4786bab18fca11f672cab (diff) | |
| download | gcc-roland/6.3.0/zircon.tar.gz | |
PR target/80180roland/6.3.0/zircon
* config/i386/i386.c (ix86_expand_builtin)
<IX86_BUILTIN_RDSEED{16,32,64}_STEP>: Do not expand arg0 between
flags reg setting and flags reg using instructions.
<IX86_BUILTIN_RDRAND{16,32,64}_STEP>: Ditto. Use non-flags reg
clobbering instructions to zero extend op2.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-6-branch@246477 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/config/i386/i386.c | 30 |
2 files changed, 31 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7927c0ddeef..a1280d50fd2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2017-03-25 Uros Bizjak <ubizjak@gmail.com> + + PR target/80180 + * config/i386/i386.c (ix86_expand_builtin) + <IX86_BUILTIN_RDSEED{16,32,64}_STEP>: Do not expand arg0 between + flags reg setting and flags reg using instructions. + <IX86_BUILTIN_RDRAND{16,32,64}_STEP>: Ditto. Use non-flags reg + clobbering instructions to zero extend op2. + 2018-02-26 Roland McGrath <mcgrathr@google.com> PR other/77609 diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 91f51d58cb7..558decf7627 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -41322,9 +41322,6 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget, mode0 = DImode; rdrand_step: - op0 = gen_reg_rtx (mode0); - emit_insn (GEN_FCN (icode) (op0)); - arg0 = CALL_EXPR_ARG (exp, 0); op1 = expand_normal (arg0); if (!address_operand (op1, VOIDmode)) @@ -41332,6 +41329,10 @@ rdrand_step: op1 = convert_memory_address (Pmode, op1); op1 = copy_addr_to_reg (op1); } + + op0 = gen_reg_rtx (mode0); + emit_insn (GEN_FCN (icode) (op0)); + emit_move_insn (gen_rtx_MEM (mode0, op1), op0); op1 = gen_reg_rtx (SImode); @@ -41340,8 +41341,20 @@ rdrand_step: /* Emit SImode conditional move. */ if (mode0 == HImode) { - op2 = gen_reg_rtx (SImode); - emit_insn (gen_zero_extendhisi2 (op2, op0)); + if (TARGET_ZERO_EXTEND_WITH_AND + && optimize_function_for_speed_p (cfun)) + { + op2 = force_reg (SImode, const0_rtx); + + emit_insn (gen_movstricthi + (gen_lowpart (HImode, op2), op0)); + } + else + { + op2 = gen_reg_rtx (SImode); + + emit_insn (gen_zero_extendhisi2 (op2, op0)); + } } else if (mode0 == SImode) op2 = op0; @@ -41373,9 +41386,6 @@ rdrand_step: mode0 = DImode; rdseed_step: - op0 = gen_reg_rtx (mode0); - emit_insn (GEN_FCN (icode) (op0)); - arg0 = CALL_EXPR_ARG (exp, 0); op1 = expand_normal (arg0); if (!address_operand (op1, VOIDmode)) @@ -41383,6 +41393,10 @@ rdseed_step: op1 = convert_memory_address (Pmode, op1); op1 = copy_addr_to_reg (op1); } + + op0 = gen_reg_rtx (mode0); + emit_insn (GEN_FCN (icode) (op0)); + emit_move_insn (gen_rtx_MEM (mode0, op1), op0); op2 = gen_reg_rtx (QImode); |