alpha.c (alpha_setup_incoming_varargs): Advance a copy of CUMULATIVE_ARGS past the last named argument.

        * config/alpha/alpha.c (alpha_setup_incoming_varargs): Advance a copy
        of CUMULATIVE_ARGS past the last named argument.
        (alpha_va_start): Expect pretend_args_size only if strictly less than
        6 named arguments.
        * config/alpha/alpha.h (TARGET_FP, TARGET_FPREGS, TARGET_GAS,
        TARGET_IEEE_CONFORMANT, TARGET_IEEE, TARGET_IEEE_WITH_INEXACT,
        TARGET_BUILD_CONSTANTS, TARGET_FLOAT_VAX, TARGET_BWX, TARGET_MAX,
        TARGET_FIX, TARGET_CIX, TARGET_EXPLICIT_RELOCS, TARGET_SMALL_DATA,
        TARGET_TLS_KERNEL, TARGET_SMALL_TEXT, TARGET_LONG_DOUBLE_128,
        TARGET_CPU_EV5, TARGET_CPU_EV6, TARGET_SUPPORT_ARCH): Booleanize.

From-SVN: r98261

3 files changed, 51 insertions, 38 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ba3aab92b99..ae1333eb6a5 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+2005-04-17  Richard Henderson  <rth@redhat.com>
+
+	PR target/20375
+	* config/alpha/alpha.c (alpha_setup_incoming_varargs): Advance a copy
+	of CUMULATIVE_ARGS past the last named argument.
+	(alpha_va_start): Expect pretend_args_size only if strictly less than
+	6 named arguments.
+	* config/alpha/alpha.h (TARGET_FP, TARGET_FPREGS, TARGET_GAS,
+	TARGET_IEEE_CONFORMANT, TARGET_IEEE, TARGET_IEEE_WITH_INEXACT,
+	TARGET_BUILD_CONSTANTS, TARGET_FLOAT_VAX, TARGET_BWX, TARGET_MAX,
+	TARGET_FIX, TARGET_CIX, TARGET_EXPLICIT_RELOCS, TARGET_SMALL_DATA,
+	TARGET_TLS_KERNEL, TARGET_SMALL_TEXT, TARGET_LONG_DOUBLE_128,
+	TARGET_CPU_EV5, TARGET_CPU_EV6, TARGET_SUPPORT_ARCH): Booleanize.
+
 2005-04-17  Alexandre Oliva  <aoliva@redhat.com>
 
 	PR middle-end/20739
diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c
index 037dc4ad33e..ce08d6734e7 100644
--- a/gcc/config/alpha/alpha.c
+++ b/gcc/config/alpha/alpha.c
@@ -5543,22 +5543,24 @@ alpha_build_builtin_va_list (void)
    variable number of arguments.  */
 
 static void
-alpha_setup_incoming_varargs (CUMULATIVE_ARGS *pcum,
-			      enum machine_mode mode ATTRIBUTE_UNUSED,
-			      tree type ATTRIBUTE_UNUSED,
-			      int *pretend_size, int no_rtl)
+alpha_setup_incoming_varargs (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
+			      tree type, int *pretend_size, int no_rtl)
 {
+  CUMULATIVE_ARGS cum = *pcum;
+
+  /* Skip the current argument.  */
+  FUNCTION_ARG_ADVANCE (cum, mode, type, 1);
+
 #if TARGET_ABI_UNICOSMK
   /* On Unicos/Mk, the standard subroutine __T3E_MISMATCH stores all register
      arguments on the stack. Unfortunately, it doesn't always store the first
      one (i.e. the one that arrives in $16 or $f16). This is not a problem
      with stdargs as we always have at least one named argument there.  */
-  int num_reg_words = pcum->num_reg_words;
-  if (num_reg_words < 6)
+  if (cum.num_reg_words < 6)
     {
       if (!no_rtl)
 	{
-	  emit_insn (gen_umk_mismatch_args (GEN_INT (num_reg_words + 1)));
+	  emit_insn (gen_umk_mismatch_args (GEN_INT (cum.num_reg_words)));
 	  emit_insn (gen_arg_home_umk ());
 	}
       *pretend_size = 0;
@@ -5570,7 +5572,7 @@ alpha_setup_incoming_varargs (CUMULATIVE_ARGS *pcum,
      This is not only because we won't need the space, but because AP
      includes the current_pretend_args_size and we don't want to mess up
      any ap-relative addresses already made.  */
-  if (pcum->num_args < 6)
+  if (cum.num_args < 6)
     {
       if (!no_rtl)
 	{
@@ -5591,8 +5593,6 @@ alpha_setup_incoming_varargs (CUMULATIVE_ARGS *pcum,
      not the most efficient way to implement varargs with just one register
      class, but it isn't worth doing anything more efficient in this rare
      case.  */
-  CUMULATIVE_ARGS cum = *pcum;
-
   if (cum >= 6)
     return;
 
@@ -5602,18 +5602,17 @@ alpha_setup_incoming_varargs (CUMULATIVE_ARGS *pcum,
       rtx tmp;
 
       tmp = gen_rtx_MEM (BLKmode,
-		         plus_constant (virtual_incoming_args_rtx,
-				        (cum + 6) * UNITS_PER_WORD));
+			 plus_constant (virtual_incoming_args_rtx,
+					(cum + 6) * UNITS_PER_WORD));
       set_mem_alias_set (tmp, set);
       move_block_from_reg (16 + cum, tmp, 6 - cum);
 
       tmp = gen_rtx_MEM (BLKmode,
-		         plus_constant (virtual_incoming_args_rtx,
-				        cum * UNITS_PER_WORD));
+			 plus_constant (virtual_incoming_args_rtx,
+					cum * UNITS_PER_WORD));
       set_mem_alias_set (tmp, set);
-      move_block_from_reg (16 + (TARGET_FPREGS ? 32 : 0) + cum, tmp,
-			   6 - cum);
-     }
+      move_block_from_reg (16 + cum + TARGET_FPREGS*32, tmp, 6 - cum);
+    }
   *pretend_size = 12 * UNITS_PER_WORD;
 #endif
 }
@@ -5642,7 +5641,7 @@ alpha_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
      integer argument register; that futzes with pretend_args_size,
      which changes the meaning of AP.  */
 
-  if (NUM_ARGS <= 6)
+  if (NUM_ARGS < 6)
     offset = TARGET_ABI_OPEN_VMS ? UNITS_PER_WORD : 6 * UNITS_PER_WORD;
   else
     offset = -6 * UNITS_PER_WORD + current_function_pretend_args_size;
diff --git a/gcc/config/alpha/alpha.h b/gcc/config/alpha/alpha.h
index 884156f7f97..7b298b77e69 100644
--- a/gcc/config/alpha/alpha.h
+++ b/gcc/config/alpha/alpha.h
@@ -156,99 +156,99 @@ extern int alpha_tls_size;
 /* This means that floating-point support exists in the target implementation
    of the Alpha architecture.  This is usually the default.  */
 #define MASK_FP		(1 << 0)
-#define TARGET_FP	(target_flags & MASK_FP)
+#define TARGET_FP	((target_flags & MASK_FP) != 0)
 
 /* This means that floating-point registers are allowed to be used.  Note
    that Alpha implementations without FP operations are required to
    provide the FP registers.  */
 
 #define MASK_FPREGS	(1 << 1)
-#define TARGET_FPREGS	(target_flags & MASK_FPREGS)
+#define TARGET_FPREGS	((target_flags & MASK_FPREGS) != 0)
 
 /* This means that gas is used to process the assembler file.  */
 
 #define MASK_GAS	(1 << 2)
-#define TARGET_GAS	(target_flags & MASK_GAS)
+#define TARGET_GAS	((target_flags & MASK_GAS) != 0)
 
 /* This means that we should mark procedures as IEEE conformant.  */
 
 #define MASK_IEEE_CONFORMANT (1 << 3)
-#define TARGET_IEEE_CONFORMANT	(target_flags & MASK_IEEE_CONFORMANT)
+#define TARGET_IEEE_CONFORMANT	((target_flags & MASK_IEEE_CONFORMANT) != 0)
 
 /* This means we should be IEEE-compliant except for inexact.  */
 
 #define MASK_IEEE	(1 << 4)
-#define TARGET_IEEE	(target_flags & MASK_IEEE)
+#define TARGET_IEEE	((target_flags & MASK_IEEE) != 0)
 
 /* This means we should be fully IEEE-compliant.  */
 
 #define MASK_IEEE_WITH_INEXACT (1 << 5)
-#define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT)
+#define TARGET_IEEE_WITH_INEXACT ((target_flags & MASK_IEEE_WITH_INEXACT) != 0)
 
 /* This means we must construct all constants rather than emitting
    them as literal data.  */
 
 #define MASK_BUILD_CONSTANTS (1 << 6)
-#define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS)
+#define TARGET_BUILD_CONSTANTS ((target_flags & MASK_BUILD_CONSTANTS) != 0)
 
 /* This means we handle floating points in VAX F- (float)
    or G- (double) Format.  */
 
 #define MASK_FLOAT_VAX	(1 << 7)
-#define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX)
+#define TARGET_FLOAT_VAX ((target_flags & MASK_FLOAT_VAX) != 0)
 
 /* This means that the processor has byte and half word loads and stores
    (the BWX extension).  */
 
 #define MASK_BWX	(1 << 8)
-#define TARGET_BWX	(target_flags & MASK_BWX)
+#define TARGET_BWX	((target_flags & MASK_BWX) != 0)
 
 /* This means that the processor has the MAX extension.  */
 #define MASK_MAX	(1 << 9)
-#define TARGET_MAX	(target_flags & MASK_MAX)
+#define TARGET_MAX	((target_flags & MASK_MAX) != 0)
 
 /* This means that the processor has the FIX extension.  */
 #define MASK_FIX	(1 << 10)
-#define TARGET_FIX	(target_flags & MASK_FIX)
+#define TARGET_FIX	((target_flags & MASK_FIX) != 0)
 
 /* This means that the processor has the CIX extension.  */
 #define MASK_CIX	(1 << 11)
-#define TARGET_CIX	(target_flags & MASK_CIX)
+#define TARGET_CIX	((target_flags & MASK_CIX) != 0)
 
 /* This means use !literal style explicit relocations.  */
 #define MASK_EXPLICIT_RELOCS (1 << 12)
-#define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)
+#define TARGET_EXPLICIT_RELOCS ((target_flags & MASK_EXPLICIT_RELOCS) != 0)
 
 /* This means use 16-bit relocations to .sdata/.sbss.  */
 #define MASK_SMALL_DATA (1 << 13)
-#define TARGET_SMALL_DATA (target_flags & MASK_SMALL_DATA)
+#define TARGET_SMALL_DATA ((target_flags & MASK_SMALL_DATA) != 0)
 
 /* This means emit thread pointer loads for kernel not user.  */
 #define MASK_TLS_KERNEL	(1 << 14)
-#define TARGET_TLS_KERNEL (target_flags & MASK_TLS_KERNEL)
+#define TARGET_TLS_KERNEL ((target_flags & MASK_TLS_KERNEL) != 0)
 
 /* This means use direct branches to local functions.  */
 #define MASK_SMALL_TEXT (1 << 15)
-#define TARGET_SMALL_TEXT (target_flags & MASK_SMALL_TEXT)
+#define TARGET_SMALL_TEXT ((target_flags & MASK_SMALL_TEXT) != 0)
 
 /* This means use IEEE quad-format for long double.  Assumes the
    presence of the GEM support library routines.  */
 #define MASK_LONG_DOUBLE_128 (1 << 16)
-#define TARGET_LONG_DOUBLE_128 (target_flags & MASK_LONG_DOUBLE_128)
+#define TARGET_LONG_DOUBLE_128 ((target_flags & MASK_LONG_DOUBLE_128) != 0)
 
 /* This means that the processor is an EV5, EV56, or PCA56.
    Unlike alpha_cpu this is not affected by -mtune= setting.  */
 #define MASK_CPU_EV5	(1 << 28)
-#define TARGET_CPU_EV5	(target_flags & MASK_CPU_EV5)
+#define TARGET_CPU_EV5	((target_flags & MASK_CPU_EV5) != 0)
 
 /* Likewise for EV6.  */
 #define MASK_CPU_EV6	(1 << 29)
-#define TARGET_CPU_EV6	(target_flags & MASK_CPU_EV6)
+#define TARGET_CPU_EV6	((target_flags & MASK_CPU_EV6) != 0)
 
 /* This means we support the .arch directive in the assembler.  Only
    defined in TARGET_CPU_DEFAULT.  */
 #define MASK_SUPPORT_ARCH (1 << 30)
-#define TARGET_SUPPORT_ARCH	(target_flags & MASK_SUPPORT_ARCH)
+#define TARGET_SUPPORT_ARCH	((target_flags & MASK_SUPPORT_ARCH) != 0)
 
 /* These are for target os support and cannot be changed at runtime.  */
 #define TARGET_ABI_WINDOWS_NT 0