diff options
| author | Steve Ellcey <sje@cup.hp.com> | 2005-04-14 15:43:03 +0000 |
|---|---|---|
| committer | Steve Ellcey <sje@gcc.gnu.org> | 2005-04-14 15:43:03 +0000 |
| commit | 36d9b8aecf0055c532f0f02966fc658127a00cf5 (patch) | |
| tree | 73818b5577aa132e62674afe2c6ed5cb49fb837d | |
| parent | 8855129ec6c189de33d51a25fe61ea0b54815c17 (diff) | |
| download | gcc-36d9b8aecf0055c532f0f02966fc658127a00cf5.tar.gz | |
re PR target/20924 (inline float divide does not set correct fpu status flags)
PR target/20924
* config/ia64/ia64.md (divsf3_internal_lat): Generate frcpa with
fpsr 0 instead of fpsr 1.
(divsf3_internal_thr): Ditto.
(divdf3_internal_lat): Ditto.
(divdf3_internal_thr): Ditto.
(divxf3_internal_lat): Ditto.
(divxf3_internal_thr): Ditto.
From-SVN: r98139
| -rw-r--r-- | gcc/ChangeLog | 11 | ||||
| -rw-r--r-- | gcc/config/ia64/ia64.md | 12 |
2 files changed, 17 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b61ac29154e..2ea5c71b44c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2005-04-14 Steve Ellcey <sje@cup.hp.com> + + PR target/20924 + * config/ia64/ia64.md (divsf3_internal_lat): Generate frcpa with + fpsr 0 instead of fpsr 1. + (divsf3_internal_thr): Ditto. + (divdf3_internal_lat): Ditto. + (divdf3_internal_thr): Ditto. + (divxf3_internal_lat): Ditto. + (divxf3_internal_thr): Ditto. + 2005-04-14 Ulrich Weigand <uweigand@de.ibm.com> PR target/20927 diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md index 365c0a8ce24..ef06b4596ab 100644 --- a/gcc/config/ia64/ia64.md +++ b/gcc/config/ia64/ia64.md @@ -2699,7 +2699,7 @@ [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8))) (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] UNSPEC_FR_RECIP_APPROX)) - (use (const_int 1))]) + (use (const_int 0))]) (cond_exec (ne (match_dup 5) (const_int 0)) (parallel [(set (match_dup 3) (mult:XF (match_dup 7) (match_dup 6))) (use (const_int 1))])) @@ -2756,7 +2756,7 @@ [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8))) (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] UNSPEC_FR_RECIP_APPROX)) - (use (const_int 1))]) + (use (const_int 0))]) (cond_exec (ne (match_dup 5) (const_int 0)) (parallel [(set (match_dup 3) (minus:XF (match_dup 10) @@ -3182,7 +3182,7 @@ [(parallel [(set (match_dup 7) (div:XF (const_int 1) (match_dup 9))) (set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)] UNSPEC_FR_RECIP_APPROX)) - (use (const_int 1))]) + (use (const_int 0))]) (cond_exec (ne (match_dup 6) (const_int 0)) (parallel [(set (match_dup 3) (mult:XF (match_dup 8) (match_dup 7))) (use (const_int 1))])) @@ -3262,7 +3262,7 @@ [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8))) (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] UNSPEC_FR_RECIP_APPROX)) - (use (const_int 1))]) + (use (const_int 0))]) (cond_exec (ne (match_dup 5) (const_int 0)) (parallel [(set (match_dup 3) (minus:XF (match_dup 10) @@ -3847,7 +3847,7 @@ [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) (set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)] UNSPEC_FR_RECIP_APPROX)) - (use (const_int 1))]) + (use (const_int 0))]) (cond_exec (ne (match_dup 7) (const_int 0)) (parallel [(set (match_dup 3) (minus:XF (match_dup 8) @@ -3925,7 +3925,7 @@ [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] UNSPEC_FR_RECIP_APPROX)) - (use (const_int 1))]) + (use (const_int 0))]) (cond_exec (ne (match_dup 5) (const_int 0)) (parallel [(set (match_dup 3) (minus:XF (match_dup 6) |