alpha: Remove all big-endian code.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@171438 138bc75d-0d04-0410-961f-82ee72b054a4

3 files changed, 184 insertions, 812 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a523f45c44e..26187881b26 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,29 @@
 2011-02-24  Richard Henderson  <rth@redhat.com>
 
+	* config/alpha/alpha.c (get_aligned_mem): Don't test WORDS_BIG_ENDIAN.
+	(alpha_expand_unaligned_load): Likewise.
+	(alpha_expand_unaligned_store): Likewise.
+	(alpha_expand_unaligned_load_words): Likewise.
+	(alpha_expand_unaligned_store_words): Likewise.
+	(emit_insxl, alpha_split_compare_and_swap_12): Likewise.
+	(alpha_split_lock_test_and_set_12): Likewise.
+	(print_operand, alpha_fold_builtin_extxx): Likewise.
+	(alpha_fold_builtin_insxx, alpha_fold_builtin_mskxx): Likewise.
+	* config/alpha/alpha.md (bswapsi2, insv, extv, extzv): Likewise.
+	(builtin_extwh, builtin_extlh, builtin_extql): Likewise.
+	(unaligned_extendqidi_be, unaligned_extendhidi_be, extxl_be): Remove.
+	(*extxl_1_be, *extql_2_be, extqh_be, extlh_be, extwh_be): Remove.
+	(insbl_be, inswl_be, insll_be, insql_be, mskxl_be): Remove.
+	(unaligned_loadqi_be, unaligned_loadhi_be): Remove.
+	(unaligned_storeqi_be, unaligned_storehi_be): Remove.
+	(extbl): Rename from builtin_extbl; don't test WORDS_BIG_ENDIAN.
+	(extwl, extll, extql): Similarly.
+	(inswh, inslh, insqh): Similarly.
+	(mskbl, mskwl, mskll, mskql): Similarly.
+	(mskwh, msklh, mskqh): Similarly.
+
+2011-02-24  Richard Henderson  <rth@redhat.com>
+
 	* config/alpha/alpha.md (attribute isa): Add er, ner.
 	(attribute enabled): Handle them.
 	(*movdi): Merge *movdi_{er_nofix,nofix,er_fix,fix}.
diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c
index d8d2f4126d1..4885be6227e 100644
--- a/gcc/config/alpha/alpha.c
+++ b/gcc/config/alpha/alpha.c
@@ -1453,10 +1453,7 @@ get_aligned_mem (rtx ref, rtx *paligned_mem, rtx *pbitnum)
   *paligned_mem = widen_memory_access (ref, SImode, -offset);
 
   /* Convert the byte offset within the word to a bit offset.  */
-  if (WORDS_BIG_ENDIAN)
-    offset = 32 - (GET_MODE_BITSIZE (GET_MODE (ref)) + offset * 8);
-  else
-    offset *= 8;
+  offset *= BITS_PER_UNIT;
   *pbitnum = GEN_INT (offset);
 }
 
@@ -3295,8 +3292,6 @@ alpha_expand_unaligned_load (rtx tgt, rtx mem, HOST_WIDE_INT size,
     {
       meml = adjust_address (mem, QImode, ofs);
       memh = adjust_address (mem, QImode, ofs+1);
-      if (BYTES_BIG_ENDIAN)
-	tmp = meml, meml = memh, memh = tmp;
       extl = gen_reg_rtx (DImode);
       exth = gen_reg_rtx (DImode);
       emit_insn (gen_zero_extendqidi2 (extl, meml));
@@ -3348,23 +3343,12 @@ alpha_expand_unaligned_load (rtx tgt, rtx mem, HOST_WIDE_INT size,
   set_mem_alias_set (tmp, 0);
   emit_move_insn (memh, tmp);
 
-  if (WORDS_BIG_ENDIAN && sign && (size == 2 || size == 4))
-    {
-      emit_move_insn (addr, plus_constant (mema, -1));
-
-      emit_insn (gen_extqh_be (extl, meml, addr));
-      emit_insn (gen_extxl_be (exth, memh, GEN_INT (64), addr));
-
-      addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN);
-      addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (64 - size*8),
-			   addr, 1, OPTAB_WIDEN);
-    }
-  else if (sign && size == 2)
+  if (sign && size == 2)
     {
       emit_move_insn (addr, plus_constant (mema, ofs+2));
 
-      emit_insn (gen_extxl_le (extl, meml, GEN_INT (64), addr));
-      emit_insn (gen_extqh_le (exth, memh, addr));
+      emit_insn (gen_extxl (extl, meml, GEN_INT (64), addr));
+      emit_insn (gen_extqh (exth, memh, addr));
 
       /* We must use tgt here for the target.  Alpha-vms port fails if we use
 	 addr for the target, because addr is marked as a pointer and combine
@@ -3375,55 +3359,27 @@ alpha_expand_unaligned_load (rtx tgt, rtx mem, HOST_WIDE_INT size,
     }
   else
     {
-      if (WORDS_BIG_ENDIAN)
-	{
-	  emit_move_insn (addr, plus_constant (mema, ofs+size-1));
-	  switch ((int) size)
-	    {
-	    case 2:
-	      emit_insn (gen_extwh_be (extl, meml, addr));
-	      mode = HImode;
-	      break;
-
-	    case 4:
-	      emit_insn (gen_extlh_be (extl, meml, addr));
-	      mode = SImode;
-	      break;
-
-	    case 8:
-	      emit_insn (gen_extqh_be (extl, meml, addr));
-	      mode = DImode;
-	      break;
-
-	    default:
-	      gcc_unreachable ();
-	    }
-	  emit_insn (gen_extxl_be (exth, memh, GEN_INT (size*8), addr));
-	}
-      else
+      emit_move_insn (addr, plus_constant (mema, ofs));
+      emit_insn (gen_extxl (extl, meml, GEN_INT (size*8), addr));
+      switch ((int) size)
 	{
-	  emit_move_insn (addr, plus_constant (mema, ofs));
-	  emit_insn (gen_extxl_le (extl, meml, GEN_INT (size*8), addr));
-	  switch ((int) size)
-	    {
-	    case 2:
-	      emit_insn (gen_extwh_le (exth, memh, addr));
-	      mode = HImode;
-	      break;
+	case 2:
+	  emit_insn (gen_extwh (exth, memh, addr));
+	  mode = HImode;
+	  break;
 
-	    case 4:
-	      emit_insn (gen_extlh_le (exth, memh, addr));
-	      mode = SImode;
-	      break;
+	case 4:
+	  emit_insn (gen_extlh (exth, memh, addr));
+	  mode = SImode;
+	  break;
 
-	    case 8:
-	      emit_insn (gen_extqh_le (exth, memh, addr));
-	      mode = DImode;
-	      break;
+	case 8:
+	  emit_insn (gen_extqh (exth, memh, addr));
+	  mode = DImode;
+	  break;
 
-	    default:
-	      gcc_unreachable ();
-	    }
+	default:
+	  gcc_unreachable ();
 	}
 
       addr = expand_binop (mode, ior_optab, gen_lowpart (mode, extl),
@@ -3457,8 +3413,6 @@ alpha_expand_unaligned_store (rtx dst, rtx src,
 
       meml = adjust_address (dst, QImode, ofs);
       memh = adjust_address (dst, QImode, ofs+1);
-      if (BYTES_BIG_ENDIAN)
-	addr = meml, meml = memh, memh = addr;
 
       emit_move_insn (meml, dstl);
       emit_move_insn (memh, dsth);
@@ -3492,86 +3446,48 @@ alpha_expand_unaligned_store (rtx dst, rtx src,
 
   emit_move_insn (dsth, memh);
   emit_move_insn (dstl, meml);
-  if (WORDS_BIG_ENDIAN)
-    {
-      addr = copy_addr_to_reg (plus_constant (dsta, ofs+size-1));
 
-      if (src != const0_rtx)
-	{
-	  switch ((int) size)
-	    {
-	    case 2:
-	      emit_insn (gen_inswl_be (insh, gen_lowpart (HImode,src), addr));
-	      break;
-	    case 4:
-	      emit_insn (gen_insll_be (insh, gen_lowpart (SImode,src), addr));
-	      break;
-	    case 8:
-	      emit_insn (gen_insql_be (insh, gen_lowpart (DImode,src), addr));
-	      break;
-	    }
-	  emit_insn (gen_insxh (insl, gen_lowpart (DImode, src),
-				GEN_INT (size*8), addr));
-	}
+  addr = copy_addr_to_reg (plus_constant (dsta, ofs));
+
+  if (src != CONST0_RTX (GET_MODE (src)))
+    {
+      emit_insn (gen_insxh (insh, gen_lowpart (DImode, src),
+			    GEN_INT (size*8), addr));
 
       switch ((int) size)
 	{
 	case 2:
-	  emit_insn (gen_mskxl_be (dsth, dsth, GEN_INT (0xffff), addr));
+	  emit_insn (gen_inswl (insl, gen_lowpart (HImode, src), addr));
 	  break;
 	case 4:
-	  {
-	    rtx msk = immed_double_const (0xffffffff, 0, DImode);
-	    emit_insn (gen_mskxl_be (dsth, dsth, msk, addr));
-	    break;
-	  }
+	  emit_insn (gen_insll (insl, gen_lowpart (SImode, src), addr));
+	  break;
 	case 8:
-	  emit_insn (gen_mskxl_be (dsth, dsth, constm1_rtx, addr));
+	  emit_insn (gen_insql (insl, gen_lowpart (DImode, src), addr));
 	  break;
+	default:
+	  gcc_unreachable ();
 	}
-
-      emit_insn (gen_mskxh (dstl, dstl, GEN_INT (size*8), addr));
     }
-  else
-    {
-      addr = copy_addr_to_reg (plus_constant (dsta, ofs));
-
-      if (src != CONST0_RTX (GET_MODE (src)))
-	{
-	  emit_insn (gen_insxh (insh, gen_lowpart (DImode, src),
-				GEN_INT (size*8), addr));
-
-	  switch ((int) size)
-	    {
-	    case 2:
-	      emit_insn (gen_inswl_le (insl, gen_lowpart (HImode, src), addr));
-	      break;
-	    case 4:
-	      emit_insn (gen_insll_le (insl, gen_lowpart (SImode, src), addr));
-	      break;
-	    case 8:
-	      emit_insn (gen_insql_le (insl, gen_lowpart (DImode, src), addr));
-	      break;
-	    }
-	}
 
-      emit_insn (gen_mskxh (dsth, dsth, GEN_INT (size*8), addr));
+  emit_insn (gen_mskxh (dsth, dsth, GEN_INT (size*8), addr));
 
-      switch ((int) size)
-	{
-	case 2:
-	  emit_insn (gen_mskxl_le (dstl, dstl, GEN_INT (0xffff), addr));
-	  break;
-	case 4:
-	  {
-	    rtx msk = immed_double_const (0xffffffff, 0, DImode);
-	    emit_insn (gen_mskxl_le (dstl, dstl, msk, addr));
-	    break;
-	  }
-	case 8:
-	  emit_insn (gen_mskxl_le (dstl, dstl, constm1_rtx, addr));
-	  break;
-	}
+  switch ((int) size)
+    {
+    case 2:
+      emit_insn (gen_mskxl (dstl, dstl, GEN_INT (0xffff), addr));
+      break;
+    case 4:
+      {
+	rtx msk = immed_double_const (0xffffffff, 0, DImode);
+	emit_insn (gen_mskxl (dstl, dstl, msk, addr));
+	break;
+      }
+    case 8:
+      emit_insn (gen_mskxl (dstl, dstl, constm1_rtx, addr));
+      break;
+    default:
+      gcc_unreachable ();
     }
 
   if (src != CONST0_RTX (GET_MODE (src)))
@@ -3580,17 +3496,9 @@ alpha_expand_unaligned_store (rtx dst, rtx src,
       dstl = expand_binop (DImode, ior_optab, insl, dstl, dstl, 0, OPTAB_WIDEN);
     }
 
-  if (WORDS_BIG_ENDIAN)
-    {
-      emit_move_insn (meml, dstl);
-      emit_move_insn (memh, dsth);
-    }
-  else
-    {
-      /* Must store high before low for degenerate case of aligned.  */
-      emit_move_insn (memh, dsth);
-      emit_move_insn (meml, dstl);
-    }
+  /* Must store high before low for degenerate case of aligned.  */
+  emit_move_insn (memh, dsth);
+  emit_move_insn (meml, dstl);
 }
 
 /* The block move code tries to maximize speed by separating loads and
@@ -3653,20 +3561,10 @@ alpha_expand_unaligned_load_words (rtx *out_regs, rtx smem,
   sreg = copy_addr_to_reg (smema);
   areg = expand_binop (DImode, and_optab, sreg, GEN_INT (7), NULL,
 		       1, OPTAB_WIDEN);
-  if (WORDS_BIG_ENDIAN)
-    emit_move_insn (sreg, plus_constant (sreg, 7));
   for (i = 0; i < words; ++i)
     {
-      if (WORDS_BIG_ENDIAN)
-	{
-	  emit_insn (gen_extqh_be (data_regs[i], data_regs[i], sreg));
-	  emit_insn (gen_extxl_be (ext_tmps[i], data_regs[i+1], i64, sreg));
-	}
-      else
-	{
-	  emit_insn (gen_extxl_le (data_regs[i], data_regs[i], i64, sreg));
-	  emit_insn (gen_extqh_le (ext_tmps[i], data_regs[i+1], sreg));
-	}
+      emit_insn (gen_extxl (data_regs[i], data_regs[i], i64, sreg));
+      emit_insn (gen_extqh (ext_tmps[i], data_regs[i+1], sreg));
       emit_insn (gen_rtx_SET (VOIDmode, ext_tmps[i],
 			      gen_rtx_IF_THEN_ELSE (DImode,
 						    gen_rtx_EQ (DImode, areg,
@@ -3726,22 +3624,12 @@ alpha_expand_unaligned_store_words (rtx *data_regs, rtx dmem,
 
   /* Shift the input data into place.  */
   dreg = copy_addr_to_reg (dmema);
-  if (WORDS_BIG_ENDIAN)
-    emit_move_insn (dreg, plus_constant (dreg, 7));
   if (data_regs != NULL)
     {
       for (i = words-1; i >= 0; --i)
 	{
-	  if (WORDS_BIG_ENDIAN)
-	    {
-	      emit_insn (gen_insql_be (ins_tmps[i], data_regs[i], dreg));
-	      emit_insn (gen_insxh (data_regs[i], data_regs[i], i64, dreg));
-	    }
-	  else
-	    {
-	      emit_insn (gen_insxh (ins_tmps[i], data_regs[i], i64, dreg));
-	      emit_insn (gen_insql_le (data_regs[i], data_regs[i], dreg));
-	    }
+	  emit_insn (gen_insxh (ins_tmps[i], data_regs[i], i64, dreg));
+	  emit_insn (gen_insql (data_regs[i], data_regs[i], dreg));
 	}
       for (i = words-1; i > 0; --i)
 	{
@@ -3752,16 +3640,8 @@ alpha_expand_unaligned_store_words (rtx *data_regs, rtx dmem,
     }
 
   /* Split and merge the ends with the destination data.  */
-  if (WORDS_BIG_ENDIAN)
-    {
-      emit_insn (gen_mskxl_be (st_tmp_2, st_tmp_2, constm1_rtx, dreg));
-      emit_insn (gen_mskxh (st_tmp_1, st_tmp_1, i64, dreg));
-    }
-  else
-    {
-      emit_insn (gen_mskxh (st_tmp_2, st_tmp_2, i64, dreg));
-      emit_insn (gen_mskxl_le (st_tmp_1, st_tmp_1, constm1_rtx, dreg));
-    }
+  emit_insn (gen_mskxh (st_tmp_2, st_tmp_2, i64, dreg));
+  emit_insn (gen_mskxl (st_tmp_1, st_tmp_1, constm1_rtx, dreg));
 
   if (data_regs != NULL)
     {
@@ -3772,24 +3652,17 @@ alpha_expand_unaligned_store_words (rtx *data_regs, rtx dmem,
     }
 
   /* Store it all.  */
-  if (WORDS_BIG_ENDIAN)
-    emit_move_insn (st_addr_1, st_tmp_1);
-  else
-    emit_move_insn (st_addr_2, st_tmp_2);
+  emit_move_insn (st_addr_2, st_tmp_2);
   for (i = words-1; i > 0; --i)
     {
       rtx tmp = change_address (dmem, DImode,
 				gen_rtx_AND (DImode,
-					     plus_constant(dmema,
-					     WORDS_BIG_ENDIAN ? i*8-1 : i*8),
+					     plus_constant (dmema, i*8),
 					     im8));
       set_mem_alias_set (tmp, 0);
       emit_move_insn (tmp, data_regs ? ins_tmps[i-1] : const0_rtx);
     }
-  if (WORDS_BIG_ENDIAN)
-    emit_move_insn (st_addr_2, st_tmp_2);
-  else
-    emit_move_insn (st_addr_1, st_tmp_1);
+  emit_move_insn (st_addr_1, st_tmp_1);
 }
 
 
@@ -4438,20 +4311,11 @@ emit_insxl (enum machine_mode mode, rtx op1, rtx op2)
   rtx ret = gen_reg_rtx (DImode);
   rtx (*fn) (rtx, rtx, rtx);
 
-  if (WORDS_BIG_ENDIAN)
-    {
-      if (mode == QImode)
-	fn = gen_insbl_be;
-      else
-	fn = gen_inswl_be;
-    }
+  if (mode == QImode)
+    fn = gen_insbl;
   else
-    {
-      if (mode == QImode)
-	fn = gen_insbl_le;
-      else
-	fn = gen_inswl_le;
-    }
+    fn = gen_inswl;
+
   /* The insbl and inswl patterns require a register operand.  */
   op1 = force_reg (mode, op1);
   emit_insn (fn (ret, op1, op2));
@@ -4584,10 +4448,7 @@ alpha_split_compare_and_swap_12 (enum machine_mode mode, rtx dest, rtx addr,
   
   width = GEN_INT (GET_MODE_BITSIZE (mode));
   mask = GEN_INT (mode == QImode ? 0xff : 0xffff);
-  if (WORDS_BIG_ENDIAN)
-    emit_insn (gen_extxl_be (dest, scratch, width, addr));
-  else
-    emit_insn (gen_extxl_le (dest, scratch, width, addr));
+  emit_insn (gen_extxl (dest, scratch, width, addr));
 
   if (oldval == const0_rtx)
     x = gen_rtx_NE (DImode, dest, const0_rtx);
@@ -4599,10 +4460,7 @@ alpha_split_compare_and_swap_12 (enum machine_mode mode, rtx dest, rtx addr,
     }
   emit_unlikely_jump (x, label2);
 
-  if (WORDS_BIG_ENDIAN)
-    emit_insn (gen_mskxl_be (scratch, scratch, mask, addr));
-  else
-    emit_insn (gen_mskxl_le (scratch, scratch, mask, addr));
+  emit_insn (gen_mskxl (scratch, scratch, mask, addr));
   emit_insn (gen_iordi3 (scratch, scratch, newval));
 
   emit_store_conditional (DImode, scratch, mem, scratch);
@@ -4678,16 +4536,8 @@ alpha_split_lock_test_and_set_12 (enum machine_mode mode, rtx dest, rtx addr,
   
   width = GEN_INT (GET_MODE_BITSIZE (mode));
   mask = GEN_INT (mode == QImode ? 0xff : 0xffff);
-  if (WORDS_BIG_ENDIAN)
-    {
-      emit_insn (gen_extxl_be (dest, scratch, width, addr));
-      emit_insn (gen_mskxl_be (scratch, scratch, mask, addr));
-    }
-  else
-    {
-      emit_insn (gen_extxl_le (dest, scratch, width, addr));
-      emit_insn (gen_mskxl_le (scratch, scratch, mask, addr));
-    }
+  emit_insn (gen_extxl (dest, scratch, width, addr));
+  emit_insn (gen_mskxl (scratch, scratch, mask, addr));
   emit_insn (gen_iordi3 (scratch, scratch, val));
 
   emit_store_conditional (DImode, scratch, mem, scratch);
@@ -5279,20 +5129,13 @@ print_operand (FILE *file, rtx x, int code)
       break;
 
     case 's':
-      /* Write the constant value divided by 8 for little-endian mode or
-	 (56 - value) / 8 for big-endian mode.  */
-
+      /* Write the constant value divided by 8.  */
       if (!CONST_INT_P (x)
-	  || (unsigned HOST_WIDE_INT) INTVAL (x) >= (WORDS_BIG_ENDIAN
-						     ? 56
-						     : 64)
+	  || (unsigned HOST_WIDE_INT) INTVAL (x) >= 64
 	  || (INTVAL (x) & 7) != 0)
 	output_operand_lossage ("invalid %%s value");
 
-      fprintf (file, HOST_WIDE_INT_PRINT_DEC,
-	       WORDS_BIG_ENDIAN
-	       ? (56 - INTVAL (x)) / 8
-	       : INTVAL (x) / 8);
+      fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) / 8);
       break;
 
     case 'S':
@@ -6391,27 +6234,27 @@ enum alpha_builtin
 
 static enum insn_code const code_for_builtin[ALPHA_BUILTIN_max] = {
   CODE_FOR_builtin_cmpbge,
-  CODE_FOR_builtin_extbl,
-  CODE_FOR_builtin_extwl,
-  CODE_FOR_builtin_extll,
-  CODE_FOR_builtin_extql,
-  CODE_FOR_builtin_extwh,
-  CODE_FOR_builtin_extlh,
-  CODE_FOR_builtin_extqh,
+  CODE_FOR_extbl,
+  CODE_FOR_extwl,
+  CODE_FOR_extll,
+  CODE_FOR_extql,
+  CODE_FOR_extwh,
+  CODE_FOR_extlh,
+  CODE_FOR_extqh,
   CODE_FOR_builtin_insbl,
   CODE_FOR_builtin_inswl,
   CODE_FOR_builtin_insll,
-  CODE_FOR_builtin_insql,
-  CODE_FOR_builtin_inswh,
-  CODE_FOR_builtin_inslh,
-  CODE_FOR_builtin_insqh,
-  CODE_FOR_builtin_mskbl,
-  CODE_FOR_builtin_mskwl,
-  CODE_FOR_builtin_mskll,
-  CODE_FOR_builtin_mskql,
-  CODE_FOR_builtin_mskwh,
-  CODE_FOR_builtin_msklh,
-  CODE_FOR_builtin_mskqh,
+  CODE_FOR_insql,
+  CODE_FOR_inswh,
+  CODE_FOR_inslh,
+  CODE_FOR_insqh,
+  CODE_FOR_mskbl,
+  CODE_FOR_mskwl,
+  CODE_FOR_mskll,
+  CODE_FOR_mskql,
+  CODE_FOR_mskwh,
+  CODE_FOR_msklh,
+  CODE_FOR_mskqh,
   CODE_FOR_umuldi3_highpart,
   CODE_FOR_builtin_zap,
   CODE_FOR_builtin_zapnot,
@@ -6779,9 +6622,7 @@ alpha_fold_builtin_extxx (tree op[], unsigned HOST_WIDE_INT opint[],
       unsigned HOST_WIDE_INT loc;
 
       loc = opint[1] & 7;
-      if (BYTES_BIG_ENDIAN)
-        loc ^= 7;
-      loc *= 8;
+      loc *= BITS_PER_UNIT;
 
       if (loc != 0)
 	{
@@ -6820,8 +6661,6 @@ alpha_fold_builtin_insxx (tree op[], unsigned HOST_WIDE_INT opint[],
       tree *zap_op = NULL;
 
       loc = opint[1] & 7;
-      if (BYTES_BIG_ENDIAN)
-        loc ^= 7;
       bytemask <<= loc;
 
       temp = opint[0];
@@ -6861,8 +6700,6 @@ alpha_fold_builtin_mskxx (tree op[], unsigned HOST_WIDE_INT opint[],
       unsigned HOST_WIDE_INT loc;
 
       loc = opint[1] & 7;
-      if (BYTES_BIG_ENDIAN)
-        loc ^= 7;
       bytemask <<= loc;
 
       if (is_high)
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index 2161e64adbd..2e3ac9e075d 100644
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -1320,8 +1320,7 @@
   t0 = gen_reg_rtx (DImode);
   t1 = gen_reg_rtx (DImode);
 
-  emit_insn (gen_insxh (t0, gen_lowpart (DImode, operands[1]),
-			GEN_INT (32), GEN_INT (WORDS_BIG_ENDIAN ? 0 : 7)));
+  emit_insn (gen_inslh (t0, gen_lowpart (DImode, operands[1]), GEN_INT (7)));
   emit_insn (gen_inswl_const (t1, gen_lowpart (HImode, operands[1]),
 			      GEN_INT (24)));
   emit_insn (gen_iordi3 (t1, t0, t1));
@@ -1520,106 +1519,45 @@
 ;; the unaligned loads (see below).
 ;;
 ;; Operand 1 is the address, operand 0 is the result.
-(define_expand "unaligned_extendqidi"
-  [(use (match_operand:QI 0 "register_operand" ""))
-   (use (match_operand:DI 1 "address_operand" ""))]
-  ""
-{
-  operands[0] = gen_lowpart (DImode, operands[0]);
-  if (WORDS_BIG_ENDIAN)
-    emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
-  else
-    emit_insn (gen_unaligned_extendqidi_le (operands[0], operands[1]));
-  DONE;
-})
 
-(define_expand "unaligned_extendqidi_le"
+(define_expand "unaligned_extendqidi"
   [(set (match_dup 3)
-	(mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
+	(mem:DI (and:DI (match_operand:DI 1 "address_operand" "") (const_int -8))))
    (set (match_dup 4)
 	(ashift:DI (match_dup 3)
 		   (minus:DI (const_int 64)
 			     (ashift:DI
 			      (and:DI (match_dup 2) (const_int 7))
 			      (const_int 3)))))
-   (set (match_operand:DI 0 "register_operand" "")
+   (set (match_operand:QI 0 "register_operand" "")
 	(ashiftrt:DI (match_dup 4) (const_int 56)))]
-  "! WORDS_BIG_ENDIAN"
+  ""
 {
+  operands[0] = gen_lowpart (DImode, operands[0]);
   operands[2] = get_unaligned_offset (operands[1], 1);
   operands[3] = gen_reg_rtx (DImode);
   operands[4] = gen_reg_rtx (DImode);
 })
 
-(define_expand "unaligned_extendqidi_be"
-  [(set (match_dup 3)
-	(mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
-   (set (match_dup 4)
-	(ashift:DI (match_dup 3)
-		   (ashift:DI
-		     (and:DI
-		       (plus:DI (match_dup 2) (const_int 1))
-		       (const_int 7))
-		     (const_int 3))))
-   (set (match_operand:DI 0 "register_operand" "")
-	(ashiftrt:DI (match_dup 4) (const_int 56)))]
-  "WORDS_BIG_ENDIAN"
-{
-  operands[2] = get_unaligned_offset (operands[1], -1);
-  operands[3] = gen_reg_rtx (DImode);
-  operands[4] = gen_reg_rtx (DImode);
-})
-
 (define_expand "unaligned_extendhidi"
-  [(use (match_operand:QI 0 "register_operand" ""))
-   (use (match_operand:DI 1 "address_operand" ""))]
-  ""
-{
-  operands[0] = gen_lowpart (DImode, operands[0]);
-  if (WORDS_BIG_ENDIAN)
-    emit_insn (gen_unaligned_extendhidi_be (operands[0], operands[1]));
-  else
-    emit_insn (gen_unaligned_extendhidi_le (operands[0], operands[1]));
-  DONE;
-})
-
-(define_expand "unaligned_extendhidi_le"
   [(set (match_dup 3)
-	(mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
+	(mem:DI (and:DI (match_operand:DI 1 "address_operand" "") (const_int -8))))
    (set (match_dup 4)
 	(ashift:DI (match_dup 3)
 		   (minus:DI (const_int 64)
 			     (ashift:DI
 			      (and:DI (match_dup 2) (const_int 7))
 			      (const_int 3)))))
-   (set (match_operand:DI 0 "register_operand" "")
+   (set (match_operand:HI 0 "register_operand" "")
 	(ashiftrt:DI (match_dup 4) (const_int 48)))]
-  "! WORDS_BIG_ENDIAN"
+  ""
 {
+  operands[0] = gen_lowpart (DImode, operands[0]);
   operands[2] = get_unaligned_offset (operands[1], 2);
   operands[3] = gen_reg_rtx (DImode);
   operands[4] = gen_reg_rtx (DImode);
 })
 
-(define_expand "unaligned_extendhidi_be"
-  [(set (match_dup 3)
-	(mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
-   (set (match_dup 4)
-	(ashift:DI (match_dup 3)
-		   (ashift:DI
-		     (and:DI
-		       (plus:DI (match_dup 2) (const_int 1))
-		       (const_int 7))
-		     (const_int 3))))
-   (set (match_operand:DI 0 "register_operand" "")
-	(ashiftrt:DI (match_dup 4) (const_int 48)))]
-  "WORDS_BIG_ENDIAN"
-{
-  operands[2] = get_unaligned_offset (operands[1], -1);
-  operands[3] = gen_reg_rtx (DImode);
-  operands[4] = gen_reg_rtx (DImode);
-})
-
 (define_insn "*extxl_const"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
@@ -1629,26 +1567,13 @@
   "ext%M2l %r1,%s3,%0"
   [(set_attr "type" "shift")])
 
-(define_insn "extxl_le"
+(define_insn "extxl"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
 			 (match_operand:DI 2 "mode_width_operand" "n")
 			 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
 				    (const_int 3))))]
-  "! WORDS_BIG_ENDIAN"
-  "ext%M2l %r1,%3,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn "extxl_be"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
-			 (match_operand:DI 2 "mode_width_operand" "n")
-			 (minus:DI
-			   (const_int 56)
-			   (ashift:DI
-			     (match_operand:DI 3 "reg_or_8bit_operand" "rI")
-			     (const_int 3)))))]
-  "WORDS_BIG_ENDIAN"
+  ""
   "ext%M2l %r1,%3,%0"
   [(set_attr "type" "shift")])
 
@@ -1656,50 +1581,26 @@
 ;; in shifts larger than a word size.  So capture these patterns that it
 ;; should have turned into zero_extracts.
 
-(define_insn "*extxl_1_le"
+(define_insn "*extxl_1"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
 		  (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
 			     (const_int 3)))
 	     (match_operand:DI 3 "mode_mask_operand" "n")))]
-  "! WORDS_BIG_ENDIAN"
-  "ext%U3l %1,%2,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn "*extxl_1_be"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(and:DI (lshiftrt:DI
-		  (match_operand:DI 1 "reg_or_0_operand" "rJ")
-		  (minus:DI (const_int 56)
-		    (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
-			       (const_int 3))))
-		(match_operand:DI 3 "mode_mask_operand" "n")))]
-  "WORDS_BIG_ENDIAN"
+  ""
   "ext%U3l %1,%2,%0"
   [(set_attr "type" "shift")])
 
-(define_insn "*extql_2_le"
+(define_insn "*extql_2"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
 	  (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
 		     (const_int 3))))]
-  "! WORDS_BIG_ENDIAN"
-  "extql %1,%2,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn "*extql_2_be"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(lshiftrt:DI
-	  (match_operand:DI 1 "reg_or_0_operand" "rJ")
-	  (minus:DI (const_int 56)
-		    (ashift:DI
-		      (match_operand:DI 2 "reg_or_8bit_operand" "rI")
-		      (const_int 3)))))]
-  "WORDS_BIG_ENDIAN"
+  ""
   "extql %1,%2,%0"
   [(set_attr "type" "shift")])
 
-(define_insn "extqh_le"
+(define_insn "extqh"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ashift:DI
 	 (match_operand:DI 1 "reg_or_0_operand" "rJ")
@@ -1709,25 +1610,11 @@
 		      (match_operand:DI 2 "reg_or_8bit_operand" "rI")
 		      (const_int 7))
 		     (const_int 3)))))]
-  "! WORDS_BIG_ENDIAN"
-  "extqh %r1,%2,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn "extqh_be"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ashift:DI
-	  (match_operand:DI 1 "reg_or_0_operand" "rJ")
-	  (ashift:DI
-	    (and:DI
-	      (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
-		       (const_int 1))
-	      (const_int 7))
-	    (const_int 3))))]
-  "WORDS_BIG_ENDIAN"
+  ""
   "extqh %r1,%2,%0"
   [(set_attr "type" "shift")])
 
-(define_insn "extlh_le"
+(define_insn "extlh"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ashift:DI
 	 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
@@ -1738,28 +1625,11 @@
 		      (match_operand:DI 2 "reg_or_8bit_operand" "rI")
 		      (const_int 7))
 		     (const_int 3)))))]
-  "! WORDS_BIG_ENDIAN"
-  "extlh %r1,%2,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn "extlh_be"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(and:DI
-	  (ashift:DI
-	    (match_operand:DI 1 "reg_or_0_operand" "rJ")
-	    (ashift:DI
-	      (and:DI
-		(plus:DI
-		  (match_operand:DI 2 "reg_or_8bit_operand" "rI")
-		  (const_int 1))
-		(const_int 7))
-	      (const_int 3)))
-	  (const_int 2147483647)))]
-  "WORDS_BIG_ENDIAN"
+  ""
   "extlh %r1,%2,%0"
   [(set_attr "type" "shift")])
 
-(define_insn "extwh_le"
+(define_insn "extwh"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ashift:DI
 	 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
@@ -1770,23 +1640,7 @@
 		      (match_operand:DI 2 "reg_or_8bit_operand" "rI")
 		      (const_int 7))
 		     (const_int 3)))))]
-  "! WORDS_BIG_ENDIAN"
-  "extwh %r1,%2,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn "extwh_be"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(and:DI
-	  (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
-		     (ashift:DI
-		       (and:DI
-			 (plus:DI
-			   (match_operand:DI 2 "reg_or_8bit_operand" "rI")
-			   (const_int 1))
-			 (const_int 7))
-		       (const_int 3)))
-	  (const_int 65535)))]
-  "WORDS_BIG_ENDIAN"
+  ""
   "extwh %r1,%2,%0"
   [(set_attr "type" "shift")])
 
@@ -1840,79 +1694,39 @@
   "insll %1,%s2,%0"
   [(set_attr "type" "shift")])
 
-(define_insn "insbl_le"
+(define_insn "insbl"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
 		   (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
 			      (const_int 3))))]
-  "! WORDS_BIG_ENDIAN"
-  "insbl %1,%2,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn "insbl_be"
- [(set (match_operand:DI 0 "register_operand" "=r")
-       (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
-	 (minus:DI (const_int 56)
-	   (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
-		      (const_int 3)))))]
-  "WORDS_BIG_ENDIAN"
+  ""
   "insbl %1,%2,%0"
   [(set_attr "type" "shift")])
 
-(define_insn "inswl_le"
+(define_insn "inswl"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
 		   (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
 			      (const_int 3))))]
-  "! WORDS_BIG_ENDIAN"
-  "inswl %1,%2,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn "inswl_be"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
-	  (minus:DI (const_int 56)
-	    (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
-		       (const_int 3)))))]
-  "WORDS_BIG_ENDIAN"
+  ""
   "inswl %1,%2,%0"
   [(set_attr "type" "shift")])
 
-(define_insn "insll_le"
+(define_insn "insll"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
 		   (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
 			      (const_int 3))))]
-  "! WORDS_BIG_ENDIAN"
-  "insll %1,%2,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn "insll_be"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
-	  (minus:DI (const_int 56)
-	    (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
-		       (const_int 3)))))]
-  "WORDS_BIG_ENDIAN"
+  ""
   "insll %1,%2,%0"
   [(set_attr "type" "shift")])
 
-(define_insn "insql_le"
+(define_insn "insql"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ashift:DI (match_operand:DI 1 "register_operand" "r")
 		   (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
 			      (const_int 3))))]
-  "! WORDS_BIG_ENDIAN"
-  "insql %1,%2,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn "insql_be"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ashift:DI (match_operand:DI 1 "register_operand" "r")
-	  (minus:DI (const_int 56)
-	    (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
-		       (const_int 3)))))]
-  "WORDS_BIG_ENDIAN"
+  ""
   "insql %1,%2,%0"
   [(set_attr "type" "shift")])
 
@@ -1963,7 +1777,7 @@
   "ins%M2h %1,%3,%0"
   [(set_attr "type" "shift")])
 
-(define_insn "mskxl_le"
+(define_insn "mskxl"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(and:DI (not:DI (ashift:DI
 			 (match_operand:DI 2 "mode_mask_operand" "n")
@@ -1971,20 +1785,7 @@
 			  (match_operand:DI 3 "reg_or_8bit_operand" "rI")
 			  (const_int 3))))
 		(match_operand:DI 1 "reg_or_0_operand" "rJ")))]
-  "! WORDS_BIG_ENDIAN"
-  "msk%U2l %r1,%3,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn "mskxl_be"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(and:DI (not:DI (ashift:DI
-			  (match_operand:DI 2 "mode_mask_operand" "n")
-			  (minus:DI (const_int 56)
-			    (ashift:DI
-			      (match_operand:DI 3 "reg_or_8bit_operand" "rI")
-			      (const_int 3)))))
-		(match_operand:DI 1 "reg_or_0_operand" "rJ")))]
-  "WORDS_BIG_ENDIAN"
+  ""
   "msk%U2l %r1,%3,%0"
   [(set_attr "type" "shift")])
 
@@ -5049,22 +4850,6 @@
 ;; operand 3 can overlap the input and output registers.
 
 (define_expand "unaligned_loadqi"
-  [(use (match_operand:DI 0 "register_operand" ""))
-   (use (match_operand:DI 1 "address_operand" ""))
-   (use (match_operand:DI 2 "register_operand" ""))
-   (use (match_operand:DI 3 "register_operand" ""))]
-  ""
-{
-  if (WORDS_BIG_ENDIAN)
-    emit_insn (gen_unaligned_loadqi_be (operands[0], operands[1],
-					operands[2], operands[3]));
-  else
-    emit_insn (gen_unaligned_loadqi_le (operands[0], operands[1],
-					operands[2], operands[3]));
-  DONE;
-})
-
-(define_expand "unaligned_loadqi_le"
   [(set (match_operand:DI 2 "register_operand" "")
 	(mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
 			(const_int -8))))
@@ -5074,41 +4859,10 @@
 	(zero_extract:DI (match_dup 2)
 			 (const_int 8)
 			 (ashift:DI (match_dup 3) (const_int 3))))]
-  "! WORDS_BIG_ENDIAN"
-  "")
-
-(define_expand "unaligned_loadqi_be"
-  [(set (match_operand:DI 2 "register_operand" "")
-	(mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
-			(const_int -8))))
-   (set (match_operand:DI 3 "register_operand" "")
-	(match_dup 1))
-   (set (match_operand:DI 0 "register_operand" "")
-	(zero_extract:DI (match_dup 2)
-			 (const_int 8)
-			 (minus:DI
-			   (const_int 56)
-			   (ashift:DI (match_dup 3) (const_int 3)))))]
-  "WORDS_BIG_ENDIAN"
+  ""
   "")
 
 (define_expand "unaligned_loadhi"
-  [(use (match_operand:DI 0 "register_operand" ""))
-   (use (match_operand:DI 1 "address_operand" ""))
-   (use (match_operand:DI 2 "register_operand" ""))
-   (use (match_operand:DI 3 "register_operand" ""))]
-  ""
-{
-  if (WORDS_BIG_ENDIAN)
-    emit_insn (gen_unaligned_loadhi_be (operands[0], operands[1],
-					operands[2], operands[3]));
-  else
-    emit_insn (gen_unaligned_loadhi_le (operands[0], operands[1],
-					operands[2], operands[3]));
-  DONE;
-})
-
-(define_expand "unaligned_loadhi_le"
   [(set (match_operand:DI 2 "register_operand" "")
 	(mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
 			(const_int -8))))
@@ -5118,22 +4872,7 @@
 	(zero_extract:DI (match_dup 2)
 			 (const_int 16)
 			 (ashift:DI (match_dup 3) (const_int 3))))]
-  "! WORDS_BIG_ENDIAN"
-  "")
-
-(define_expand "unaligned_loadhi_be"
-  [(set (match_operand:DI 2 "register_operand" "")
-	(mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
-			(const_int -8))))
-   (set (match_operand:DI 3 "register_operand" "")
-	(plus:DI (match_dup 1) (const_int 1)))
-   (set (match_operand:DI 0 "register_operand" "")
-	(zero_extract:DI (match_dup 2)
-			 (const_int 16)
-			 (minus:DI
-			   (const_int 56)
-			   (ashift:DI (match_dup 3) (const_int 3)))))]
-  "WORDS_BIG_ENDIAN"
+  ""
   "")
 
 ;; Storing an aligned byte or word requires two temporaries.  Operand 0 is the
@@ -5166,25 +4905,6 @@
 ;; operand 2 can be that register.
 
 (define_expand "unaligned_storeqi"
-  [(use (match_operand:DI 0 "address_operand" ""))
-   (use (match_operand:QI 1 "register_operand" ""))
-   (use (match_operand:DI 2 "register_operand" ""))
-   (use (match_operand:DI 3 "register_operand" ""))
-   (use (match_operand:DI 4 "register_operand" ""))]
-  ""
-{
-  if (WORDS_BIG_ENDIAN)
-    emit_insn (gen_unaligned_storeqi_be (operands[0], operands[1],
-					 operands[2], operands[3],
-					 operands[4]));
-  else
-    emit_insn (gen_unaligned_storeqi_le (operands[0], operands[1],
-					 operands[2], operands[3],
-					 operands[4]));
-  DONE;
-})
-
-(define_expand "unaligned_storeqi_le"
   [(set (match_operand:DI 3 "register_operand" "")
 	(mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
 			(const_int -8))))
@@ -5200,50 +4920,10 @@
    (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
    (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
 	(match_dup 4))]
-  "! WORDS_BIG_ENDIAN"
-  "")
-
-(define_expand "unaligned_storeqi_be"
-  [(set (match_operand:DI 3 "register_operand" "")
-	(mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
-			(const_int -8))))
-   (set (match_operand:DI 2 "register_operand" "")
-	(match_dup 0))
-   (set (match_dup 3)
-	(and:DI (not:DI (ashift:DI (const_int 255)
-			  (minus:DI (const_int 56)
-				    (ashift:DI (match_dup 2) (const_int 3)))))
-		(match_dup 3)))
-   (set (match_operand:DI 4 "register_operand" "")
-	(ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
-		   (minus:DI (const_int 56)
-		     (ashift:DI (match_dup 2) (const_int 3)))))
-   (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
-   (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
-	(match_dup 4))]
-  "WORDS_BIG_ENDIAN"
+  ""
   "")
 
 (define_expand "unaligned_storehi"
-  [(use (match_operand:DI 0 "address_operand" ""))
-   (use (match_operand:HI 1 "register_operand" ""))
-   (use (match_operand:DI 2 "register_operand" ""))
-   (use (match_operand:DI 3 "register_operand" ""))
-   (use (match_operand:DI 4 "register_operand" ""))]
-  ""
-{
-  if (WORDS_BIG_ENDIAN)
-    emit_insn (gen_unaligned_storehi_be (operands[0], operands[1],
-					 operands[2], operands[3],
-					 operands[4]));
-  else
-    emit_insn (gen_unaligned_storehi_le (operands[0], operands[1],
-					 operands[2], operands[3],
-					 operands[4]));
-  DONE;
-})
-
-(define_expand "unaligned_storehi_le"
   [(set (match_operand:DI 3 "register_operand" "")
 	(mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
 			(const_int -8))))
@@ -5259,31 +4939,9 @@
    (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
    (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
 	(match_dup 4))]
-  "! WORDS_BIG_ENDIAN"
+  ""
   "")
 
-(define_expand "unaligned_storehi_be"
-  [(set (match_operand:DI 3 "register_operand" "")
-	(mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
-			(const_int -8))))
-   (set (match_operand:DI 2 "register_operand" "")
-	(plus:DI (match_dup 5) (const_int 1)))
-   (set (match_dup 3)
-	(and:DI (not:DI (ashift:DI
-			  (const_int 65535)
-			  (minus:DI (const_int 56)
-				    (ashift:DI (match_dup 2) (const_int 3)))))
-		(match_dup 3)))
-   (set (match_operand:DI 4 "register_operand" "")
-	(ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
-		   (minus:DI (const_int 56)
-			     (ashift:DI (match_dup 2) (const_int 3)))))
-   (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
-   (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
-	(match_dup 4))]
-  "WORDS_BIG_ENDIAN"
-  "operands[5] = force_reg (DImode, operands[0]);")
-
 ;; Here are the define_expand's for QI and HI moves that use the above
 ;; patterns.  We have the normal sets, plus the ones that need scratch
 ;; registers for reload.
@@ -5708,16 +5366,7 @@
   if (!MEM_P (operands[1]))
     FAIL;
 
-  /* The bit number is relative to the mode of operand 1 which is
-     usually QImode (this might actually be a bug in expmed.c). Note 
-     that the bit number is negative in big-endian mode in this case.
-     We have to convert that to the offset.  */
-  if (WORDS_BIG_ENDIAN)
-    ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
-          - INTVAL (operands[2]) - INTVAL (operands[3]);
-  else
-    ofs = INTVAL (operands[3]);
-
+  ofs = INTVAL (operands[3]);
   ofs = ofs / 8;
 
   alpha_expand_unaligned_load (operands[0], operands[1],
@@ -5749,16 +5398,7 @@
       if (INTVAL (operands[2]) == 8)
 	FAIL;
 
-      /* The bit number is relative to the mode of operand 1 which is
-	 usually QImode (this might actually be a bug in expmed.c). Note 
-	 that the bit number is negative in big-endian mode in this case.
-	 We have to convert that to the offset.  */
-      if (WORDS_BIG_ENDIAN)
-	ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
-	      - INTVAL (operands[2]) - INTVAL (operands[3]);
-      else
-	ofs = INTVAL (operands[3]);
-
+      ofs = INTVAL (operands[3]);
       ofs = ofs / 8;
 
       alpha_expand_unaligned_load (operands[0], operands[1],
@@ -5789,16 +5429,7 @@
   if (!MEM_P (operands[0]))
     FAIL;
 
-  /* The bit number is relative to the mode of operand 1 which is
-     usually QImode (this might actually be a bug in expmed.c). Note 
-     that the bit number is negative in big-endian mode in this case.
-     We have to convert that to the offset.  */
-  if (WORDS_BIG_ENDIAN)
-    ofs = GET_MODE_BITSIZE (GET_MODE (operands[0]))
-          - INTVAL (operands[1]) - INTVAL (operands[2]);
-  else
-    ofs = INTVAL (operands[2]);
-
+  ofs = INTVAL (operands[2]);
   ofs = ofs / 8;
 
   alpha_expand_unaligned_store (operands[0], operands[3],
@@ -6402,108 +6033,43 @@
   ;; actually differentiate between ILOG and ICMP in the schedule.
   [(set_attr "type" "icmp")])
 
-(define_expand "builtin_extbl"
-  [(match_operand:DI 0 "register_operand" "")
-   (match_operand:DI 1 "reg_or_0_operand" "")
-   (match_operand:DI 2 "reg_or_8bit_operand" "")]
-  ""
-{
-  rtx (*gen) (rtx, rtx, rtx, rtx);
-  if (WORDS_BIG_ENDIAN)
-    gen = gen_extxl_be;
-  else
-    gen = gen_extxl_le;
-  emit_insn ((*gen) (operands[0], operands[1], GEN_INT (8), operands[2]));
-  DONE;
-})
-
-(define_expand "builtin_extwl"
-  [(match_operand:DI 0 "register_operand" "")
-   (match_operand:DI 1 "reg_or_0_operand" "")
-   (match_operand:DI 2 "reg_or_8bit_operand" "")]
-  ""
-{
-  rtx (*gen) (rtx, rtx, rtx, rtx);
-  if (WORDS_BIG_ENDIAN)
-    gen = gen_extxl_be;
-  else
-    gen = gen_extxl_le;
-  emit_insn ((*gen) (operands[0], operands[1], GEN_INT (16), operands[2]));
-  DONE;
-})
-
-(define_expand "builtin_extll"
+(define_expand "extbl"
   [(match_operand:DI 0 "register_operand" "")
    (match_operand:DI 1 "reg_or_0_operand" "")
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
   ""
 {
-  rtx (*gen) (rtx, rtx, rtx, rtx);
-  if (WORDS_BIG_ENDIAN)
-    gen = gen_extxl_be;
-  else
-    gen = gen_extxl_le;
-  emit_insn ((*gen) (operands[0], operands[1], GEN_INT (32), operands[2]));
+  emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (8), operands[2]));
   DONE;
 })
 
-(define_expand "builtin_extql"
+(define_expand "extwl"
   [(match_operand:DI 0 "register_operand" "")
    (match_operand:DI 1 "reg_or_0_operand" "")
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
   ""
 {
-  rtx (*gen) (rtx, rtx, rtx, rtx);
-  if (WORDS_BIG_ENDIAN)
-    gen = gen_extxl_be;
-  else
-    gen = gen_extxl_le;
-  emit_insn ((*gen) (operands[0], operands[1], GEN_INT (64), operands[2]));
+  emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (16), operands[2]));
   DONE;
 })
 
-(define_expand "builtin_extwh"
+(define_expand "extll"
   [(match_operand:DI 0 "register_operand" "")
    (match_operand:DI 1 "reg_or_0_operand" "")
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
   ""
 {
-  rtx (*gen) (rtx, rtx, rtx);
-  if (WORDS_BIG_ENDIAN)
-    gen = gen_extwh_be;
-  else
-    gen = gen_extwh_le;
-  emit_insn ((*gen) (operands[0], operands[1], operands[2]));
+  emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (32), operands[2]));
   DONE;
 })
 
-(define_expand "builtin_extlh"
+(define_expand "extql"
   [(match_operand:DI 0 "register_operand" "")
    (match_operand:DI 1 "reg_or_0_operand" "")
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
   ""
 {
-  rtx (*gen) (rtx, rtx, rtx);
-  if (WORDS_BIG_ENDIAN)
-    gen = gen_extlh_be;
-  else
-    gen = gen_extlh_le;
-  emit_insn ((*gen) (operands[0], operands[1], operands[2]));
-  DONE;
-})
-
-(define_expand "builtin_extqh"
-  [(match_operand:DI 0 "register_operand" "")
-   (match_operand:DI 1 "reg_or_0_operand" "")
-   (match_operand:DI 2 "reg_or_8bit_operand" "")]
-  ""
-{
-  rtx (*gen) (rtx, rtx, rtx);
-  if (WORDS_BIG_ENDIAN)
-    gen = gen_extqh_be;
-  else
-    gen = gen_extqh_le;
-  emit_insn ((*gen) (operands[0], operands[1], operands[2]));
+  emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (64), operands[2]));
   DONE;
 })
 
@@ -6513,13 +6079,8 @@
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
   ""
 {
-  rtx (*gen) (rtx, rtx, rtx);
-  if (WORDS_BIG_ENDIAN)
-    gen = gen_insbl_be;
-  else
-    gen = gen_insbl_le;
   operands[1] = gen_lowpart (QImode, operands[1]);
-  emit_insn ((*gen) (operands[0], operands[1], operands[2]));
+  emit_insn (gen_insbl (operands[0], operands[1], operands[2]));
   DONE;
 })
 
@@ -6529,13 +6090,8 @@
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
   ""
 {
-  rtx (*gen) (rtx, rtx, rtx);
-  if (WORDS_BIG_ENDIAN)
-    gen = gen_inswl_be;
-  else
-    gen = gen_inswl_le;
   operands[1] = gen_lowpart (HImode, operands[1]);
-  emit_insn ((*gen) (operands[0], operands[1], operands[2]));
+  emit_insn (gen_inswl (operands[0], operands[1], operands[2]));
   DONE;
 })
 
@@ -6545,33 +6101,12 @@
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
   ""
 {
-  rtx (*gen) (rtx, rtx, rtx);
-  if (WORDS_BIG_ENDIAN)
-    gen = gen_insll_be;
-  else
-    gen = gen_insll_le;
   operands[1] = gen_lowpart (SImode, operands[1]);
-  emit_insn ((*gen) (operands[0], operands[1], operands[2]));
-  emit_insn ((*gen) (operands[0], operands[1], operands[2]));
+  emit_insn (gen_insll (operands[0], operands[1], operands[2]));
   DONE;
 })
 
-(define_expand "builtin_insql"
-  [(match_operand:DI 0 "register_operand" "")
-   (match_operand:DI 1 "reg_or_0_operand" "")
-   (match_operand:DI 2 "reg_or_8bit_operand" "")]
-  ""
-{
-  rtx (*gen) (rtx, rtx, rtx);
-  if (WORDS_BIG_ENDIAN)
-    gen = gen_insql_be;
-  else
-    gen = gen_insql_le;
-  emit_insn ((*gen) (operands[0], operands[1], operands[2]));
-  DONE;
-})
-
-(define_expand "builtin_inswh"
+(define_expand "inswh"
   [(match_operand:DI 0 "register_operand" "")
    (match_operand:DI 1 "register_operand" "")
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
@@ -6581,7 +6116,7 @@
   DONE;
 })
 
-(define_expand "builtin_inslh"
+(define_expand "inslh"
   [(match_operand:DI 0 "register_operand" "")
    (match_operand:DI 1 "register_operand" "")
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
@@ -6591,7 +6126,7 @@
   DONE;
 })
 
-(define_expand "builtin_insqh"
+(define_expand "insqh"
   [(match_operand:DI 0 "register_operand" "")
    (match_operand:DI 1 "register_operand" "")
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
@@ -6601,75 +6136,51 @@
   DONE;
 })
 
-(define_expand "builtin_mskbl"
+(define_expand "mskbl"
   [(match_operand:DI 0 "register_operand" "")
    (match_operand:DI 1 "reg_or_0_operand" "")
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
   ""
 {
-  rtx (*gen) (rtx, rtx, rtx, rtx);
-  rtx mask;
-  if (WORDS_BIG_ENDIAN)
-    gen = gen_mskxl_be;
-  else
-    gen = gen_mskxl_le;
-  mask = GEN_INT (0xff);
-  emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
+  rtx mask = GEN_INT (0xff);
+  emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2]));
   DONE;
 })
 
-(define_expand "builtin_mskwl"
+(define_expand "mskwl"
   [(match_operand:DI 0 "register_operand" "")
    (match_operand:DI 1 "reg_or_0_operand" "")
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
   ""
 {
-  rtx (*gen) (rtx, rtx, rtx, rtx);
-  rtx mask;
-  if (WORDS_BIG_ENDIAN)
-    gen = gen_mskxl_be;
-  else
-    gen = gen_mskxl_le;
-  mask = GEN_INT (0xffff);
-  emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
+  rtx mask = GEN_INT (0xffff);
+  emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2]));
   DONE;
 })
 
-(define_expand "builtin_mskll"
+(define_expand "mskll"
   [(match_operand:DI 0 "register_operand" "")
    (match_operand:DI 1 "reg_or_0_operand" "")
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
   ""
 {
-  rtx (*gen) (rtx, rtx, rtx, rtx);
-  rtx mask;
-  if (WORDS_BIG_ENDIAN)
-    gen = gen_mskxl_be;
-  else
-    gen = gen_mskxl_le;
-  mask = immed_double_const (0xffffffff, 0, DImode);
-  emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
+  rtx mask = immed_double_const (0xffffffff, 0, DImode);
+  emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2]));
   DONE;
 })
 
-(define_expand "builtin_mskql"
+(define_expand "mskql"
   [(match_operand:DI 0 "register_operand" "")
    (match_operand:DI 1 "reg_or_0_operand" "")
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
   ""
 {
-  rtx (*gen) (rtx, rtx, rtx, rtx);
-  rtx mask;
-  if (WORDS_BIG_ENDIAN)
-    gen = gen_mskxl_be;
-  else
-    gen = gen_mskxl_le;
-  mask = constm1_rtx;
-  emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
+  rtx mask = constm1_rtx;
+  emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2]));
   DONE;
 })
 
-(define_expand "builtin_mskwh"
+(define_expand "mskwh"
   [(match_operand:DI 0 "register_operand" "")
    (match_operand:DI 1 "register_operand" "")
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
@@ -6679,7 +6190,7 @@
   DONE;
 })
 
-(define_expand "builtin_msklh"
+(define_expand "msklh"
   [(match_operand:DI 0 "register_operand" "")
    (match_operand:DI 1 "register_operand" "")
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
@@ -6689,7 +6200,7 @@
   DONE;
 })
 
-(define_expand "builtin_mskqh"
+(define_expand "mskqh"
   [(match_operand:DI 0 "register_operand" "")
    (match_operand:DI 1 "register_operand" "")
    (match_operand:DI 2 "reg_or_8bit_operand" "")]