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| author | Yvan Roux <yvan.roux@linaro.org> | 2016-04-12 13:39:01 +0200 |
|---|---|---|
| committer | Yvan Roux <yvan.roux@linaro.org> | 2016-04-14 08:32:53 +0200 |
| commit | 8d7043e84c526ead366949c3c30ce74f964efe91 (patch) | |
| tree | 78fe3a1a7554a848fc30717c71105e45359bf3ef | |
| parent | 55d3bceea8eef018564a026e615af58cca5d6273 (diff) | |
| download | gcc-8d7043e84c526ead366949c3c30ce74f964efe91.tar.gz | |
Merge branches/gcc-5-branch rev 234898.
Change-Id: I076a131171e689eede74dd1827406c6d3855fcbd
200 files changed, 4800 insertions, 511 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 18348002be1..9ce777a3789 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,520 @@ +2016-04-12 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + Backport from mainline + 2016-04-08 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + PR target/70566 + * config/arm/thumb2.md (tst + branch-> lsls + branch + peephole below *orsi_not_shiftsi_si): Require that condition + register is dead after the peephole. + (second peephole after the above): Likewise. + +2016-04-11 Alan Modra <amodra@gmail.com> + + PR target/70117 + * builtins.c (fold_builtin_classify): For IBM extended precision, + look at just the high-order double to test for NaN. + (fold_builtin_interclass_mathfn): Similarly for Inf. For isnormal + test just the high double for Inf but both doubles for subnormal + limit. + +2016-04-09 Oleg Endo <olegendo@gcc.gnu.org> + + Backport from mainline + 2016-04-03 Oleg Endo <olegendo@gcc.gnu.org> + + PR target/70416 + PR target/67391 + * config/sh/sh.md (*addsi3): Allow pattern when reload_in_progress is + set, but not for SP_REG operands. + +2016-04-06 Uros Bizjak <ubizjak@gmail.com> + + * config/i386/sse.md (shuffletype): Add V32HI and V4TI modes. + (ssescalarsize): Add V8SF, V4SF, V4DF and V2DF modes. + +2016-04-06 Richard Biener <rguenther@suse.de> + + Backport from mainline + 2016-03-11 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/70177 + * gimple-expr.h (extract_ops_from_tree_1): Renamed to ... + (extract_ops_from_tree): ... this. In the 2 argument + overload remove _1 suffix. + * gimple-expr.c (extract_ops_from_tree_1): Renamed to ... + (extract_ops_from_tree): ... this. + * gimple.c (gimple_build_assign, gimple_assign_set_rhs_from_tree): + Adjust callers. + * tree-ssa-loop-niter.c (derive_constant_upper_bound): Likewise. + * tree-ssa-forwprop.c (defcodefor_name): Call 3 operand + extract_ops_from_tree instead of 2 operand one. + +2016-04-06 Richard Biener <rguenther@suse.de> + + Backport from mainline + 2016-02-24 Richard Biener <rguenther@suse.de> + Jakub Jelinek <jakub@redhat.com> + + PR middle-end/69760 + * tree-scalar-evolution.c (interpret_rhs_expr): Re-write + conditionally executed ops to well-defined overflow behavior. + + 2016-03-01 Richard Biener <rguenther@suse.de> + + PR tree-optimization/69983 + * tree-chrec.c (eq_evolutions_p): Handle conversions, compare + types and fall back to operand_equal_p. + +2016-04-06 Richard Biener <rguenther@suse.de> + + Backport from mainline + 2016-02-24 Richard Biener <rguenther@suse.de> + + PR middle-end/68963 + * tree-ssa-loop-niter.c (derive_constant_upper_bound_ops): Fix + bogus check. + (record_nonwrapping_iv): Do not fall back to the low/high bound + for non-constant IV bases if the stmt is not always executed. + +2016-04-06 Richard Biener <rguenther@suse.de> + + Backport from mainline + 2016-03-01 Richard Biener <rguenther@suse.de> + + PR middle-end/70022 + * fold-const.c (fold_indirect_ref_1): Fix range checking for + vector BIT_FIELD_REF extract. + + 2016-03-07 Richard Biener <rguenther@suse.de> + + PR tree-optimization/70115 + * tree-ssa-loop-ivcanon.c (propagate_into_all_uses): Remove. + (propagate_constants_for_unrolling): Use replace_uses_by. + + 2016-03-29 Richard Biener <rguenther@suse.de> + + PR middle-end/70424 + * ipa-prop.c (ipa_compute_jump_functions_for_edge): Always + use alignment returned by get_pointer_alignment_1 if it is + bigger than BITS_PER_UNIT. + * builtins.c (get_pointer_alignment_1): Do not return true + for alignment extracted from SSA info. + +2016-04-06 Richard Biener <rguenther@suse.de> + + Backport from mainline + 2016-03-30 Richard Biener <rguenther@suse.de> + + PR middle-end/70450 + * fold-const.c (extract_muldiv_1): Fix thinko in wide_int::from + usage. + + 2016-03-22 Richard Biener <rguenther@suse.de> + + PR middle-end/70333 + * fold-const.c (extract_muldiv_1): Properly perform multiplication + in the wide type. + + 2016-04-04 Richard Biener <rguenther@suse.de> + + PR rtl-optimization/70484 + * rtl.h (canon_output_dependence): Declare. + * alias.c (canon_output_dependence): New function. + * dse.c (record_store): Use canon_output_dependence rather + than canon_true_dependence. + +2016-04-05 John David Anglin <danglin@gcc.gnu.org> + + * config/pa/predicates.md (integer_store_memory_operand): Accept + REG+D operands with a large offset when reload_in_progress is true. + (floating_point_store_memory_operand): Likewise. + +2016-04-05 Uros Bizjak <ubizjak@gmail.com> + + Backport from mainline + 2015-12-08 Kirill Yukhin <kirill.yukhin@intel.com> + + * config/i386/sse.md (define_insn "<avx512>_vec_dup<mode>_1"): Fix + assembler to make source always 128bit. + +2016-04-05 Uros Bizjak <ubizjak@gmail.com> + + PR target/70510 + * config/i386/sse.md (iptr): Add V64QI, V32HI, V16SI and V8DI modes. + +2016-04-05 Jakub Jelinek <jakub@redhat.com> + + PR target/70525 + * config/i386/sse.md (*andnot<mode>3): Simplify assertions. + Use vpandn<ssemodesuffix> for V16SI/V8DImode, vpandnq for + V32HI/V64QImode, don't use <mask_operand3_1>, fix up formatting. + (*andnot<mode>3_mask): Remove insn with VI12_AVX512VL iterator. + +2016-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + Jakub Jelinek <jakub@redhat.com> + + PR middle-end/70457 + * tree-inline.c (estimate_num_insn): Use gimple_call_builtin_p + to ensure a call statement is compatible with a built-in's + prototype. + * tree-ssa-math-opts.c (execute_cse_sincos_1): Likewise. + (pass_cse_sincos::execute): Likewise. + (pass_optimize_widening_mul::execute): Likewise. + +2016-01-04 Christophe Lyon <christophe.lyon@linaro.org> + + Backport from mainline + 2015-11-10 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + PR rtl-optimization/68236 + * haifa-sched.c (autopref_multipass_dfa_lookahead_guard): Return 0 + if insn_queue doesn't exist. + (haifa_sched_finish): Reset insn_queue to NULL. + +2016-04-01 James Greenhalgh <james.greenhalgh@arm.com> + + Backport from mainline + 2016-01-26 Roger Ferrer Ibáñez <rofirrim@gmail.com> + + PR target/67896 + * config/aarch64/aarch64-builtins.c + (aarch64_init_simd_builtin_types): Do not set structural + equality to __Poly{8,16,64,128}_t types. + +2016-03-31 Nathan Sidwell <nathan@acm.org> + + PR c++/70393 + * varasm.c (output_constructor_regular_field): Flush bitfield + earlier. Assert we don't want to move backwards. + +2016-03-31 Kirill Yukhin <kirill.yukhin@intel.com> + + PR target/70453 + * config/i386/sse.md (define_mode_attr shuffletype): Fix typo. + +2016-03-31 Andrey Belevantsev <abel@ispras.ru> + + Backport from mainline + 2016-03-12 Andrey Belevantsev <abel@ispras.ru> + + PR rtl-optimization/69307 + * sel-sched.c (choose_best_pseudo_reg): Properly check for hard + registers in modes that span more than one register. + +2016-03-31 Andrey Belevantsev <abel@ispras.ru> + + Backport from mainline + 2016-03-21 Andrey Belevantsev <abel@ispras.ru> + + PR rtl-optimization/69102 + * sched-deps.c (sched_analyze_insn): Do not set last_args_size field + when we have a readonly dependency context. + +2016-03-31 Andrey Belevantsev <abel@ispras.ru> + + Backport from mainline + 2016-03-15 Andrey Belevantsev <abel@ispras.ru> + + PR rtl-optimization/69032 + * sel-sched-ir.c (get_seqno_by_preds): Include both insn and head when + looping backwards over basic block insns. + +2016-03-31 Andrey Belevantsev <abel@ispras.ru> + + Backport from mainline + 2016-03-15 Andrey Belevantsev <abel@ispras.ru> + + PR target/66660 + * sel-sched-ir.c (merge_expr): Avoid changing the speculative pattern + to non-speculative when propagating trap bits. + +2016-03-31 Andrey Belevantsev <abel@ispras.ru> + + Backport from mainline + 2016-03-15 Andrey Belevantsev <abel@ispras.ru> + + PR target/64411 + * sched-deps.c (get_implicit_reg_pending_clobbers): New function, + factored out from ... + (sched_analyze_insn): ... here. + * sched-int.h (get_implicit_reg_pending_clobbers): Declare it. + * sel-sched-ir.c (setup_id_implicit_regs): New function, use + get_implicit_reg_pending_clobbers in it. + (setup_id_reg_sets): Use setup_id_implicit_regs. + (deps_init_id): Ditto. + +2016-03-31 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/70460 + * ira.c (indirect_jump_optimize): Don't substitute LABEL_REF + with operand from REG_LABEL_OPERAND, instead substitute + SET_SRC or REG_EQUAL note content if it is a LABEL_REF. + Don't do anything for REG_NON_LOCAL_GOTO jumps. + +2016-03-31 Alan Modra <amodra@gmail.com> + + Backport from mainline + 2016-02-16 Alan Modra <amodra@gmail.com> + PR target/68973 + * config/rs6000/rs6000.md (reload_vsx_from_gprsf): Rewrite splitter. + (p8_mtvsrd_df, p8_mtvsrd_sf): New. + (p8_mtvsrd_1, p8_mtvsrd_2): Delete. + (p8_mtvsrwz): New. + (p8_mtvsrwz_1, p8_mtvsrwz_2): Delete. + (p8_xxpermdi_<mode>): Take two DF inputs rather than one TF. + (p8_fmrgow_<mode>): Likewise. + (reload_vsx_from_gpr<mode>): Adjust for above. Use "wa" for + clobber constraint. + (reload_fpr_from_gpr<mode>): Adjust for above. Use "d" for + op0 constraint. + (reload_vsx_from_gprsf): Use p8_mtvsrd_sf rather than attempting + to use movdi_internal64. Remove op0_di. + * config/rs6000/vsx.md (vsx_xscvspdpn_directmove): Make op1 SFmode. + +2016-03-30 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> + + Backport from mainline + 2016-03-23 Ilya Enkovich <enkovich.gnu@gmail.com> + + PR target/69917 + * config/i386/sol2.h (ASM_OUTPUT_DEF_FROM_DECLS): Follow + transparent alias chain for decl assembler name. + * config/sol2.c (solaris_assemble_visibility): Likewise. + +2016-03-30 Vladimir Makarov <vmakarov@redhat.com> + + Backported from the mainline + 2016-03-12 Vladimir Makarov <vmakarov@redhat.com> + + PR target/69614 + * lra-constraints.c (delete_move_and_clobber): New. + (remove_inheritance_pseudos): Use it. + +2016-03-30 Jakub Jelinek <jakub@redhat.com> + + PR target/70421 + * config/i386/i386.c (ix86_expand_vector_set): Fix up argument order + in gen_blendm expander. + + Backported from mainline + 2016-03-29 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/70429 + * combine.c (simplify_shift_const_1): For ASHIFTRT don't optimize + (cst1 >> count) >> cst2 into (cst1 >> cst2) >> count if + mode != result_mode. + + 2016-03-22 Jakub Jelinek <jakub@redhat.com> + + PR target/70329 + * config/i386/i386.c (ix86_expand_vecop_qihi): Don't bother computing + d.perm[i] for i >= d.nelt. If not full_interleave, compute d.perm[i] + in a way that works also for AVX512BW. + + 2016-03-21 Jakub Jelinek <jakub@redhat.com> + + PR target/70296 + * config/rs6000/rs6000-c.c (rs6000_macro_to_expand): If IDENT is + function-like macro, peek following token(s) if it is followed + by CPP_OPEN_PAREN token with optional padding in between, and + if not, don't treat it like a macro. + + 2016-03-15 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/70222 + * combine.c (simplify_shift_const_1): For A >> B >> C LSHIFTRT + optimization if mode is different from result_mode, queue up masking + of the result in outer_op. Formatting fix. + + 2016-03-11 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/70169 + * tree-ssa-loop.c (gen_lsm_tmp_name): Handle FUNCTION_DECL and + LABEL_DECL like VAR_DECL. Emit nothing instead of gcc_unreachable + for unknown codes. + + 2016-03-09 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/70152 + * tree-sra.c (replace_removed_params_ssa_names): Copy over + SSA_NAME_OCCURS_IN_ABNORMAL_PHI from old_name to new_name. + + 2016-03-04 Jakub Jelinek <jakub@redhat.com> + + PR target/70062 + * config/i386/i386.c (decide_alg): Add RECUR argument. Revert + 2016-02-22 changes, instead don't recurse if RECUR is already true. + Don't change *dynamic_check if RECUR. Adjust recursive caller + to pass true to the new argument. + (ix86_expand_set_or_movmem): Adjust decide_alg caller. + + 2016-02-22 Jakub Jelinek <jakub@redhat.com> + + PR target/69888 + * config/i386/i386.c (decide_alg): Ensure we don't recurse with + identical arguments. Formatting and spelling fixes. + + 2016-03-02 Jakub Jelinek <jakub@redhat.com> + + PR target/70028 + * config/i386/i386.md (kmovw): Move m constraint to 2nd alternative. + (*movhi_internal): Put mask moves from and to memory separately + from moves from/to GPRs. + + 2016-02-26 Jakub Jelinek <jakub@redhat.com> + + PR target/69969 + * config/rs6000/rs6000.c (rs6000_option_override_internal): Don't + complain about -mallow-movmisalign without -mvsx if + TARGET_ALLOW_MOVMISALIGN was not set explicitly. + + 2016-02-26 Jakub Jelinek <jakub@redhat.com> + Eric Botcazou <ebotcazou@adacore.com> + + PR rtl-optimization/69891 + * dse.c (scan_insn): If we can't figure out memset arguments + or they are non-constant, call clear_rhs_from_active_local_stores. + + 2016-02-24 Jakub Jelinek <jakub@redhat.com> + + PR debug/69705 + * dwarf2out.c (gen_variable_die): Work around buggy LTO + - allow NULL decl for Fortran DW_TAG_common_block variables. + + 2016-02-19 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/69838 + * lra.c (lra_process_new_insns): If non-call exceptions are enabled, + call copy_reg_eh_region_note_forward on before and/or after sequences + and remove note from insn if it no longer can throw. + + 2016-02-16 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/69802 + * tree-ssa-reassoc.c (update_range_test): If op is + SSA_NAME_IS_DEFAULT_DEF, give up unless tem is a positive + op == 1 test of precision 1 integral op, otherwise handle + that case as op itself. Fix up formatting. + (optimize_range_tests_to_bit_test, optimize_range_tests): Fix + up formatting. + + PR rtl-optimization/69764 + PR rtl-optimization/69771 + * optabs.c (expand_binop): Ensure for shift optabs invalid CONST_INT + op1 is valid for GET_MODE_INNER (mode) and force it into a reg. + + 2016-02-12 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/69764 + PR rtl-optimization/69771 + * optabs.c (expand_binop_directly): For shift_optab_p, force + convert_modes with VOIDmode if xop1 has VOIDmode. + + PR ipa/68672 + * ipa-split.c (split_function): Compute retval early in all cases + if split_part_return_p and return_bb is not EXIT. Remove all + clobber stmts and reset all debug stmts that refer to SSA_NAMEs + defined in split part, except if it is retval, in that case replace + the old retval with the lhs of the call to the split part. + +2016-03-30 Alan Modra <amodra@gmail.com> + + PR target/70052 + * config/rs6000/constraints.md (j): Simplify. + * config/rs6000/predicates.md (easy_fp_constant): Exclude + decimal float 0.D. + * config/rs6000/rs6000.md (zero_fp): New mode_attr. + (mov<mode>_hardfloat, mov<mode>_hardfloat32, mov<mode>_hardfloat64, + mov<mode>_64bit_dm, mov<mode>_32bit): Use zero_fp in place of j + in all constraint alternatives. + (movtd_64bit_nodm): Delete "j" constraint alternative. + +2016-03-29 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + PR target/69875 + * config/arm/arm.h (TARGET_HAVE_LPAE): Define. + * config/arm/unspecs.md (VUNSPEC_LDRD_ATOMIC): New value. + * config/arm/sync.md (arm_atomic_loaddi2_ldrd): New pattern. + (atomic_loaddi_1): Delete. + (atomic_loaddi): Rewrite expander using the above changes. + +2016-03-28 Kirill Yukhin <kirill.yukhin@intel.com> + + PR target/70406 + * config/i386/i386.md (define_split, andn): Fix modes. + +2016-03-24 John David Anglin <danglin@gcc.gnu.org> + + PR target/70319 + * config/pa/pa.md (bswapdi2): Use a scratch register. + +2016-03-22 Martin Liska <mliska@suse.cz> + + backport from trunk: + + 2016-03-21 Martin Liska <mliska@suse.cz> + + PR ipa/70306 + * ipa-icf.c (sem_function::parse): Skip static + constructors and destructors. + +2016-03-22 Kirill Yukhin <kirill.yukhin@intel.com> + + PR target/70325 + * config/i386/i386.c (def_builtin): Handle + OPTION_MASK_ISA_AVX512VL to be and-ed with other bits. + (const struct builtin_description bdesc_special_args[]): + Remove duplicate ISA bits. + +2016-03-21 Uros Bizjak <ubizjak@gmail.com> + + PR target/70327 + * config/i386/i386.md (movxi): Use ix86_expand_vector_move instead + of ix86_expand_move. + (movoi): Ditto. + (movti): Use general_operand for operand 1 predicate. + +2016-03-21 Tom de Vries <tom@codesourcery.com> + + backport from trunk: + PR ipa/70269 + 2016-03-18 Tom de Vries <tom@codesourcery.com> + + * cgraph.c (cgraph_node::get_body): Set dump_file to NULL after save. + +2016-03-21 Tom de Vries <tom@codesourcery.com> + + backport from trunk: + 2016-03-18 Tom de Vries <tom@codesourcery.com> + + PR ipa/70161 + * cgraph.c (cgraph_node::get_body): Save, reset and restore + dump_file_name. + * passes.c (execute_one_ipa_transform_pass): Add missing argument to + execute_function_dump. + (execute_one_pass): Don't dump function if it will be dumped after ipa + transform. + +2016-03-21 Kirill Yukhin <kirill.yukhin@intel.com> + + PR target/70293 + * config/i386/sse.md: (define_insn "*vec_dup<mode>"/AVX2): + Block third alternative for AVX-512VL target, + +2016-03-17 John David Anglin <danglin@gcc.gnu.org> + + PR target/70188 + * config/pa/constraints.md: Revert 2015-02-13 change. Use + define_constraint for "Q" and "T" constraints. + +2016-03-16 Alan Modra <amodra@gmail.com> + + PR rtl-optimization/69195 + PR rtl-optimization/47992 + * ira.c (indirect_jump_optimize): Ignore artificial defs. + Add comments. + 2016-03-15 Bernd Schmidt <bschmidt@redhat.com> Backport from mainline diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 4ed5216e588..4e3167d42c1 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20160315 +20160412 diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog index d8215871d77..b6998220ce5 100644 --- a/gcc/ada/ChangeLog +++ b/gcc/ada/ChangeLog @@ -1,6 +1,16 @@ +2016-04-02 Eric Botcazou <ebotcazou@adacore.com> + + * gcc-interface/decl.c (components_to_record): Restrict the previous + change to fields with variable size. + +2016-03-27 Eric Botcazou <ebotcazou@adacore.com> + + * gcc-interface/decl.c (components_to_record): Add special case for + single field with representation clause at offset 0. + 2016-02-17 Eric Botcazou <ebotcazou@adacore.com> - * exp_ch4.adb (Expand_N_Indexed_Component): Active synchronization if + * exp_ch4.adb (Expand_N_Indexed_Component): Activate synchronization if the prefix denotes an entity which Has_Atomic_Components. 2016-02-16 Eric Botcazou <ebotcazou@adacore.com> diff --git a/gcc/ada/gcc-interface/decl.c b/gcc/ada/gcc-interface/decl.c index a77ca6634e0..d3f30897116 100644 --- a/gcc/ada/gcc-interface/decl.c +++ b/gcc/ada/gcc-interface/decl.c @@ -7381,6 +7381,25 @@ components_to_record (tree gnu_record_type, Node_Id gnat_component_list, if (p_gnu_rep_list && gnu_rep_list) *p_gnu_rep_list = chainon (*p_gnu_rep_list, gnu_rep_list); + /* Deal with the annoying case of an extension of a record with variable size + and partial rep clause, for which the _Parent field is forced at offset 0 + and has variable size, which we do not support below. Note that we cannot + do it if the field has fixed size because we rely on the presence of the + REP part built below to trigger the reordering of the fields in a derived + record type when all the fields have a fixed position. */ + else if (gnu_rep_list + && !DECL_CHAIN (gnu_rep_list) + && TREE_CODE (DECL_SIZE (gnu_rep_list)) != INTEGER_CST + && !variants_have_rep + && first_free_pos + && integer_zerop (first_free_pos) + && integer_zerop (bit_position (gnu_rep_list))) + { + DECL_CHAIN (gnu_rep_list) = gnu_field_list; + gnu_field_list = gnu_rep_list; + gnu_rep_list = NULL_TREE; + } + /* Otherwise, sort the fields by bit position and put them into their own record, before the others, if we also have fields without rep clause. */ else if (gnu_rep_list) diff --git a/gcc/alias.c b/gcc/alias.c index 5d2d3333c9a..6949a157d4a 100644 --- a/gcc/alias.c +++ b/gcc/alias.c @@ -2700,6 +2700,20 @@ output_dependence (const_rtx mem, const_rtx x) /*mem_canonicalized=*/false, /*x_canonicalized*/false, /*writep=*/true); } + +/* Likewise, but we already have a canonicalized MEM, and X_ADDR for X. + Also, consider X in X_MODE (which might be from an enclosing + STRICT_LOW_PART / ZERO_EXTRACT). + If MEM_CANONICALIZED is true, MEM is canonicalized. */ + +int +canon_output_dependence (const_rtx mem, bool mem_canonicalized, + const_rtx x, machine_mode x_mode, rtx x_addr) +{ + return write_dependence_p (mem, x, x_mode, x_addr, + mem_canonicalized, /*x_canonicalized=*/true, + /*writep=*/true); +} diff --git a/gcc/builtins.c b/gcc/builtins.c index 166abbeea02..ca24982b67d 100644 --- a/gcc/builtins.c +++ b/gcc/builtins.c @@ -502,7 +502,7 @@ get_pointer_alignment_1 (tree exp, unsigned int *alignp, if (*alignp == 0) *alignp = 1u << (HOST_BITS_PER_INT - 1); /* We cannot really tell whether this result is an approximation. */ - return true; + return false; } else { @@ -9559,6 +9559,8 @@ fold_builtin_interclass_mathfn (location_t loc, tree fndecl, tree arg) mode = TYPE_MODE (TREE_TYPE (arg)); + bool is_ibm_extended = MODE_COMPOSITE_P (mode); + /* If there is no optab, try generic code. */ switch (DECL_FUNCTION_CODE (fndecl)) { @@ -9568,10 +9570,18 @@ fold_builtin_interclass_mathfn (location_t loc, tree fndecl, tree arg) { /* isinf(x) -> isgreater(fabs(x),DBL_MAX). */ tree const isgr_fn = builtin_decl_explicit (BUILT_IN_ISGREATER); - tree const type = TREE_TYPE (arg); + tree type = TREE_TYPE (arg); REAL_VALUE_TYPE r; char buf[128]; + if (is_ibm_extended) + { + /* NaN and Inf are encoded in the high-order double value + only. The low-order value is not significant. */ + type = double_type_node; + mode = DFmode; + arg = fold_build1_loc (loc, NOP_EXPR, type, arg); + } get_max_float (REAL_MODE_FORMAT (mode), buf, sizeof (buf)); real_from_string (&r, buf); result = build_call_expr (isgr_fn, 2, @@ -9584,10 +9594,18 @@ fold_builtin_interclass_mathfn (location_t loc, tree fndecl, tree arg) { /* isfinite(x) -> islessequal(fabs(x),DBL_MAX). */ tree const isle_fn = builtin_decl_explicit (BUILT_IN_ISLESSEQUAL); - tree const type = TREE_TYPE (arg); + tree type = TREE_TYPE (arg); REAL_VALUE_TYPE r; char buf[128]; + if (is_ibm_extended) + { + /* NaN and Inf are encoded in the high-order double value + only. The low-order value is not significant. */ + type = double_type_node; + mode = DFmode; + arg = fold_build1_loc (loc, NOP_EXPR, type, arg); + } get_max_float (REAL_MODE_FORMAT (mode), buf, sizeof (buf)); real_from_string (&r, buf); result = build_call_expr (isle_fn, 2, @@ -9607,21 +9625,72 @@ fold_builtin_interclass_mathfn (location_t loc, tree fndecl, tree arg) /* isnormal(x) -> isgreaterequal(fabs(x),DBL_MIN) & islessequal(fabs(x),DBL_MAX). */ tree const isle_fn = builtin_decl_explicit (BUILT_IN_ISLESSEQUAL); - tree const isge_fn = builtin_decl_explicit (BUILT_IN_ISGREATEREQUAL); - tree const type = TREE_TYPE (arg); + tree type = TREE_TYPE (arg); + tree orig_arg, max_exp, min_exp; + machine_mode orig_mode = mode; REAL_VALUE_TYPE rmax, rmin; char buf[128]; + orig_arg = arg = builtin_save_expr (arg); + if (is_ibm_extended) + { + /* Use double to test the normal range of IBM extended + precision. Emin for IBM extended precision is + different to emin for IEEE double, being 53 higher + since the low double exponent is at least 53 lower + than the high double exponent. */ + type = double_type_node; + mode = DFmode; + arg = fold_build1_loc (loc, NOP_EXPR, type, arg); + } + arg = fold_build1_loc (loc, ABS_EXPR, type, arg); + get_max_float (REAL_MODE_FORMAT (mode), buf, sizeof (buf)); real_from_string (&rmax, buf); - sprintf (buf, "0x1p%d", REAL_MODE_FORMAT (mode)->emin - 1); + sprintf (buf, "0x1p%d", REAL_MODE_FORMAT (orig_mode)->emin - 1); real_from_string (&rmin, buf); - arg = builtin_save_expr (fold_build1_loc (loc, ABS_EXPR, type, arg)); - result = build_call_expr (isle_fn, 2, arg, - build_real (type, rmax)); - result = fold_build2 (BIT_AND_EXPR, integer_type_node, result, - build_call_expr (isge_fn, 2, arg, - build_real (type, rmin))); + max_exp = build_real (type, rmax); + min_exp = build_real (type, rmin); + + max_exp = build_call_expr (isle_fn, 2, arg, max_exp); + if (is_ibm_extended) + { + /* Testing the high end of the range is done just using + the high double, using the same test as isfinite(). + For the subnormal end of the range we first test the + high double, then if its magnitude is equal to the + limit of 0x1p-969, we test whether the low double is + non-zero and opposite sign to the high double. */ + tree const islt_fn = builtin_decl_explicit (BUILT_IN_ISLESS); + tree const isgt_fn = builtin_decl_explicit (BUILT_IN_ISGREATER); + tree gt_min = build_call_expr (isgt_fn, 2, arg, min_exp); + tree eq_min = fold_build2 (EQ_EXPR, integer_type_node, + arg, min_exp); + tree as_complex = build1 (VIEW_CONVERT_EXPR, + complex_double_type_node, orig_arg); + tree hi_dbl = build1 (REALPART_EXPR, type, as_complex); + tree lo_dbl = build1 (IMAGPART_EXPR, type, as_complex); + tree zero = build_real (type, dconst0); + tree hilt = build_call_expr (islt_fn, 2, hi_dbl, zero); + tree lolt = build_call_expr (islt_fn, 2, lo_dbl, zero); + tree logt = build_call_expr (isgt_fn, 2, lo_dbl, zero); + tree ok_lo = fold_build1 (TRUTH_NOT_EXPR, integer_type_node, + fold_build3 (COND_EXPR, + integer_type_node, + hilt, logt, lolt)); + eq_min = fold_build2 (TRUTH_ANDIF_EXPR, integer_type_node, + eq_min, ok_lo); + min_exp = fold_build2 (TRUTH_ORIF_EXPR, integer_type_node, + gt_min, eq_min); + } + else + { + tree const isge_fn + = builtin_decl_explicit (BUILT_IN_ISGREATEREQUAL); + min_exp = build_call_expr (isge_fn, 2, arg, min_exp); + } + result = fold_build2 (BIT_AND_EXPR, integer_type_node, + max_exp, min_exp); return result; } default: @@ -9716,6 +9785,15 @@ fold_builtin_classify (location_t loc, tree fndecl, tree arg, int builtin_index) return real_isnan (&r) ? integer_one_node : integer_zero_node; } + { + bool is_ibm_extended = MODE_COMPOSITE_P (TYPE_MODE (TREE_TYPE (arg))); + if (is_ibm_extended) + { + /* NaN and Inf are encoded in the high-order double value + only. The low-order value is not significant. */ + arg = fold_build1_loc (loc, NOP_EXPR, double_type_node, arg); + } + } arg = builtin_save_expr (arg); return fold_build2_loc (loc, UNORDERED_EXPR, type, arg, arg); diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog index 8c6a7a7d0ce..494e9655b61 100644 --- a/gcc/c-family/ChangeLog +++ b/gcc/c-family/ChangeLog @@ -1,3 +1,19 @@ +2016-03-30 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2016-02-19 Jakub Jelinek <jakub@redhat.com> + + PR c++/69826 + * c-pragma.c (c_pp_lookup_pragma): Handle PRAGMA_CILK_GRAINSIZE. + (init_pragma): Register PRAGMA_CILK_GRAINSIZE even for + flag_preprocess_only. + + 2016-02-15 Jakub Jelinek <jakub@redhat.com> + + PR c++/69797 + * c-common.c (sync_resolve_size): Diagnose too few arguments + even when params is non-NULL empty vector. + 2016-02-10 Jakub Jelinek <jakub@redhat.com> Backported from mainline diff --git a/gcc/c-family/c-common.c b/gcc/c-family/c-common.c index 75de6dc6147..d2e3c1e4168 100644 --- a/gcc/c-family/c-common.c +++ b/gcc/c-family/c-common.c @@ -10533,7 +10533,7 @@ sync_resolve_size (tree function, vec<tree, va_gc> *params) tree type; int size; - if (!params) + if (vec_safe_is_empty (params)) { error ("too few arguments to function %qE", function); return 0; diff --git a/gcc/c-family/c-pragma.c b/gcc/c-family/c-pragma.c index 6894f0e7c3d..03c10397c8b 100644 --- a/gcc/c-family/c-pragma.c +++ b/gcc/c-family/c-pragma.c @@ -1273,6 +1273,13 @@ c_pp_lookup_pragma (unsigned int id, const char **space, const char **name) return; } + if (id == PRAGMA_CILK_GRAINSIZE) + { + *space = "cilk"; + *name = "grainsize"; + return; + } + if (id >= PRAGMA_FIRST_EXTERNAL && (id < PRAGMA_FIRST_EXTERNAL + registered_pp_pragmas.length ())) { @@ -1459,7 +1466,7 @@ init_pragma (void) cpp_register_deferred_pragma (parse_in, "GCC", "ivdep", PRAGMA_IVDEP, false, false); - if (flag_cilkplus && !flag_preprocess_only) + if (flag_cilkplus) cpp_register_deferred_pragma (parse_in, "cilk", "grainsize", PRAGMA_CILK_GRAINSIZE, true, false); diff --git a/gcc/cgraph.c b/gcc/cgraph.c index 22ae8127378..e25ecb3fb96 100644 --- a/gcc/cgraph.c +++ b/gcc/cgraph.c @@ -3313,7 +3313,10 @@ cgraph_node::get_body (void) { opt_pass *saved_current_pass = current_pass; FILE *saved_dump_file = dump_file; + const char *saved_dump_file_name = dump_file_name; int saved_dump_flags = dump_flags; + dump_file_name = NULL; + dump_file = NULL; push_cfun (DECL_STRUCT_FUNCTION (decl)); execute_all_ipa_transforms (); @@ -3325,6 +3328,7 @@ cgraph_node::get_body (void) current_pass = saved_current_pass; dump_file = saved_dump_file; + dump_file_name = saved_dump_file_name; dump_flags = saved_dump_flags; } return updated; diff --git a/gcc/combine.c b/gcc/combine.c index 7d098cfb6cb..7f4f065308a 100644 --- a/gcc/combine.c +++ b/gcc/combine.c @@ -10534,9 +10534,24 @@ simplify_shift_const_1 (enum rtx_code code, machine_mode result_mode, && CONST_INT_P (XEXP (varop, 0)) && !CONST_INT_P (XEXP (varop, 1))) { + /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make + sure the result will be masked. See PR70222. */ + if (code == LSHIFTRT + && mode != result_mode + && !merge_outer_ops (&outer_op, &outer_const, AND, + GET_MODE_MASK (result_mode) + >> orig_count, result_mode, + &complement_p)) + break; + /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing + up outer sign extension (often left and right shift) is + hardly more efficient than the original. See PR70429. */ + if (code == ASHIFTRT && mode != result_mode) + break; + rtx new_rtx = simplify_const_binary_operation (code, mode, - XEXP (varop, 0), - GEN_INT (count)); + XEXP (varop, 0), + GEN_INT (count)); varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1)); count = 0; continue; diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index a301d5b0210..f60ec4f834e 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -254,6 +254,10 @@ extern void (*arm_lang_output_object_attributes_hook)(void); /* Nonzero if this chip supports ldrex and strex */ #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7) +/* Nonzero if this chip supports LPAE. */ +#define TARGET_HAVE_LPAE \ + (arm_arch7 && ARM_FSET_HAS_CPU1 (insn_flags, FL_FOR_ARCH7VE)) + /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */ #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7) diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index fc7836fea7c..9e0978ef3d4 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -96,32 +96,62 @@ [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no")]) -;; Note that ldrd and vldr are *not* guaranteed to be single-copy atomic, -;; even for a 64-bit aligned address. Instead we use a ldrexd unparied -;; with a store. +;; An LDRD instruction usable by the atomic_loaddi expander on LPAE targets + +(define_insn "arm_atomic_loaddi2_ldrd" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec_volatile:DI + [(match_operand:DI 1 "arm_sync_memory_operand" "Q")] + VUNSPEC_LDRD_ATOMIC))] + "ARM_DOUBLEWORD_ALIGN && TARGET_HAVE_LPAE" + "ldrd%?\t%0, %H0, %C1" + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) + +;; There are three ways to expand this depending on the architecture +;; features available. As for the barriers, a load needs a barrier +;; after it on all non-relaxed memory models except when the load +;; has acquire semantics (for ARMv8-A). + (define_expand "atomic_loaddi" [(match_operand:DI 0 "s_register_operand") ;; val out (match_operand:DI 1 "mem_noofs_operand") ;; memory (match_operand:SI 2 "const_int_operand")] ;; model - "TARGET_HAVE_LDREXD && ARM_DOUBLEWORD_ALIGN" + "(TARGET_HAVE_LDREXD || TARGET_HAVE_LPAE || TARGET_HAVE_LDACQ) + && ARM_DOUBLEWORD_ALIGN" { - enum memmodel model = memmodel_from_int (INTVAL (operands[2])); - expand_mem_thread_fence (model); - emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); - if (is_mm_seq_cst (model)) + memmodel model = memmodel_from_int (INTVAL (operands[2])); + + /* For ARMv8-A we can use an LDAEXD to atomically load two 32-bit registers + when acquire or stronger semantics are needed. When the relaxed model is + used this can be relaxed to a normal LDRD. */ + if (TARGET_HAVE_LDACQ) + { + if (is_mm_relaxed (model)) + emit_insn (gen_arm_atomic_loaddi2_ldrd (operands[0], operands[1])); + else + emit_insn (gen_arm_load_acquire_exclusivedi (operands[0], operands[1])); + + DONE; + } + + /* On LPAE targets LDRD and STRD accesses to 64-bit aligned + locations are 64-bit single-copy atomic. We still need barriers in the + appropriate places to implement the ordering constraints. */ + if (TARGET_HAVE_LPAE) + emit_insn (gen_arm_atomic_loaddi2_ldrd (operands[0], operands[1])); + else + emit_insn (gen_arm_load_exclusivedi (operands[0], operands[1])); + + + /* All non-relaxed models need a barrier after the load when load-acquire + instructions are not available. */ + if (!is_mm_relaxed (model)) expand_mem_thread_fence (model); + DONE; }) -(define_insn "atomic_loaddi_1" - [(set (match_operand:DI 0 "s_register_operand" "=r") - (unspec:DI [(match_operand:DI 1 "mem_noofs_operand" "Ua")] - UNSPEC_LL))] - "TARGET_HAVE_LDREXD && ARM_DOUBLEWORD_ALIGN" - "ldrexd%?\t%0, %H0, %C1" - [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) - (define_expand "atomic_compare_and_swap<mode>" [(match_operand:SI 0 "s_register_operand" "") ;; bool out (match_operand:QHSD 1 "s_register_operand" "") ;; val out diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index ad8a0041648..dd965c3352f 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -138,6 +138,7 @@ VUNSPEC_ATOMIC_XCHG ; Represent an atomic exchange. VUNSPEC_ATOMIC_OP ; Represent an atomic operation. VUNSPEC_LL ; Represent a load-register-exclusive. + VUNSPEC_LDRD_ATOMIC ; Represent an LDRD used as an atomic DImode load. VUNSPEC_SC ; Represent a store-register-exclusive. VUNSPEC_LAX ; Represent a load-register-acquire-exclusive. VUNSPEC_SLX ; Represent a store-register-release-exclusive. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index e61d2c55ea5..5ab999db6a7 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -24621,9 +24621,10 @@ alg_usable_p (enum stringop_alg alg, bool memset) static enum stringop_alg decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, unsigned HOST_WIDE_INT min_size, unsigned HOST_WIDE_INT max_size, - bool memset, bool zero_memset, int *dynamic_check, bool *noalign) + bool memset, bool zero_memset, int *dynamic_check, bool *noalign, + bool recur) { - const struct stringop_algs * algs; + const struct stringop_algs *algs; bool optimize_for_speed; int max = 0; const struct processor_costs *cost; @@ -24657,7 +24658,7 @@ decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, any_alg_usable_p |= usable; if (candidate != libcall && candidate && usable) - max = algs->size[i].max; + max = algs->size[i].max; } /* If expected size is not known but max size is small enough @@ -24667,7 +24668,7 @@ decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, && expected_size == -1) expected_size = min_size / 2 + max_size / 2; - /* If user specified the algorithm, honnor it if possible. */ + /* If user specified the algorithm, honor it if possible. */ if (ix86_stringop_alg != no_stringop && alg_usable_p (ix86_stringop_alg, memset)) return ix86_stringop_alg; @@ -24742,21 +24743,20 @@ decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, || !alg_usable_p (algs->unknown_size, memset))) { enum stringop_alg alg; + HOST_WIDE_INT new_expected_size = (max > 0 ? max : 4096) / 2; - /* If there aren't any usable algorithms, then recursing on - smaller sizes isn't going to find anything. Just return the - simple byte-at-a-time copy loop. */ - if (!any_alg_usable_p) - { - /* Pick something reasonable. */ - if (TARGET_INLINE_STRINGOPS_DYNAMICALLY) - *dynamic_check = 128; - return loop_1_byte; - } - if (max <= 0) - max = 4096; - alg = decide_alg (count, max / 2, min_size, max_size, memset, - zero_memset, dynamic_check, noalign); + /* If there aren't any usable algorithms or if recursing already, + then recursing on smaller sizes or same size isn't going to + find anything. Just return the simple byte-at-a-time copy loop. */ + if (!any_alg_usable_p || recur) + { + /* Pick something reasonable. */ + if (TARGET_INLINE_STRINGOPS_DYNAMICALLY && !recur) + *dynamic_check = 128; + return loop_1_byte; + } + alg = decide_alg (count, new_expected_size, min_size, max_size, memset, + zero_memset, dynamic_check, noalign, true); gcc_assert (*dynamic_check == -1); if (TARGET_INLINE_STRINGOPS_DYNAMICALLY) *dynamic_check = max; @@ -25012,7 +25012,7 @@ ix86_expand_set_or_movmem (rtx dst, rtx src, rtx count_exp, rtx val_exp, alg = decide_alg (count, expected_size, min_size, probable_max_size, issetmem, issetmem && val_exp == const0_rtx, - &dynamic_check, &noalign); + &dynamic_check, &noalign, false); if (alg == libcall) return false; gcc_assert (alg != no_stringop); @@ -30804,6 +30804,14 @@ def_builtin (HOST_WIDE_INT mask, const char *name, { ix86_builtins_isa[(int) code].isa = mask; + /* OPTION_MASK_ISA_AVX512VL has special meaning. Despite of generic case, + where any bit set means that built-in is enable, this bit must be *and-ed* + with another one. E.g.: OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL + means that *both* cpuid bits must be set for the built-in to be available. + Handle this here. */ + if (mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512VL) + mask &= ~OPTION_MASK_ISA_AVX512VL; + mask &= ~OPTION_MASK_ISA_64BIT; if (mask == 0 || (mask & ix86_isa_flags) != 0 @@ -32465,9 +32473,9 @@ static const struct builtin_description bdesc_args[] = { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16hi_mask, "__builtin_ia32_permvarhi256_mask", IX86_BUILTIN_VPERMVARHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI }, { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv8hi_mask, "__builtin_ia32_permvarhi128_mask", IX86_BUILTIN_VPERMVARHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI }, { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_mask, "__builtin_ia32_vpermt2varhi256_mask", IX86_BUILTIN_VPERMT2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI }, - { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_maskz, "__builtin_ia32_vpermt2varhi256_maskz", IX86_BUILTIN_VPERMT2VARHI256_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI }, + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_maskz, "__builtin_ia32_vpermt2varhi256_maskz", IX86_BUILTIN_VPERMT2VARHI256_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI }, { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_mask, "__builtin_ia32_vpermt2varhi128_mask", IX86_BUILTIN_VPERMT2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI }, - { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_maskz, "__builtin_ia32_vpermt2varhi128_maskz", IX86_BUILTIN_VPERMT2VARHI128_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI }, + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_maskz, "__builtin_ia32_vpermt2varhi128_maskz", IX86_BUILTIN_VPERMT2VARHI128_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI }, { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16hi3_mask, "__builtin_ia32_vpermi2varhi256_mask", IX86_BUILTIN_VPERMI2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI }, { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8hi3_mask, "__builtin_ia32_vpermi2varhi128_mask", IX86_BUILTIN_VPERMI2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI }, { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4df_mask, "__builtin_ia32_rcp14pd256_mask", IX86_BUILTIN_RCP14PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI }, @@ -33182,9 +33190,9 @@ static const struct builtin_description bdesc_args[] = { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv32qi_mask, "__builtin_ia32_permvarqi256_mask", IX86_BUILTIN_VPERMVARQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI }, { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16qi_mask, "__builtin_ia32_permvarqi128_mask", IX86_BUILTIN_VPERMVARQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI }, { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_mask, "__builtin_ia32_vpermt2varqi256_mask", IX86_BUILTIN_VPERMT2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI }, - { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_maskz, "__builtin_ia32_vpermt2varqi256_maskz", IX86_BUILTIN_VPERMT2VARQI256_MASKZ, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI }, + { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_maskz, "__builtin_ia32_vpermt2varqi256_maskz", IX86_BUILTIN_VPERMT2VARQI256_MASKZ, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI }, { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_mask, "__builtin_ia32_vpermt2varqi128_mask", IX86_BUILTIN_VPERMT2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI }, - { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_maskz, "__builtin_ia32_vpermt2varqi128_maskz", IX86_BUILTIN_VPERMT2VARQI128_MASKZ, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI }, + { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_maskz, "__builtin_ia32_vpermt2varqi128_maskz", IX86_BUILTIN_VPERMT2VARQI128_MASKZ, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI }, { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv32qi3_mask, "__builtin_ia32_vpermi2varqi256_mask", IX86_BUILTIN_VPERMI2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI }, { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16qi3_mask, "__builtin_ia32_vpermi2varqi128_mask", IX86_BUILTIN_VPERMI2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI }, }; @@ -45211,7 +45219,12 @@ half: tmp = gen_reg_rtx (mode); emit_insn (gen_rtx_SET (VOIDmode, tmp, gen_rtx_VEC_DUPLICATE (mode, val))); - emit_insn (gen_blendm (target, tmp, target, + /* The avx512*_blendm<mode> expanders have different operand order + from VEC_MERGE. In VEC_MERGE, the first input operand is used for + elements where the mask is set and second input operand otherwise, + in {sse,avx}*_*blend* the first input operand is used for elements + where the mask is clear and second input operand otherwise. */ + emit_insn (gen_blendm (target, target, tmp, force_reg (mmode, gen_int_mode (1 << elt, mmode)))); } @@ -50028,16 +50041,24 @@ ix86_expand_vecop_qihi (enum rtx_code code, rtx dest, rtx op1, rtx op2) { /* For SSE2, we used an full interleave, so the desired results are in the even elements. */ - for (i = 0; i < 64; ++i) + for (i = 0; i < d.nelt; ++i) d.perm[i] = i * 2; } else { /* For AVX, the interleave used above was not cross-lane. So the extraction is evens but with the second and third quarter swapped. - Happily, that is even one insn shorter than even extraction. */ - for (i = 0; i < 64; ++i) - d.perm[i] = i * 2 + ((i & 24) == 8 ? 16 : (i & 24) == 16 ? -16 : 0); + Happily, that is even one insn shorter than even extraction. + For AVX512BW we have 4 lanes. We extract evens from within a lane, + always first from the first and then from the second source operand, + the index bits above the low 4 bits remains the same. + Thus, for d.nelt == 32 we want permutation + 0,2,4,..14, 32,34,36,..46, 16,18,20,..30, 48,50,52,..62 + and for d.nelt == 64 we want permutation + 0,2,4,..14, 64,66,68,..78, 16,18,20,..30, 80,82,84,..94, + 32,34,36,..46, 96,98,100,..110, 48,50,52,..62, 112,114,116,..126. */ + for (i = 0; i < d.nelt; ++i) + d.perm[i] = ((i * 2) & 14) + ((i & 8) ? d.nelt : 0) + (i & ~15); } ok = ix86_expand_vec_perm_const_1 (&d); diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 89e8161645e..87619db4dbc 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -1866,7 +1866,7 @@ [(set (match_operand:XI 0 "nonimmediate_operand") (match_operand:XI 1 "general_operand"))] "TARGET_AVX512F" - "ix86_expand_move (XImode, operands); DONE;") + "ix86_expand_vector_move (XImode, operands); DONE;") ;; Reload patterns to support multi-word load/store ;; with non-offsetable address. @@ -1906,11 +1906,11 @@ [(set (match_operand:OI 0 "nonimmediate_operand") (match_operand:OI 1 "general_operand"))] "TARGET_AVX" - "ix86_expand_move (OImode, operands); DONE;") + "ix86_expand_vector_move (OImode, operands); DONE;") (define_expand "movti" [(set (match_operand:TI 0 "nonimmediate_operand") - (match_operand:TI 1 "nonimmediate_operand"))] + (match_operand:TI 1 "general_operand"))] "TARGET_64BIT || TARGET_SSE" { if (TARGET_64BIT) @@ -2416,7 +2416,7 @@ (define_insn "kmovw" [(set (match_operand:HI 0 "nonimmediate_operand" "=k,k") (unspec:HI - [(match_operand:HI 1 "nonimmediate_operand" "rm,k")] + [(match_operand:HI 1 "nonimmediate_operand" "r,km")] UNSPEC_KMOV))] "!(MEM_P (operands[0]) && MEM_P (operands[1])) && TARGET_AVX512F" "@ @@ -2428,8 +2428,8 @@ (define_insn "*movhi_internal" - [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r ,r ,m ,k,k,rm") - (match_operand:HI 1 "general_operand" "r ,rn,rm,rn,rm,k,k"))] + [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r ,r ,m ,k,k, r,m") + (match_operand:HI 1 "general_operand" "r ,rn,rm,rn,r,km,k,k"))] "!(MEM_P (operands[0]) && MEM_P (operands[1]))" { switch (get_attr_type (insn)) @@ -2443,7 +2443,8 @@ switch (which_alternative) { case 4: return "kmovw\t{%k1, %0|%0, %k1}"; - case 5: return "kmovw\t{%1, %0|%0, %1}"; + case 5: /* FALLTHRU */ + case 7: return "kmovw\t{%1, %0|%0, %1}"; case 6: return "kmovw\t{%1, %k0|%k0, %1}"; default: gcc_unreachable (); } @@ -2456,7 +2457,7 @@ } } [(set (attr "type") - (cond [(eq_attr "alternative" "4,5,6") + (cond [(eq_attr "alternative" "4,5,6,7") (const_string "mskmov") (match_test "optimize_function_for_size_p (cfun)") (const_string "imov") @@ -2473,7 +2474,7 @@ ] (const_string "imov"))) (set (attr "prefix") - (if_then_else (eq_attr "alternative" "4,5,6") + (if_then_else (eq_attr "alternative" "4,5,6,7") (const_string "vex") (const_string "orig"))) (set (attr "mode") @@ -7998,10 +7999,10 @@ (clobber (reg:CC FLAGS_REG))] "TARGET_AVX512F && !TARGET_BMI && reload_completed" [(set (match_dup 0) - (not:HI (match_dup 0))) + (not:SWI12 (match_dup 0))) (parallel [(set (match_dup 0) - (and:HI (match_dup 0) - (match_dup 1))) + (and:SWI12 (match_dup 0) + (match_dup 1))) (clobber (reg:CC FLAGS_REG))])]) ;; Turn *anddi_1 into *andsi_1_zext if possible. diff --git a/gcc/config/i386/sol2.h b/gcc/config/i386/sol2.h index f213388413a..0ed4b68c15b 100644 --- a/gcc/config/i386/sol2.h +++ b/gcc/config/i386/sol2.h @@ -137,8 +137,9 @@ along with GCC; see the file COPYING3. If not see /* The Solaris assembler wants a .local for non-exported aliases. */ #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ do { \ - const char *declname = \ - IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (DECL)); \ + tree id = DECL_ASSEMBLER_NAME (DECL); \ + ultimate_transparent_alias_target (&id); \ + const char *declname = IDENTIFIER_POINTER (id); \ ASM_OUTPUT_DEF ((FILE), declname, \ IDENTIFIER_POINTER (TARGET)); \ if (! TREE_PUBLIC (DECL)) \ diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index fc58030003d..5692a11aa29 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -483,8 +483,9 @@ [(V16SF "f") (V16SI "i") (V8DF "f") (V8DI "i") (V8SF "f") (V8SI "i") (V4DF "f") (V4DI "i") (V4SF "f") (V4SI "i") (V2DF "f") (V2DI "i") - (V32QI "i") (V16HI "u") (V16QI "i") (V8HI "i") - (V64QI "i") (V1TI "i") (V2TI "i")]) + (V32HI "i") (V16HI "i") (V8HI "i") + (V64QI "i") (V32QI "i") (V16QI "i") + (V4TI "i") (V2TI "i") (V1TI "i")]) (define_mode_attr ssequartermode [(V16SF "V4SF") (V8DF "V2DF") (V16SI "V4SI") (V8DI "V2DI")]) @@ -677,7 +678,8 @@ ;; Pointer size override for scalar modes (Intel asm dialect) (define_mode_attr iptr - [(V32QI "b") (V16HI "w") (V8SI "k") (V4DI "q") + [(V64QI "b") (V32HI "w") (V16SI "k") (V8DI "q") + (V32QI "b") (V16HI "w") (V8SI "k") (V4DI "q") (V16QI "b") (V8HI "w") (V4SI "k") (V2DI "q") (V8SF "k") (V4DF "q") (V4SF "k") (V2DF "q") @@ -704,7 +706,8 @@ (V64QI "8") (V32QI "8") (V16QI "8") (V32HI "16") (V16HI "16") (V8HI "16") (V16SI "32") (V8SI "32") (V4SI "32") - (V16SF "32") (V8DF "64")]) + (V16SF "32") (V8SF "32") (V4SF "32") + (V8DF "64") (V4DF "64") (V2DF "64")]) ;; SSE prefix for integer vector modes (define_mode_attr sseintprefix @@ -10824,45 +10827,46 @@ case MODE_XI: gcc_assert (TARGET_AVX512F); case MODE_OI: - gcc_assert (TARGET_AVX2 || TARGET_AVX512VL); + gcc_assert (TARGET_AVX2); case MODE_TI: - gcc_assert (TARGET_SSE2 || TARGET_AVX512VL); + gcc_assert (TARGET_SSE2); switch (<MODE>mode) - { - case V16SImode: - case V8DImode: - if (TARGET_AVX512F) - { - tmp = "pandn<ssemodesuffix>"; - break; - } - case V8SImode: - case V4DImode: - case V4SImode: - case V2DImode: - if (TARGET_AVX512VL) - { - tmp = "pandn<ssemodesuffix>"; - break; - } - default: - tmp = TARGET_AVX512VL ? "pandnq" : "pandn"; - } + { + case V64QImode: + case V32HImode: + /* There is no vpandnb or vpandnw instruction, nor vpandn for + 512-bit vectors. Use vpandnq instead. */ + tmp = "pandnq"; + break; + case V16SImode: + case V8DImode: + tmp = "pandn<ssemodesuffix>"; + break; + case V8SImode: + case V4DImode: + case V4SImode: + case V2DImode: + tmp = TARGET_AVX512VL ? "pandn<ssemodesuffix>" : "pandn"; + break; + default: + tmp = TARGET_AVX512VL ? "pandnq" : "pandn"; + break; + } break; - case MODE_V16SF: + case MODE_V16SF: gcc_assert (TARGET_AVX512F); - case MODE_V8SF: + case MODE_V8SF: gcc_assert (TARGET_AVX); - case MODE_V4SF: + case MODE_V4SF: gcc_assert (TARGET_SSE); tmp = "andnps"; break; - default: + default: gcc_unreachable (); - } + } switch (which_alternative) { @@ -10870,7 +10874,7 @@ ops = "%s\t{%%2, %%0|%%0, %%2}"; break; case 1: - ops = "v%s\t{%%2, %%1, %%0<mask_operand3_1>|%%0<mask_operand3_1>, %%1, %%2}"; + ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; break; default: gcc_unreachable (); @@ -10920,21 +10924,6 @@ (set_attr "prefix" "evex") (set_attr "mode" "<sseinsnmode>")]) -(define_insn "*andnot<mode>3_mask" - [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") - (vec_merge:VI12_AVX512VL - (and:VI12_AVX512VL - (not:VI12_AVX512VL - (match_operand:VI12_AVX512VL 1 "register_operand" "v")) - (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")) - (match_operand:VI12_AVX512VL 3 "vector_move_operand" "0C") - (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))] - "TARGET_AVX512BW" - "vpandn<ssemodesuffix>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}"; - [(set_attr "type" "sselog") - (set_attr "prefix" "evex") - (set_attr "mode" "<sseinsnmode>")]) - (define_expand "<code><mode>3" [(set (match_operand:VI 0 "register_operand") (any_logic:VI @@ -16655,8 +16644,9 @@ (match_operand:VI_AVX512BW 1 "nonimmediate_operand" "v,m") (parallel [(const_int 0)]))))] "TARGET_AVX512F" - "vpbroadcast<ssemodesuffix>\t{%1, %0|%0, %<iptr>1} - vpbroadcast<ssemodesuffix>\t{%x1, %0|%0, %x1}" + "@ + vpbroadcast<ssemodesuffix>\t{%x1, %0|%0, %x1} + vpbroadcast<ssemodesuffix>\t{%x1, %0|%0, %<iptr>1}" [(set_attr "type" "ssemov") (set_attr "prefix" "evex") (set_attr "mode" "<sseinsnmode>")]) @@ -16811,7 +16801,8 @@ v<sseintprefix>broadcast<bcstscalarsuff>\t{%1, %0|%0, %1} v<sseintprefix>broadcast<bcstscalarsuff>\t{%x1, %0|%0, %x1} #" - [(set_attr "type" "ssemov") + [(set_attr "isa" "*,*,noavx512vl") + (set_attr "type" "ssemov") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_evex") (set_attr "mode" "<sseinsnmode>")]) diff --git a/gcc/config/pa/constraints.md b/gcc/config/pa/constraints.md index fed0b58af81..296337c29d7 100644 --- a/gcc/config/pa/constraints.md +++ b/gcc/config/pa/constraints.md @@ -106,7 +106,7 @@ (and (match_code "mem") (match_test "IS_LO_SUM_DLT_ADDR_P (XEXP (op, 0))"))) -(define_memory_constraint "Q" +(define_constraint "Q" "A memory operand that can be used as the destination operand of an integer store, or the source operand of an integer load. That is any memory operand that isn't a symbolic, indexed or lo_sum memory @@ -122,7 +122,7 @@ (and (match_code "mem") (match_test "IS_INDEX_ADDR_P (XEXP (op, 0))"))) -(define_memory_constraint "T" +(define_constraint "T" "A memory operand for floating-point loads and stores." (match_test "floating_point_store_memory_operand (op, mode)")) diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index fde81bf3e78..11a84fcf8fe 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -1229,9 +1229,10 @@ (define_insn "bswapdi2" [(set (match_operand:DI 0 "register_operand" "=&r") - (bswap:DI (match_operand:DI 1 "register_operand" "+r")))] + (bswap:DI (match_operand:DI 1 "register_operand" "r"))) + (clobber (match_scratch:DI 2 "=r"))] "TARGET_64BIT" - "permh,3210 %1,%1\;hshl %1,8,%0\;hshr,u %1,8,%1\;or %0,%1,%0" + "permh,3210 %1,%2\;hshl %2,8,%0\;hshr,u %2,8,%2\;or %0,%2,%0" [(set_attr "type" "multi") (set_attr "length" "16")]) diff --git a/gcc/config/pa/predicates.md b/gcc/config/pa/predicates.md index fcf68462d4c..aa9c10460c8 100644 --- a/gcc/config/pa/predicates.md +++ b/gcc/config/pa/predicates.md @@ -301,6 +301,9 @@ if (reg_plus_base_memory_operand (op, mode)) { + if (reload_in_progress) + return true; + /* Extract CONST_INT operand. */ if (GET_CODE (op) == SUBREG) op = SUBREG_REG (op); @@ -335,6 +338,9 @@ if (reg_plus_base_memory_operand (op, mode)) { + if (reload_in_progress) + return true; + /* Extract CONST_INT operand. */ if (GET_CODE (op) == SUBREG) op = SUBREG_REG (op); diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index eb3ffbe73c5..98118450a4b 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -259,4 +259,4 @@ usually better to use @samp{m} or @samp{es} in @code{asm} statements)" (define_constraint "j" "Zero vector constant" - (match_test "op == const0_rtx || op == CONST0_RTX (GET_MODE (op))")) + (match_test "op == const0_rtx || op == CONST0_RTX (mode)")) diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 2a52c9cb488..978ed9ba1eb 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -441,13 +441,14 @@ && mode != DImode) return 1; + /* 0.0D is not all zero bits. */ + if (DECIMAL_FLOAT_MODE_P (mode)) + return 0; + /* The constant 0.0 is easy under VSX. */ if (TARGET_VSX && SCALAR_FLOAT_MODE_P (mode) && op == CONST0_RTX (mode)) return 1; - if (DECIMAL_FLOAT_MODE_P (mode)) - return 0; - /* If we are using V.4 style PIC, consider all constants to be hard. */ if (flag_pic && DEFAULT_ABI == ABI_V4) return 0; diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index 06afab3e3ce..fbb8e2d4eb8 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -231,7 +231,21 @@ rs6000_macro_to_expand (cpp_reader *pfile, const cpp_token *tok) else if (ident && (ident != C_CPP_HASHNODE (__vector_keyword))) { enum rid rid_code = (enum rid)(ident->rid_code); - if (ident->type == NT_MACRO) + enum node_type itype = ident->type; + /* If there is a function-like macro, check if it is going to be + invoked with or without arguments. Without following ( treat + it like non-macro, otherwise the following cpp_get_token eats + what should be preserved. */ + if (itype == NT_MACRO && cpp_fun_like_macro_p (ident)) + { + int idx2 = idx; + do + tok = cpp_peek_token (pfile, idx2++); + while (tok->type == CPP_PADDING); + if (tok->type != CPP_OPEN_PAREN) + itype = NT_VOID; + } + if (itype == NT_MACRO) { do (void) cpp_get_token (pfile); diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 00eef5ab066..89ed76576b0 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -3701,7 +3701,8 @@ rs6000_option_override_internal (bool global_init_p) else if (TARGET_ALLOW_MOVMISALIGN && !TARGET_VSX) { - if (TARGET_ALLOW_MOVMISALIGN > 0) + if (TARGET_ALLOW_MOVMISALIGN > 0 + && global_options_set.x_TARGET_ALLOW_MOVMISALIGN) error ("-mallow-movmisalign requires -mvsx"); TARGET_ALLOW_MOVMISALIGN = 0; diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 110944b66fa..7720e9c71c7 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -388,6 +388,14 @@ (SD "REAL_VALUE_TO_TARGET_DECIMAL32") (DD "REAL_VALUE_TO_TARGET_DECIMAL64")]) +; Whether 0.0 has an all-zero bit pattern +(define_mode_attr zero_fp [(SF "j") + (DF "j") + (TF "j") + (SD "wn") + (DD "wn") + (TD "wn")]) + ; Definitions for load to 32-bit fpr register (define_mode_attr f32_lr [(SF "f") (SD "wz")]) (define_mode_attr f32_lm [(SF "m") (SD "Z")]) @@ -8083,7 +8091,7 @@ (define_insn "mov<mode>_hardfloat" [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,<f32_vsx>,<f32_vsx>,!r,<f32_lr>,<f32_sm>,<f32_av>,Z,?<f32_dm>,?r,*c*l,!r,*h") - (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,<f32_vsx>,j,j,<f32_lm>,<f32_sr>,Z,<f32_av>,r,<f32_dm>,r,h,0"))] + (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,<f32_vsx>,<zero_fp>,<zero_fp>,<f32_lm>,<f32_sr>,Z,<f32_av>,r,<f32_dm>,r,h,0"))] "(gpc_reg_operand (operands[0], <MODE>mode) || gpc_reg_operand (operands[1], <MODE>mode)) && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)" @@ -8224,7 +8232,7 @@ (define_insn "*mov<mode>_hardfloat32" [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_vsx>,<f64_vsx>,!r,Y,r,!r") - (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,<f64_vsx>,j,j,r,Y,r"))] + (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r"))] "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && (gpc_reg_operand (operands[0], <MODE>mode) || gpc_reg_operand (operands[1], <MODE>mode))" @@ -8260,7 +8268,7 @@ ; List Y->r and r->Y before r->r for reload. (define_insn "*mov<mode>_hardfloat64" [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_vsx>,<f64_vsx>,!r,Y,r,!r,*c*l,!r,*h,r,wg,r,<f64_dm>") - (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,<f64_vsx>,j,j,r,Y,r,r,h,0,wg,r,<f64_dm>,r"))] + (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r,r,h,0,wg,r,<f64_dm>,r"))] "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && (gpc_reg_operand (operands[0], <MODE>mode) || gpc_reg_operand (operands[1], <MODE>mode))" @@ -8321,7 +8329,7 @@ (define_insn_and_split "*mov<mode>_64bit_dm" [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,ws,Y,r,r,r,wm") - (match_operand:FMOVE128 1 "input_operand" "d,m,d,j,r,jY,r,wm,r"))] + (match_operand:FMOVE128 1 "input_operand" "d,m,d,<zero_fp>,r,<zero_fp>Y,r,wm,r"))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && (<MODE>mode != TDmode || WORDS_BIG_ENDIAN) && (gpc_reg_operand (operands[0], <MODE>mode) @@ -8333,8 +8341,8 @@ [(set_attr "length" "8,8,8,8,12,12,8,8,8")]) (define_insn_and_split "*movtd_64bit_nodm" - [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,ws,Y,r,r") - (match_operand:TD 1 "input_operand" "d,m,d,j,r,jY,r"))] + [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r") + (match_operand:TD 1 "input_operand" "d,m,d,r,Y,r"))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN && (gpc_reg_operand (operands[0], TDmode) || gpc_reg_operand (operands[1], TDmode))" @@ -8342,11 +8350,11 @@ "&& reload_completed" [(pc)] { rs6000_split_multireg_move (operands[0], operands[1]); DONE; } - [(set_attr "length" "8,8,8,8,12,12,8")]) + [(set_attr "length" "8,8,8,12,12,8")]) (define_insn_and_split "*mov<mode>_32bit" [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,ws,Y,r,r") - (match_operand:FMOVE128 1 "input_operand" "d,m,d,j,r,jY,r"))] + (match_operand:FMOVE128 1 "input_operand" "d,m,d,<zero_fp>,r,<zero_fp>Y,r"))] "TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_POWERPC64 && (gpc_reg_operand (operands[0], <MODE>mode) || gpc_reg_operand (operands[1], <MODE>mode))" @@ -8731,38 +8739,28 @@ ;; value, since it is allocated in reload and not all of the flow information ;; is setup for it. We have two patterns to do the two moves between gprs and ;; fprs. There isn't a dependancy between the two, but we could potentially -;; schedule other instructions between the two instructions. TFmode is -;; currently limited to traditional FPR registers. If/when this is changed, we -;; will need to revist %L to make sure it works with VSX registers, or add an -;; %x version of %L. +;; schedule other instructions between the two instructions. (define_insn "p8_fmrgow_<mode>" [(set (match_operand:FMOVE64X 0 "register_operand" "=d") - (unspec:FMOVE64X [(match_operand:TF 1 "register_operand" "d")] + (unspec:FMOVE64X [ + (match_operand:DF 1 "register_operand" "d") + (match_operand:DF 2 "register_operand" "d")] UNSPEC_P8V_FMRGOW))] "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE" - "fmrgow %0,%1,%L1" + "fmrgow %0,%1,%2" [(set_attr "type" "vecperm")]) -(define_insn "p8_mtvsrwz_1" - [(set (match_operand:TF 0 "register_operand" "=d") - (unspec:TF [(match_operand:SI 1 "register_operand" "r")] +(define_insn "p8_mtvsrwz" + [(set (match_operand:DF 0 "register_operand" "=d") + (unspec:DF [(match_operand:SI 1 "register_operand" "r")] UNSPEC_P8V_MTVSRWZ))] "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE" "mtvsrwz %x0,%1" [(set_attr "type" "mftgpr")]) -(define_insn "p8_mtvsrwz_2" - [(set (match_operand:TF 0 "register_operand" "+d") - (unspec:TF [(match_dup 0) - (match_operand:SI 1 "register_operand" "r")] - UNSPEC_P8V_MTVSRWZ))] - "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE" - "mtvsrwz %L0,%1" - [(set_attr "type" "mftgpr")]) - (define_insn_and_split "reload_fpr_from_gpr<mode>" - [(set (match_operand:FMOVE64X 0 "register_operand" "=ws") + [(set (match_operand:FMOVE64X 0 "register_operand" "=d") (unspec:FMOVE64X [(match_operand:FMOVE64X 1 "register_operand" "r")] UNSPEC_P8V_RELOAD_FROM_GPR)) (clobber (match_operand:TF 2 "register_operand" "=d"))] @@ -8773,42 +8771,36 @@ { rtx dest = operands[0]; rtx src = operands[1]; - rtx tmp = operands[2]; + rtx tmp_hi = simplify_gen_subreg (DFmode, operands[2], TFmode, 0); + rtx tmp_lo = simplify_gen_subreg (DFmode, operands[2], TFmode, 8); rtx gpr_hi_reg = gen_highpart (SImode, src); rtx gpr_lo_reg = gen_lowpart (SImode, src); - emit_insn (gen_p8_mtvsrwz_1 (tmp, gpr_hi_reg)); - emit_insn (gen_p8_mtvsrwz_2 (tmp, gpr_lo_reg)); - emit_insn (gen_p8_fmrgow_<mode> (dest, tmp)); + emit_insn (gen_p8_mtvsrwz (tmp_hi, gpr_hi_reg)); + emit_insn (gen_p8_mtvsrwz (tmp_lo, gpr_lo_reg)); + emit_insn (gen_p8_fmrgow_<mode> (dest, tmp_hi, tmp_lo)); DONE; } [(set_attr "length" "12") (set_attr "type" "three")]) ;; Move 128 bit values from GPRs to VSX registers in 64-bit mode -(define_insn "p8_mtvsrd_1" - [(set (match_operand:TF 0 "register_operand" "=ws") - (unspec:TF [(match_operand:DI 1 "register_operand" "r")] - UNSPEC_P8V_MTVSRD))] - "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" - "mtvsrd %0,%1" - [(set_attr "type" "mftgpr")]) - -(define_insn "p8_mtvsrd_2" - [(set (match_operand:TF 0 "register_operand" "+ws") - (unspec:TF [(match_dup 0) - (match_operand:DI 1 "register_operand" "r")] +(define_insn "p8_mtvsrd_df" + [(set (match_operand:DF 0 "register_operand" "=wa") + (unspec:DF [(match_operand:DI 1 "register_operand" "r")] UNSPEC_P8V_MTVSRD))] "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" - "mtvsrd %L0,%1" + "mtvsrd %x0,%1" [(set_attr "type" "mftgpr")]) (define_insn "p8_xxpermdi_<mode>" [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa") - (unspec:FMOVE128_GPR [(match_operand:TF 1 "register_operand" "ws")] - UNSPEC_P8V_XXPERMDI))] + (unspec:FMOVE128_GPR [ + (match_operand:DF 1 "register_operand" "wa") + (match_operand:DF 2 "register_operand" "wa")] + UNSPEC_P8V_XXPERMDI))] "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" - "xxpermdi %x0,%1,%L1,0" + "xxpermdi %x0,%x1,%x2,0" [(set_attr "type" "vecperm")]) (define_insn_and_split "reload_vsx_from_gpr<mode>" @@ -8816,7 +8808,7 @@ (unspec:FMOVE128_GPR [(match_operand:FMOVE128_GPR 1 "register_operand" "r")] UNSPEC_P8V_RELOAD_FROM_GPR)) - (clobber (match_operand:TF 2 "register_operand" "=ws"))] + (clobber (match_operand:TF 2 "register_operand" "=wa"))] "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" "#" "&& reload_completed" @@ -8824,13 +8816,18 @@ { rtx dest = operands[0]; rtx src = operands[1]; - rtx tmp = operands[2]; + /* You might think that we could use op0 as one temp and a DF clobber + as op2, but you'd be wrong. Secondary reload move patterns don't + check for overlap of the clobber and the destination. */ + rtx tmp_hi = simplify_gen_subreg (DFmode, operands[2], TFmode, 0); + rtx tmp_lo = simplify_gen_subreg (DFmode, operands[2], TFmode, 8); rtx gpr_hi_reg = gen_highpart (DImode, src); rtx gpr_lo_reg = gen_lowpart (DImode, src); - emit_insn (gen_p8_mtvsrd_1 (tmp, gpr_hi_reg)); - emit_insn (gen_p8_mtvsrd_2 (tmp, gpr_lo_reg)); - emit_insn (gen_p8_xxpermdi_<mode> (dest, tmp)); + emit_insn (gen_p8_mtvsrd_df (tmp_hi, gpr_hi_reg)); + emit_insn (gen_p8_mtvsrd_df (tmp_lo, gpr_lo_reg)); + emit_insn (gen_p8_xxpermdi_<mode> (dest, tmp_hi, tmp_lo)); + DONE; } [(set_attr "length" "12") (set_attr "type" "three")]) @@ -8847,6 +8844,13 @@ ;; Move SFmode to a VSX from a GPR register. Because scalar floating point ;; type is stored internally as double precision in the VSX registers, we have ;; to convert it from the vector format. +(define_insn "p8_mtvsrd_sf" + [(set (match_operand:SF 0 "register_operand" "=wa") + (unspec:SF [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_P8V_MTVSRD))] + "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" + "mtvsrd %x0,%1" + [(set_attr "type" "mftgpr")]) (define_insn_and_split "reload_vsx_from_gprsf" [(set (match_operand:SF 0 "register_operand" "=wa") @@ -8861,16 +8865,12 @@ rtx op0 = operands[0]; rtx op1 = operands[1]; rtx op2 = operands[2]; - /* Also use the destination register to hold the unconverted DImode value. - This is conceptually a separate value from OP0, so we use gen_rtx_REG - rather than simplify_gen_subreg. */ - rtx op0_di = gen_rtx_REG (DImode, REGNO (op0)); rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0); /* Move SF value to upper 32-bits for xscvspdpn. */ emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32))); - emit_move_insn (op0_di, op2); - emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0_di)); + emit_insn (gen_p8_mtvsrd_sf (op0, op2)); + emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0)); DONE; } [(set_attr "length" "8") diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index d7a235e9137..f2abdcd846a 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -1354,7 +1354,7 @@ ;; Used by direct move to move a SFmode value from GPR to VSX register (define_insn "vsx_xscvspdpn_directmove" [(set (match_operand:SF 0 "vsx_register_operand" "=wa") - (unspec:SF [(match_operand:DI 1 "vsx_register_operand" "wa")] + (unspec:SF [(match_operand:SF 1 "vsx_register_operand" "wa")] UNSPEC_VSX_CVSPDPN))] "TARGET_XSCVSPDPN" "xscvspdpn %x0,%x1" diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md index 826e2f3a07c..f655387737d 100644 --- a/gcc/config/sh/sh.md +++ b/gcc/config/sh/sh.md @@ -2199,14 +2199,23 @@ [(set_attr "type" "arith")]) ;; Old reload might generate add insns directly (not through the expander) for -;; the memory address of complex insns like atomic insns when reloading. +;; address register calculations when reloading, in which case it won't try +;; the addsi_scr pattern. Because reload will sometimes try to validate +;; the generated insns and their constraints, this pattern must be +;; recognizable during and after reload. However, when reload generates +;; address register calculations for the stack pointer, we don't allow this +;; pattern. This will make reload prefer using indexed @(reg + reg) address +;; modes when the displacement of a @(disp + reg) doesn't fit. (define_insn_and_split "*addsi3" [(set (match_operand:SI 0 "arith_reg_dest" "=r") (plus:SI (match_operand:SI 1 "arith_reg_operand" "r") (match_operand:SI 2 "arith_or_int_operand" "rn")))] "TARGET_SH1 && !sh_lra_p () - && reload_completed - && !reg_overlap_mentioned_p (operands[0], operands[1])" + && (reload_completed || reload_in_progress) + && !reg_overlap_mentioned_p (operands[0], operands[1]) + && (!reload_in_progress + || ((!REG_P (operands[1]) || REGNO (operands[1]) != SP_REG) + && (!REG_P (operands[2]) || REGNO (operands[2]) != SP_REG)))" "#" "&& 1" [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))] diff --git a/gcc/config/sol2.c b/gcc/config/sol2.c index d256776a980..cdc133bab0c 100644 --- a/gcc/config/sol2.c +++ b/gcc/config/sol2.c @@ -155,8 +155,11 @@ solaris_assemble_visibility (tree decl, int vis ATTRIBUTE_UNUSED) }; const char *name, *type; + tree id = DECL_ASSEMBLER_NAME (decl); - name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); + while (IDENTIFIER_TRANSPARENT_ALIAS (id)) + id = TREE_CHAIN (id); + name = IDENTIFIER_POINTER (id); type = visibility_types[vis]; fprintf (asm_out_file, "\t.%s\t", type); diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 73ea50e3768..646862f013b 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,48 @@ +2016-04-06 Richard Biener <rguenther@suse.de> + + Backport from mainline + 2016-03-31 Richard Biener <rguenther@suse.de> + + PR c++/70430 + * typeck.c (cp_build_binary_op): Fix operand order of vector + conditional in truth op handling. + +2016-03-31 Nathan Sidwell <nathan@acm.org> + + PR c++/70393 + * constexpr.c (cxx_eval_store_expression): Keep CONSTRUCTOR + elements in field order. + +2016-03-30 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2016-03-17 Jakub Jelinek <jakub@redhat.com> + + PR c++/70272 + * decl.c (begin_destructor_body): Don't insert clobber if + is_empty_class (current_class_type). + + 2016-02-19 Jakub Jelinek <jakub@redhat.com> + + PR c++/67767 + * parser.c (cp_parser_std_attribute_spec_seq): Don't assume + attr_spec is always single element chain, chain all the attributes + properly together in the right order. + +2016-03-21 Marek Polacek <polacek@redhat.com> + + Backported from mainline + 2016-03-15 Marek Polacek <polacek@redhat.com> + + PR c++/70209 + * tree.c (strip_typedefs): Call strip_typedefs again on the + DECL_ORIGINAL_TYPE result. + +2016-03-18 Jason Merrill <jason@redhat.com> + + PR c++/70139 + * constexpr.c (cxx_eval_call_expression): Don't shortcut trivial copy. + 2016-03-05 Jason Merrill <jason@redhat.com> PR c++/67364 diff --git a/gcc/cp/constexpr.c b/gcc/cp/constexpr.c index 49c869b2a92..390cc5a3b14 100644 --- a/gcc/cp/constexpr.c +++ b/gcc/cp/constexpr.c @@ -1242,21 +1242,6 @@ cxx_eval_call_expression (const constexpr_ctx *ctx, tree t, return t; } - /* Shortcut trivial constructor/op=. */ - if (trivial_fn_p (fun)) - { - if (call_expr_nargs (t) == 2) - { - tree arg = convert_from_reference (get_nth_callarg (t, 1)); - return cxx_eval_constant_expression (ctx, arg, - lval, non_constant_p, - overflow_p); - } - else if (TREE_CODE (t) == AGGR_INIT_EXPR - && AGGR_INIT_ZERO_FIRST (t)) - return build_zero_init (DECL_CONTEXT (fun), NULL_TREE, false); - } - /* We can't defer instantiating the function any longer. */ if (!DECL_INITIAL (fun) && DECL_TEMPLOID_INSTANTIATION (fun)) @@ -2867,16 +2852,39 @@ cxx_eval_store_expression (const constexpr_ctx *ctx, tree t, else { gcc_assert (TREE_CODE (index) == FIELD_DECL); - for (unsigned HOST_WIDE_INT idx = 0; + + /* We must keep the CONSTRUCTOR's ELTS in FIELD order. + Usually we meet initializers in that order, but it is + possible for base types to be placed not in program + order. */ + tree fields = TYPE_FIELDS (DECL_CONTEXT (index)); + unsigned HOST_WIDE_INT idx; + + for (idx = 0; vec_safe_iterate (CONSTRUCTOR_ELTS (*valp), idx, &cep); idx++) - if (index == cep->index) - break; - if (!cep) { - constructor_elt ce = { index, NULL_TREE }; - cep = vec_safe_push (CONSTRUCTOR_ELTS (*valp), ce); + if (index == cep->index) + goto found; + + /* The field we're initializing must be on the field + list. Look to see if it is present before the + field the current ELT initializes. */ + for (; fields != cep->index; fields = DECL_CHAIN (fields)) + if (index == fields) + goto insert; } + + /* We fell off the end of the CONSTRUCTOR, so insert a new + entry at the end. */ + insert: + { + constructor_elt ce = { index, NULL_TREE }; + + vec_safe_insert (CONSTRUCTOR_ELTS (*valp), idx, ce); + cep = CONSTRUCTOR_ELT (*valp, idx); + } + found:; } valp = &cep->value; } diff --git a/gcc/cp/decl.c b/gcc/cp/decl.c index 3c0c9732e97..c9e87ef7760 100644 --- a/gcc/cp/decl.c +++ b/gcc/cp/decl.c @@ -13938,7 +13938,9 @@ begin_destructor_body (void) initialize_vtbl_ptrs (current_class_ptr); finish_compound_stmt (compound_stmt); - if (flag_lifetime_dse) + if (flag_lifetime_dse + /* Clobbering an empty base is harmful if it overlays real data. */ + && !is_empty_class (current_class_type)) { /* Insert a cleanup to let the back end know that the object is dead when we exit the destructor, either normally or via exception. */ diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c index fc5090e2415..e92fff78a8f 100644 --- a/gcc/cp/parser.c +++ b/gcc/cp/parser.c @@ -22645,7 +22645,8 @@ cp_parser_std_attribute_spec (cp_parser *parser) static tree cp_parser_std_attribute_spec_seq (cp_parser *parser) { - tree attr_specs = NULL; + tree attr_specs = NULL_TREE; + tree attr_last = NULL_TREE; while (true) { @@ -22655,11 +22656,13 @@ cp_parser_std_attribute_spec_seq (cp_parser *parser) if (attr_spec == error_mark_node) return error_mark_node; - TREE_CHAIN (attr_spec) = attr_specs; - attr_specs = attr_spec; + if (attr_last) + TREE_CHAIN (attr_last) = attr_spec; + else + attr_specs = attr_last = attr_spec; + attr_last = tree_last (attr_last); } - attr_specs = nreverse (attr_specs); return attr_specs; } diff --git a/gcc/cp/tree.c b/gcc/cp/tree.c index 5f1735a942f..4a7008b5a23 100644 --- a/gcc/cp/tree.c +++ b/gcc/cp/tree.c @@ -1368,9 +1368,12 @@ strip_typedefs (tree t) if (!result) { if (typedef_variant_p (t)) - /* Explicitly get the underlying type, as TYPE_MAIN_VARIANT doesn't - strip typedefs with attributes. */ - result = TYPE_MAIN_VARIANT (DECL_ORIGINAL_TYPE (TYPE_NAME (t))); + { + /* Explicitly get the underlying type, as TYPE_MAIN_VARIANT doesn't + strip typedefs with attributes. */ + result = TYPE_MAIN_VARIANT (DECL_ORIGINAL_TYPE (TYPE_NAME (t))); + result = strip_typedefs (result); + } else result = TYPE_MAIN_VARIANT (t); } diff --git a/gcc/cp/typeck.c b/gcc/cp/typeck.c index e79c71e2081..9e438c9297f 100644 --- a/gcc/cp/typeck.c +++ b/gcc/cp/typeck.c @@ -4233,7 +4233,7 @@ cp_build_binary_op (location_t location, { tree m1 = build_all_ones_cst (TREE_TYPE (op0)); tree z = build_zero_cst (TREE_TYPE (op0)); - op1 = build_conditional_expr (location, op1, z, m1, complain); + op1 = build_conditional_expr (location, op1, m1, z, complain); } else if (!COMPARISON_CLASS_P (op1)) op1 = cp_build_binary_op (EXPR_LOCATION (op1), NE_EXPR, op1, diff --git a/gcc/dse.c b/gcc/dse.c index 1e74f6b4e92..4e195c2a5c6 100644 --- a/gcc/dse.c +++ b/gcc/dse.c @@ -1665,10 +1665,9 @@ record_store (rtx body, bb_info_t bb_info) the value of store_info. If it is, set the rhs to NULL to keep it from being used to remove a load. */ { - if (canon_true_dependence (s_info->mem, - GET_MODE (s_info->mem), - s_info->mem_addr, - mem, mem_addr)) + if (canon_output_dependence (s_info->mem, true, + mem, GET_MODE (mem), + mem_addr)) { s_info->rhs = NULL; s_info->const_rhs = NULL; @@ -2616,6 +2615,8 @@ scan_insn (bb_info_t bb_info, rtx_insn *insn) active_local_stores = insn_info; } } + else + clear_rhs_from_active_local_stores (); } } else if (SIBLING_CALL_P (insn) && reload_completed) diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c index 9077a64b98e..e7e5788c4e3 100644 --- a/gcc/dwarf2out.c +++ b/gcc/dwarf2out.c @@ -19129,7 +19129,7 @@ gen_variable_die (tree decl, tree origin, dw_die_ref context_die) DW_TAG_common_block and DW_TAG_variable. */ loc = loc_list_from_tree (com_decl, 2, NULL); } - else if (DECL_EXTERNAL (decl)) + else if (DECL_EXTERNAL (decl_or_origin)) add_AT_flag (com_die, DW_AT_declaration, 1); if (want_pubnames ()) add_pubname_string (cnam, com_die); /* ??? needed? */ @@ -19144,9 +19144,9 @@ gen_variable_die (tree decl, tree origin, dw_die_ref context_die) remove_AT (com_die, DW_AT_declaration); } var_die = new_die (DW_TAG_variable, com_die, decl); - add_name_and_src_coords_attributes (var_die, decl); - add_type_attribute (var_die, TREE_TYPE (decl), decl_quals (decl), - context_die); + add_name_and_src_coords_attributes (var_die, decl_or_origin); + add_type_attribute (var_die, TREE_TYPE (decl_or_origin), + decl_quals (decl_or_origin), context_die); add_AT_flag (var_die, DW_AT_external, 1); if (loc) { @@ -19167,9 +19167,10 @@ gen_variable_die (tree decl, tree origin, dw_die_ref context_die) } add_AT_location_description (var_die, DW_AT_location, loc); } - else if (DECL_EXTERNAL (decl)) + else if (DECL_EXTERNAL (decl_or_origin)) add_AT_flag (var_die, DW_AT_declaration, 1); - equate_decl_number_to_die (decl, var_die); + if (decl) + equate_decl_number_to_die (decl, var_die); return; } diff --git a/gcc/fold-const.c b/gcc/fold-const.c index d9d5304bb44..540d4478684 100644 --- a/gcc/fold-const.c +++ b/gcc/fold-const.c @@ -6241,18 +6241,19 @@ extract_muldiv_1 (tree t, tree c, enum tree_code code, tree wide_type, bool overflow_p = false; bool overflow_mul_p; signop sign = TYPE_SIGN (ctype); - wide_int mul = wi::mul (op1, c, sign, &overflow_mul_p); + unsigned prec = TYPE_PRECISION (ctype); + wide_int mul = wi::mul (wide_int::from (op1, prec, + TYPE_SIGN (TREE_TYPE (op1))), + wide_int::from (c, prec, + TYPE_SIGN (TREE_TYPE (c))), + sign, &overflow_mul_p); overflow_p = TREE_OVERFLOW (c) | TREE_OVERFLOW (op1); if (overflow_mul_p && ((sign == UNSIGNED && tcode != MULT_EXPR) || sign == SIGNED)) overflow_p = true; if (!overflow_p) - { - mul = wide_int::from (mul, TYPE_PRECISION (ctype), - TYPE_SIGN (TREE_TYPE (op1))); - return fold_build2 (tcode, ctype, fold_convert (ctype, op0), - wide_int_to_tree (ctype, mul)); - } + return fold_build2 (tcode, ctype, fold_convert (ctype, op0), + wide_int_to_tree (ctype, mul)); } /* If these operations "cancel" each other, we have the main diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index 4112e1e7365..3e3d160f735 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,36 @@ +2016-04-04 Andre Vehreschild <vehre@gmx.de> + + PR fortran/66911 + * trans-stmt.c (gfc_trans_allocate): Get the deferred length of an + expression by converting the expression when the length is not set + in the symbol's ts. + +2016-04-04 Andre Vehreschild <vehre@gcc.gnu.org> + + PR fortran/65795 + * trans-array.c (gfc_array_allocate): When the array is a coarray, + do not nullyfing its allocatable components in array_allocate, because + the nullify missed the array ref and nullifies the wrong component. + Cosmetics. + +2016-03-28 Andre Vehreschild <vehre@gcc.gnu.org> + + PR fortran/70397 + * trans-expr.c (gfc_class_len_or_zero_get): Add function to return a + constant zero tree, when the class to get the _len component from is + not unlimited polymorphic. + (gfc_copy_class_to_class): Use the new function. + * trans.h: Added interface of new function gfc_class_len_or_zero_get. + +2016-03-28 Alessandro Fanfarillo <fanfarillo.gcc@gmail.com> + + Backport from trunk. + * trans-decl.c (gfc_build_builtin_function_decls): + caf_stop_numeric and caf_stop_str definition. + * trans-stmt.c (gfc_trans_stop): invoke external functions + for stop and stop_str when coarrays are used. + * trans.h: extern for new functions. + 2016-03-09 Paul Thomas <pault@gcc.gnu.org> Backport from trunk. diff --git a/gcc/fortran/trans-array.c b/gcc/fortran/trans-array.c index c2a248a7e2f..a40194f3284 100644 --- a/gcc/fortran/trans-array.c +++ b/gcc/fortran/trans-array.c @@ -5390,8 +5390,8 @@ gfc_array_allocate (gfc_se * se, gfc_expr * expr, tree status, tree errmsg, else gfc_add_expr_to_block (&se->pre, set_descriptor); - if ((expr->ts.type == BT_DERIVED) - && expr->ts.u.derived->attr.alloc_comp) + if (expr->ts.type == BT_DERIVED && expr->ts.u.derived->attr.alloc_comp + && !coarray) { tmp = gfc_nullify_alloc_comp (expr->ts.u.derived, se->expr, ref->u.ar.as->rank); diff --git a/gcc/fortran/trans-decl.c b/gcc/fortran/trans-decl.c index e046a5e8d5c..fb44fa1177f 100644 --- a/gcc/fortran/trans-decl.c +++ b/gcc/fortran/trans-decl.c @@ -155,6 +155,8 @@ tree gfor_fndecl_caf_sendget; tree gfor_fndecl_caf_sync_all; tree gfor_fndecl_caf_sync_memory; tree gfor_fndecl_caf_sync_images; +tree gfor_fndecl_caf_stop_str; +tree gfor_fndecl_caf_stop_numeric; tree gfor_fndecl_caf_error_stop; tree gfor_fndecl_caf_error_stop_str; tree gfor_fndecl_caf_atomic_def; @@ -3491,6 +3493,18 @@ gfc_build_builtin_function_decls (void) /* CAF's ERROR STOP doesn't return. */ TREE_THIS_VOLATILE (gfor_fndecl_caf_error_stop_str) = 1; + gfor_fndecl_caf_stop_numeric = gfc_build_library_function_decl_with_spec ( + get_identifier (PREFIX("caf_stop_numeric")), ".R.", + void_type_node, 1, gfc_int4_type_node); + /* CAF's STOP doesn't return. */ + TREE_THIS_VOLATILE (gfor_fndecl_caf_stop_numeric) = 1; + + gfor_fndecl_caf_stop_str = gfc_build_library_function_decl_with_spec ( + get_identifier (PREFIX("caf_stop_str")), ".R.", + void_type_node, 2, pchar_type_node, gfc_int4_type_node); + /* CAF's STOP doesn't return. */ + TREE_THIS_VOLATILE (gfor_fndecl_caf_stop_str) = 1; + gfor_fndecl_caf_atomic_def = gfc_build_library_function_decl_with_spec ( get_identifier (PREFIX("caf_atomic_define")), "R..RW", void_type_node, 7, pvoid_type_node, size_type_node, integer_type_node, diff --git a/gcc/fortran/trans-expr.c b/gcc/fortran/trans-expr.c index 1681d142871..642ce26d02b 100644 --- a/gcc/fortran/trans-expr.c +++ b/gcc/fortran/trans-expr.c @@ -173,6 +173,24 @@ gfc_class_len_get (tree decl) } +/* Try to get the _len component of a class. When the class is not unlimited + poly, i.e. no _len field exists, then return a zero node. */ + +tree +gfc_class_len_or_zero_get (tree decl) +{ + tree len; + if (POINTER_TYPE_P (TREE_TYPE (decl))) + decl = build_fold_indirect_ref_loc (input_location, decl); + len = gfc_advance_chain (TYPE_FIELDS (TREE_TYPE (decl)), + CLASS_LEN_FIELD); + return len != NULL_TREE ? fold_build3_loc (input_location, COMPONENT_REF, + TREE_TYPE (len), decl, len, + NULL_TREE) + : integer_zero_node; +} + + /* Get the specified FIELD from the VPTR. */ static tree @@ -250,6 +268,7 @@ gfc_vptr_size_get (tree vptr) #undef CLASS_DATA_FIELD #undef CLASS_VPTR_FIELD +#undef CLASS_LEN_FIELD #undef VTABLE_HASH_FIELD #undef VTABLE_SIZE_FIELD #undef VTABLE_EXTENDS_FIELD @@ -1070,7 +1089,7 @@ gfc_copy_class_to_class (tree from, tree to, tree nelems, bool unlimited) if (unlimited) { if (from_class_base != NULL_TREE) - from_len = gfc_class_len_get (from_class_base); + from_len = gfc_class_len_or_zero_get (from_class_base); else from_len = integer_zero_node; } diff --git a/gcc/fortran/trans-stmt.c b/gcc/fortran/trans-stmt.c index 7414c0d2338..25c2a0c60eb 100644 --- a/gcc/fortran/trans-stmt.c +++ b/gcc/fortran/trans-stmt.c @@ -647,7 +647,9 @@ gfc_trans_stop (gfc_code *code, bool error_stop) ? (flag_coarray == GFC_FCOARRAY_LIB ? gfor_fndecl_caf_error_stop_str : gfor_fndecl_error_stop_string) - : gfor_fndecl_stop_string, + : (flag_coarray == GFC_FCOARRAY_LIB + ? gfor_fndecl_caf_stop_str + : gfor_fndecl_stop_string), 2, build_int_cst (pchar_type_node, 0), tmp); } else if (code->expr1->ts.type == BT_INTEGER) @@ -658,7 +660,9 @@ gfc_trans_stop (gfc_code *code, bool error_stop) ? (flag_coarray == GFC_FCOARRAY_LIB ? gfor_fndecl_caf_error_stop : gfor_fndecl_error_stop_numeric) - : gfor_fndecl_stop_numeric_f08, 1, + : (flag_coarray == GFC_FCOARRAY_LIB + ? gfor_fndecl_caf_stop_numeric + : gfor_fndecl_stop_numeric_f08), 1, fold_convert (gfc_int4_type_node, se.expr)); } else @@ -669,7 +673,9 @@ gfc_trans_stop (gfc_code *code, bool error_stop) ? (flag_coarray == GFC_FCOARRAY_LIB ? gfor_fndecl_caf_error_stop_str : gfor_fndecl_error_stop_string) - : gfor_fndecl_stop_string, + : (flag_coarray == GFC_FCOARRAY_LIB + ? gfor_fndecl_caf_stop_str + : gfor_fndecl_stop_string), 2, se.expr, se.string_length); } @@ -5530,14 +5536,23 @@ gfc_trans_allocate (gfc_code * code) if (expr3_len == NULL_TREE && code->expr3->ts.type == BT_CHARACTER) { + gfc_init_se (&se, NULL); if (code->expr3->ts.u.cl && code->expr3->ts.u.cl->length) { - gfc_init_se (&se, NULL); gfc_conv_expr (&se, code->expr3->ts.u.cl->length); gfc_add_block_to_block (&block, &se.pre); expr3_len = gfc_evaluate_now (se.expr, &block); } + else + { + /* The string_length is not set in the symbol, which prevents + it being set in the ts. Deduce it by converting expr3. */ + gfc_conv_expr (&se, code->expr3); + gfc_add_block_to_block (&block, &se.pre); + gcc_assert (se.string_length); + expr3_len = gfc_evaluate_now (se.string_length, &block); + } gcc_assert (expr3_len); } /* For character arrays only the kind's size is needed, because diff --git a/gcc/fortran/trans.h b/gcc/fortran/trans.h index e6544f91878..7ad7daaa98f 100644 --- a/gcc/fortran/trans.h +++ b/gcc/fortran/trans.h @@ -356,6 +356,7 @@ tree gfc_class_set_static_fields (tree, tree, tree); tree gfc_class_data_get (tree); tree gfc_class_vptr_get (tree); tree gfc_class_len_get (tree); +tree gfc_class_len_or_zero_get (tree); gfc_expr * gfc_find_and_cut_at_last_class_ref (gfc_expr *); /* Get an accessor to the class' vtab's * field, when a class handle is available. */ @@ -750,6 +751,8 @@ extern GTY(()) tree gfor_fndecl_caf_sendget; extern GTY(()) tree gfor_fndecl_caf_sync_all; extern GTY(()) tree gfor_fndecl_caf_sync_memory; extern GTY(()) tree gfor_fndecl_caf_sync_images; +extern GTY(()) tree gfor_fndecl_caf_stop_numeric; +extern GTY(()) tree gfor_fndecl_caf_stop_str; extern GTY(()) tree gfor_fndecl_caf_error_stop; extern GTY(()) tree gfor_fndecl_caf_error_stop_str; extern GTY(()) tree gfor_fndecl_caf_atomic_def; diff --git a/gcc/gimple-expr.c b/gcc/gimple-expr.c index f555189a541..22cb5add1fe 100644 --- a/gcc/gimple-expr.c +++ b/gcc/gimple-expr.c @@ -570,8 +570,8 @@ create_tmp_reg_fn (struct function *fn, tree type, const char *prefix) *OP1_P, *OP2_P and *OP3_P respectively. */ void -extract_ops_from_tree_1 (tree expr, enum tree_code *subcode_p, tree *op1_p, - tree *op2_p, tree *op3_p) +extract_ops_from_tree (tree expr, enum tree_code *subcode_p, tree *op1_p, + tree *op2_p, tree *op3_p) { enum gimple_rhs_class grhs_class; diff --git a/gcc/gimple-expr.h b/gcc/gimple-expr.h index a50a90a959b..20815b098b8 100644 --- a/gcc/gimple-expr.h +++ b/gcc/gimple-expr.h @@ -36,8 +36,8 @@ extern tree create_tmp_reg (tree, const char * = NULL); extern tree create_tmp_reg_fn (struct function *, tree, const char *); -extern void extract_ops_from_tree_1 (tree, enum tree_code *, tree *, tree *, - tree *); +extern void extract_ops_from_tree (tree, enum tree_code *, tree *, tree *, + tree *); extern void gimple_cond_get_ops_from_tree (tree, enum tree_code *, tree *, tree *); extern bool is_gimple_lvalue (tree); @@ -146,15 +146,15 @@ is_gimple_constant (const_tree t) } } -/* A wrapper around extract_ops_from_tree_1, for callers which expect - to see only a maximum of two operands. */ +/* A wrapper around extract_ops_from_tree with 3 ops, for callers which + expect to see only a maximum of two operands. */ static inline void extract_ops_from_tree (tree expr, enum tree_code *code, tree *op0, tree *op1) { tree op2; - extract_ops_from_tree_1 (expr, code, op0, op1, &op2); + extract_ops_from_tree (expr, code, op0, op1, &op2); gcc_assert (op2 == NULL_TREE); } diff --git a/gcc/gimple.c b/gcc/gimple.c index 1f31914d0fe..a0e542fa47d 100644 --- a/gcc/gimple.c +++ b/gcc/gimple.c @@ -411,7 +411,7 @@ gimple_build_assign (tree lhs, tree rhs MEM_STAT_DECL) enum tree_code subcode; tree op1, op2, op3; - extract_ops_from_tree_1 (rhs, &subcode, &op1, &op2, &op3); + extract_ops_from_tree (rhs, &subcode, &op1, &op2, &op3); return gimple_build_assign (lhs, subcode, op1, op2, op3 PASS_MEM_STAT); } @@ -1595,7 +1595,7 @@ gimple_assign_set_rhs_from_tree (gimple_stmt_iterator *gsi, tree expr) enum tree_code subcode; tree op1, op2, op3; - extract_ops_from_tree_1 (expr, &subcode, &op1, &op2, &op3); + extract_ops_from_tree (expr, &subcode, &op1, &op2, &op3); gimple_assign_set_rhs_with_ops (gsi, subcode, op1, op2, op3); } diff --git a/gcc/ipa-icf.c b/gcc/ipa-icf.c index 47f2bf62780..729bc068153 100644 --- a/gcc/ipa-icf.c +++ b/gcc/ipa-icf.c @@ -1528,6 +1528,11 @@ sem_function::parse (cgraph_node *node, bitmap_obstack *stack) if (lookup_attribute_by_prefix ("omp ", DECL_ATTRIBUTES (node->decl)) != NULL) return NULL; + /* PR ipa/70306. */ + if (DECL_STATIC_CONSTRUCTOR (node->decl) + || DECL_STATIC_DESTRUCTOR (node->decl)) + return NULL; + sem_function *f = new sem_function (node, 0, stack); f->init (); diff --git a/gcc/ipa-prop.c b/gcc/ipa-prop.c index 9298fac9d56..747ab18f845 100644 --- a/gcc/ipa-prop.c +++ b/gcc/ipa-prop.c @@ -1683,7 +1683,8 @@ ipa_compute_jump_functions_for_edge (struct ipa_func_body_info *fbi, unsigned HOST_WIDE_INT hwi_bitpos; unsigned align; - if (get_pointer_alignment_1 (arg, &align, &hwi_bitpos) + get_pointer_alignment_1 (arg, &align, &hwi_bitpos); + if (align > BITS_PER_UNIT && align % BITS_PER_UNIT == 0 && hwi_bitpos % BITS_PER_UNIT == 0) { diff --git a/gcc/ipa-split.c b/gcc/ipa-split.c index 5d6763d102d..b9678e11db0 100644 --- a/gcc/ipa-split.c +++ b/gcc/ipa-split.c @@ -1306,8 +1306,8 @@ split_function (basic_block return_bb, struct split_point *split_point, FIXME: Once we are able to change return type, we should change function to return void instead of just outputting function with undefined return value. For structures this affects quality of codegen. */ - else if (!split_point->split_part_set_retval - && find_retval (return_bb)) + else if ((retval = find_retval (return_bb)) + && !split_point->split_part_set_retval) { bool redirected = true; basic_block new_return_bb = create_basic_block (NULL, 0, return_bb); @@ -1402,6 +1402,44 @@ split_function (basic_block return_bb, struct split_point *split_point, DECL_FUNCTION_CODE (node->decl) = (enum built_in_function) 0; } + /* If return_bb contains any clobbers that refer to SSA_NAMEs + set in the split part, remove them. Also reset debug stmts that + refer to SSA_NAMEs set in the split part. */ + if (return_bb != EXIT_BLOCK_PTR_FOR_FN (cfun)) + { + gimple_stmt_iterator gsi = gsi_start_bb (return_bb); + while (!gsi_end_p (gsi)) + { + tree op; + ssa_op_iter iter; + gimple stmt = gsi_stmt (gsi); + bool remove = false; + if (gimple_clobber_p (stmt) || is_gimple_debug (stmt)) + FOR_EACH_SSA_TREE_OPERAND (op, stmt, iter, SSA_OP_USE) + { + basic_block bb = gimple_bb (SSA_NAME_DEF_STMT (op)); + if (op != retval + && bb + && bb != return_bb + && bitmap_bit_p (split_point->split_bbs, bb->index)) + { + if (is_gimple_debug (stmt)) + { + gimple_debug_bind_reset_value (stmt); + update_stmt (stmt); + } + else + remove = true; + break; + } + } + if (remove) + gsi_remove (&gsi, true); + else + gsi_next (&gsi); + } + } + /* If the original function is instrumented then it's part is also instrumented. */ if (with_bounds) @@ -1554,7 +1592,7 @@ split_function (basic_block return_bb, struct split_point *split_point, return value into and put call just before it. */ if (return_bb != EXIT_BLOCK_PTR_FOR_FN (cfun)) { - real_retval = retval = find_retval (return_bb); + real_retval = retval; retbnd = find_retbnd (return_bb); if (real_retval && split_point->split_part_set_retval) @@ -1600,6 +1638,28 @@ split_function (basic_block return_bb, struct split_point *split_point, break; } update_stmt (gsi_stmt (bsi)); + /* Also adjust clobbers and debug stmts in return_bb. */ + for (bsi = gsi_start_bb (return_bb); !gsi_end_p (bsi); + gsi_next (&bsi)) + { + gimple stmt = gsi_stmt (bsi); + if (gimple_clobber_p (stmt) + || is_gimple_debug (stmt)) + { + ssa_op_iter iter; + use_operand_p use_p; + bool update = false; + FOR_EACH_SSA_USE_OPERAND (use_p, stmt, iter, + SSA_OP_USE) + if (USE_FROM_PTR (use_p) == real_retval) + { + SET_USE (use_p, retval); + update = true; + } + if (update) + update_stmt (stmt); + } + } } /* Replace retbnd with new one. */ diff --git a/gcc/ira.c b/gcc/ira.c index e9a95e2ca45..cbc5bd0fe29 100644 --- a/gcc/ira.c +++ b/gcc/ira.c @@ -3872,7 +3872,8 @@ update_equiv_regs (void) free (pdx_subregs); } -/* A pass over indirect jumps, converting simple cases to direct jumps. */ +/* A pass over indirect jumps, converting simple cases to direct jumps. + Combine does this optimization too, but only within a basic block. */ static void indirect_jump_optimize (void) { @@ -3882,7 +3883,8 @@ indirect_jump_optimize (void) FOR_EACH_BB_REVERSE_FN (bb, cfun) { rtx_insn *insn = BB_END (bb); - if (!JUMP_P (insn)) + if (!JUMP_P (insn) + || find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX)) continue; rtx x = pc_set (insn); @@ -3892,13 +3894,21 @@ indirect_jump_optimize (void) int regno = REGNO (SET_SRC (x)); if (DF_REG_DEF_COUNT (regno) == 1) { - rtx_insn *def_insn = DF_REF_INSN (DF_REG_DEF_CHAIN (regno)); - rtx note = find_reg_note (def_insn, REG_LABEL_OPERAND, NULL_RTX); - - if (note) + df_ref def = DF_REG_DEF_CHAIN (regno); + if (!DF_REF_IS_ARTIFICIAL (def)) { - rtx lab = gen_rtx_LABEL_REF (Pmode, XEXP (note, 0)); - if (validate_replace_rtx (SET_SRC (x), lab, insn)) + rtx_insn *def_insn = DF_REF_INSN (def); + rtx lab = NULL_RTX; + rtx set = single_set (def_insn); + if (set && GET_CODE (SET_SRC (set)) == LABEL_REF) + lab = SET_SRC (set); + else + { + rtx eqnote = find_reg_note (def_insn, REG_EQUAL, NULL_RTX); + if (eqnote && GET_CODE (XEXP (eqnote, 0)) == LABEL_REF) + lab = XEXP (eqnote, 0); + } + if (lab && validate_replace_rtx (SET_SRC (x), lab, insn)) rebuild_p = true; } } diff --git a/gcc/lra.c b/gcc/lra.c index 2efc2860051..84c7211dc5c 100644 --- a/gcc/lra.c +++ b/gcc/lra.c @@ -1801,20 +1801,29 @@ lra_process_new_insns (rtx_insn *insn, rtx_insn *before, rtx_insn *after, } if (before != NULL_RTX) { + if (cfun->can_throw_non_call_exceptions) + copy_reg_eh_region_note_forward (insn, before, NULL); emit_insn_before (before, insn); push_insns (PREV_INSN (insn), PREV_INSN (before)); setup_sp_offset (before, PREV_INSN (insn)); } if (after != NULL_RTX) { + if (cfun->can_throw_non_call_exceptions) + copy_reg_eh_region_note_forward (insn, after, NULL); for (last = after; NEXT_INSN (last) != NULL_RTX; last = NEXT_INSN (last)) ; emit_insn_after (after, insn); push_insns (last, insn); setup_sp_offset (after, last); } + if (cfun->can_throw_non_call_exceptions) + { + rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); + if (note && !insn_could_throw_p (insn)) + remove_note (insn, note); + } } - /* Replace all references to register OLD_REGNO in *LOC with pseudo diff --git a/gcc/optabs.c b/gcc/optabs.c index 3230e8ac1e1..e9702e15bb0 100644 --- a/gcc/optabs.c +++ b/gcc/optabs.c @@ -1419,6 +1419,7 @@ expand_binop_directly (machine_mode mode, optab binoptab, rtx pat; rtx xop0 = op0, xop1 = op1; rtx swap; + bool canonicalize_op1 = false; /* If it is a commutative operator and the modes would match if we would swap the operands, we can save the conversions. */ @@ -1436,6 +1437,11 @@ expand_binop_directly (machine_mode mode, optab binoptab, xop0 = avoid_expensive_constant (xmode0, binoptab, 0, xop0, unsignedp); if (!shift_optab_p (binoptab)) xop1 = avoid_expensive_constant (xmode1, binoptab, 1, xop1, unsignedp); + else if (xmode1 != VOIDmode) + /* Shifts and rotates often use a different mode for op1 from op0; + for VOIDmode constants we don't know the mode, so force it + to be canonicalized using convert_modes. */ + canonicalize_op1 = true; /* In case the insn wants input operands in modes different from those of the actual operands, convert the operands. It would @@ -1450,7 +1456,8 @@ expand_binop_directly (machine_mode mode, optab binoptab, mode0 = xmode0; } - mode1 = GET_MODE (xop1) != VOIDmode ? GET_MODE (xop1) : mode; + mode1 = ((GET_MODE (xop1) != VOIDmode || canonicalize_op1) + ? GET_MODE (xop1) : mode); if (xmode1 != VOIDmode && xmode1 != mode1) { xop1 = convert_modes (xmode1, mode1, xop1, unsignedp); @@ -1535,7 +1542,7 @@ expand_binop (machine_mode mode, optab binoptab, rtx op0, rtx op1, = (methods == OPTAB_LIB || methods == OPTAB_LIB_WIDEN ? OPTAB_WIDEN : methods); enum mode_class mclass; - machine_mode wider_mode; + machine_mode wider_mode, inner_mode; rtx libfunc; rtx temp; rtx_insn *entry_last = get_last_insn (); @@ -1551,6 +1558,18 @@ expand_binop (machine_mode mode, optab binoptab, rtx op0, rtx op1, op1 = negate_rtx (mode, op1); binoptab = add_optab; } + /* For shifts, constant invalid op1 might be expanded from different + mode than MODE. As those are invalid, force them to a register + to avoid further problems during expansion. */ + else if (CONST_INT_P (op1) + && shift_optab_p (binoptab) + && (inner_mode = (GET_MODE_INNER (mode) == VOIDmode + ? mode : GET_MODE_INNER (mode))) != VOIDmode + && UINTVAL (op1) >= GET_MODE_BITSIZE (inner_mode)) + { + op1 = gen_int_mode (INTVAL (op1), inner_mode); + op1 = force_reg (inner_mode, op1); + } /* Record where to delete back to if we backtrack. */ last = get_last_insn (); diff --git a/gcc/passes.c b/gcc/passes.c index 062ae4f0d1b..455f9ba736a 100644 --- a/gcc/passes.c +++ b/gcc/passes.c @@ -2208,7 +2208,7 @@ execute_one_ipa_transform_pass (struct cgraph_node *node, check_profile_consistency (pass->static_pass_number, 1, true); if (dump_file) - do_per_function (execute_function_dump, NULL); + do_per_function (execute_function_dump, pass); pass_fini_dump_file (pass); current_pass = NULL; @@ -2345,14 +2345,15 @@ execute_one_pass (opt_pass *pass) check_profile_consistency (pass->static_pass_number, 1, true); verify_interpass_invariants (); - if (dump_file) - do_per_function (execute_function_dump, pass); - if (pass->type == IPA_PASS) + if (pass->type == IPA_PASS + && ((ipa_opt_pass_d *)pass)->function_transform) { struct cgraph_node *node; FOR_EACH_FUNCTION_WITH_GIMPLE_BODY (node) node->ipa_transforms_to_apply.safe_push ((ipa_opt_pass_d *)pass); } + else if (dump_file) + do_per_function (execute_function_dump, pass); if (!current_function_decl) symtab->process_new_functions (); diff --git a/gcc/rtl.h b/gcc/rtl.h index 59c60f5716d..22e50f36bed 100644 --- a/gcc/rtl.h +++ b/gcc/rtl.h @@ -3521,6 +3521,8 @@ extern int anti_dependence (const_rtx, const_rtx); extern int canon_anti_dependence (const_rtx, bool, const_rtx, machine_mode, rtx); extern int output_dependence (const_rtx, const_rtx); +extern int canon_output_dependence (const_rtx, bool, + const_rtx, machine_mode, rtx); extern int may_alias_p (const_rtx, const_rtx); extern void init_alias_target (void); extern void init_alias_analysis (void); diff --git a/gcc/sched-deps.c b/gcc/sched-deps.c index 66dbfaedde1..e7ed32e4b75 100644 --- a/gcc/sched-deps.c +++ b/gcc/sched-deps.c @@ -2893,6 +2893,17 @@ sched_macro_fuse_insns (rtx_insn *insn) } +/* Get the implicit reg pending clobbers for INSN and save them in TEMP. */ +void +get_implicit_reg_pending_clobbers (HARD_REG_SET *temp, rtx_insn *insn) +{ + extract_insn (insn); + preprocess_constraints (insn); + alternative_mask preferred = get_preferred_alternatives (insn); + ira_implicitly_set_insn_hard_regs (temp, preferred); + AND_COMPL_HARD_REG_SET (*temp, ira_no_alloc_regs); +} + /* Analyze an INSN with pattern X to find all dependencies. */ static void sched_analyze_insn (struct deps_desc *deps, rtx x, rtx_insn *insn) @@ -2905,12 +2916,7 @@ sched_analyze_insn (struct deps_desc *deps, rtx x, rtx_insn *insn) if (! reload_completed) { HARD_REG_SET temp; - - extract_insn (insn); - preprocess_constraints (insn); - alternative_mask prefrred = get_preferred_alternatives (insn); - ira_implicitly_set_insn_hard_regs (&temp, prefrred); - AND_COMPL_HARD_REG_SET (temp, ira_no_alloc_regs); + get_implicit_reg_pending_clobbers (&temp, insn); IOR_HARD_REG_SET (implicit_reg_pending_clobbers, temp); } @@ -3523,7 +3529,8 @@ sched_analyze_insn (struct deps_desc *deps, rtx x, rtx_insn *insn) { if (deps->last_args_size) add_dependence (insn, deps->last_args_size, REG_DEP_OUTPUT); - deps->last_args_size = insn; + if (!deps->readonly) + deps->last_args_size = insn; } } diff --git a/gcc/sched-int.h b/gcc/sched-int.h index cc68522714e..5ad38b565ac 100644 --- a/gcc/sched-int.h +++ b/gcc/sched-int.h @@ -1355,6 +1355,7 @@ extern void finish_deps_global (void); extern void deps_analyze_insn (struct deps_desc *, rtx_insn *); extern void remove_from_deps (struct deps_desc *, rtx_insn *); extern void init_insn_reg_pressure_info (rtx); +extern void get_implicit_reg_pending_clobbers (HARD_REG_SET *, rtx_insn *); extern dw_t get_dep_weak (ds_t, ds_t); extern ds_t set_dep_weak (ds_t, ds_t, dw_t); diff --git a/gcc/sel-sched-ir.c b/gcc/sel-sched-ir.c index 94f6c43a284..c681d3710ee 100644 --- a/gcc/sel-sched-ir.c +++ b/gcc/sel-sched-ir.c @@ -1891,12 +1891,16 @@ merge_expr (expr_t to, expr_t from, insn_t split_point) /* Make sure that speculative pattern is propagated into exprs that have non-speculative one. This will provide us with consistent speculative bits and speculative patterns inside expr. */ - if ((EXPR_SPEC_DONE_DS (from) != 0 - && EXPR_SPEC_DONE_DS (to) == 0) - /* Do likewise for volatile insns, so that we always retain - the may_trap_p bit on the resulting expression. */ - || (VINSN_MAY_TRAP_P (EXPR_VINSN (from)) - && !VINSN_MAY_TRAP_P (EXPR_VINSN (to)))) + if (EXPR_SPEC_DONE_DS (to) == 0 + && (EXPR_SPEC_DONE_DS (from) != 0 + /* Do likewise for volatile insns, so that we always retain + the may_trap_p bit on the resulting expression. However, + avoid propagating the trapping bit into the instructions + already speculated. This would result in replacing the + speculative pattern with the non-speculative one and breaking + the speculation support. */ + || (!VINSN_MAY_TRAP_P (EXPR_VINSN (to)) + && VINSN_MAY_TRAP_P (EXPR_VINSN (from))))) change_vinsn_in_expr (to, EXPR_VINSN (from)); merge_expr_data (to, from, split_point); @@ -2670,6 +2674,23 @@ maybe_downgrade_id_to_use (idata_t id, insn_t insn) IDATA_TYPE (id) = USE; } +/* Setup implicit register clobbers calculated by sched-deps for INSN + before reload and save them in ID. */ +static void +setup_id_implicit_regs (idata_t id, insn_t insn) +{ + if (reload_completed) + return; + + HARD_REG_SET temp; + unsigned regno; + hard_reg_set_iterator hrsi; + + get_implicit_reg_pending_clobbers (&temp, insn); + EXECUTE_IF_SET_IN_HARD_REG_SET (temp, 0, regno, hrsi) + SET_REGNO_REG_SET (IDATA_REG_SETS (id), regno); +} + /* Setup register sets describing INSN in ID. */ static void setup_id_reg_sets (idata_t id, insn_t insn) @@ -2724,6 +2745,9 @@ setup_id_reg_sets (idata_t id, insn_t insn) } } + /* Also get implicit reg clobbers from sched-deps. */ + setup_id_implicit_regs (id, insn); + return_regset_to_pool (tmp); } @@ -2755,20 +2779,18 @@ deps_init_id (idata_t id, insn_t insn, bool force_unique_p) deps_init_id_data.force_use_p = false; init_deps (dc, false); - memcpy (&deps_init_id_sched_deps_info, &const_deps_init_id_sched_deps_info, sizeof (deps_init_id_sched_deps_info)); - if (spec_info != NULL) deps_init_id_sched_deps_info.generate_spec_deps = 1; - sched_deps_info = &deps_init_id_sched_deps_info; deps_analyze_insn (dc, insn); + /* Implicit reg clobbers received from sched-deps separately. */ + setup_id_implicit_regs (id, insn); free_deps (dc); - deps_init_id_data.id = NULL; } @@ -4104,11 +4126,14 @@ get_seqno_by_preds (rtx_insn *insn) insn_t *preds; int n, i, seqno; - while (tmp != head) + /* Loop backwards from INSN to HEAD including both. */ + while (1) { - tmp = PREV_INSN (tmp); if (INSN_P (tmp)) - return INSN_SEQNO (tmp); + return INSN_SEQNO (tmp); + if (tmp == head) + break; + tmp = PREV_INSN (tmp); } cfg_preds (bb, &preds, &n); diff --git a/gcc/sel-sched.c b/gcc/sel-sched.c index 0a322a84dcb..dab06ec10da 100644 --- a/gcc/sel-sched.c +++ b/gcc/sel-sched.c @@ -1486,31 +1486,44 @@ choose_best_pseudo_reg (regset used_regs, gcc_assert (mode == GET_MODE (dest)); orig_regno = REGNO (dest); - if (!REGNO_REG_SET_P (used_regs, orig_regno)) - { - if (orig_regno < FIRST_PSEUDO_REGISTER) - { - gcc_assert (df_regs_ever_live_p (orig_regno)); + /* Check that nothing in used_regs intersects with orig_regno. When + we have a hard reg here, still loop over hard_regno_nregs. */ + if (HARD_REGISTER_NUM_P (orig_regno)) + { + int j, n; + for (j = 0, n = hard_regno_nregs[orig_regno][mode]; j < n; j++) + if (REGNO_REG_SET_P (used_regs, orig_regno + j)) + break; + if (j < n) + continue; + } + else + { + if (REGNO_REG_SET_P (used_regs, orig_regno)) + continue; + } + if (HARD_REGISTER_NUM_P (orig_regno)) + { + gcc_assert (df_regs_ever_live_p (orig_regno)); - /* For hard registers, we have to check hardware imposed - limitations (frame/stack registers, calls crossed). */ - if (!TEST_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs, - orig_regno)) - { - /* Don't let register cross a call if it doesn't already - cross one. This condition is written in accordance with - that in sched-deps.c sched_analyze_reg(). */ - if (!reg_rename_p->crosses_call - || REG_N_CALLS_CROSSED (orig_regno) > 0) - return gen_rtx_REG (mode, orig_regno); - } + /* For hard registers, we have to check hardware imposed + limitations (frame/stack registers, calls crossed). */ + if (!TEST_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs, + orig_regno)) + { + /* Don't let register cross a call if it doesn't already + cross one. This condition is written in accordance with + that in sched-deps.c sched_analyze_reg(). */ + if (!reg_rename_p->crosses_call + || REG_N_CALLS_CROSSED (orig_regno) > 0) + return gen_rtx_REG (mode, orig_regno); + } - bad_hard_regs = true; - } - else - return dest; - } - } + bad_hard_regs = true; + } + else + return dest; + } *is_orig_reg_p_ptr = false; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 8a3313b8ffe..e272d7be718 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,577 @@ +2016-04-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + Backport from mainline + 2016-04-08 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + PR target/70566 + * gcc.c-torture/execute/pr70566.c: New test. + +2016-04-11 Alan Modra <amodra@gmail.com> + + * gcc.target/powerpc/pr70117.c: New. + +2016-04-09 Dominique d'Humieres <dominiq@lps.ens.fr> + + PR fortran/70592 + * gfortran.dg/deferred_character_17.f90: New test. + +2016-04-09 John David Anglin <danglin@gcc.gnu.org> + + * gcc.dg/uninit-19.c: Fix warning line for hppa*64*-*-*. + + PR tree-optimization/68644 + * gcc.dg/tree-ssa/ivopts-lt-2.c: Skip on hppa*-*-*. + + PR rtl-optimization/64886 + * gcc.dg/pr64434.c: Skip on hppa*-*-hpux*. + +2016-04-09 Oleg Endo <olegendo@gcc.gnu.org> + + Backport from mainline + 2016-04-03 Oleg Endo <olegendo@gcc.gnu.org> + + PR target/70416 + PR target/67391 + * gcc.target/sh/torture/pr70416.c: New. + +2016-04-06 Eric Botcazou <ebotcazou@adacore.com> + + * gcc.c-torture/execute/20101011-1.c (__VISIUM__): Set DO_TEST to 0. + +2016-04-06 Richard Biener <rguenther@suse.de> + + Backport from mainline + 2016-03-11 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/70177 + * gcc.dg/pr70177.c: New test. + +2016-04-06 Richard Biener <rguenther@suse.de> + + Backport from mainline + 2016-02-24 Richard Biener <rguenther@suse.de> + Jakub Jelinek <jakub@redhat.com> + + PR middle-end/69760 + * gcc.dg/torture/pr69760.c: New testcase. + + 2016-03-01 Richard Biener <rguenther@suse.de> + + PR tree-optimization/69983 + * gcc.dg/graphite/isl-codegen-loop-dumping.c: Adjust. + +2016-04-06 Richard Biener <rguenther@suse.de> + + Backport from mainline + 2016-02-24 Richard Biener <rguenther@suse.de> + + PR middle-end/68963 + * gcc.dg/torture/pr68963.c: New testcase. + +2016-04-06 Richard Biener <rguenther@suse.de> + + Backport from mainline + 2016-03-01 Richard Biener <rguenther@suse.de> + + PR middle-end/70022 + * gcc.dg/pr70022.c: New testcase. + + 2016-03-07 Richard Biener <rguenther@suse.de> + + PR tree-optimization/70115 + * gcc.dg/torture/pr70115.c: New testcase. + +2016-04-06 Richard Biener <rguenther@suse.de> + + Backport from mainline + 2016-03-30 Richard Biener <rguenther@suse.de> + + PR middle-end/70450 + * gcc.dg/torture/pr70450.c: New testcase. + + 2016-03-22 Richard Biener <rguenther@suse.de> + + PR middle-end/70333 + * gcc.dg/torture/pr70333.c: New testcase. + + 2016-04-04 Richard Biener <rguenther@suse.de> + + PR rtl-optimization/70484 + * gcc.dg/torture/pr70484.c: New testcase. + + 2016-03-31 Richard Biener <rguenther@suse.de> + + PR c++/70430 + * g++.dg/ext/vector30.C: New testcase. + +2016-04-05 Dominique d'Humieres <dominiq@lps.ens.fr> + Jerry DeLisle <jvdelisle@gcc.gnu.org> + + * gfortran.dg/fmt_pf.f90: New test. + +2016-04-05 Jakub Jelinek <jakub@redhat.com> + + PR target/70525 + * gcc.target/i386/pr70525.c: New test. + +2016-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + Jakub Jelinek <jakub@redhat.com> + + PR middle-end/70457 + * gcc.dg/torture/pr70457.c: New. + +2016-04-04 Andre Vehreschild <vehre@gmx.de> + + PR fortran/66911 + * gfortran.dg/deferred_character_16.f90: New test. + +2016-04-04 Andre Vehreschild <vehre@gcc.gnu.org> + + PR fortran/65795 + * gfortran.dg/coarray_allocate_6.f08: New test. + +2016-04-01 Ilya Enkovich <enkovich.gnu@gmail.com> + + Backport from mainline r234666. + 2016-04-01 Ilya Enkovich <enkovich.gnu@gmail.com> + + PR target/69890 + * gcc.dg/strlenopt.h (memmove): New. + * gcc.target/i386/chkp-strlen-1.c: Include "../../gcc.dg/strlenopt.h" + instead of "string.h". + * gcc.target/i386/chkp-strlen-2.c: Likewise. + * gcc.target/i386/chkp-strlen-3.c: Likewise. + * gcc.target/i386/chkp-strlen-4.c: Likewise. + * gcc.target/i386/chkp-strlen-5.c: Likewise. + * gcc.target/i386/chkp-stropt-1.c: Likewise. + * gcc.target/i386/chkp-stropt-10.c: Likewise. + * gcc.target/i386/chkp-stropt-11.c: Likewise. + * gcc.target/i386/chkp-stropt-12.c: Likewise. + * gcc.target/i386/chkp-stropt-13.c: Likewise. + * gcc.target/i386/chkp-stropt-14.c: Likewise. + * gcc.target/i386/chkp-stropt-15.c: Likewise. + * gcc.target/i386/chkp-stropt-16.c: Likewise. + * gcc.target/i386/chkp-stropt-2.c: Likewise. + * gcc.target/i386/chkp-stropt-3.c: Likewise. + * gcc.target/i386/chkp-stropt-4.c: Likewise. + * gcc.target/i386/chkp-stropt-5.c: Likewise. + * gcc.target/i386/chkp-stropt-6.c: Likewise. + * gcc.target/i386/chkp-stropt-7.c: Likewise. + * gcc.target/i386/chkp-stropt-8.c: Likewise. + * gcc.target/i386/chkp-stropt-9.c: Likewise. + +2016-01-04 Christophe Lyon <christophe.lyon@linaro.org> + + Backport from mainline + 2016-03-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + PR target/70004 + * gcc.target/aarch64/scalar_shift_1.c: (test_corners_sisd_di): + Delete. + (test_corners_sisd_si): Likewise. + (main): Remove checks of the above. + * gcc.target/aarch64/shift_wide_invalid_1.c: New test. + +2016-04-01 James Greenhalgh <james.greenhalgh@srm.com> + + Backport from mainline + 2016-01-26 Roger Ferrer Ibáñez <rofirrim@gmail.com> + + PR target/67896 + * gcc.target/aarch64/simd/pr67896.C: New. + +2016-03-31 Nathan Sidwell <nathan@acm.org> + + PR c++/70393 + * g++.dg/cpp0x/constexpr-virtual6.C: New. + +2016-03-31 Kirill Yukhin <kirill.yukhin@intel.com> + + PR target/70453 + * gcc.target/i386/pr70453.c: New test. + +2016-03-31 Andrey Belevantsev <abel@ispras.ru> + + Backport from mainline + 2016-03-21 Andrey Belevantsev <abel@ispras.ru> + + PR rtl-optimization/69102 + * gcc.c-torture/compile/pr69102.c: New test. + +2016-03-31 Andrey Belevantsev <abel@ispras.ru> + + Backport from mainline + 2016-03-15 Andrey Belevantsev <abel@ispras.ru> + + PR rtl-optimization/69032 + * gcc.dg/pr69032.c: New test. + +2016-03-31 Andrey Belevantsev <abel@ispras.ru> + + Backport from mainline + 2016-03-15 Andrey Belevantsev <abel@ispras.ru> + + PR target/64411 + * gcc.target/i386/pr64411.C: New test. + +2016-03-31 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/70460 + * gcc.c-torture/execute/pr70460.c: New test. + +2016-03-30 Jakub Jelinek <jakub@redhat.com> + + PR testsuite/70356 + * gcc.target/i386/avx-vextractf128-256-5.c: Move + dg-require-effective-target after dg-do. + +2016-03-30 Vladimir Makarov <vmakarov@redhat.com> + + Backported from the mainline + 2016-03-12 Vladimir Makarov <vmakarov@redhat.com> + + PR target/69614 + * gcc.target/arm/pr69614.c: New. + +2016-03-30 Jakub Jelinek <jakub@redhat.com> + + PR target/70421 + * gcc.dg/torture/pr70421.c: New test. + * gcc.target/i386/avx512f-pr70421.c: New test. + + Backported from mainline + 2016-03-29 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/70429 + * gcc.c-torture/execute/pr70429.c: New test. + + 2016-03-22 Jakub Jelinek <jakub@redhat.com> + + PR target/70329 + * gcc.target/i386/avx512bw-pr70329-1.c: New test. + * gcc.target/i386/avx512bw-pr70329-2.c: New test. + + 2016-03-21 Jakub Jelinek <jakub@redhat.com> + + PR target/70296 + * gcc.target/powerpc/altivec-36.c: New test. + + 2016-03-17 Jakub Jelinek <jakub@redhat.com> + + PR c++/70272 + * g++.dg/opt/flifetime-dse6.C: New test. + * g++.dg/tree-ssa/ehcleanup-1.C: Adjust unreachable count. + + 2016-03-15 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/70222 + * gcc.c-torture/execute/pr70222-1.c: New test. + * gcc.c-torture/execute/pr70222-2.c: New test. + + 2016-03-11 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/70169 + * gcc.dg/pr70169.c: New test. + + 2016-03-09 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/70152 + * gcc.dg/pr70152.c: New test. + + 2016-03-04 Jakub Jelinek <jakub@redhat.com> + + PR target/70062 + * gcc.target/i386/pr70062.c: New test. + + 2016-02-22 Jakub Jelinek <jakub@redhat.com> + + PR target/69888 + * gcc.target/i386/pr69888.c: New test. + + 2016-03-02 Jakub Jelinek <jakub@redhat.com> + + PR target/70028 + * gcc.target/i386/pr70028.c: New test. + + 2016-02-26 Jakub Jelinek <jakub@redhat.com> + + PR target/69969 + * gcc.target/powerpc/pr69969.c: New test. + + PR rtl-optimization/69891 + * gcc.target/i386/pr69891.c: New test. + + 2016-02-19 Jakub Jelinek <jakub@redhat.com> + + PR c++/69826 + * c-c++-common/cilk-plus/CK/pr69826-1.c: New test. + * c-c++-common/cilk-plus/CK/pr69826-2.c: New test. + + PR c++/67767 + * g++.dg/cpp0x/pr67767.C: New test. + + 2016-02-16 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/69802 + * gcc.dg/pr69802.c: New test. + + 2016-02-15 Jakub Jelinek <jakub@redhat.com> + + PR c++/69797 + * c-c++-common/pr69797.c: New test. + + 2016-02-22 Jakub Jelinek <jakub@redhat.com> + + PR target/69885 + * gcc.dg/pr69885.c: New test. + + 2016-02-12 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/69764 + PR rtl-optimization/69771 + * c-c++-common/pr69764.c: New test. + * gcc.dg/torture/pr69771.c: New test. + + PR ipa/68672 + * g++.dg/ipa/pr68672-1.C: New test. + * g++.dg/ipa/pr68672-2.C: New test. + * g++.dg/ipa/pr68672-3.C: New test. + +2016-03-30 Alan Modra <amodra@gmail.com> + + * gcc.dg/dfp/pr70052.c: New test. + +2016-02-29 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + PR target/69875 + * gcc.target/arm/atomic_loaddi_acquire.x: New file. + * gcc.target/arm/atomic_loaddi_relaxed.x: Likewise. + * gcc.target/arm/atomic_loaddi_seq_cst.x: Likewise. + * gcc.target/arm/atomic_loaddi_1.c: New test. + * gcc.target/arm/atomic_loaddi_2.c: Likewise. + * gcc.target/arm/atomic_loaddi_3.c: Likewise. + * gcc.target/arm/atomic_loaddi_4.c: Likewise. + * gcc.target/arm/atomic_loaddi_5.c: Likewise. + * gcc.target/arm/atomic_loaddi_6.c: Likewise. + * gcc.target/arm/atomic_loaddi_7.c: Likewise. + * gcc.target/arm/atomic_loaddi_8.c: Likewise. + * gcc.target/arm/atomic_loaddi_9.c: Likewise. + +2016-03-29 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + Backport from mainline + 2016-03-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * lib/target-supports.exp: Remove v7ve entry from loop + creating effective target checks. + (check_effective_target_arm_arch_v7ve_ok): New procedure. + (add_options_for_arm_arch_v7ve): Likewise. + +2016-03-28 Andre Vehreschild <vehre@gcc.gnu.org> + + PR fortran/70397 + * gfortran.dg/unlimited_polymorphic_25.f90: New test. + * gfortran.dg/unlimited_polymorphic_26.f90: New test. + +2016-03-28 Kirill Yukhin <kirill.yukhin@intel.com> + + PR target/70406 + * gcc.target/i386/pr70406.c: New test. + +2016-03-27 Eric Botcazou <ebotcazou@adacore.com> + + * gnat.dg/specs/double_record_extension3.ads: New test. + +2016-03-23 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> + + Backport from mainline + 2016-01-06 Eric Botcazou <ebotcazou@adacore.com> + + * gcc.target/sparc/20151219-1.c: Skip in 64-bit mode. + +2016-03-22 Martin Liska <mliska@suse.cz> + + PR ipa/70306 + * gcc.dg/ipa/pr70306.c: New test. + +2016-03-22 Kirill Yukhin <kirill.yukhin@intel.com> + + PR target/70325 + * gcc.target/i386/pr70325.c: New test. + +2016-03-21 Uros Bizjak <ubizjak@gmail.com> + + PR target/70327 + * gcc.target/i386/pr70327.c: New test. + +2016-03-21 Tom de Vries <tom@codesourcery.com> + + backport from trunk: + PR ipa/70269 + 2016-03-18 Tom de Vries <tom@codesourcery.com> + + * gcc.dg/pr70269.c: New test. + +2016-03-21 Tom de Vries <tom@codesourcery.com> + + backport from trunk: + 2016-03-18 Tom de Vries <tom@codesourcery.com> + + * gcc.dg/pr70161-2.c: New test. + * gcc.dg/pr70161.c: New test. + +2016-03-21 Marek Polacek <polacek@redhat.com> + + Backported from mainline + 2016-03-15 Marek Polacek <polacek@redhat.com> + + PR c++/70209 + * g++.dg/ext/attribute-may-alias-4.C: New test. + +2016-03-21 Kirill Yukhin <kirill.yukhin@intel.com> + + PR target/70293 + * gcc.target/i386/pr70293.c: New test. + +2016-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> + + Backport from mainline + 2015-06-09 James Greenhalgh <james.greenhalgh@arm.com> + + * g++.dg/ext/pr57735.C: Do not override -mfloat-abi directives + passed by the testsuite driver. + +2016-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> + + Backport from mainline + 2015-07-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * gcc.target/arm/no-volatile-in-it.c: Skip if -mcpu is overriden. + +2016-03-17 Andre Vieira <Andre.SimoesDiasVieira@arm.com> + + Backport from mainline. + 2015-05-21 Sandra Loosemore <sandra@codesourcery.com> + + * gcc.target/arm/simd/simd.exp: Skip all tests if no arm_neon_ok + effective target support. If no arm_neon_hw support, do not attempt + to execute the tests; only compile them. + * gcc.target/arm/simd/vextf32_1.c: Remove explicit "dg-do run" + and "dg-require-effective-target arm_neon_ok". + * gcc.target/arm/simd/vextp16_1.c: Likewise. + * gcc.target/arm/simd/vextp64_1.c: Likewise. + * gcc.target/arm/simd/vextp8_1.c: Likewise. + * gcc.target/arm/simd/vextQf32_1.c: Likewise. + * gcc.target/arm/simd/vextQp16_1.c: Likewise. + * gcc.target/arm/simd/vextQp64_1.c: Likewise. + * gcc.target/arm/simd/vextQp8_1.c: Likewise. + * gcc.target/arm/simd/vextQs16_1.c: Likewise. + * gcc.target/arm/simd/vextQs32_1.c: Likewise. + * gcc.target/arm/simd/vextQs64_1.c: Likewise. + * gcc.target/arm/simd/vextQs8_1.c: Likewise. + * gcc.target/arm/simd/vextQu16_1.c: Likewise. + * gcc.target/arm/simd/vextQu32_1.c: Likewise. + * gcc.target/arm/simd/vextQu64_1.c: Likewise. + * gcc.target/arm/simd/vextQu8_1.c: Likewise. + * gcc.target/arm/simd/vexts16_1.c: Likewise. + * gcc.target/arm/simd/vexts32_1.c: Likewise. + * gcc.target/arm/simd/vexts64_1.c: Likewise. + * gcc.target/arm/simd/vexts8_1.c: Likewise. + * gcc.target/arm/simd/vextu16_1.c: Likewise. + * gcc.target/arm/simd/vextu32_1.c: Likewise. + * gcc.target/arm/simd/vextu64_1.c: Likewise. + * gcc.target/arm/simd/vextu8_1.c: Likewise. + * gcc.target/arm/simd/vrev16p8_1.c: Likewise. + * gcc.target/arm/simd/vrev16qp8_1.c: Likewise. + * gcc.target/arm/simd/vrev16qs8_1.c: Likewise. + * gcc.target/arm/simd/vrev16qu8_1.c: Likewise. + * gcc.target/arm/simd/vrev16s8_1.c: Likewise. + * gcc.target/arm/simd/vrev16u8_1.c: Likewise. + * gcc.target/arm/simd/vrev32p16_1.c: Likewise. + * gcc.target/arm/simd/vrev32p8_1.c: Likewise. + * gcc.target/arm/simd/vrev32qp16_1.c: Likewise. + * gcc.target/arm/simd/vrev32qp8_1.c: Likewise. + * gcc.target/arm/simd/vrev32qs16_1.c: Likewise. + * gcc.target/arm/simd/vrev32qs8_1.c: Likewise. + * gcc.target/arm/simd/vrev32qu16_1.c: Likewise. + * gcc.target/arm/simd/vrev32qu8_1.c: Likewise. + * gcc.target/arm/simd/vrev32s16_1.c: Likewise. + * gcc.target/arm/simd/vrev32s8_1.c: Likewise. + * gcc.target/arm/simd/vrev32u16_1.c: Likewise. + * gcc.target/arm/simd/vrev32u8_1.c: Likewise. + * gcc.target/arm/simd/vrev64f32_1.c: Likewise. + * gcc.target/arm/simd/vrev64p16_1.c: Likewise. + * gcc.target/arm/simd/vrev64p8_1.c: Likewise. + * gcc.target/arm/simd/vrev64qf32_1.c: Likewise. + * gcc.target/arm/simd/vrev64qp16_1.c: Likewise. + * gcc.target/arm/simd/vrev64qp8_1.c: Likewise. + * gcc.target/arm/simd/vrev64qs16_1.c: Likewise. + * gcc.target/arm/simd/vrev64qs32_1.c: Likewise. + * gcc.target/arm/simd/vrev64qs8_1.c: Likewise. + * gcc.target/arm/simd/vrev64qu16_1.c: Likewise. + * gcc.target/arm/simd/vrev64qu32_1.c: Likewise. + * gcc.target/arm/simd/vrev64qu8_1.c: Likewise. + * gcc.target/arm/simd/vrev64s16_1.c: Likewise. + * gcc.target/arm/simd/vrev64s32_1.c: Likewise. + * gcc.target/arm/simd/vrev64s8_1.c: Likewise. + * gcc.target/arm/simd/vrev64u16_1.c: Likewise. + * gcc.target/arm/simd/vrev64u32_1.c: Likewise. + * gcc.target/arm/simd/vrev64u8_1.c: Likewise. + * gcc.target/arm/simd/vtrnf32_1.c: Likewise. + * gcc.target/arm/simd/vtrnp16_1.c: Likewise. + * gcc.target/arm/simd/vtrnp8_1.c: Likewise. + * gcc.target/arm/simd/vtrnqf32_1.c: Likewise. + * gcc.target/arm/simd/vtrnqp16_1.c: Likewise. + * gcc.target/arm/simd/vtrnqp8_1.c: Likewise. + * gcc.target/arm/simd/vtrnqs16_1.c: Likewise. + * gcc.target/arm/simd/vtrnqs32_1.c: Likewise. + * gcc.target/arm/simd/vtrnqs8_1.c: Likewise. + * gcc.target/arm/simd/vtrnqu16_1.c: Likewise. + * gcc.target/arm/simd/vtrnqu32_1.c: Likewise. + * gcc.target/arm/simd/vtrnqu8_1.c: Likewise. + * gcc.target/arm/simd/vtrns16_1.c: Likewise. + * gcc.target/arm/simd/vtrns32_1.c: Likewise. + * gcc.target/arm/simd/vtrns8_1.c: Likewise. + * gcc.target/arm/simd/vtrnu16_1.c: Likewise. + * gcc.target/arm/simd/vtrnu32_1.c: Likewise. + * gcc.target/arm/simd/vtrnu8_1.c: Likewise. + * gcc.target/arm/simd/vuzpf32_1.c: Likewise. + * gcc.target/arm/simd/vuzpp16_1.c: Likewise. + * gcc.target/arm/simd/vuzpp8_1.c: Likewise. + * gcc.target/arm/simd/vuzpqf32_1.c: Likewise. + * gcc.target/arm/simd/vuzpqp16_1.c: Likewise. + * gcc.target/arm/simd/vuzpqp8_1.c: Likewise. + * gcc.target/arm/simd/vuzpqs16_1.c: Likewise. + * gcc.target/arm/simd/vuzpqs32_1.c: Likewise. + * gcc.target/arm/simd/vuzpqs8_1.c: Likewise. + * gcc.target/arm/simd/vuzpqu16_1.c: Likewise. + * gcc.target/arm/simd/vuzpqu32_1.c: Likewise. + * gcc.target/arm/simd/vuzpqu8_1.c: Likewise. + * gcc.target/arm/simd/vuzps16_1.c: Likewise. + * gcc.target/arm/simd/vuzps32_1.c: Likewise. + * gcc.target/arm/simd/vuzps8_1.c: Likewise. + * gcc.target/arm/simd/vuzpu16_1.c: Likewise. + * gcc.target/arm/simd/vuzpu32_1.c: Likewise. + * gcc.target/arm/simd/vuzpu8_1.c: Likewise. + * gcc.target/arm/simd/vzipf32_1.c: Likewise. + * gcc.target/arm/simd/vzipp16_1.c: Likewise. + * gcc.target/arm/simd/vzipp8_1.c: Likewise. + * gcc.target/arm/simd/vzipqf32_1.c: Likewise. + * gcc.target/arm/simd/vzipqp16_1.c: Likewise. + * gcc.target/arm/simd/vzipqp8_1.c: Likewise. + * gcc.target/arm/simd/vzipqs16_1.c: Likewise. + * gcc.target/arm/simd/vzipqs32_1.c: Likewise. + * gcc.target/arm/simd/vzipqs8_1.c: Likewise. + * gcc.target/arm/simd/vzipqu16_1.c: Likewise. + * gcc.target/arm/simd/vzipqu32_1.c: Likewise. + * gcc.target/arm/simd/vzipqu8_1.c: Likewise. + * gcc.target/arm/simd/vzips16_1.c: Likewise. + * gcc.target/arm/simd/vzips32_1.c: Likewise. + * gcc.target/arm/simd/vzips8_1.c: Likewise. + * gcc.target/arm/simd/vzipu16_1.c: Likewise. + * gcc.target/arm/simd/vzipu32_1.c: Likewise. + * gcc.target/arm/simd/vzipu8_1.c: Likewise. + 2016-03-15 Bernd Schmidt <bschmidt@redhat.com> Backport from mainline diff --git a/gcc/testsuite/c-c++-common/cilk-plus/CK/pr69826-1.c b/gcc/testsuite/c-c++-common/cilk-plus/CK/pr69826-1.c new file mode 100644 index 00000000000..bcf7727f0ae --- /dev/null +++ b/gcc/testsuite/c-c++-common/cilk-plus/CK/pr69826-1.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { i?86-*-* x86_64-*-* } } } */ +/* { dg-options "-fcilkplus" } */ +/* { dg-additional-options "-std=gnu99" { target c } } */ +/* { dg-additional-options "-lcilkrts" { target { i?86-*-* x86_64-*-* } } } */ + +#define GRAINSIZE 2 + +int +main () +{ + int a[64]; + #pragma cilk grainsize=GRAINSIZE + _Cilk_for (int i = 0; i < 64; i++) + a[i] = 0; + #pragma cilk grainsize =GRAINSIZE + _Cilk_for (int i = 0; i < 64; i++) + a[i]++; + #pragma cilk grainsize = GRAINSIZE + _Cilk_for (int i = 0; i < 64; i++) + a[i]++; + for (int i = 0; i < 64; i++) + if (a[i] != 2) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/c-c++-common/cilk-plus/CK/pr69826-2.c b/gcc/testsuite/c-c++-common/cilk-plus/CK/pr69826-2.c new file mode 100644 index 00000000000..f4056c62e34 --- /dev/null +++ b/gcc/testsuite/c-c++-common/cilk-plus/CK/pr69826-2.c @@ -0,0 +1,6 @@ +/* { dg-do run { target { i?86-*-* x86_64-*-* } } } */ +/* { dg-options "-fcilkplus -save-temps" } */ +/* { dg-additional-options "-std=gnu99" { target c } } */ +/* { dg-additional-options "-lcilkrts" { target { i?86-*-* x86_64-*-* } } } */ + +#include "pr69826-1.c" diff --git a/gcc/testsuite/c-c++-common/pr69764.c b/gcc/testsuite/c-c++-common/pr69764.c new file mode 100644 index 00000000000..79623ec7373 --- /dev/null +++ b/gcc/testsuite/c-c++-common/pr69764.c @@ -0,0 +1,38 @@ +/* PR rtl-optimization/69764 */ +/* { dg-do compile { target int32plus } } */ + +unsigned char +fn1 (unsigned char a) +{ + return a >> ~6; /* { dg-warning "right shift count is negative" } */ +} + +unsigned short +fn2 (unsigned short a) +{ + return a >> ~6; /* { dg-warning "right shift count is negative" } */ +} + +unsigned int +fn3 (unsigned int a) +{ + return a >> ~6; /* { dg-warning "right shift count is negative" } */ +} + +unsigned char +fn4 (unsigned char a) +{ + return a >> 0xff03; /* { dg-warning "right shift count >= width of type" } */ +} + +unsigned short +fn5 (unsigned short a) +{ + return a >> 0xff03; /* { dg-warning "right shift count >= width of type" } */ +} + +unsigned int +fn6 (unsigned int a) +{ + return a >> 0xff03; /* { dg-warning "right shift count >= width of type" } */ +} diff --git a/gcc/testsuite/c-c++-common/pr69797.c b/gcc/testsuite/c-c++-common/pr69797.c new file mode 100644 index 00000000000..fe2d4304c34 --- /dev/null +++ b/gcc/testsuite/c-c++-common/pr69797.c @@ -0,0 +1,8 @@ +/* PR c++/69797 */ +/* { dg-do compile } */ + +void +foo () +{ + __atomic_fetch_add (); /* { dg-error "too few arguments to function" } */ +} diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-trivial1.C b/gcc/testsuite/g++.dg/cpp0x/constexpr-trivial1.C new file mode 100644 index 00000000000..f4b74a7eec9 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-trivial1.C @@ -0,0 +1,20 @@ +// PR c++/70139 +// { dg-options "-fno-elide-constructors" } +// { dg-do compile { target c++11 } } + +template<class T, class U> +struct A +{ + T a; + U b; + constexpr A () : a (), b () { } + constexpr A (const T &x, const U &y) : a (x), b (y) { } +}; +struct B +{ + constexpr B (const bool x) : c (x) {} + constexpr bool operator!= (const B x) const { return c != x.c; } + bool c; +}; +constexpr static A<B, B*> d[] = { { B (true), nullptr }, { B (false), nullptr } }; +static_assert (d[0].a != d[1].a, ""); diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-virtual6.C b/gcc/testsuite/g++.dg/cpp0x/constexpr-virtual6.C new file mode 100644 index 00000000000..f5abf2cf9b9 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-virtual6.C @@ -0,0 +1,49 @@ +// PR c++/70393 +// { dg-do run { target c++11 } } + +/* 'ab' has a static initializer, but we flubbed the initializer, + because of B being the primary base. */ + +struct A +{ + int a = 1; +}; + +struct B +{ + B *element = (B*)2; + + virtual int vfunc() = 0; + + int call_element() + { + return element->vfunc(); + } + + void set_element() + { + element = this; + } +}; + +struct AB : public A, public B +{ + int vfunc() + { + return 0; + } +}; + +static AB ab; + +int main() +{ + if (ab.a != 1) + return 1; + if (ab.element != (void*)2) + return 2; + + ab.set_element(); + return ab.call_element(); +} + diff --git a/gcc/testsuite/g++.dg/cpp0x/pr67767.C b/gcc/testsuite/g++.dg/cpp0x/pr67767.C new file mode 100644 index 00000000000..fd4ae2d3f35 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/pr67767.C @@ -0,0 +1,10 @@ +// PR c++/67767 +// { dg-do compile { target c++11 } } +// { dg-options "-Wsuggest-attribute=noreturn" } + +void foo [[gnu::cold, gnu::noreturn]] (); + +void foo () // { dg-bogus "function might be candidate for attribute" } +{ + throw 1; +} diff --git a/gcc/testsuite/g++.dg/ext/attribute-may-alias-4.C b/gcc/testsuite/g++.dg/ext/attribute-may-alias-4.C new file mode 100644 index 00000000000..a459d49e9ee --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/attribute-may-alias-4.C @@ -0,0 +1,17 @@ +// PR c++/70209 + +struct V { + typedef float F; + template <typename S> void m_fn1(S); +}; + +template <typename> struct A { + typedef V::F Ta __attribute__((__may_alias__)); + Ta *m_data; + void m_fn2(V &); +}; + +template <> +void A<int>::m_fn2(V &p) { + p.m_fn1(m_data); +} diff --git a/gcc/testsuite/g++.dg/ext/vector30.C b/gcc/testsuite/g++.dg/ext/vector30.C new file mode 100644 index 00000000000..68326e3db5b --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/vector30.C @@ -0,0 +1,15 @@ +// PR c++/70430 +// { dg-do run } +extern "C" void abort (void); +typedef int v4si __attribute__ ((vector_size (16))); +int main() +{ + v4si b = {1,0,-1,2}, c; + c = b && 1; + if (c[0] != -1 || c[1] != 0 || c[2] != -1 || c[3] != -1) + abort (); + c = b && 0; + if (c[0] != 0 || c[1] != 0 || c[2] != 0 || c[3] != 0) + abort (); + return 0; +} diff --git a/gcc/testsuite/g++.dg/ipa/pr68672-1.C b/gcc/testsuite/g++.dg/ipa/pr68672-1.C new file mode 100644 index 00000000000..fddabe17a43 --- /dev/null +++ b/gcc/testsuite/g++.dg/ipa/pr68672-1.C @@ -0,0 +1,20 @@ +// PR ipa/68672 +// { dg-do compile } +// { dg-options "-O -finline-small-functions -fpartial-inlining --param=partial-inlining-entry-probability=100" } + +void f2 (void *); +void *a; +struct C { virtual void m1 (); }; +struct D { C *m2 () { if (a) __builtin_abort (); } }; +D f1 (); +struct E { int e; ~E () { if (e) f2 (&e); } }; +E *b; +struct I { virtual void m3 (); }; + +void +I::m3 () +{ + if (a) + f1 ().m2 ()->m1 (); + b->~E (); +} diff --git a/gcc/testsuite/g++.dg/ipa/pr68672-2.C b/gcc/testsuite/g++.dg/ipa/pr68672-2.C new file mode 100644 index 00000000000..f23ae80c7a2 --- /dev/null +++ b/gcc/testsuite/g++.dg/ipa/pr68672-2.C @@ -0,0 +1,54 @@ +// PR ipa/68672 +// { dg-do compile } +// { dg-options "-O3 --param=partial-inlining-entry-probability=100 -g" } + +struct S { ~S () {} }; +S *a; +int *b; +void bar (); +void baz (); +void fn (int *); + +static int +foo () +{ + S *c = a; + if (c) + { + bar (); + if (a) + __builtin_abort (); + baz (); + } + int p = *b; + if (p) + { + fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); + fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); + fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); + fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); + } + c->~S (); + int q = 2 * p; + int r = 3 * q; + S *d = c; + return p; +} + +void +use1 () +{ + foo (); +} + +void +use2 () +{ + foo (); +} + +void +use3 () +{ + foo (); +} diff --git a/gcc/testsuite/g++.dg/ipa/pr68672-3.C b/gcc/testsuite/g++.dg/ipa/pr68672-3.C new file mode 100644 index 00000000000..971ddf6c6b7 --- /dev/null +++ b/gcc/testsuite/g++.dg/ipa/pr68672-3.C @@ -0,0 +1,57 @@ +// PR ipa/68672 +// { dg-do compile } +// { dg-options "-O3 --param=partial-inlining-entry-probability=100 -g" } + +struct S { ~S () {} }; +S *a, *e; +int *b; +void bar (); +void baz (); +void fn (int *); +void fn2 (S *); + +static int +foo () +{ + S *c = a; + if (c) + { + bar (); + if (a) + __builtin_abort (); + baz (); + } + int p = *b; + S *f = e; + if (p) + { + fn2 (f); + fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); + fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); + fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); + fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); fn (b); + } + f->~S (); + int q = 2 * p; + int r = 3 * q; + S *d = c; + return p; +} + +void +use1 () +{ + foo (); +} + +void +use2 () +{ + foo (); +} + +void +use3 () +{ + foo (); +} diff --git a/gcc/testsuite/g++.dg/opt/flifetime-dse6.C b/gcc/testsuite/g++.dg/opt/flifetime-dse6.C new file mode 100644 index 00000000000..6c805586252 --- /dev/null +++ b/gcc/testsuite/g++.dg/opt/flifetime-dse6.C @@ -0,0 +1,11 @@ +// PR c++/70272 +// { dg-options -O2 } +// { dg-do run } + +struct Empty { }; +struct A { A() : a(true) { } bool a; ~A() { if (!a) __builtin_abort(); } }; +struct B : Empty { B() : Empty() { } ~B() { } }; +struct C : A, B { C() : A(), B() { } ~C() { } }; +int main() { + C c; +} diff --git a/gcc/testsuite/g++.dg/tree-ssa/ehcleanup-1.C b/gcc/testsuite/g++.dg/tree-ssa/ehcleanup-1.C index a5dc2aa38d7..d6e4cf37205 100644 --- a/gcc/testsuite/g++.dg/tree-ssa/ehcleanup-1.C +++ b/gcc/testsuite/g++.dg/tree-ssa/ehcleanup-1.C @@ -26,5 +26,5 @@ t (void) // { dg-final { scan-tree-dump-times "Empty EH handler" 2 "ehcleanup1" } } // // And as a result also contained control flow. -// { dg-final { scan-tree-dump-times "Removing unreachable" 6 "ehcleanup1" } } +// { dg-final { scan-tree-dump-times "Removing unreachable" 4 "ehcleanup1" } } // diff --git a/gcc/testsuite/gcc.c-torture/compile/pr69102.c b/gcc/testsuite/gcc.c-torture/compile/pr69102.c new file mode 100644 index 00000000000..b1328cad974 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/pr69102.c @@ -0,0 +1,21 @@ +/* { dg-options "-Og -fPIC -fschedule-insns2 -fselective-scheduling2 -fno-tree-fre --param=max-sched-extend-regions-iters=10" } */ +void bar (unsigned int); + +void +foo (void) +{ + char buf[1] = { 3 }; + const char *p = buf; + const char **q = &p; + unsigned int ch; + switch (**q) + { + case 1: ch = 5; break; + case 2: ch = 4; break; + case 3: ch = 3; break; + case 4: ch = 2; break; + case 5: ch = 1; break; + default: ch = 0; break; + } + bar (ch); +} diff --git a/gcc/testsuite/gcc.c-torture/execute/20101011-1.c b/gcc/testsuite/gcc.c-torture/execute/20101011-1.c index 34d03137e26..28b5540a884 100644 --- a/gcc/testsuite/gcc.c-torture/execute/20101011-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/20101011-1.c @@ -18,6 +18,9 @@ #elif defined (__TMS320C6X__) /* On TI C6X division by zero does not trap. */ # define DO_TEST 0 +#elif defined (__VISIUM__) + /* On Visium division by zero does not trap. */ +# define DO_TEST 0 #elif defined (__mips__) && !defined(__linux__) /* MIPS divisions do trap by default, but libgloss targets do not intercept the trap and raise a SIGFPE. The same is probably diff --git a/gcc/testsuite/gcc.c-torture/execute/pr70222-1.c b/gcc/testsuite/gcc.c-torture/execute/pr70222-1.c new file mode 100644 index 00000000000..d79672e7fb4 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/execute/pr70222-1.c @@ -0,0 +1,30 @@ +/* PR rtl-optimization/70222 */ + +int a = 1; +unsigned int b = 2; +int c = 0; +int d = 0; + +void +foo () +{ + int e = ((-(c >= c)) < b) > ((int) (-1ULL >> ((a / a) * 15))); + d = -e; +} + +__attribute__((noinline, noclone)) void +bar (int x) +{ + if (x != -1) + __builtin_abort (); +} + +int +main () +{ +#if __CHAR_BIT__ == 8 && __SIZEOF_INT__ == 4 && __SIZEOF_LONG_LONG__ == 8 + foo (); + bar (d); +#endif + return 0; +} diff --git a/gcc/testsuite/gcc.c-torture/execute/pr70222-2.c b/gcc/testsuite/gcc.c-torture/execute/pr70222-2.c new file mode 100644 index 00000000000..7611c986a9b --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/execute/pr70222-2.c @@ -0,0 +1,20 @@ +/* PR rtl-optimization/70222 */ + +#if __CHAR_BIT__ == 8 && __SIZEOF_INT__ == 4 && __SIZEOF_LONG_LONG__ == 8 +__attribute__((noinline, noclone)) unsigned int +foo (int x) +{ + unsigned long long y = -1ULL >> x; + return (unsigned int) y >> 31; +} +#endif + +int +main () +{ +#if __CHAR_BIT__ == 8 && __SIZEOF_INT__ == 4 && __SIZEOF_LONG_LONG__ == 8 + if (foo (15) != 1 || foo (32) != 1 || foo (33) != 0) + __builtin_abort (); +#endif + return 0; +} diff --git a/gcc/testsuite/gcc.c-torture/execute/pr70429.c b/gcc/testsuite/gcc.c-torture/execute/pr70429.c new file mode 100644 index 00000000000..6b08c8ead08 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/execute/pr70429.c @@ -0,0 +1,17 @@ +/* PR rtl-optimization/70429 */ + +__attribute__((noinline, noclone)) int +foo (int a) +{ + return (int) (0x14ff6e2207db5d1fLL >> a) >> 4; +} + +int +main () +{ + if (sizeof (int) != 4 || sizeof (long long) != 8 || __CHAR_BIT__ != 8) + return 0; + if (foo (1) != 0x3edae8 || foo (2) != -132158092) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.c-torture/execute/pr70460.c b/gcc/testsuite/gcc.c-torture/execute/pr70460.c new file mode 100644 index 00000000000..bfecea0932e --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/execute/pr70460.c @@ -0,0 +1,29 @@ +/* PR rtl-optimization/70460 */ + +int c; + +__attribute__((noinline, noclone)) void +foo (int x) +{ + static int b[] = { &&lab1 - &&lab0, &&lab2 - &&lab0 }; + void *a = &&lab0 + b[x]; + goto *a; +lab1: + c += 2; +lab2: + c++; +lab0: + ; +} + +int +main () +{ + foo (0); + if (c != 3) + __builtin_abort (); + foo (1); + if (c != 4) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/dfp/pr70052.c b/gcc/testsuite/gcc.dg/dfp/pr70052.c new file mode 100644 index 00000000000..53eb0757a81 --- /dev/null +++ b/gcc/testsuite/gcc.dg/dfp/pr70052.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O1" } */ + +typedef struct +{ + _Decimal128 td0; + _Decimal128 td1; +} TDx2_t; + + +TDx2_t +D256_add_finite (void) +{ + _Decimal128 z, zz; + TDx2_t result = {0.DL, 0.DL}; + + if (zz == 0.DL) + { + result.td0 = z; + return result; + } + + return result; +} diff --git a/gcc/testsuite/gcc.dg/graphite/isl-codegen-loop-dumping.c b/gcc/testsuite/gcc.dg/graphite/isl-codegen-loop-dumping.c index cb5d802db8e..a3981989b97 100644 --- a/gcc/testsuite/gcc.dg/graphite/isl-codegen-loop-dumping.c +++ b/gcc/testsuite/gcc.dg/graphite/isl-codegen-loop-dumping.c @@ -12,4 +12,4 @@ main (int n, int *a) return 0; } -/* { dg-final { scan-tree-dump-times "ISL AST generated by ISL: \nfor \\(int c1 = 0; c1 < n - 1; c1 \\+= 1\\)\n for \\(int c3 = 0; c3 < n; c3 \\+= 1\\)\n S_4\\(c1, c3\\);" 1 "graphite"} } */ +/* { dg-final { scan-tree-dump-times "ISL AST generated by ISL: \nfor \\(int c1 = 0; c1 < n - 1; c1 \\+= 1\\) {\n S_10\\(c1\\);\n for \\(int c3 = 0; c3 < n; c3 \\+= 1\\)\n S_4\\(c1, c3\\);\n}" 1 "graphite"} } */ diff --git a/gcc/testsuite/gcc.dg/ipa/pr70306.c b/gcc/testsuite/gcc.dg/ipa/pr70306.c new file mode 100644 index 00000000000..be18208afd4 --- /dev/null +++ b/gcc/testsuite/gcc.dg/ipa/pr70306.c @@ -0,0 +1,45 @@ +/* { dg-options "-O2 -fdump-ipa-icf" } */ +/* { dg-do run } */ + +int ctor_counter = 1; +int dtor_counter; + +__attribute__((constructor)) +void A() +{ + ctor_counter++; +} + +__attribute__((destructor)) +void B() +{ + if (dtor_counter == 0) + __builtin_abort (); + + dtor_counter--; +} + +__attribute__((constructor)) +static void C() { + ctor_counter++; +} + +__attribute__((destructor)) +static void D() { + if (dtor_counter == 0) + __builtin_abort (); + + dtor_counter--; +} + +int main() +{ + if (ctor_counter != 3) + __builtin_abort (); + + dtor_counter = 2; + + return 0; +} + +/* { dg-final { scan-ipa-dump "Equal symbols: 0" "icf" } } */ diff --git a/gcc/testsuite/gcc.dg/pr64434.c b/gcc/testsuite/gcc.dg/pr64434.c index 550a63d2b13..699687136fd 100644 --- a/gcc/testsuite/gcc.dg/pr64434.c +++ b/gcc/testsuite/gcc.dg/pr64434.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O1 -fdump-rtl-expand-details" } */ +/* { dg-skip-if "PR64886" { hppa*-*-hpux* } { "*" } { "" } } */ #define N 256 int a1[N], a2[N], a3[N], a4[N]; diff --git a/gcc/testsuite/gcc.dg/pr69032.c b/gcc/testsuite/gcc.dg/pr69032.c new file mode 100644 index 00000000000..e0925cd8c56 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr69032.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target powerpc*-*-* ia64-*-* i?86-*-* x86_64-*-* } } */ +/* { dg-options "-O2 -fsched-pressure -fsel-sched-pipelining -fselective-scheduling" } */ + +void foo (long long i) +{ + while (i != -1) + { + ++i; + __asm__ (""); + } +} diff --git a/gcc/testsuite/gcc.dg/pr69307.c b/gcc/testsuite/gcc.dg/pr69307.c new file mode 100644 index 00000000000..d9d343e973a --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr69307.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fselective-scheduling2" } */ + +typedef unsigned char uint8_t; +typedef unsigned short int uint16_t; +typedef unsigned int uint32_t; +typedef unsigned long long int uint64_t; +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +typedef uint64_t u64; +u64 __attribute__((noinline, noclone)) +foo(u8 u8_0, u16 u16_0, u32 u32_0, u64 u64_0, u8 u8_1, u16 u16_1, u32 u32_1, u64 u64_1, u8 u8_2, u16 u16_2, u32 u32_2, u64 u64_2, u8 u8_3, u16 u16_3, u32 u32_3, u64 u64_3) +{ + u8 *p8_2 = &u8_2; + u16 *p16_2 = &u16_2; + u8 *p8_3 = &u8_3; + u64 *p64_3 = &u64_3; + p8_2 = &u8_3; + *p8_3 -= *p64_3; + *p8_2 = (u64)*p8_2 % ((u64)*p8_2 | 3); + u8_2 = (u64)u8_2 / ((u64)*p16_2 | 1); + u16_0 = (u64)u16_0 % ((u64)*p8_2 | 3); + return u8_0 + u16_0 + u32_0 + u64_0 + u8_1 + u16_1 + u32_1 + u64_1 + u8_2 + u16_2 + u32_2 + u64_2 + u8_3 + u16_3 + u32_3 + u64_3; +} +int main() +{ + u64 x = 0; + x += foo(3llu, 6llu, 15llu, 28llu, 5llu, 11llu, 20llu, 44llu, 7llu, 10llu, 20llu, 55llu, 0llu, 9llu, 17llu, 48llu); + if (x != 0x1f3) + __builtin_abort(); + return 0; +} + diff --git a/gcc/testsuite/gcc.dg/pr69802.c b/gcc/testsuite/gcc.dg/pr69802.c new file mode 100644 index 00000000000..27ee02f36b5 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr69802.c @@ -0,0 +1,23 @@ +/* PR tree-optimization/69802 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wall" } */ + +struct S { unsigned f : 1; }; +int a, d; + +int +foo (void) +{ + unsigned b = 0; + struct S c; + d = ((1 && b) < c.f) & c.f; /* { dg-warning "is used uninitialized" } */ + return a; +} + +int +bar (_Bool c) +{ + unsigned b = 0; + d = ((1 && b) < c) & c; + return a; +} diff --git a/gcc/testsuite/gcc.dg/pr69885.c b/gcc/testsuite/gcc.dg/pr69885.c new file mode 100644 index 00000000000..e3a218b8153 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr69885.c @@ -0,0 +1,13 @@ +/* PR target/69885 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-additional-options "-m68000" { target m68k*-*-* } } */ + +void bar (void); + +void +foo (long long x) +{ + if (x >> 1) + bar (); +} diff --git a/gcc/testsuite/gcc.dg/pr70022.c b/gcc/testsuite/gcc.dg/pr70022.c new file mode 100644 index 00000000000..30eb7ece250 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr70022.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-w -Wno-psabi" } */ + +typedef int v4si __attribute__ ((vector_size (16))); + +int +foo (v4si v) +{ + return v[~0UL]; +} diff --git a/gcc/testsuite/gcc.dg/pr70152.c b/gcc/testsuite/gcc.dg/pr70152.c new file mode 100644 index 00000000000..27a092d199a --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr70152.c @@ -0,0 +1,27 @@ +/* PR tree-optimization/70152 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int a; +int foo (void); +int setjmp (char *); +char buf[64]; + +static int +bar (int x) +{ + x = 0; + setjmp (buf); + for (;;) + { + switch (x) + case 5: + x = foo (); + } +} + +void +baz (void) +{ + bar (a); +} diff --git a/gcc/testsuite/gcc.dg/pr70161-2.c b/gcc/testsuite/gcc.dg/pr70161-2.c new file mode 100644 index 00000000000..d2cb22140c3 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr70161-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-ipa-all-graph -fipa-pta" } */ + +void +foo (void) +{ +} diff --git a/gcc/testsuite/gcc.dg/pr70161.c b/gcc/testsuite/gcc.dg/pr70161.c new file mode 100644 index 00000000000..0b173c7ee9d --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr70161.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-ipa-all-graph" } */ + +void +foo (void) +{ +} diff --git a/gcc/testsuite/gcc.dg/pr70169.c b/gcc/testsuite/gcc.dg/pr70169.c new file mode 100644 index 00000000000..8d08f5c6472 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr70169.c @@ -0,0 +1,40 @@ +/* PR tree-optimization/70169 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -fno-strict-aliasing -fno-tree-dce" } */ + +int printf (const char *, ...); + +void +foo () +{ + unsigned char *p = (unsigned char *) &printf; + for (;;) + (*p)++; +} + +void +bar (int x) +{ + unsigned char *p = (unsigned char *) &printf; + int i; + for (i = 0; i < x; i++) + (*p)++; +} + +void +baz (int x, int y) +{ + unsigned char *p = (unsigned char *) &&lab; + int i; + if (y) + { + for (i = 0; i < x; i++) + (*p)++; + } + else + { + lab: + asm volatile (""); + foo (); + } +} diff --git a/gcc/testsuite/gcc.dg/pr70177.c b/gcc/testsuite/gcc.dg/pr70177.c new file mode 100644 index 00000000000..1b2bec11e30 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr70177.c @@ -0,0 +1,15 @@ +/* PR tree-optimization/70177 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int b[128]; + +void +foo (int i, int j) +{ + int c, f, g, h; + for (g = 0; g < 64; g++) + for (h = g, f = 0; f <= i; f++, h++) + for (c = 0; c < j; c++) + b[h] = 0; +} diff --git a/gcc/testsuite/gcc.dg/pr70269.c b/gcc/testsuite/gcc.dg/pr70269.c new file mode 100644 index 00000000000..030cea1e605 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr70269.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fipa-pta -fdump-ipa-pta-graph" } */ + +void +foo (void) +{ +} diff --git a/gcc/testsuite/gcc.dg/strlenopt.h b/gcc/testsuite/gcc.dg/strlenopt.h index ef47e5ac9ad..8f69940b027 100644 --- a/gcc/testsuite/gcc.dg/strlenopt.h +++ b/gcc/testsuite/gcc.dg/strlenopt.h @@ -10,6 +10,7 @@ void free (void *); char *strdup (const char *); size_t strlen (const char *); void *memcpy (void *__restrict, const void *__restrict, size_t); +void *memmove (void *, const void *, size_t); char *strcpy (char *__restrict, const char *__restrict); char *strcat (char *__restrict, const char *__restrict); char *strchr (const char *, int); @@ -31,6 +32,12 @@ memcpy (void *__restrict dest, const void *__restrict src, size_t len) return __builtin___memcpy_chk (dest, src, len, bos0 (dest)); } +extern inline __attribute__((gnu_inline, always_inline, artificial)) void * +memmove (void *dest, const void *src, size_t len) +{ + return __builtin___memmove_chk (dest, src, len, bos0 (dest)); +} + extern inline __attribute__((gnu_inline, always_inline, artificial)) char * strcpy (char *__restrict dest, const char *__restrict src) { diff --git a/gcc/testsuite/gcc.dg/torture/pr68963.c b/gcc/testsuite/gcc.dg/torture/pr68963.c new file mode 100644 index 00000000000..c83b543fa03 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr68963.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ + +static const float a[3] = { 1, 2, 3 }; +int b = 3; + +__attribute__((noinline, noclone)) void +bar (int x) +{ + if (x != b++) + __builtin_abort (); +} + +void +foo (float *x, int y) +{ + int i; + for (i = 0; i < 2 * y; ++i) + { + if (i < y) + x[i] = a[i]; + else + { + bar (i); + x[i] = a[i - y]; + } + } +} + +int +main () +{ + float x[10]; + unsigned int i; + for (i = 0; i < 10; ++i) + x[i] = 1337; + foo (x, 3); + for (i = 0; i < 10; ++i) + if (x[i] != (i < 6 ? (i % 3) + 1 : 1337)) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/torture/pr69760.c b/gcc/testsuite/gcc.dg/torture/pr69760.c new file mode 100644 index 00000000000..8f24608d232 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr69760.c @@ -0,0 +1,50 @@ +/* PR tree-optimization/69760 */ +/* { dg-do run { target { { *-*-linux* *-*-gnu* } && mmap } } } */ +/* { dg-options "-O2" } */ + +#include <unistd.h> +#include <sys/mman.h> + +__attribute__((noinline, noclone)) void +test_func (double *a, int L, int m, int n, int N) +{ + int i, k; + for (i = 0; i < N; i++) + { + k = i - m; + if (k >= 0 && k < n) + a[L * k] = 0.0; + } +} + +int +main () +{ + char *p; + int L, m, n, N; + long l; + L = 10000000; + n = 4; + N = 100 * n; + long pgsz = sysconf(_SC_PAGESIZE); + if (pgsz < sizeof (double) || pgsz > L * sizeof (double)) + return 0; + p = mmap ((void *) 0, L * n * sizeof (double), PROT_NONE, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + if (p == MAP_FAILED) + return 0; + if (mprotect (p, pgsz, PROT_READ | PROT_WRITE)) + return 0; + l = (L * sizeof (double)) / pgsz * pgsz; + if (mprotect (p + l, pgsz, PROT_READ | PROT_WRITE)) + return 0; + l = (2 * L * sizeof (double)) / pgsz * pgsz; + if (mprotect (p + l, pgsz, PROT_READ | PROT_WRITE)) + return 0; + l = (3 * L * sizeof (double)) / pgsz * pgsz; + if (mprotect (p + l, pgsz, PROT_READ | PROT_WRITE)) + return 0; + for (m = 0; m < N; m += n) + test_func ((double *) p, L, m, n, N); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/torture/pr69771.c b/gcc/testsuite/gcc.dg/torture/pr69771.c new file mode 100644 index 00000000000..4aa5962b480 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr69771.c @@ -0,0 +1,12 @@ +/* PR rtl-optimization/69771 */ +/* { dg-do compile } */ + +unsigned char a = 5, c; +unsigned short b = 0; +unsigned d = 0x76543210; + +void +foo (void) +{ + c = d >> ~(a || ~b); /* { dg-warning "shift count is negative" "" { xfail *-*-* } } */ +} diff --git a/gcc/testsuite/gcc.dg/torture/pr70115.c b/gcc/testsuite/gcc.dg/torture/pr70115.c new file mode 100644 index 00000000000..0044fe4c2b1 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr70115.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ + +typedef int size_t; +char a; +int main() +{ + size_t b, c; + for (;;) + { + b = 0; + for (; c;) + ; + for (; b < sizeof(long); b++) + ; + for (; b < c; b++) + a++; + for (; c < b; c++) + ; + } +} diff --git a/gcc/testsuite/gcc.dg/torture/pr70333.c b/gcc/testsuite/gcc.dg/torture/pr70333.c new file mode 100644 index 00000000000..854e6d59e1a --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr70333.c @@ -0,0 +1,19 @@ +/* { dg-do run } */ +/* { dg-require-effective-target lp64 } */ + +unsigned long int +foo (signed char b, signed char e) +{ + return ((2ULL * b) * (e * 13)) * (32 << 24); +} + +int +main () +{ + if (__CHAR_BIT__ == 8 + && sizeof (int) == 4 + && sizeof (long long) == 8 + && foo (-60, 1) != 0xffffff3d00000000ULL) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/torture/pr70421.c b/gcc/testsuite/gcc.dg/torture/pr70421.c new file mode 100644 index 00000000000..8f97acd42be --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr70421.c @@ -0,0 +1,22 @@ +/* PR target/70421 */ +/* { dg-do run } */ +/* { dg-additional-options "-Wno-psabi -w" } */ + +typedef unsigned V __attribute__ ((vector_size (64))); + +unsigned __attribute__ ((noinline, noclone)) +foo (unsigned x, V u, V v) +{ + v[1] ^= v[2]; + x ^= ((V) v)[u[0]]; + return x; +} + +int +main () +{ + unsigned x = foo (0x10, (V) { 1 }, (V) { 0x100, 0x1000, 0x10000 }); + if (x != 0x11010) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/torture/pr70450.c b/gcc/testsuite/gcc.dg/torture/pr70450.c new file mode 100644 index 00000000000..ee5e24d0522 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr70450.c @@ -0,0 +1,19 @@ +/* { dg-do run } */ +/* { dg-require-effective-target lp64 } */ + +unsigned long int a = 2UL; +int b = 2; +unsigned long int c = 2UL; + +void foo () +{ + c = 2 * ((2 * a) * (2 * (-b))); +} + +int main () +{ + foo(); + if (c != 18446744073709551584UL) + __builtin_abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/torture/pr70457.c b/gcc/testsuite/gcc.dg/torture/pr70457.c new file mode 100644 index 00000000000..74daed4d36f --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr70457.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ + +/* This formerly ICEd when trying to expand pow as a built-in with + the wrong number of arguments. */ + +extern double pow (double, double) __attribute__ ((__nothrow__ , __leaf__)); + +typedef struct { + long long data; + int tag; +} Object; + +extern Object Make_Flonum (double); +extern Object P_Pow (Object, Object); + +Object General_Function (Object x, Object y, double (*fun)()) { + double d, ret; + + d = 1.0; + + if (y.tag >> 1) + ret = (*fun) (d); + else + ret = (*fun) (d, 0.0); + + return Make_Flonum (ret); +} + +Object P_Pow (Object x, Object y) { return General_Function (x, y, pow); } diff --git a/gcc/testsuite/gcc.dg/torture/pr70484.c b/gcc/testsuite/gcc.dg/torture/pr70484.c new file mode 100644 index 00000000000..7604c654fbe --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr70484.c @@ -0,0 +1,19 @@ +/* { dg-do run } */ + +extern void abort (void); + +int __attribute__((noinline,noclone)) +f(int *pi, long *pl) +{ + *pi = 1; + *pl = 0; + return *(char *)pi; +} + +int main() +{ + union { long l; int i; } a; + if (f (&a.i, &a.l) != 0) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ivopts-lt-2.c b/gcc/testsuite/gcc.dg/tree-ssa/ivopts-lt-2.c index 0f3f301d773..c809c9aa483 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ivopts-lt-2.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ivopts-lt-2.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -fdump-tree-ivopts" } */ +/* { dg-skip-if "PR68644" { hppa*-*-* } { "*" } { "" } } */ void f1 (int *p, unsigned int i) diff --git a/gcc/testsuite/gcc.dg/uninit-19.c b/gcc/testsuite/gcc.dg/uninit-19.c index fc7aceaa70b..b6c44b01a92 100644 --- a/gcc/testsuite/gcc.dg/uninit-19.c +++ b/gcc/testsuite/gcc.dg/uninit-19.c @@ -22,5 +22,5 @@ fn2 () fn1 (l, &d, &e, &g, &i, &h, &k, n); /* 22. */
}
-/* { dg-warning "may be used uninitialized" "" { target nonpic } 13 } */
-/* { dg-warning "may be used uninitialized" "" { target { ! nonpic } } 22 } */
+/* { dg-warning "may be used uninitialized" "" { target { { nonpic } || { hppa*64*-*-* } } } 13 } */
+/* { dg-warning "may be used uninitialized" "" { target { ! { { nonpic } || { hppa*64*-*-* } } } } 22 } */
diff --git a/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c b/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c index 363f5541a28..7be1b12a75b 100644 --- a/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c +++ b/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c @@ -181,34 +181,6 @@ test_ashift_right_int_si (Int32x1 b, Int32x1 c) /* { dg-final { scan-assembler "asr\tw\[0-9\]+,\ w\[0-9\]+,\ 4" } } */ /* { dg-final { scan-assembler "asr\tw\[0-9\]+,\ w\[0-9\]+,\ w\[0-9\]+" } } */ -Int64x1 -test_corners_sisd_di (Int64x1 b) -{ - force_simd_di (b); - b = b >> 63; - b = b >> 0; - b += b >> 65; /* { dg-warning "right shift count >= width of type" } */ - force_simd_di (b); - - return b; -} -/* { dg-final { scan-assembler "sshr\td\[0-9\]+,\ d\[0-9\]+,\ 63" } } */ - -Int32x1 -test_corners_sisd_si (Int32x1 b) -{ - force_simd_si (b); - b = b >> 31; - b = b >> 0; - b += b >> 33; /* { dg-warning "right shift count >= width of type" } */ - force_simd_si (b); - - return b; -} -/* { dg-final { scan-assembler "sshr\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 31" } } */ - - - #define CHECK(var,val) \ do \ { \ @@ -236,8 +208,6 @@ main () CHECK (x, 0xffffffff21524110ull); x = test_ashift_right_sisd_di (x, 8); CHECK (x, 0xffffffffffff2152ull); - x = test_corners_sisd_di (x); - CHECK (x, 0xfffffffffffffffeull); y = test_lshift_left_sisd_si (y, 4); CHECK (y, 0xadbeef00); @@ -252,8 +222,6 @@ main () CHECK (y, 0xffff5241); y = test_ashift_right_sisd_si (y, 4); CHECK (y, 0xffffff52); - y = test_corners_sisd_si (y); - CHECK (y, 0xfffffffe); return 0; } diff --git a/gcc/testsuite/gcc.target/aarch64/shift_wide_invalid_1.c b/gcc/testsuite/gcc.target/aarch64/shift_wide_invalid_1.c new file mode 100644 index 00000000000..6b71cb58092 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/shift_wide_invalid_1.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +/* These contain undefined behavior but may trigger edge cases in the + vector shift patterns. We don't check for their generation, we only + care about not ICEing. */ + +typedef long long int Int64x1; +typedef int Int32x1; + +#define force_simd_di(v) asm volatile ("mov %d0, %1.d[0]" : "=w"(v) : "w"(v) :) +#define force_simd_si(v) asm volatile ("mov %s0, %1.s[0]" : "=w"(v) : "w"(v) :) + +Int64x1 +foo_di (Int64x1 b) +{ + force_simd_di (b); + b = b >> 63; + force_simd_di (b); + b = b >> 0; + b += b >> 65; /* { dg-warning "right shift count >= width of type" } */ + + return b; +} + +Int32x1 +foo_si (Int32x1 b) +{ + force_simd_si (b); + b = b >> 31; + force_simd_si (b); + b = b >> 0; + b += b >> 33; /* { dg-warning "right shift count >= width of type" } */ + + return b; +} diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_1.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_1.c new file mode 100644 index 00000000000..4f39971a336 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-std=c11 -O" } */ +/* { dg-require-effective-target arm_arch_v7a_ok } */ +/* { dg-add-options arm_arch_v7a } */ + +#include "atomic_loaddi_acquire.x" + +/* { dg-final { scan-assembler-times "ldrexd\tr\[0-9\]+, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 1 } } */ +/* { dg-final { scan-assembler-times "dmb\tish" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_2.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_2.c new file mode 100644 index 00000000000..0b18f03e09d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-std=c11 -O" } */ +/* { dg-require-effective-target arm_arch_v7ve_ok } */ +/* { dg-add-options arm_arch_v7ve } */ + +#include "atomic_loaddi_acquire.x" + +/* { dg-final { scan-assembler-times "ldrd\tr\[0-9\]+, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 1 } } */ +/* { dg-final { scan-assembler-times "dmb\tish" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_3.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_3.c new file mode 100644 index 00000000000..080a9362abb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_3.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-std=c11 -O" } */ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "atomic_loaddi_acquire.x" + +/* { dg-final { scan-assembler-times "ldaexd\tr\[0-9\]+, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 1 } } */ +/* { dg-final { scan-assembler-not "dmb\tish" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_4.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_4.c new file mode 100644 index 00000000000..8f94ba61b4d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_4.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-std=c11 -O" } */ +/* { dg-require-effective-target arm_arch_v7a_ok } */ +/* { dg-add-options arm_arch_v7a } */ + +#include "atomic_loaddi_relaxed.x" + +/* { dg-final { scan-assembler-times "ldrexd\tr\[0-9\]+, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 1 } } */ +/* { dg-final { scan-assembler-not "dmb\tish" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_5.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_5.c new file mode 100644 index 00000000000..72c4604b4a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_5.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-std=c11 -O" } */ +/* { dg-require-effective-target arm_arch_v7ve_ok } */ +/* { dg-add-options arm_arch_v7ve } */ + +#include "atomic_loaddi_relaxed.x" + +/* { dg-final { scan-assembler-times "ldrd\tr\[0-9\]+, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 1 } } */ +/* { dg-final { scan-assembler-not "dmb\tish" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_6.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_6.c new file mode 100644 index 00000000000..fd6fd015b5b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_6.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-std=c11 -O" } */ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "atomic_loaddi_relaxed.x" + +/* { dg-final { scan-assembler-times "ldrd\tr\[0-9\]+, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 1 } } */ +/* { dg-final { scan-assembler-not "dmb\tish" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_7.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_7.c new file mode 100644 index 00000000000..6743663f1e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_7.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-std=c11 -O" } */ +/* { dg-require-effective-target arm_arch_v7a_ok } */ +/* { dg-add-options arm_arch_v7a } */ + +#include "atomic_loaddi_seq_cst.x" + +/* { dg-final { scan-assembler-times "ldrexd\tr\[0-9\]+, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 1 } } */ +/* { dg-final { scan-assembler-times "dmb\tish" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_8.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_8.c new file mode 100644 index 00000000000..f7bd3e5a2b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-std=c11 -O" } */ +/* { dg-require-effective-target arm_arch_v7ve_ok } */ +/* { dg-add-options arm_arch_v7ve } */ + +#include "atomic_loaddi_seq_cst.x" + +/* { dg-final { scan-assembler-times "ldrd\tr\[0-9\]+, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 1 } } */ +/* { dg-final { scan-assembler-times "dmb\tish" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_9.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_9.c new file mode 100644 index 00000000000..68b293409ff --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_9.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-std=c11 -O" } */ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "atomic_loaddi_seq_cst.x" + +/* { dg-final { scan-assembler-times "ldaexd\tr\[0-9\]+, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 1 } } */ +/* { dg-final { scan-assembler-not "dmb\tish" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_acquire.x b/gcc/testsuite/gcc.target/arm/atomic_loaddi_acquire.x new file mode 100644 index 00000000000..28997ef565b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_acquire.x @@ -0,0 +1,11 @@ +#include <stdatomic.h> + +atomic_ullong foo; +int glob; + +int +main (void) +{ + atomic_load_explicit (&foo, memory_order_acquire); + return glob; +} diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_relaxed.x b/gcc/testsuite/gcc.target/arm/atomic_loaddi_relaxed.x new file mode 100644 index 00000000000..701b3c42c09 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_relaxed.x @@ -0,0 +1,11 @@ +#include <stdatomic.h> + +atomic_ullong foo; +int glob; + +int +main (void) +{ + atomic_load_explicit (&foo, memory_order_relaxed); + return glob; +} diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_seq_cst.x b/gcc/testsuite/gcc.target/arm/atomic_loaddi_seq_cst.x new file mode 100644 index 00000000000..32e78da67e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_seq_cst.x @@ -0,0 +1,11 @@ +#include <stdatomic.h> + +atomic_ullong foo; +int glob; + +int +main (void) +{ + atomic_load_explicit (&foo, memory_order_seq_cst); + return glob; +} diff --git a/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-5.c b/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-5.c index 5359eb7f4b5..3a1db4b3bb4 100644 --- a/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-5.c +++ b/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-5.c @@ -1,5 +1,5 @@ -/* { dg-require-effective-target avx512f } */ /* { dg-do assemble { target { ! ia32 } } } */ +/* { dg-require-effective-target avx512f } */ /* { dg-options "-O2 -mavx512f" } */ #include <immintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-pr70329-1.c b/gcc/testsuite/gcc.target/i386/avx512bw-pr70329-1.c new file mode 100644 index 00000000000..bb9a9551d0c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512bw-pr70329-1.c @@ -0,0 +1,27 @@ +/* PR target/70329 */ +/* { dg-do run } */ +/* { dg-options "-O0 -mavx512bw" } */ +/* { dg-require-effective-target avx512bw } */ + +#define AVX512BW +#include "avx512f-helper.h" + +typedef unsigned char A __attribute__ ((vector_size (64))); +typedef unsigned int B __attribute__ ((vector_size (64))); + +unsigned __attribute__ ((noinline, noclone)) +foo (A a, A b, B c) +{ + a *= b; + c[1] += a[8]; + return c[1]; +} + +void +TEST (void) +{ + A a = (A) { 1, 2, 3, 4, 5, 6, 7, 8, 9 }; + unsigned x = foo (a, a, (B) { 1, 2 }); + if (x != 83) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-pr70329-2.c b/gcc/testsuite/gcc.target/i386/avx512bw-pr70329-2.c new file mode 100644 index 00000000000..731b9260794 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512bw-pr70329-2.c @@ -0,0 +1,33 @@ +/* PR target/70329 */ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize -mavx512bw" } */ +/* { dg-require-effective-target avx512bw } */ + +#define AVX512BW +#include "avx512f-helper.h" + +__attribute__((noinline, noclone)) void +foo (unsigned char *src1, unsigned char *src2, unsigned char *dst) +{ + int i; + + for (i = 0; i < 64; i++) + dst[i] = (unsigned char) ((int) src1[i] * (int) src2[i]); +} + +void +TEST (void) +{ + unsigned char a[64], b[64], c[64]; + int i; + + for (i = 0; i < 64; i++) + { + a[i] = i; + b[i] = (i + 1); + } + foo (a, b, c); + for (i = 0; i < 64; i++) + if (c[i] != (unsigned char) (i * (i + 1))) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-pr70421.c b/gcc/testsuite/gcc.target/i386/avx512f-pr70421.c new file mode 100644 index 00000000000..60e1e2a8863 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-pr70421.c @@ -0,0 +1,15 @@ +/* PR target/70421 */ +/* { dg-do run } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-options "-O2 -mavx512f" } */ + +#include "avx512f-check.h" + +#define main() do_main() +#include "../../gcc.dg/torture/pr70421.c" + +static void +avx512f_test (void) +{ + do_main (); +} diff --git a/gcc/testsuite/gcc.target/i386/chkp-strlen-1.c b/gcc/testsuite/gcc.target/i386/chkp-strlen-1.c index de6279f1dfa..38d53900627 100644 --- a/gcc/testsuite/gcc.target/i386/chkp-strlen-1.c +++ b/gcc/testsuite/gcc.target/i386/chkp-strlen-1.c @@ -2,7 +2,7 @@ /* { dg-options "-fcheck-pointer-bounds -mmpx -O2 -fdump-tree-strlen" } */ /* { dg-final { scan-tree-dump "memcpy.chkp" "strlen" } } */ -#include "string.h" +#include "../../gcc.dg/strlenopt.h" char *test (char *str1, char *str2) { diff --git a/gcc/testsuite/gcc.target/i386/chkp-strlen-2.c b/gcc/testsuite/gcc.target/i386/chkp-strlen-2.c index 9f584efee0a..789ebc1f2d8 100644 --- a/gcc/testsuite/gcc.target/i386/chkp-strlen-2.c +++ b/gcc/testsuite/gcc.target/i386/chkp-strlen-2.c @@ -3,7 +3,8 @@ /* { dg-options "-fcheck-pointer-bounds -mmpx -O2 -fdump-tree-strlen" } */ /* { dg-final { scan-tree-dump-not "strlen" "strlen" } } */ -#include "string.h" +#define USE_GNU +#include "../../gcc.dg/strlenopt.h" char *test (char *str1, char *str2) { diff --git a/gcc/testsuite/gcc.target/i386/chkp-strlen-3.c b/gcc/testsuite/gcc.target/i386/chkp-strlen-3.c index 311c9a042e0..276f4127975 100644 --- a/gcc/testsuite/gcc.target/i386/chkp-strlen-3.c +++ b/gcc/testsuite/gcc.target/i386/chkp-strlen-3.c @@ -2,7 +2,7 @@ /* { dg-options "-fcheck-pointer-bounds -mmpx -O2 -fdump-tree-strlen" } */ /* { dg-final { scan-tree-dump-times "strlen" 1 "strlen" } } */ -#include "string.h" +#include "../../gcc.dg/strlenopt.h" size_t test (char *str1, char *str2) { diff --git a/gcc/testsuite/gcc.target/i386/chkp-strlen-4.c b/gcc/testsuite/gcc.target/i386/chkp-strlen-4.c index 794c8a860da..6866b9869ec 100644 --- a/gcc/testsuite/gcc.target/i386/chkp-strlen-4.c +++ b/gcc/testsuite/gcc.target/i386/chkp-strlen-4.c @@ -3,7 +3,8 @@ /* { dg-options "-fcheck-pointer-bounds -mmpx -O2 -fdump-tree-strlen -D_GNU_SOURCE" } */ /* { dg-final { scan-tree-dump-times "strlen" 1 "strlen" } } */ -#include "string.h" +#define USE_GNU +#include "../../gcc.dg/strlenopt.h" char * test (char *str1, char *str2) { diff --git a/gcc/testsuite/gcc.target/i386/chkp-strlen-5.c b/gcc/testsuite/gcc.target/i386/chkp-strlen-5.c index e44096cd429..bbafecc3063 100644 --- a/gcc/testsuite/gcc.target/i386/chkp-strlen-5.c +++ b/gcc/testsuite/gcc.target/i386/chkp-strlen-5.c @@ -3,7 +3,7 @@ /* { dg-final { scan-tree-dump-times "strlen" 2 "strlen" } } */ /* { dg-final { scan-tree-dump "memcpy" "strlen" } } */ -#include "string.h" +#include "../../gcc.dg/strlenopt.h" size_t test (char *str1, char *str2) { diff --git a/gcc/testsuite/gcc.target/i386/chkp-stropt-1.c b/gcc/testsuite/gcc.target/i386/chkp-stropt-1.c index 18aa2819cdf..d6148a87fd1 100644 --- a/gcc/testsuite/gcc.target/i386/chkp-stropt-1.c +++ b/gcc/testsuite/gcc.target/i386/chkp-stropt-1.c @@ -2,7 +2,7 @@ /* { dg-options "-fcheck-pointer-bounds -mmpx -O2 -fdump-tree-chkpopt -fchkp-use-nochk-string-functions" } */ /* { dg-final { scan-tree-dump "memcpy_nochk" "chkpopt" } } */ -#include "string.h" +#include "../../gcc.dg/strlenopt.h" void test (int *buf1, int *buf2, size_t len) { diff --git a/gcc/testsuite/gcc.target/i386/chkp-stropt-10.c b/gcc/testsuite/gcc.target/i386/chkp-stropt-10.c index 26e9f13a190..18cff739b01 100644 --- a/gcc/testsuite/gcc.target/i386/chkp-stropt-10.c +++ b/gcc/testsuite/gcc.target/i386/chkp-stropt-10.c @@ -2,7 +2,7 @@ /* { dg-options "-fcheck-pointer-bounds -mmpx -O2 -fdump-tree-chkpopt -fchkp-use-fast-string-functions" } */ /* { dg-final { scan-tree-dump-not "memset_nobnd" "chkpopt" } } */ -#include "string.h" +#include "../../gcc.dg/strlenopt.h" void test (void *buf1, int c, size_t len) { diff --git a/gcc/testsuite/gcc.target/i386/chkp-stropt-11.c b/gcc/testsuite/gcc.target/i386/chkp-stropt-11.c index e84963f11f7..c53db6a17e4 100644 --- a/gcc/testsuite/gcc.target/i386/chkp-stropt-11.c +++ b/gcc/testsuite/gcc.target/i386/chkp-stropt-11.c @@ -2,7 +2,7 @@ /* { dg-options "-fcheck-pointer-bounds -mmpx -O2 -fdump-tree-chkpopt -fchkp-use-fast-string-functions" } */ /* { dg-final { scan-tree-dump-not "memmove_nobnd" "chkpopt" } } */ -#include "string.h" +#include "../../gcc.dg/strlenopt.h" void test (void *buf1, void *buf2, size_t len) { diff --git a/gcc/testsuite/gcc.target/i386/chkp-stropt-12.c b/gcc/testsuite/gcc.target/i386/chkp-stropt-12.c index 898e7768b30..ee73e09d875 100644 --- a/gcc/testsuite/gcc.target/i386/chkp-stropt-12.c +++ b/gcc/testsuite/gcc.target/i386/chkp-stropt-12.c @@ -3,7 +3,8 @@ /* { dg-options "-fcheck-pointer-bounds -mmpx -O2 -fdump-tree-chkpopt -fchkp-use-fast-string-functions -D_GNU_SOURCE" } */ /* { dg-final { scan-tree-dump-not "mempcpy_nobnd" "chkpopt" } } */ -#include "string.h" +#define USE_GNU +#include "../../gcc.dg/strlenopt.h" void test (void *buf1, void *buf2, size_t len) { diff --git a/gcc/testsuite/gcc.target/i386/chkp-stropt-13.c b/gcc/testsuite/gcc.target/i386/chkp-stropt-13.c index 3b926b11f83..279cae3e5bf 100644 --- a/gcc/testsuite/gcc.target/i386/chkp-stropt-13.c +++ b/gcc/testsuite/gcc.target/i386/chkp-stropt-13.c @@ -2,7 +2,7 @@ /* { dg-options "-fcheck-pointer-bounds -mmpx -O2 -fdump-tree-chkpopt -fchkp-use-nochk-string-functions -fchkp-use-fast-string-functions" } */ /* { dg-final { scan-tree-dump "memcpy_nobnd_nochk" "chkpopt" } } */ -#include "string.h" +#include "../../gcc.dg/strlenopt.h" void test (int *buf1, int *buf2, size_t len) { diff --git a/gcc/testsuite/gcc.target/i386/chkp-stropt-14.c b/gcc/testsuite/gcc.target/i386/chkp-stropt-14.c index a8d000ba1fa..b810c682569 100644 --- a/gcc/testsuite/gcc.target/i386/chkp-stropt-14.c +++ b/gcc/testsuite/gcc.target/i386/chkp-stropt-14.c @@ -2,7 +2,7 @@ /* { dg-options "-fcheck-pointer-bounds -mmpx -O2 -fdump-tree-chkpopt -fchkp-use-nochk-string-functions -fchkp-use-fast-string-functions" } */ /* { dg-final { scan-tree-dump "memset_nobnd_nochk" "chkpopt" } } */ -#include "string.h" +#include "../../gcc.dg/strlenopt.h" void test (int *buf1, int c, size_t len) { diff --git a/gcc/testsuite/gcc.target/i386/chkp-stropt-15.c b/gcc/testsuite/gcc.target/i386/chkp-stropt-15.c index 7c6065657c0..a9a79c1e330 100644 --- a/gcc/testsuite/gcc.target/i386/chkp-stropt-15.c +++ b/gcc/testsuite/gcc.target/i386/chkp-stropt-15.c @@ -2,7 +2,7 @@ /* { dg-options "-fcheck-pointer-bounds -mmpx -O2 -fdump-tree-chkpopt -fchkp-use-nochk-string-functions -fchkp-use-fast-string-functions" } */ /* { dg-final { scan-tree-dump "memmove_nobnd_nochk" "chkpopt" } } */ -#include "string.h" +#include "../../gcc.dg/strlenopt.h" void test (int *buf1, int *buf2, size_t len) { diff --git a/gcc/testsuite/gcc.target/i386/chkp-stropt-16.c b/gcc/testsuite/gcc.target/i386/chkp-stropt-16.c index 891adb4f293..29ea674363a 100644 --- a/gcc/testsuite/gcc.target/i386/chkp-stropt-16.c +++ b/gcc/testsuite/gcc.target/i386/chkp-stropt-16.c @@ -3,7 +3,8 @@ /* { dg-options "-fcheck-pointer-bounds -mmpx -O2 -fdump-tree-chkpopt -fchkp-use-nochk-string-functions -fchkp-use-fast-string-functions -D_GNU_SOURCE" } */ /* { dg-final { scan-tree-dump "mempcpy_nobnd_nochk" "chkpopt" } } */ -#include "string.h" +#define USE_GNU +#include "../../gcc.dg/strlenopt.h" void test (int *buf1, int *buf2, size_t len) { diff --git a/gcc/testsuite/gcc.target/i386/chkp-stropt-2.c b/gcc/testsuite/gcc.target/i386/chkp-stropt-2.c index cac0feaecbb..6a0c24ee887 100644 --- a/gcc/testsuite/gcc.target/i386/chkp-stropt-2.c +++ b/gcc/testsuite/gcc.target/i386/chkp-stropt-2.c @@ -2,7 +2,7 @@ /* { dg-options "-fcheck-pointer-bounds -mmpx -O2 -fdump-tree-chkpopt -fchkp-use-nochk-string-functions" } */ /* { dg-final { scan-tree-dump "memset_nochk" "chkpopt" } } */ -#include "string.h" +#include "../../gcc.dg/strlenopt.h" void test (int *buf1, int c, size_t len) { diff --git a/gcc/testsuite/gcc.target/i386/chkp-stropt-3.c b/gcc/testsuite/gcc.target/i386/chkp-stropt-3.c index 72ff3869f7b..310dec77456 100644 --- a/gcc/testsuite/gcc.target/i386/chkp-stropt-3.c +++ b/gcc/testsuite/gcc.target/i386/chkp-stropt-3.c @@ -2,7 +2,7 @@ /* { dg-options "-fcheck-pointer-bounds -mmpx -O2 -fdump-tree-chkpopt -fchkp-use-nochk-string-functions" } */ /* { dg-final { scan-tree-dump "memmove_nochk" "chkpopt" } } */ -#include "string.h" +#include "../../gcc.dg/strlenopt.h" void test (int *buf1, int *buf2, size_t len) { diff --git a/gcc/testsuite/gcc.target/i386/chkp-stropt-4.c b/gcc/testsuite/gcc.target/i386/chkp-stropt-4.c index 3faa58b0aea..34c61cc5b9c 100644 --- a/gcc/testsuite/gcc.target/i386/chkp-stropt-4.c +++ b/gcc/testsuite/gcc.target/i386/chkp-stropt-4.c @@ -3,7 +3,8 @@ /* { dg-options "-fcheck-pointer-bounds -mmpx -O2 -fdump-tree-chkpopt -fchkp-use-nochk-string-functions -D_GNU_SOURCE" } */ /* { dg-final { scan-tree-dump "mempcpy_nochk" "chkpopt" } } */ -#include "string.h" +#define USE_GNU +#include "../../gcc.dg/strlenopt.h" void test (int *buf1, int *buf2, size_t len) { diff --git a/gcc/testsuite/gcc.target/i386/chkp-stropt-5.c b/gcc/testsuite/gcc.target/i386/chkp-stropt-5.c index 02ad9ccc496..39850d62be8 100644 --- a/gcc/testsuite/gcc.target/i386/chkp-stropt-5.c +++ b/gcc/testsuite/gcc.target/i386/chkp-stropt-5.c @@ -2,7 +2,7 @@ /* { dg-options "-fcheck-pointer-bounds -mmpx -O2 -fdump-tree-chkpopt -fchkp-use-fast-string-functions" } */ /* { dg-final { scan-tree-dump "memcpy_nobnd" "chkpopt" } } */ -#include "string.h" +#include "../../gcc.dg/strlenopt.h" void test (int *buf1, int *buf2, size_t len) { diff --git a/gcc/testsuite/gcc.target/i386/chkp-stropt-6.c b/gcc/testsuite/gcc.target/i386/chkp-stropt-6.c index 6db5d83a0bc..06dcbfb9a25 100644 --- a/gcc/testsuite/gcc.target/i386/chkp-stropt-6.c +++ b/gcc/testsuite/gcc.target/i386/chkp-stropt-6.c @@ -2,7 +2,7 @@ /* { dg-options "-fcheck-pointer-bounds -mmpx -O2 -fdump-tree-chkpopt -fchkp-use-fast-string-functions" } */ /* { dg-final { scan-tree-dump "memset_nobnd" "chkpopt" } } */ -#include "string.h" +#include "../../gcc.dg/strlenopt.h" void test (int *buf1, int c, size_t len) { diff --git a/gcc/testsuite/gcc.target/i386/chkp-stropt-7.c b/gcc/testsuite/gcc.target/i386/chkp-stropt-7.c index 761e6263d86..40ded068f8e 100644 --- a/gcc/testsuite/gcc.target/i386/chkp-stropt-7.c +++ b/gcc/testsuite/gcc.target/i386/chkp-stropt-7.c @@ -2,7 +2,7 @@ /* { dg-options "-fcheck-pointer-bounds -mmpx -O2 -fdump-tree-chkpopt -fchkp-use-fast-string-functions" } */ /* { dg-final { scan-tree-dump "memmove_nobnd" "chkpopt" } } */ -#include "string.h" +#include "../../gcc.dg/strlenopt.h" void test (int *buf1, int *buf2, size_t len) { diff --git a/gcc/testsuite/gcc.target/i386/chkp-stropt-8.c b/gcc/testsuite/gcc.target/i386/chkp-stropt-8.c index 01bff6930a3..8fef8fdd85a 100644 --- a/gcc/testsuite/gcc.target/i386/chkp-stropt-8.c +++ b/gcc/testsuite/gcc.target/i386/chkp-stropt-8.c @@ -3,7 +3,8 @@ /* { dg-options "-fcheck-pointer-bounds -mmpx -O2 -fdump-tree-chkpopt -fchkp-use-fast-string-functions -D_GNU_SOURCE" } */ /* { dg-final { scan-tree-dump "mempcpy_nobnd" "chkpopt" } } */ -#include "string.h" +#define USE_GNU +#include "../../gcc.dg/strlenopt.h" void test (int *buf1, int *buf2, size_t len) { diff --git a/gcc/testsuite/gcc.target/i386/chkp-stropt-9.c b/gcc/testsuite/gcc.target/i386/chkp-stropt-9.c index b79d09633dd..bf26874e5a8 100644 --- a/gcc/testsuite/gcc.target/i386/chkp-stropt-9.c +++ b/gcc/testsuite/gcc.target/i386/chkp-stropt-9.c @@ -2,7 +2,7 @@ /* { dg-options "-fcheck-pointer-bounds -mmpx -O2 -fdump-tree-chkpopt -fchkp-use-fast-string-functions" } */ /* { dg-final { scan-tree-dump-not "memcpy_nobnd" "chkpopt" } } */ -#include "string.h" +#include "../../gcc.dg/strlenopt.h" void test (void *buf1, void *buf2, size_t len) { diff --git a/gcc/testsuite/gcc.target/i386/pr64411.C b/gcc/testsuite/gcc.target/i386/pr64411.C new file mode 100644 index 00000000000..55858fb48eb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr64411.C @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-Os -mcmodel=medium -fPIC -fschedule-insns -fselective-scheduling" } */ + +typedef __SIZE_TYPE__ size_t; + +extern "C" long strtol () + { return 0; } + +static struct { + void *sp[2]; +} info; + +union S813 +{ + void * c[5]; +} +s813; + +S813 a813[5]; +S813 check813 (S813, S813 *, S813); + +void checkx813 () +{ + __builtin_memset (&s813, '\0', sizeof (s813)); + __builtin_memset (&info, '\0', sizeof (info)); + check813 (s813, &a813[1], a813[2]); +} diff --git a/gcc/testsuite/gcc.target/i386/pr69888.c b/gcc/testsuite/gcc.target/i386/pr69888.c new file mode 100644 index 00000000000..498fe5acc2c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr69888.c @@ -0,0 +1,10 @@ +/* PR target/69888 */ +/* { dg-do compile } */ +/* { dg-options "-minline-all-stringops -mmemset-strategy=no_stringop:-1:noalign" } */ +/* { dg-additional-options "-march=geode" { target ia32 } } */ + +void +foo (char *p) +{ + __builtin_memset (p, 0, 32); +} diff --git a/gcc/testsuite/gcc.target/i386/pr69891.c b/gcc/testsuite/gcc.target/i386/pr69891.c new file mode 100644 index 00000000000..2c5e86372e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr69891.c @@ -0,0 +1,30 @@ +/* PR rtl-optimization/69891 */ +/* { dg-do run } */ +/* { dg-options "-O -fno-tree-fre -mstringop-strategy=libcall -Wno-psabi" } */ +/* { dg-additional-options "-mno-sse" { target ia32 } } */ + +typedef unsigned short A; +typedef unsigned short B __attribute__ ((vector_size (32))); +typedef unsigned int C; +typedef unsigned int D __attribute__ ((vector_size (32))); +typedef unsigned long long E; +typedef unsigned long long F __attribute__ ((vector_size (32))); + +__attribute__((noinline, noclone)) unsigned +foo(D a, B b, D c, F d) +{ + b /= (B) {1, -c[0]} | 1; + c[0] |= 7; + a %= c | 1; + c ^= c; + return a[0] + b[15] + c[0] + d[3]; +} + +int +main () +{ + unsigned x = foo ((D) {}, (B) {}, (D) {}, (F) {}); + if (x != 0) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr70028.c b/gcc/testsuite/gcc.target/i386/pr70028.c new file mode 100644 index 00000000000..c071aad7403 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr70028.c @@ -0,0 +1,19 @@ +/* PR target/70028 */ +/* { dg-do assemble { target avx512bw } } */ +/* { dg-require-effective-target int128 } */ +/* { dg-require-effective-target masm_intel } */ +/* { dg-options "-O2 -fno-forward-propagate -mavx512bw -masm=intel" } */ + +typedef unsigned short A; +typedef int B __attribute__ ((vector_size (32))); +typedef unsigned __int128 C; +typedef __int128 D __attribute__ ((vector_size (32))); + +C +foo (A a, int b, unsigned c, C d, A e, unsigned f, B g, D h) +{ + g[1] ^= (A) ~ a; + a ^= (unsigned) g[0]; + h %= (D) h | 1; + return a + b + c + d + e + g[0] + g[1] + h[1]; +} diff --git a/gcc/testsuite/gcc.target/i386/pr70062.c b/gcc/testsuite/gcc.target/i386/pr70062.c new file mode 100644 index 00000000000..e5cb854f2ee --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr70062.c @@ -0,0 +1,11 @@ +/* PR target/70062 */ +/* { dg-options "-minline-all-stringops -minline-stringops-dynamically -mmemcpy-strategy=libcall:-1:noalign -Wno-psabi" } */ +/* { dg-additional-options "-mtune=k6-2" { target ia32 } } */ + +typedef int V __attribute__ ((vector_size (32))); + +V +foo (V x) +{ + return (V) { x[0] }; +} diff --git a/gcc/testsuite/gcc.target/i386/pr70293.c b/gcc/testsuite/gcc.target/i386/pr70293.c new file mode 100644 index 00000000000..4510166ead8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr70293.c @@ -0,0 +1,38 @@ +/* PR target/70293 */ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-mtune=westmere -mavx512vl -O2" } */ + +typedef short __v8hi __attribute__((__vector_size__(16))); +typedef int __v8hu __attribute__((__vector_size__(16))); +typedef long __m128i __attribute__((__vector_size__(16))); +__m128i _mm_madd_epi16___B, _mm_mullo_epi16___A, + scaled_bilinear_scanline_sse2_8888_8_8888_OVER_xmm_b, + scaled_bilinear_scanline_sse2_8888_8_8888_OVER___trans_tmp_16, + scaled_bilinear_scanline_sse2_8888_8_8888_OVER___trans_tmp_13; +int _mm_srli_epi16___B, scaled_bilinear_scanline_sse2_8888_8_8888_OVER_m, + scaled_bilinear_scanline_sse2_8888_8_8888_OVER_dst, + scaled_bilinear_scanline_sse2_8888_8_8888_OVER_wt; +__m128i _mm_set_epi16(); +void _mm_cvtsi128_si32(); +void +scaled_bilinear_scanline_sse2_8888_8_8888_OVER(int p1) { + __m128i __trans_tmp_12, __trans_tmp_6, __trans_tmp_5, xmm_x = _mm_set_epi16(); + int mask; + __trans_tmp_5 = (__m128i){scaled_bilinear_scanline_sse2_8888_8_8888_OVER_wt}; + __trans_tmp_6 = (__m128i)(__v8hi){p1, p1, p1, p1, p1, p1, p1, p1}; + while (scaled_bilinear_scanline_sse2_8888_8_8888_OVER_dst) { + scaled_bilinear_scanline_sse2_8888_8_8888_OVER_m = mask++; + if (scaled_bilinear_scanline_sse2_8888_8_8888_OVER_m) { + __trans_tmp_12 = + (__m128i)((__v8hu)_mm_mullo_epi16___A * (__v8hu)__trans_tmp_6); + scaled_bilinear_scanline_sse2_8888_8_8888_OVER_xmm_b = __trans_tmp_12; + scaled_bilinear_scanline_sse2_8888_8_8888_OVER___trans_tmp_13 = + (__m128i)__builtin_ia32_psrlwi128((__v8hi)xmm_x, _mm_srli_epi16___B); + scaled_bilinear_scanline_sse2_8888_8_8888_OVER___trans_tmp_16 = + (__m128i)__builtin_ia32_pmaddwd128((__v8hi)__trans_tmp_5, + (__v8hi)_mm_madd_epi16___B); + _mm_cvtsi128_si32(); + } + } +} diff --git a/gcc/testsuite/gcc.target/i386/pr70325.c b/gcc/testsuite/gcc.target/i386/pr70325.c new file mode 100644 index 00000000000..e2b9342658c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr70325.c @@ -0,0 +1,12 @@ +/* PR target/70325 */ +/* { dg-do compile } */ +/* { dg-options "-mavx512vl -O2" } */ + +typedef char C __attribute((__vector_size__(32))); +typedef int I __attribute((__vector_size__(32))); + +void +f(int a,I b) +{ + __builtin_ia32_storedquqi256_mask((C*)f,(C)b,a); /* { dg-warning "implicit declaration of function" } */ +} diff --git a/gcc/testsuite/gcc.target/i386/pr70327.c b/gcc/testsuite/gcc.target/i386/pr70327.c new file mode 100644 index 00000000000..035bb68d458 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr70327.c @@ -0,0 +1,12 @@ +/* PR target/70327 */ +/* { dg-do compile } */ +/* { dg-require-effective-target int128 } */ +/* { dg-options "-mavx512f" } */ + +typedef unsigned __int128 v4ti __attribute__ ((vector_size (64))); + +void +foo (v4ti v) +{ + foo(v); +} diff --git a/gcc/testsuite/gcc.target/i386/pr70406.c b/gcc/testsuite/gcc.target/i386/pr70406.c new file mode 100644 index 00000000000..b75a5af450e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr70406.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O -mtune=pentium2 -mavx512f" } */ + +typedef int v4si __attribute__ ((vector_size (16))); + +unsigned +foo (unsigned char i, unsigned x, v4si u, v4si v, v4si w) +{ + i &= (unsigned)~x; + v <<= w[x]; + return i + u[x] + v[i]; +} diff --git a/gcc/testsuite/gcc.target/i386/pr70453.c b/gcc/testsuite/gcc.target/i386/pr70453.c new file mode 100644 index 00000000000..2ff1fbb804d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr70453.c @@ -0,0 +1,18 @@ +/* PR target/70453 */ +/* { dg-do assemble { target { lp64 } } } */ +/* { dg-require-effective-target avx512vbmi } */ +/* { dg-options "-Og -fschedule-insns -mavx512vbmi" } */ + + +typedef char v64u8 __attribute__ ((vector_size (64))); +typedef short v64u16 __attribute__ ((vector_size (64))); +typedef __int128 v64u128 __attribute__ ((vector_size (64))); + +int +foo(v64u8 v64u8_0, v64u16 v64u16_0, v64u128 v64u128_0) +{ + v64u128_0 /= (v64u128){ v64u8_0[28] } | 0x1424171b0c; + v64u8_0 %= (v64u8){ v64u16_0[25], v64u128_0[1]} ; + v64u128_0 %= (v64u128){ v64u16_0[8] }; + return v64u8_0[0] + v64u8_0[1] + v64u16_0[0] + v64u128_0[0]; +} diff --git a/gcc/testsuite/gcc.target/i386/pr70510.c b/gcc/testsuite/gcc.target/i386/pr70510.c new file mode 100644 index 00000000000..fdad97a16f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr70510.c @@ -0,0 +1,14 @@ +/* PR target/70510 */ +/* { dg-do assemble { target avx512bw } } */ +/* { dg-require-effective-target masm_intel } */ +/* { dg-options "-Og -mavx512bw -masm=intel" } */ + +typedef int V __attribute__ ((vector_size (64))); + +V +foo (V u, V v) +{ + v[0] |= v[u[0]]; + u /= ((V)v)[0]; + return u; +} diff --git a/gcc/testsuite/gcc.target/i386/pr70525.c b/gcc/testsuite/gcc.target/i386/pr70525.c new file mode 100644 index 00000000000..78ba752f94b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr70525.c @@ -0,0 +1,32 @@ +/* PR target/70525 */ +/* { dg-do assemble { target avx512bw } } */ +/* { dg-options "-O2 -mavx512bw -mno-avx512vl" } */ + +typedef char v64qi __attribute__ ((vector_size (64))); +typedef short v32hi __attribute__ ((vector_size (64))); +typedef int v16si __attribute__ ((vector_size (64))); +typedef long long v8di __attribute__ ((vector_size (64))); + +v64qi +f1 (v64qi x, v64qi y) +{ + return x & ~y; +} + +v32hi +f2 (v32hi x, v32hi y) +{ + return x & ~y; +} + +v16si +f3 (v16si x, v16si y) +{ + return x & ~y; +} + +v8di +f4 (v8di x, v8di y) +{ + return x & ~y; +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-36.c b/gcc/testsuite/gcc.target/powerpc/altivec-36.c new file mode 100644 index 00000000000..ce9e6a36b5d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-36.c @@ -0,0 +1,46 @@ +/* PR target/70296 */ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -std=gnu11" } */ + +#define c(x) x +#define f(x) +#define i int +#define k +typedef int vector; +typedef vector int V; +vector int a; +vector b; +vector c(int) d; +vector c(e); +vector c; +vector f(int) int g; +vector f(int) h; +vector i j; +vector k int l; +vector k m; +#define int(x) x +vector int n; +vector int(int) o; +vector int(r); +#undef int + +void +foo () +{ + V *p; + p = &a; + p = &d; + p = &g; + p = &j; + p = &l; + p = &n; + p = &o; + int *q; + q = &b; + q = &e; + q = &c; + q = &h; + q = &m; + q = &r; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr69969.c b/gcc/testsuite/gcc.target/powerpc/pr69969.c new file mode 100644 index 00000000000..1ca2c7581ef --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr69969.c @@ -0,0 +1,7 @@ +/* PR target/69969 */ +/* { dg-do compile } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-options "-mcpu=power8" } */ + +int bar (int x) { return x; } +__attribute__((__target__("no-vsx"))) int foo (int x) { return x; } /* { dg-bogus "-mallow-movmisalign requires -mvsx" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr70117.c b/gcc/testsuite/gcc.target/powerpc/pr70117.c new file mode 100644 index 00000000000..f1fdedb6c59 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr70117.c @@ -0,0 +1,92 @@ +/* { dg-do run { target { powerpc*-*-linux* powerpc*-*-darwin* powerpc*-*-aix* rs6000-*-* } } } */ +/* { dg-options "-std=c99 -mlong-double-128 -O2" } */ + +#include <float.h> + +union gl_long_double_union +{ + struct { double hi; double lo; } dd; + long double ld; +}; + +/* This is gnulib's LDBL_MAX which, being 107 bits in precision, is + slightly larger than gcc's 106 bit precision LDBL_MAX. */ +volatile union gl_long_double_union gl_LDBL_MAX = + { { DBL_MAX, DBL_MAX / (double)134217728UL / (double)134217728UL } }; + +volatile double min_denorm = 0x1p-1074; +volatile double ld_low = 0x1p-969; +volatile double dinf = 1.0/0.0; +volatile double dnan = 0.0/0.0; + +int +main (void) +{ + long double ld; + + ld = gl_LDBL_MAX.ld; + if (__builtin_isinfl (ld)) + __builtin_abort (); + ld = -gl_LDBL_MAX.ld; + if (__builtin_isinfl (ld)) + __builtin_abort (); + + ld = gl_LDBL_MAX.ld; + if (!__builtin_isfinite (ld)) + __builtin_abort (); + ld = -gl_LDBL_MAX.ld; + if (!__builtin_isfinite (ld)) + __builtin_abort (); + + ld = ld_low; + if (!__builtin_isnormal (ld)) + __builtin_abort (); + ld = -ld_low; + if (!__builtin_isnormal (ld)) + __builtin_abort (); + + ld = -min_denorm; + ld += ld_low; + if (__builtin_isnormal (ld)) + __builtin_abort (); + ld = min_denorm; + ld -= ld_low; + if (__builtin_isnormal (ld)) + __builtin_abort (); + + ld = 0.0; + if (__builtin_isnormal (ld)) + __builtin_abort (); + ld = -0.0; + if (__builtin_isnormal (ld)) + __builtin_abort (); + + ld = LDBL_MAX; + if (!__builtin_isnormal (ld)) + __builtin_abort (); + ld = -LDBL_MAX; + if (!__builtin_isnormal (ld)) + __builtin_abort (); + + ld = gl_LDBL_MAX.ld; + if (!__builtin_isnormal (ld)) + __builtin_abort (); + ld = -gl_LDBL_MAX.ld; + if (!__builtin_isnormal (ld)) + __builtin_abort (); + + ld = dinf; + if (__builtin_isnormal (ld)) + __builtin_abort (); + ld = -dinf; + if (__builtin_isnormal (ld)) + __builtin_abort (); + + ld = dnan; + if (__builtin_isnormal (ld)) + __builtin_abort (); + ld = -dnan; + if (__builtin_isnormal (ld)) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/sh/torture/pr70416.c b/gcc/testsuite/gcc.target/sh/torture/pr70416.c new file mode 100644 index 00000000000..b1123bee029 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/torture/pr70416.c @@ -0,0 +1,136 @@ +/* { dg-additional-options "-std=gnu99 -fpic" } */ +/* { dg-do compile } */ + +typedef unsigned long VALUE; +typedef unsigned long ID; + +typedef struct rb_callable_method_entry_struct +{ + ID called_id; + const VALUE owner; +} rb_callable_method_entry_t; + +typedef struct rb_iseq_struct rb_iseq_t; + +struct __jmp_buf_tag { int xx; }; +typedef struct __jmp_buf_tag jmp_buf[1]; + +struct rb_iseq_struct +{ + const struct iseq_catch_table *catch_table; +}; + +typedef struct rb_control_frame_struct +{ + const VALUE *pc; + VALUE *sp; + const rb_iseq_t *iseq; + VALUE flag; + VALUE *ep; +} rb_control_frame_t; + +typedef jmp_buf rb_jmpbuf_t; +struct rb_vm_tag +{ + rb_jmpbuf_t buf; +}rb_ensure_list_t; + +typedef struct rb_thread_struct +{ + rb_control_frame_t *cfp; + struct rb_vm_tag *tag; +} rb_thread_t; + +struct iseq_catch_table_entry +{ + const rb_iseq_t *iseq; +}; + +struct iseq_catch_table +{ + unsigned int size; +}; + +extern unsigned long long __sdt_unsp; +extern unsigned short ruby_cmethod__return_semaphore; + +struct ruby_dtrace_method_hook_args +{ + const char *classname; + const char *methodname; + const char *filename; + int line_no; +}; + +int ruby_th_dtrace_setup(rb_thread_t *th, VALUE klass, ID id, struct ruby_dtrace_method_hook_args *args); +int rb_threadptr_tag_state (rb_thread_t *th); +VALUE vm_exec_core (rb_thread_t *th, VALUE initial); +const rb_callable_method_entry_t *rb_vm_frame_method_entry (const rb_control_frame_t *cfp); + +struct vm_throw_data; +const rb_control_frame_t * THROW_DATA_CATCH_FRAME(const struct vm_throw_data *obj); +rb_control_frame_t * vm_push_frame(rb_thread_t *th, const rb_iseq_t *iseq, VALUE type, VALUE self, VALUE specval, VALUE cref_or_me, const VALUE *pc, VALUE *sp, int local_size, int stack_max); + + +VALUE vm_exec(rb_thread_t *th) +{ + int state; + VALUE result; + VALUE initial = 0; + struct vm_throw_data *err; + rb_thread_t * const _th = (th); + struct rb_vm_tag _tag; + + if ((state = (__builtin_setjmp((_tag.buf)) ? rb_threadptr_tag_state((_th)) : ((void)(_th->tag = &_tag), 0))) == 0) + { + result = vm_exec_core(th, initial); + } + else + { + unsigned int i; + const struct iseq_catch_table_entry *entry; + const struct iseq_catch_table *ct; + unsigned long epc, cont_pc, cont_sp; + const rb_iseq_t *catch_iseq; + rb_control_frame_t *cfp; + const rb_control_frame_t *escape_cfp; + + while (th->cfp->pc == 0 || th->cfp->iseq == 0) + { + if (ruby_cmethod__return_semaphore) + { + struct ruby_dtrace_method_hook_args args; + if (ruby_th_dtrace_setup(th, rb_vm_frame_method_entry(th->cfp)->owner, rb_vm_frame_method_entry(th->cfp)->called_id, &args)) + { + __asm__ __volatile__ ( + ".asciz \"%n[_SDT_S1]@%[_SDT_A1] %n[_SDT_S2]@%[_SDT_A2] %n[_SDT_S3]@%[_SDT_A3] %n[_SDT_S4]@%[_SDT_A4]\"\n" + : + : [_SDT_S1] "n" (((!__extension__ (__builtin_constant_p ((((unsigned long long) (__typeof (__builtin_choose_expr (((__builtin_classify_type ( args.classname ) + 3) & -4) == 4, ( args.classname ), 0U))) __sdt_unsp) & ((unsigned long long)1 << (sizeof (unsigned long long) * 8 - 1))) == 0) || (__typeof (__builtin_choose_expr (((__builtin_classify_type ( args.classname ) + 3) & -4) == 4, ( args.classname ), 0U))) -1 > (__typeof (__builtin_choose_expr (((__builtin_classify_type ( args.classname ) + 3) & -4) == 4, ( args.classname ), 0U))) 0)) ? 1 : -1) * (int) ((__builtin_classify_type ( args.classname ) == 14 || __builtin_classify_type ( args.classname ) == 5) ? sizeof (void *) : sizeof ( args.classname ))), + [_SDT_A1] "nor" (( args.classname )), + [_SDT_S2] "n" (((!__extension__ (__builtin_constant_p ((((unsigned long long) (__typeof (__builtin_choose_expr (((__builtin_classify_type ( args.methodname ) + 3) & -4) == 4, ( args.methodname ), 0U))) __sdt_unsp) & ((unsigned long long)1 << (sizeof (unsigned long long) * 8 - 1))) == 0) || (__typeof (__builtin_choose_expr (((__builtin_classify_type ( args.methodname ) + 3) & -4) == 4, ( args.methodname ), 0U))) -1 > (__typeof (__builtin_choose_expr (((__builtin_classify_type ( args.methodname ) + 3) & -4) == 4, ( args.methodname ), 0U))) 0)) ? 1 : -1) * (int) ((__builtin_classify_type ( args.methodname ) == 14 || __builtin_classify_type ( args.methodname ) == 5) ? sizeof (void *) : sizeof ( args.methodname ))), + [_SDT_A2] "nor" (( args.methodname )), + [_SDT_S3] "n" (((!__extension__ (__builtin_constant_p ((((unsigned long long) (__typeof (__builtin_choose_expr (((__builtin_classify_type ( args.filename ) + 3) & -4) == 4, ( args.filename ), 0U))) __sdt_unsp) & ((unsigned long long)1 << (sizeof (unsigned long long) * 8 - 1))) == 0) || (__typeof (__builtin_choose_expr (((__builtin_classify_type ( args.filename ) + 3) & -4) == 4, ( args.filename ), 0U))) -1 > (__typeof (__builtin_choose_expr (((__builtin_classify_type ( args.filename ) + 3) & -4) == 4, ( args.filename ), 0U))) 0)) ? 1 : -1) * (int) ((__builtin_classify_type ( args.filename ) == 14 || __builtin_classify_type ( args.filename ) == 5) ? sizeof (void *) : sizeof ( args.filename ))), + [_SDT_A3] "nor" (( args.filename )), + [_SDT_S4] "n" (((!__extension__ (__builtin_constant_p ((((unsigned long long) (__typeof (__builtin_choose_expr (((__builtin_classify_type ( args.line_no ) + 3) & -4) == 4, ( args.line_no ), 0U))) __sdt_unsp) & ((unsigned long long)1 << (sizeof (unsigned long long) * 8 - 1))) == 0) || (__typeof (__builtin_choose_expr (((__builtin_classify_type ( args.line_no ) + 3) & -4) == 4, ( args.line_no ), 0U))) -1 > (__typeof (__builtin_choose_expr (((__builtin_classify_type ( args.line_no ) + 3) & -4) == 4, ( args.line_no ), 0U))) 0)) ? 1 : -1) * (int) ((__builtin_classify_type ( args.line_no ) == 14 || __builtin_classify_type ( args.line_no ) == 5) ? sizeof (void *) : sizeof ( args.line_no ))), + [_SDT_A4] "nor" (( args.line_no )) + ); + } + } + } + + if (cfp == escape_cfp && !(((cfp)->flag & 0x0200) != 0)) + catch_iseq = entry->iseq; + + if (state == 6) + { + escape_cfp = THROW_DATA_CATCH_FRAME(err); + + if (ct) + for (i = 0; i < ct->size; i++) { } + } + else + ct = cfp->iseq->catch_table; + + vm_push_frame(th, catch_iseq, 0xb1, 0, 1, 0, 0, 0, 5, 123); + } +} diff --git a/gcc/testsuite/gcc.target/sparc/20151219-1.c b/gcc/testsuite/gcc.target/sparc/20151219-1.c index efe720af6cd..e331d3eecdb 100644 --- a/gcc/testsuite/gcc.target/sparc/20151219-1.c +++ b/gcc/testsuite/gcc.target/sparc/20151219-1.c @@ -2,6 +2,7 @@ /* Reported by Sebastian Huber <sebastian.huber@embedded-brains.de> */ /* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mtune=supersparc" } */ typedef unsigned int size_t; diff --git a/gcc/testsuite/gfortran.dg/coarray_allocate_6.f08 b/gcc/testsuite/gfortran.dg/coarray_allocate_6.f08 new file mode 100644 index 00000000000..2fdd4c128ef --- /dev/null +++ b/gcc/testsuite/gfortran.dg/coarray_allocate_6.f08 @@ -0,0 +1,27 @@ +! { dg-do run } +! { dg-options "-fcoarray=single -fdump-tree-original" } + +! Contributed by Tobias Burnus <burnus@gcc.gnu.org> +! Test fix for pr65795. + +implicit none + +type t2 + integer, allocatable :: x +end type t2 + +type t3 + type(t2), allocatable :: caf[:] +end type t3 + +!type(t3), save, target :: c, d +type(t3), target :: c, d +integer :: stat + +allocate(c%caf[*], stat=stat) +end + +! Besides checking that the executable does not crash anymore, check +! that the cause has been remove. +! { dg-final { scan-tree-dump-not "c.caf.x = 0B" "original" } } + diff --git a/gcc/testsuite/gfortran.dg/deferred_character_16.f90 b/gcc/testsuite/gfortran.dg/deferred_character_16.f90 new file mode 100644 index 00000000000..27fb11249a8 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/deferred_character_16.f90 @@ -0,0 +1,24 @@ +! { dg-do run } + +program truc +implicit none + +type t_env_table + character(len=:), allocatable :: key +end type + +type(t_env_table), dimension(:), allocatable :: environment_table + +character(len=:), allocatable :: s + +allocate(environment_table(1)) +environment_table(1)%key='tt' + +allocate(s, source=environment_table(1)%key) + +if ( .not. allocated(s) ) call abort() +if ( s /= "tt" ) call abort() +if ( len(s) /= 2 ) call abort() +!print *, 's:"', s, '" derived:"',environment_table(1)%key,'"' + +end program diff --git a/gcc/testsuite/gfortran.dg/deferred_character_17.f90 b/gcc/testsuite/gfortran.dg/deferred_character_17.f90 new file mode 100644 index 00000000000..f5931acd3c7 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/deferred_character_17.f90 @@ -0,0 +1,19 @@ +! { dg-do run } +! PR70592 dynamically-allocated character array +! Contributed by Peter Knowles <KnowlesPJ@Cardiff.ac.uk> +! +PROGRAM main + character(len=7) :: res + CHARACTER(len=:), DIMENSION(:), POINTER :: cp + INTEGER :: i + ALLOCATE(CHARACTER(len=1) :: cp(1:6)) + if (SIZE(cp) /= 6 .or. LBOUND(cp,1) /= 1 .or. UBOUND(cp,1) /= 6) call abort() + cp(1)='1' + cp(2)='2' + cp(3)='3' + cp(4)='4' + cp(5)='5' + cp(6)='6' + write (res, *) cp + if (res /= ' 123456') call abort() +END PROGRAM main diff --git a/gcc/testsuite/gfortran.dg/fmt_pf.f90 b/gcc/testsuite/gfortran.dg/fmt_pf.f90 new file mode 100644 index 00000000000..6cefa86e4a8 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/fmt_pf.f90 @@ -0,0 +1,226 @@ +! { dg-do run } +! PR70235 Incorrect output with PF format. +! Test case provided by Antoine Gardeux. +program pr70235 +use ISO_FORTRAN_ENV + implicit none + integer, parameter :: j(size(real_kinds)+4)=[REAL_KINDS, [4, 4, 4, 4]] + logical :: l_skip(4) = .false. + integer :: i + integer :: n_tst = 0, n_cnt = 0, n_skip = 0 + character(len=20) :: s, s1 + +! Check that the default rounding mode is to nearest and to even on tie. + do i=1,size(real_kinds) + if (i == 1) then + write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(1)), & + real(9.49999905,kind=j(1)), & + real(9.5,kind=j(1)), real(8.5,kind=j(1)) + write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(1)), & + real(98765.0,kind=j(1)) + else if (i == 2) then + write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(2)), & + real(9.49999905,kind=j(2)), & + real(9.5,kind=j(2)), real(8.5,kind=j(2)) + write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(2)), & + real(98765.0,kind=j(2)) + else if (i == 3) then + write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(3)), & + real(9.49999905,kind=j(3)), & + real(9.5,kind=j(3)), real(8.5,kind=j(3)) + write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(3)), & + real(98765.0,kind=j(3)) + else if (i == 4) then + write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(4)), & + real(9.49999905,kind=j(4)), & + real(9.5,kind=j(4)), real(8.5,kind=j(4)) + write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(4)), & + real(98765.0,kind=j(4)) + end if + if (s /= '-9.5 9.5 10. 8.' .or. s1 /= ' 987.4E+03 98.76E+03') then + l_skip(i) = .true. +! print "('Unsupported rounding for real(',i0,')')", j(i) + end if + end do + + +! Original test. + call checkfmt("(-6PF8.3)", 1.0e4, " 0.010") + call checkfmt("(-6PF8.3)", 0.0, " 0.000") + +! Test for the bug in comment 6. + call checkfmt("(-8pf18.3)", 643.125, " 0.000") + call checkfmt("(-7pf18.3)", 643.125, " 0.000") + call checkfmt("(-6pf18.3)", 643.125, " 0.001") + call checkfmt("(-5pf18.3)", 643.125, " 0.006") + call checkfmt("(-4pf18.3)", 643.125, " 0.064") + call checkfmt("(-3pf18.3)", 643.125, " 0.643") + call checkfmt("(-2pf18.3)", 643.125, " 6.431") + call checkfmt("(-1pf18.3)", 643.125, " 64.312") + call checkfmt("( 0pf18.3)", 643.125, " 643.125") + + call checkfmt("(ru,-8pf18.3)", 643.125, " 0.001") + call checkfmt("(ru,-7pf18.3)", 643.125, " 0.001") + call checkfmt("(ru,-6pf18.3)", 643.125, " 0.001") + call checkfmt("(ru,-5pf18.3)", 643.125, " 0.007") + call checkfmt("(ru,-4pf18.3)", 643.125, " 0.065") + call checkfmt("(ru,-3pf18.3)", 643.125, " 0.644") + call checkfmt("(ru,-2pf18.3)", 643.125, " 6.432") + call checkfmt("(ru,-1pf18.3)", 643.125, " 64.313") + call checkfmt("(ru, 0pf18.3)", 643.125, " 643.125") + + call checkfmt("(rd,-8pf18.3)", 643.125, " 0.000") + call checkfmt("(rd,-7pf18.3)", 643.125, " 0.000") + call checkfmt("(rd,-6pf18.3)", 643.125, " 0.000") + call checkfmt("(rd,-5pf18.3)", 643.125, " 0.006") + call checkfmt("(rd,-4pf18.3)", 643.125, " 0.064") + call checkfmt("(rd,-3pf18.3)", 643.125, " 0.643") + call checkfmt("(rd,-2pf18.3)", 643.125, " 6.431") + call checkfmt("(rd,-1pf18.3)", 643.125, " 64.312") + call checkfmt("(rd, 0pf18.3)", 643.125, " 643.125") + + call checkfmt("(rz,-8pf18.3)", 643.125, " 0.000") + call checkfmt("(rz,-7pf18.3)", 643.125, " 0.000") + call checkfmt("(rz,-6pf18.3)", 643.125, " 0.000") + call checkfmt("(rz,-5pf18.3)", 643.125, " 0.006") + call checkfmt("(rz,-4pf18.3)", 643.125, " 0.064") + call checkfmt("(rz,-3pf18.3)", 643.125, " 0.643") + call checkfmt("(rz,-2pf18.3)", 643.125, " 6.431") + call checkfmt("(rz,-1pf18.3)", 643.125, " 64.312") + call checkfmt("(rz, 0pf18.3)", 643.125, " 643.125") + + call checkfmt("(rc,-8pf18.3)", 643.125, " 0.000") + call checkfmt("(rc,-7pf18.3)", 643.125, " 0.000") + call checkfmt("(rc,-6pf18.3)", 643.125, " 0.001") + call checkfmt("(rc,-5pf18.3)", 643.125, " 0.006") + call checkfmt("(rc,-4pf18.3)", 643.125, " 0.064") + call checkfmt("(rc,-3pf18.3)", 643.125, " 0.643") + call checkfmt("(rc,-2pf18.3)", 643.125, " 6.431") + call checkfmt("(rc,-1pf18.3)", 643.125, " 64.313") + call checkfmt("(rc, 0pf18.3)", 643.125, " 643.125") + + call checkfmt("(rn,-8pf18.3)", 643.125, " 0.000") + call checkfmt("(rn,-7pf18.3)", 643.125, " 0.000") + call checkfmt("(rn,-6pf18.3)", 643.125, " 0.001") + call checkfmt("(rn,-5pf18.3)", 643.125, " 0.006") + call checkfmt("(rn,-4pf18.3)", 643.125, " 0.064") + call checkfmt("(rn,-3pf18.3)", 643.125, " 0.643") + call checkfmt("(rn,-2pf18.3)", 643.125, " 6.431") + call checkfmt("(rn,-1pf18.3)", 643.125, " 64.312") + call checkfmt("(rn, 0pf18.3)", 643.125, " 643.125") + + call checkfmt("(rp,-8pf18.3)", 643.125, " 0.000") + call checkfmt("(rp,-7pf18.3)", 643.125, " 0.000") + call checkfmt("(rp,-6pf18.3)", 643.125, " 0.001") + call checkfmt("(rp,-5pf18.3)", 643.125, " 0.006") + call checkfmt("(rp,-4pf18.3)", 643.125, " 0.064") + call checkfmt("(rp,-3pf18.3)", 643.125, " 0.643") + call checkfmt("(rp,-2pf18.3)", 643.125, " 6.431") + call checkfmt("(rp,-1pf18.3)", 643.125, " 64.312") + call checkfmt("(rp, 0pf18.3)", 643.125, " 643.125") + + call checkfmt("(-8pf18.3)", -643.125, " -0.000") + call checkfmt("(-7pf18.3)", -643.125, " -0.000") + call checkfmt("(-6pf18.3)", -643.125, " -0.001") + call checkfmt("(-5pf18.3)", -643.125, " -0.006") + call checkfmt("(-4pf18.3)", -643.125, " -0.064") + call checkfmt("(-3pf18.3)", -643.125, " -0.643") + call checkfmt("(-2pf18.3)", -643.125, " -6.431") + call checkfmt("(-1pf18.3)", -643.125, " -64.312") + call checkfmt("( 0pf18.3)", -643.125, " -643.125") + + call checkfmt("(ru,-8pf18.3)", -643.125, " -0.000") + call checkfmt("(ru,-7pf18.3)", -643.125, " -0.000") + call checkfmt("(ru,-6pf18.3)", -643.125, " -0.000") + call checkfmt("(ru,-5pf18.3)", -643.125, " -0.006") + call checkfmt("(ru,-4pf18.3)", -643.125, " -0.064") + call checkfmt("(ru,-3pf18.3)", -643.125, " -0.643") + call checkfmt("(ru,-2pf18.3)", -643.125, " -6.431") + call checkfmt("(ru,-1pf18.3)", -643.125, " -64.312") + call checkfmt("(ru, 0pf18.3)", -643.125, " -643.125") + + call checkfmt("(rd,-8pf18.3)", -643.125, " -0.001") + call checkfmt("(rd,-7pf18.3)", -643.125, " -0.001") + call checkfmt("(rd,-6pf18.3)", -643.125, " -0.001") + call checkfmt("(rd,-5pf18.3)", -643.125, " -0.007") + call checkfmt("(rd,-4pf18.3)", -643.125, " -0.065") + call checkfmt("(rd,-3pf18.3)", -643.125, " -0.644") + call checkfmt("(rd,-2pf18.3)", -643.125, " -6.432") + call checkfmt("(rd,-1pf18.3)", -643.125, " -64.313") + call checkfmt("(rd, 0pf18.3)", -643.125, " -643.125") + + call checkfmt("(rz,-8pf18.3)", -643.125, " -0.000") + call checkfmt("(rz,-7pf18.3)", -643.125, " -0.000") + call checkfmt("(rz,-6pf18.3)", -643.125, " -0.000") + call checkfmt("(rz,-5pf18.3)", -643.125, " -0.006") + call checkfmt("(rz,-4pf18.3)", -643.125, " -0.064") + call checkfmt("(rz,-3pf18.3)", -643.125, " -0.643") + call checkfmt("(rz,-2pf18.3)", -643.125, " -6.431") + call checkfmt("(rz,-1pf18.3)", -643.125, " -64.312") + call checkfmt("(rz, 0pf18.3)", -643.125, " -643.125") + + call checkfmt("(rc,-8pf18.3)", -643.125, " -0.000") + call checkfmt("(rc,-7pf18.3)", -643.125, " -0.000") + call checkfmt("(rc,-6pf18.3)", -643.125, " -0.001") + call checkfmt("(rc,-5pf18.3)", -643.125, " -0.006") + call checkfmt("(rc,-4pf18.3)", -643.125, " -0.064") + call checkfmt("(rc,-3pf18.3)", -643.125, " -0.643") + call checkfmt("(rc,-2pf18.3)", -643.125, " -6.431") + call checkfmt("(rc,-1pf18.3)", -643.125, " -64.313") + call checkfmt("(rc, 0pf18.3)", -643.125, " -643.125") + + call checkfmt("(rn,-8pf18.3)", -643.125, " -0.000") + call checkfmt("(rn,-7pf18.3)", -643.125, " -0.000") + call checkfmt("(rn,-6pf18.3)", -643.125, " -0.001") + call checkfmt("(rn,-5pf18.3)", -643.125, " -0.006") + call checkfmt("(rn,-4pf18.3)", -643.125, " -0.064") + call checkfmt("(rn,-3pf18.3)", -643.125, " -0.643") + call checkfmt("(rn,-2pf18.3)", -643.125, " -6.431") + call checkfmt("(rn,-1pf18.3)", -643.125, " -64.312") + call checkfmt("(rn, 0pf18.3)", -643.125, " -643.125") + + call checkfmt("(rp,-8pf18.3)", -643.125, " -0.000") + call checkfmt("(rp,-7pf18.3)", -643.125, " -0.000") + call checkfmt("(rp,-6pf18.3)", -643.125, " -0.001") + call checkfmt("(rp,-5pf18.3)", -643.125, " -0.006") + call checkfmt("(rp,-4pf18.3)", -643.125, " -0.064") + call checkfmt("(rp,-3pf18.3)", -643.125, " -0.643") + call checkfmt("(rp,-2pf18.3)", -643.125, " -6.431") + call checkfmt("(rp,-1pf18.3)", -643.125, " -64.312") + call checkfmt("(rp, 0pf18.3)", -643.125, " -643.125") + + ! print *, n_tst, n_cnt, n_skip + if (n_cnt /= 0) call abort + if (all(.not. l_skip)) print *, "All kinds rounded to nearest" + +contains + subroutine checkfmt(fmt, x, cmp) + implicit none + integer :: i + character(len=*), intent(in) :: fmt + real, intent(in) :: x + character(len=*), intent(in) :: cmp + do i=1,size(real_kinds) + if (i == 1) then + write(s, fmt) real(x,kind=j(1)) + else if (i == 2) then + write(s, fmt) real(x,kind=j(2)) + else if (i == 3) then + write(s, fmt) real(x,kind=j(3)) + else if (i == 4) then + write(s, fmt) real(x,kind=j(4)) + end if + n_tst = n_tst + 1 + if (s /= cmp) then + if (l_skip(i)) then + n_skip = n_skip + 1 + else + print "(a,1x,a,' expected: ',1x,a)", fmt, s, cmp + n_cnt = n_cnt + 1 + end if + end if + end do + + end subroutine +end program +! { dg-output "All kinds rounded to nearest" { xfail { i?86-*-solaris2.9* hppa*-*-hpux* } } } diff --git a/gcc/testsuite/gfortran.dg/unlimited_polymorphic_25.f90 b/gcc/testsuite/gfortran.dg/unlimited_polymorphic_25.f90 new file mode 100644 index 00000000000..d0b2a2e32d1 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/unlimited_polymorphic_25.f90 @@ -0,0 +1,40 @@ +! { dg-do run } +! +! Test contributed by Valery Weber <valeryweber@hotmail.com> + +module mod + + TYPE, PUBLIC :: base_type + END TYPE base_type + + TYPE, PUBLIC :: dict_entry_type + CLASS( * ), ALLOCATABLE :: key + CLASS( * ), ALLOCATABLE :: val + END TYPE dict_entry_type + + +contains + + SUBROUTINE dict_put ( this, key, val ) + CLASS(dict_entry_type), INTENT(INOUT) :: this + CLASS(base_type), INTENT(IN) :: key, val + INTEGER :: istat + ALLOCATE( this%key, SOURCE=key, STAT=istat ) + end SUBROUTINE dict_put +end module mod + +program test + use mod + type(dict_entry_type) :: t + type(base_type) :: a, b + call dict_put(t, a, b) + + if (.NOT. allocated(t%key)) call abort() + select type (x => t%key) + type is (base_type) + class default + call abort() + end select + deallocate(t%key) +end + diff --git a/gcc/testsuite/gfortran.dg/unlimited_polymorphic_26.f90 b/gcc/testsuite/gfortran.dg/unlimited_polymorphic_26.f90 new file mode 100644 index 00000000000..130006907a9 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/unlimited_polymorphic_26.f90 @@ -0,0 +1,47 @@ +! { dg-do run } +! +! Test contributed by Valery Weber <valeryweber@hotmail.com> + +module mod + + TYPE, PUBLIC :: dict_entry_type + CLASS( * ), ALLOCATABLE :: key + CLASS( * ), ALLOCATABLE :: val + END TYPE dict_entry_type + + +contains + + SUBROUTINE dict_put ( this, key, val ) + CLASS(dict_entry_type), INTENT(INOUT) :: this + CLASS(*), INTENT(IN) :: key, val + INTEGER :: istat + ALLOCATE( this%key, SOURCE=key, STAT=istat ) + ALLOCATE( this%val, SOURCE=val, STAT=istat ) + end SUBROUTINE dict_put +end module mod + +program test + use mod + type(dict_entry_type) :: t + call dict_put(t, "foo", 42) + + if (.NOT. allocated(t%key)) call abort() + select type (x => t%key) + type is (CHARACTER(*)) + if (x /= "foo") call abort() + class default + call abort() + end select + deallocate(t%key) + + if (.NOT. allocated(t%val)) call abort() + select type (x => t%val) + type is (INTEGER) + if (x /= 42) call abort() + class default + call abort() + end select + deallocate(t%val) +end + diff --git a/gcc/testsuite/gnat.dg/specs/double_record_extension3.ads b/gcc/testsuite/gnat.dg/specs/double_record_extension3.ads new file mode 100644 index 00000000000..de53655bace --- /dev/null +++ b/gcc/testsuite/gnat.dg/specs/double_record_extension3.ads @@ -0,0 +1,22 @@ +-- { dg-do compile } + +package Double_Record_Extension3 is + + type Rec1 is tagged record + Id : Integer; + end record; + + for Rec1 use record + Id at 8 range 0 .. 31; + end record; + + type Rec2 (Size : Integer) is new Rec1 with record + Data : String (1 .. Size); + end record; + + type Rec3 is new Rec2 (Size => 128) with record + Valid : Boolean; + end record; + +end Double_Record_Extension3; + diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 771a0d4d593..6df3bf22e26 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -2942,7 +2942,9 @@ proc check_effective_target_arm_fp16_ok { } { # Creates a series of routines that return 1 if the given architecture # can be selected and a routine to give the flags to select that architecture # Note: Extra flags may be added to disable options from newer compilers -# (Thumb in particular - but others may be added in the future) +# (Thumb in particular - but others may be added in the future). +# -march=armv7ve is special and is handled explicitly after this loop because +# it needs more than one predefine check to identify. # Usage: /* { dg-require-effective-target arm_arch_v5_ok } */ # /* { dg-add-options arm_arch_v5 } */ # /* { dg-require-effective-target arm_arch_v5_multilib } */ @@ -2957,7 +2959,6 @@ foreach { armfunc armflag armdef } { v4 "-march=armv4 -marm" __ARM_ARCH_4__ v6z "-march=armv6z" __ARM_ARCH_6Z__ v6m "-march=armv6-m -mthumb" __ARM_ARCH_6M__ v7a "-march=armv7-a" __ARM_ARCH_7A__ - v7ve "-march=armv7ve" __ARM_ARCH_7A__ v7r "-march=armv7-r" __ARM_ARCH_7R__ v7m "-march=armv7-m -mthumb" __ARM_ARCH_7M__ v7em "-march=armv7e-m -mthumb" __ARM_ARCH_7EM__ @@ -2992,6 +2993,26 @@ foreach { armfunc armflag armdef } { v4 "-march=armv4 -marm" __ARM_ARCH_4__ }] } +# Same functions as above but for -march=armv7ve. To uniquely identify +# -march=armv7ve we need to check for __ARM_ARCH_7A__ as well as +# __ARM_FEATURE_IDIV otherwise it aliases with armv7-a. + +proc check_effective_target_arm_arch_v7ve_ok { } { + if { [ string match "*-marm*" "-march=armv7ve" ] && + ![check_effective_target_arm_arm_ok] } { + return 0 + } + return [check_no_compiler_messages arm_arch_v7ve_ok assembly { + #if !defined (__ARM_ARCH_7A__) || !defined (__ARM_FEATURE_IDIV) + #error !armv7ve + #endif + } "-march=armv7ve" ] +} + +proc add_options_for_arm_arch_v7ve { flags } { + return "$flags -march=armv7ve" +} + # Return 1 if this is an ARM target where -marm causes ARM to be # used (not Thumb) diff --git a/gcc/tree-chrec.c b/gcc/tree-chrec.c index 4f1b6bc2090..1d7bc47192a 100644 --- a/gcc/tree-chrec.c +++ b/gcc/tree-chrec.c @@ -1464,11 +1464,11 @@ eq_evolutions_p (const_tree chrec0, const_tree chrec1) if (chrec0 == chrec1) return true; + if (! types_compatible_p (TREE_TYPE (chrec0), TREE_TYPE (chrec1))) + return false; + switch (TREE_CODE (chrec0)) { - case INTEGER_CST: - return operand_equal_p (chrec0, chrec1, 0); - case POLYNOMIAL_CHREC: return (CHREC_VARIABLE (chrec0) == CHREC_VARIABLE (chrec1) && eq_evolutions_p (CHREC_LEFT (chrec0), CHREC_LEFT (chrec1)) @@ -1483,8 +1483,12 @@ eq_evolutions_p (const_tree chrec0, const_tree chrec1) && eq_evolutions_p (TREE_OPERAND (chrec0, 1), TREE_OPERAND (chrec1, 1)); + CASE_CONVERT: + return eq_evolutions_p (TREE_OPERAND (chrec0, 0), + TREE_OPERAND (chrec1, 0)); + default: - return false; + return operand_equal_p (chrec0, chrec1, 0); } } diff --git a/gcc/tree-inline.c b/gcc/tree-inline.c index 8ca8824f0f6..0099693bf17 100644 --- a/gcc/tree-inline.c +++ b/gcc/tree-inline.c @@ -4111,7 +4111,7 @@ estimate_num_insns (gimple stmt, eni_weights *weights) return 0; else if (is_inexpensive_builtin (decl)) return weights->target_builtin_call_cost; - else if (DECL_BUILT_IN_CLASS (decl) == BUILT_IN_NORMAL) + else if (gimple_call_builtin_p (stmt, BUILT_IN_NORMAL)) { /* We canonicalize x * x to pow (x, 2.0) with -ffast-math, so specialize the cheap expansion we do here. diff --git a/gcc/tree-scalar-evolution.c b/gcc/tree-scalar-evolution.c index 1b457059d0e..6f640b82f36 100644 --- a/gcc/tree-scalar-evolution.c +++ b/gcc/tree-scalar-evolution.c @@ -1724,7 +1724,7 @@ static tree interpret_rhs_expr (struct loop *loop, gimple at_stmt, tree type, tree rhs1, enum tree_code code, tree rhs2) { - tree res, chrec1, chrec2; + tree res, chrec1, chrec2, ctype; gimple def; if (get_gimple_rhs_class (code) == GIMPLE_SINGLE_RHS) @@ -1818,30 +1818,63 @@ interpret_rhs_expr (struct loop *loop, gimple at_stmt, case PLUS_EXPR: chrec1 = analyze_scalar_evolution (loop, rhs1); chrec2 = analyze_scalar_evolution (loop, rhs2); - chrec1 = chrec_convert (type, chrec1, at_stmt); - chrec2 = chrec_convert (type, chrec2, at_stmt); + ctype = type; + /* When the stmt is conditionally executed re-write the CHREC + into a form that has well-defined behavior on overflow. */ + if (at_stmt + && INTEGRAL_TYPE_P (type) + && ! TYPE_OVERFLOW_WRAPS (type) + && ! dominated_by_p (CDI_DOMINATORS, loop->latch, + gimple_bb (at_stmt))) + ctype = unsigned_type_for (type); + chrec1 = chrec_convert (ctype, chrec1, at_stmt); + chrec2 = chrec_convert (ctype, chrec2, at_stmt); chrec1 = instantiate_parameters (loop, chrec1); chrec2 = instantiate_parameters (loop, chrec2); - res = chrec_fold_plus (type, chrec1, chrec2); + res = chrec_fold_plus (ctype, chrec1, chrec2); + if (type != ctype) + res = chrec_convert (type, res, at_stmt); break; case MINUS_EXPR: chrec1 = analyze_scalar_evolution (loop, rhs1); chrec2 = analyze_scalar_evolution (loop, rhs2); - chrec1 = chrec_convert (type, chrec1, at_stmt); - chrec2 = chrec_convert (type, chrec2, at_stmt); + ctype = type; + /* When the stmt is conditionally executed re-write the CHREC + into a form that has well-defined behavior on overflow. */ + if (at_stmt + && INTEGRAL_TYPE_P (type) + && ! TYPE_OVERFLOW_WRAPS (type) + && ! dominated_by_p (CDI_DOMINATORS, + loop->latch, gimple_bb (at_stmt))) + ctype = unsigned_type_for (type); + chrec1 = chrec_convert (ctype, chrec1, at_stmt); + chrec2 = chrec_convert (ctype, chrec2, at_stmt); chrec1 = instantiate_parameters (loop, chrec1); chrec2 = instantiate_parameters (loop, chrec2); - res = chrec_fold_minus (type, chrec1, chrec2); + res = chrec_fold_minus (ctype, chrec1, chrec2); + if (type != ctype) + res = chrec_convert (type, res, at_stmt); break; case NEGATE_EXPR: chrec1 = analyze_scalar_evolution (loop, rhs1); - chrec1 = chrec_convert (type, chrec1, at_stmt); + ctype = type; + /* When the stmt is conditionally executed re-write the CHREC + into a form that has well-defined behavior on overflow. */ + if (at_stmt + && INTEGRAL_TYPE_P (type) + && ! TYPE_OVERFLOW_WRAPS (type) + && ! dominated_by_p (CDI_DOMINATORS, + loop->latch, gimple_bb (at_stmt))) + ctype = unsigned_type_for (type); + chrec1 = chrec_convert (ctype, chrec1, at_stmt); /* TYPE may be integer, real or complex, so use fold_convert. */ chrec1 = instantiate_parameters (loop, chrec1); - res = chrec_fold_multiply (type, chrec1, - fold_convert (type, integer_minus_one_node)); + res = chrec_fold_multiply (ctype, chrec1, + fold_convert (ctype, integer_minus_one_node)); + if (type != ctype) + res = chrec_convert (type, res, at_stmt); break; case BIT_NOT_EXPR: @@ -1857,11 +1890,22 @@ interpret_rhs_expr (struct loop *loop, gimple at_stmt, case MULT_EXPR: chrec1 = analyze_scalar_evolution (loop, rhs1); chrec2 = analyze_scalar_evolution (loop, rhs2); - chrec1 = chrec_convert (type, chrec1, at_stmt); - chrec2 = chrec_convert (type, chrec2, at_stmt); + ctype = type; + /* When the stmt is conditionally executed re-write the CHREC + into a form that has well-defined behavior on overflow. */ + if (at_stmt + && INTEGRAL_TYPE_P (type) + && ! TYPE_OVERFLOW_WRAPS (type) + && ! dominated_by_p (CDI_DOMINATORS, + loop->latch, gimple_bb (at_stmt))) + ctype = unsigned_type_for (type); + chrec1 = chrec_convert (ctype, chrec1, at_stmt); + chrec2 = chrec_convert (ctype, chrec2, at_stmt); chrec1 = instantiate_parameters (loop, chrec1); chrec2 = instantiate_parameters (loop, chrec2); - res = chrec_fold_multiply (type, chrec1, chrec2); + res = chrec_fold_multiply (ctype, chrec1, chrec2); + if (type != ctype) + res = chrec_convert (type, res, at_stmt); break; CASE_CONVERT: diff --git a/gcc/tree-sra.c b/gcc/tree-sra.c index 3457aac4399..98dce7d825e 100644 --- a/gcc/tree-sra.c +++ b/gcc/tree-sra.c @@ -4609,6 +4609,8 @@ replace_removed_params_ssa_names (tree old_name, gimple stmt, repl = get_replaced_param_substitute (adj); new_name = make_ssa_name (repl, stmt); + SSA_NAME_OCCURS_IN_ABNORMAL_PHI (new_name) + = SSA_NAME_OCCURS_IN_ABNORMAL_PHI (old_name); if (dump_file) { diff --git a/gcc/tree-ssa-forwprop.c b/gcc/tree-ssa-forwprop.c index 93f92f33a59..a1ba1e09d79 100644 --- a/gcc/tree-ssa-forwprop.c +++ b/gcc/tree-ssa-forwprop.c @@ -1517,7 +1517,7 @@ defcodefor_name (tree name, enum tree_code *code, tree *arg1, tree *arg2) || GIMPLE_BINARY_RHS || GIMPLE_UNARY_RHS || GIMPLE_SINGLE_RHS) - extract_ops_from_tree_1 (name, &code1, &arg11, &arg21, &arg31); + extract_ops_from_tree (name, &code1, &arg11, &arg21, &arg31); *code = code1; *arg1 = arg11; diff --git a/gcc/tree-ssa-loop-ivcanon.c b/gcc/tree-ssa-loop-ivcanon.c index 138468d396a..f97c81912a6 100644 --- a/gcc/tree-ssa-loop-ivcanon.c +++ b/gcc/tree-ssa-loop-ivcanon.c @@ -1193,38 +1193,6 @@ canonicalize_induction_variables (void) return 0; } -/* Propagate VAL into all uses of SSA_NAME. */ - -static void -propagate_into_all_uses (tree ssa_name, tree val) -{ - imm_use_iterator iter; - gimple use_stmt; - - FOR_EACH_IMM_USE_STMT (use_stmt, iter, ssa_name) - { - gimple_stmt_iterator use_stmt_gsi = gsi_for_stmt (use_stmt); - use_operand_p use; - - FOR_EACH_IMM_USE_ON_STMT (use, iter) - SET_USE (use, val); - - if (is_gimple_assign (use_stmt) - && get_gimple_rhs_class (gimple_assign_rhs_code (use_stmt)) - == GIMPLE_SINGLE_RHS) - { - tree rhs = gimple_assign_rhs1 (use_stmt); - - if (TREE_CODE (rhs) == ADDR_EXPR) - recompute_tree_invariant_for_addr_expr (rhs); - } - - fold_stmt_inplace (&use_stmt_gsi); - update_stmt (use_stmt); - maybe_clean_or_replace_eh_stmt (use_stmt, use_stmt); - } -} - /* Propagate constant SSA_NAMEs defined in basic block BB. */ static void @@ -1241,7 +1209,7 @@ propagate_constants_for_unrolling (basic_block bb) && gimple_phi_num_args (phi) == 1 && TREE_CODE (arg) == INTEGER_CST) { - propagate_into_all_uses (result, arg); + replace_uses_by (result, arg); gsi_remove (&gsi, true); release_ssa_name (result); } @@ -1260,7 +1228,7 @@ propagate_constants_for_unrolling (basic_block bb) && (lhs = gimple_assign_lhs (stmt), TREE_CODE (lhs) == SSA_NAME) && !SSA_NAME_OCCURS_IN_ABNORMAL_PHI (lhs)) { - propagate_into_all_uses (lhs, gimple_assign_rhs1 (stmt)); + replace_uses_by (lhs, gimple_assign_rhs1 (stmt)); gsi_remove (&gsi, true); release_ssa_name (lhs); } diff --git a/gcc/tree-ssa-loop-niter.c b/gcc/tree-ssa-loop-niter.c index 3ebb0f9b45c..7134718c341 100644 --- a/gcc/tree-ssa-loop-niter.c +++ b/gcc/tree-ssa-loop-niter.c @@ -2761,9 +2761,9 @@ static widest_int derive_constant_upper_bound (tree val) { enum tree_code code; - tree op0, op1; + tree op0, op1, op2; - extract_ops_from_tree (val, &code, &op0, &op1); + extract_ops_from_tree (val, &code, &op0, &op1, &op2); return derive_constant_upper_bound_ops (TREE_TYPE (val), op0, code, op1); } @@ -2776,7 +2776,7 @@ derive_constant_upper_bound_ops (tree type, tree op0, enum tree_code code, tree op1) { tree subtype, maxt; - widest_int bnd, max, mmax, cst; + widest_int bnd, max, cst; gimple stmt; if (INTEGRAL_TYPE_P (type)) @@ -2842,8 +2842,8 @@ derive_constant_upper_bound_ops (tree type, tree op0, /* OP0 + CST. We need to check that BND <= MAX (type) - CST. */ - mmax -= cst; - if (wi::ltu_p (bnd, max)) + widest_int mmax = max - cst; + if (wi::leu_p (bnd, mmax)) return max; return bnd + cst; @@ -3060,7 +3060,9 @@ record_nonwrapping_iv (struct loop *loop, tree base, tree step, gimple stmt, && get_range_info (orig_base, &min, &max) == VR_RANGE && wi::gts_p (high, max)) base = wide_int_to_tree (unsigned_type, max); - else if (TREE_CODE (base) != INTEGER_CST) + else if (TREE_CODE (base) != INTEGER_CST + && dominated_by_p (CDI_DOMINATORS, + loop->latch, gimple_bb (stmt))) base = fold_convert (unsigned_type, high); delta = fold_build2 (MINUS_EXPR, unsigned_type, base, extreme); step = fold_build1 (NEGATE_EXPR, unsigned_type, step); @@ -3075,7 +3077,9 @@ record_nonwrapping_iv (struct loop *loop, tree base, tree step, gimple stmt, && get_range_info (orig_base, &min, &max) == VR_RANGE && wi::gts_p (min, low)) base = wide_int_to_tree (unsigned_type, min); - else if (TREE_CODE (base) != INTEGER_CST) + else if (TREE_CODE (base) != INTEGER_CST + && dominated_by_p (CDI_DOMINATORS, + loop->latch, gimple_bb (stmt))) base = fold_convert (unsigned_type, low); delta = fold_build2 (MINUS_EXPR, unsigned_type, extreme, base); } diff --git a/gcc/tree-ssa-loop.c b/gcc/tree-ssa-loop.c index ccb8f9762bb..78dae5d8bae 100644 --- a/gcc/tree-ssa-loop.c +++ b/gcc/tree-ssa-loop.c @@ -698,6 +698,8 @@ gen_lsm_tmp_name (tree ref) case SSA_NAME: case VAR_DECL: case PARM_DECL: + case FUNCTION_DECL: + case LABEL_DECL: name = get_name (ref); if (!name) name = "D"; @@ -713,11 +715,9 @@ gen_lsm_tmp_name (tree ref) break; case INTEGER_CST: + default: /* Nothing. */ break; - - default: - gcc_unreachable (); } } diff --git a/gcc/tree-ssa-math-opts.c b/gcc/tree-ssa-math-opts.c index 3e460e138ca..20ca5c62765 100644 --- a/gcc/tree-ssa-math-opts.c +++ b/gcc/tree-ssa-math-opts.c @@ -770,7 +770,7 @@ execute_cse_sincos_1 (tree name) if (gimple_code (use_stmt) != GIMPLE_CALL || !gimple_call_lhs (use_stmt) || !(fndecl = gimple_call_fndecl (use_stmt)) - || DECL_BUILT_IN_CLASS (fndecl) != BUILT_IN_NORMAL) + || !gimple_call_builtin_p (use_stmt, BUILT_IN_NORMAL)) continue; switch (DECL_FUNCTION_CODE (fndecl)) @@ -1780,7 +1780,7 @@ pass_cse_sincos::execute (function *fun) if (is_gimple_call (stmt) && gimple_call_lhs (stmt) && (fndecl = gimple_call_fndecl (stmt)) - && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_NORMAL) + && gimple_call_builtin_p (stmt, BUILT_IN_NORMAL)) { tree arg, arg0, arg1, result; HOST_WIDE_INT n; @@ -3631,7 +3631,7 @@ pass_optimize_widening_mul::execute (function *fun) { tree fndecl = gimple_call_fndecl (stmt); if (fndecl - && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_NORMAL) + && gimple_call_builtin_p (stmt, BUILT_IN_NORMAL)) { switch (DECL_FUNCTION_CODE (fndecl)) { diff --git a/gcc/tree-ssa-reassoc.c b/gcc/tree-ssa-reassoc.c index 03faec5e4b3..0710bae7de0 100644 --- a/gcc/tree-ssa-reassoc.c +++ b/gcc/tree-ssa-reassoc.c @@ -2134,11 +2134,33 @@ update_range_test (struct range_entry *range, struct range_entry *otherrange, in_p, low, high); enum warn_strict_overflow_code wc = WARN_STRICT_OVERFLOW_COMPARISON; gimple_stmt_iterator gsi; - unsigned int i; + unsigned int i, uid; if (tem == NULL_TREE) return false; + /* If op is default def SSA_NAME, there is no place to insert the + new comparison. Give up, unless we can use OP itself as the + range test. */ + if (op && SSA_NAME_IS_DEFAULT_DEF (op)) + { + if (op == range->exp + && ((TYPE_PRECISION (optype) == 1 && TYPE_UNSIGNED (optype)) + || TREE_CODE (optype) == BOOLEAN_TYPE) + && (op == tem + || (TREE_CODE (tem) == EQ_EXPR + && TREE_OPERAND (tem, 0) == op + && integer_onep (TREE_OPERAND (tem, 1)))) + && opcode != BIT_IOR_EXPR + && (opcode != ERROR_MARK || oe->rank != BIT_IOR_EXPR)) + { + stmt = NULL; + tem = op; + } + else + return false; + } + if (strict_overflow_p && issue_strict_overflow_warning (wc)) warning_at (loc, OPT_Wstrict_overflow, "assuming signed overflow does not occur " @@ -2176,12 +2198,22 @@ update_range_test (struct range_entry *range, struct range_entry *otherrange, tem = invert_truthvalue_loc (loc, tem); tem = fold_convert_loc (loc, optype, tem); - gsi = gsi_for_stmt (stmt); - unsigned int uid = gimple_uid (stmt); + if (stmt) + { + gsi = gsi_for_stmt (stmt); + uid = gimple_uid (stmt); + } + else + { + gsi = gsi_none (); + uid = 0; + } + if (stmt == NULL) + gcc_checking_assert (tem == op); /* In rare cases range->exp can be equal to lhs of stmt. In that case we have to insert after the stmt rather then before it. If stmt is a PHI, insert it at the start of the basic block. */ - if (op != range->exp) + else if (op != range->exp) { gsi_insert_seq_before (&gsi, seq, GSI_SAME_STMT); tem = force_gimple_operand_gsi (&gsi, tem, true, NULL_TREE, true, diff --git a/gcc/varasm.c b/gcc/varasm.c index a62d02fb187..1747605310d 100644 --- a/gcc/varasm.c +++ b/gcc/varasm.c @@ -4947,6 +4947,14 @@ output_constructor_regular_field (oc_local_state *local) unsigned int align2; + /* Output any buffered-up bit-fields preceding this element. */ + if (local->byte_buffer_in_use) + { + assemble_integer (GEN_INT (local->byte), 1, BITS_PER_UNIT, 1); + local->total_bytes++; + local->byte_buffer_in_use = false; + } + if (local->index != NULL_TREE) { /* Perform the index calculation in modulo arithmetic but @@ -4963,22 +4971,19 @@ output_constructor_regular_field (oc_local_state *local) else fieldpos = 0; - /* Output any buffered-up bit-fields preceding this element. */ - if (local->byte_buffer_in_use) - { - assemble_integer (GEN_INT (local->byte), 1, BITS_PER_UNIT, 1); - local->total_bytes++; - local->byte_buffer_in_use = false; - } - /* Advance to offset of this element. Note no alignment needed in an array, since that is guaranteed if each element has the proper size. */ - if ((local->field != NULL_TREE || local->index != NULL_TREE) - && fieldpos > local->total_bytes) + if (local->field != NULL_TREE || local->index != NULL_TREE) { - assemble_zeros (fieldpos - local->total_bytes); - local->total_bytes = fieldpos; + if (fieldpos > local->total_bytes) + { + assemble_zeros (fieldpos - local->total_bytes); + local->total_bytes = fieldpos; + } + else + /* Must not go backwards. */ + gcc_assert (fieldpos == local->total_bytes); } /* Find the alignment of this element. */ diff --git a/libcpp/ChangeLog b/libcpp/ChangeLog index 7754af842fe..385c3b0bd10 100644 --- a/libcpp/ChangeLog +++ b/libcpp/ChangeLog @@ -1,3 +1,12 @@ +2016-03-30 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2016-03-21 Jakub Jelinek <jakub@redhat.com> + + PR target/70296 + * include/cpplib.h (cpp_fun_like_macro_p): New prototype. + * macro.c (cpp_fun_like_macro_p): New function. + 2016-02-10 Jakub Jelinek <jakub@redhat.com> Backported from mainline diff --git a/libcpp/include/cpplib.h b/libcpp/include/cpplib.h index 2d90ccd0e81..1b731d1a3ad 100644 --- a/libcpp/include/cpplib.h +++ b/libcpp/include/cpplib.h @@ -804,6 +804,7 @@ extern int cpp_avoid_paste (cpp_reader *, const cpp_token *, extern const cpp_token *cpp_get_token (cpp_reader *); extern const cpp_token *cpp_get_token_with_location (cpp_reader *, source_location *); +extern bool cpp_fun_like_macro_p (cpp_hashnode *); extern const unsigned char *cpp_macro_definition (cpp_reader *, cpp_hashnode *); extern void _cpp_backup_tokens (cpp_reader *, unsigned int); diff --git a/libcpp/macro.c b/libcpp/macro.c index 1e0a0b560ba..eb32a6f8c98 100644 --- a/libcpp/macro.c +++ b/libcpp/macro.c @@ -3307,6 +3307,15 @@ check_trad_stringification (cpp_reader *pfile, const cpp_macro *macro, } } +/* Returns true of NODE is a function-like macro. */ +bool +cpp_fun_like_macro_p (cpp_hashnode *node) +{ + return (node->type == NT_MACRO + && (node->flags & (NODE_BUILTIN | NODE_MACRO_ARG)) == 0 + && node->value.macro->fun_like); +} + /* Returns the name, arguments and expansion of a macro, in a format suitable to be read back in again, and therefore also for DWARF 2 debugging info. e.g. "PASTE(X, Y) X ## Y", or "MACNAME EXPANSION". diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog index 22a63ec4671..3e73b7694d7 100644 --- a/libgcc/ChangeLog +++ b/libgcc/ChangeLog @@ -1,3 +1,19 @@ +2016-04-04 Eric Botcazou <ebotcazou@adacore.com> + + PR target/67172 + * libgcc2.c (L__main): Undefine __LIBGCC_EH_FRAME_SECTION_NAME__ if + __MINGW32__ is defined. + +2016-03-21 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> + + Backport from mainline + 2016-03-16 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> + + PR target/38239 + * config/sol2/gmon.c [__i386__] (_mcount): Save and restore + call-clobbered registers. + (internal_mcount): Remove __i386__ handling. + 2016-02-10 Ian Lance Taylor <iant@google.com> PR go/68562 diff --git a/libgcc/config/sol2/gmon.c b/libgcc/config/sol2/gmon.c index 81a03468b6e..652fd1ed946 100644 --- a/libgcc/config/sol2/gmon.c +++ b/libgcc/config/sol2/gmon.c @@ -44,11 +44,7 @@ extern void monstartup (char *, char *); extern void _mcleanup (void); -#ifdef __i386__ -static void internal_mcount (void) __attribute__ ((used)); -#else static void internal_mcount (char *, unsigned short *) __attribute__ ((used)); -#endif static void moncontrol (int); struct phdr { @@ -223,8 +219,19 @@ _mcleanup (void) /* Solaris 2 libraries use _mcount. */ #if defined __i386__ asm(".globl _mcount\n" + " .type _mcount, @function\n" "_mcount:\n" - " jmp internal_mcount\n"); + /* Save and restore the call-clobbered registers. */ + " pushl %eax\n" + " pushl %ecx\n" + " pushl %edx\n" + " movl 12(%esp), %edx\n" + " movl 4(%ebp), %eax\n" + " call internal_mcount\n" + " popl %edx\n" + " popl %ecx\n" + " popl %eax\n" + " ret\n"); #elif defined __x86_64__ /* See GLIBC for additional information about this technique. */ asm(".globl _mcount\n" @@ -299,32 +306,13 @@ asm(".global _mcount\n" #endif static void -#ifdef __i386__ -internal_mcount (void) -#else internal_mcount (char *selfpc, unsigned short *frompcindex) -#endif { struct tostruct *top; struct tostruct *prevtop; long toindex; static char already_setup; -#ifdef __i386__ - char *selfpc; - unsigned short *frompcindex; - - /* Find the return address for mcount and the return address for mcount's - caller. */ - - /* selfpc = pc pushed by mcount call. - This identifies the function that was just entered. */ - selfpc = (void *) __builtin_return_address (0); - /* frompcindex = pc in preceding frame. - This identifies the caller of the function just entered. */ - frompcindex = (void *) __builtin_return_address (1); -#endif - /* Only necessary without the Solaris CRTs or a proper gcrt1.o, otherwise crtpg.o or gcrt1.o take care of that. diff --git a/libgcc/libgcc2.c b/libgcc/libgcc2.c index c7376206d64..0ef8823428a 100644 --- a/libgcc/libgcc2.c +++ b/libgcc/libgcc2.c @@ -2209,7 +2209,12 @@ TRANSFER_FROM_TRAMPOLINE #if !defined (HAS_INIT_SECTION) || !defined (OBJECT_FORMAT_ELF) /* Some ELF crosses use crtstuff.c to provide __CTOR_LIST__, but use this - code to run constructors. In that case, we need to handle EH here, too. */ + code to run constructors. In that case, we need to handle EH here, too. + But MINGW32 is special because it handles CRTSTUFF and EH on its own. */ + +#ifdef __MINGW32__ +#undef __LIBGCC_EH_FRAME_SECTION_NAME__ +#endif #ifdef __LIBGCC_EH_FRAME_SECTION_NAME__ #include "unwind-dw2-fde.h" diff --git a/libgfortran/ChangeLog b/libgfortran/ChangeLog index f53de385ea1..b3952c36f50 100644 --- a/libgfortran/ChangeLog +++ b/libgfortran/ChangeLog @@ -1,3 +1,17 @@ +2016-04-05 Jerry DeLisle <jvdelisle@gcc.gnu.org> + Dominique d'Humieres <dominiq@lps.ens.fr> + + PR libgfortran/70235 + * io/write_float.def: Fix PF format for negative values of the scale + factor. + +2016-03-28 Alessandro Fanfarillo <fanfarillo.gcc@gmail.com> + + Backport from trunk. + * caf/libcaf.h: caf_stop_numeric and caf_stop_str prototype. + * caf/single.c: _gfortran_caf_stop_numeric and + _gfortran_caf_stop_str implementation. + 2016-02-17 Jerry DeLisle <jvdelisle@gcc.gnu.org> PR libgfortran/69651 @@ -18,7 +32,7 @@ (read_character): Remove condition testing c = '!' which is now inside the is_separator macro. Remove code related to DELIM_NONE. (parse_real): Reject '!' unless in namelist mode. (read_complex): Reject - '!' unless in namelist mode. (read_real): Likewise reject '!'. + '!' unless in namelist mode. (read_real): Likewise reject '!'. 2015-12-29 Jerry DeLisle <jvdelisle@gcc.gnu.org> diff --git a/libgfortran/caf/libcaf.h b/libgfortran/caf/libcaf.h index ebda579d06c..ef86dd367e4 100644 --- a/libgfortran/caf/libcaf.h +++ b/libgfortran/caf/libcaf.h @@ -105,6 +105,10 @@ void _gfortran_caf_sync_all (int *, char *, int); void _gfortran_caf_sync_memory (int *, char *, int); void _gfortran_caf_sync_images (int, int[], int *, char *, int); +void _gfortran_caf_stop_numeric (int32_t) + __attribute__ ((noreturn)); +void _gfortran_caf_stop_str (const char *, int32_t) + __attribute__ ((noreturn)); void _gfortran_caf_error_stop_str (const char *, int32_t) __attribute__ ((noreturn)); void _gfortran_caf_error_stop (int32_t) __attribute__ ((noreturn)); diff --git a/libgfortran/caf/single.c b/libgfortran/caf/single.c index 9c4b3434f5c..e95b798902a 100644 --- a/libgfortran/caf/single.c +++ b/libgfortran/caf/single.c @@ -204,6 +204,23 @@ _gfortran_caf_sync_images (int count __attribute__ ((unused)), *stat = 0; } +void +_gfortran_caf_stop_numeric(int32_t stop_code) +{ + fprintf (stderr, "STOP %d\n", stop_code); + exit (0); +} + +void +_gfortran_caf_stop_str(const char *string, int32_t len) +{ + fputs ("STOP ", stderr); + while (len--) + fputc (*(string++), stderr); + fputs ("\n", stderr); + + exit (0); +} void _gfortran_caf_error_stop_str (const char *string, int32_t len) diff --git a/libgfortran/io/write_float.def b/libgfortran/io/write_float.def index b983c784498..f79bf334e5e 100644 --- a/libgfortran/io/write_float.def +++ b/libgfortran/io/write_float.def @@ -184,9 +184,6 @@ output_float (st_parameter_dt *dtp, const fnode *f, char *buffer, size_t size, memmove (digits + nbefore, digits + nbefore + 1, p); digits[nbefore + p] = '.'; nbefore += p; - nafter = d - p; - if (nafter < 0) - nafter = 0; nafter = d; nzero = 0; } @@ -204,12 +201,27 @@ output_float (st_parameter_dt *dtp, const fnode *f, char *buffer, size_t size, { nzero = -(nbefore + p); memmove (digits + 1, digits, nbefore); - digits++; - nafter = d + nbefore; + nafter = d - nzero; + if (nafter == 0 && d > 0) + { + /* This is needed to get the correct rounding. */ + memmove (digits + 1, digits, ndigits - 1); + digits[1] = '0'; + nafter = 1; + nzero = d - 1; + } + else if (nafter < 0) + { + /* Reset digits to 0 in order to get correct rounding + towards infinity. */ + for (i = 0; i < ndigits; i++) + digits[i] = '0'; + digits[ndigits - 1] = '1'; + nafter = d; + nzero = 0; + } nbefore = 0; } - if (nzero > d) - nzero = d; } } else diff --git a/libgomp/ChangeLog b/libgomp/ChangeLog index 3da9fa1732e..ed890e0095c 100644 --- a/libgomp/ChangeLog +++ b/libgomp/ChangeLog @@ -1,3 +1,16 @@ +2016-04-07 Thomas Schwinge <thomas@codesourcery.com> + + Backport trunk r234428: + + 2016-03-23 James Norris <jnorris@codesourcery.com> + Daichi Fukuoka <dc-fukuoka@sgi.com> + + PR libgomp/69414 + * oacc-mem.c (delete_copyout, update_dev_host): Fix device address. + * testsuite/libgomp.oacc-c-c++-common/update-1.c: Additional tests. + * testsuite/libgomp.oacc-c-c++-common/update-1-2.c: Likewise. + * testsuite/libgomp.oacc-fortran/update-1.f90: New file. + 2016-02-16 Tom de Vries <tom@codesourcery.com> backport from trunk: diff --git a/libgomp/oacc-mem.c b/libgomp/oacc-mem.c index 89ef5fcd887..c3e12fab3b7 100644 --- a/libgomp/oacc-mem.c +++ b/libgomp/oacc-mem.c @@ -447,7 +447,8 @@ delete_copyout (unsigned f, void *h, size_t s) if (!n) gomp_fatal ("[%p,%d] is not mapped", (void *)h, (int)s); - d = (void *) (n->tgt->tgt_start + n->tgt_offset); + d = (void *) (n->tgt->tgt_start + n->tgt_offset + + (uintptr_t) h - n->host_start); host_size = n->host_end - n->host_start; @@ -490,7 +491,8 @@ update_dev_host (int is_dev, void *h, size_t s) if (!n) gomp_fatal ("[%p,%d] is not mapped", h, (int)s); - d = (void *) (n->tgt->tgt_start + n->tgt_offset); + d = (void *) (n->tgt->tgt_start + n->tgt_offset + + (uintptr_t) h - n->host_start); if (is_dev) acc_dev->host2dev_func (acc_dev->target_id, d, h, s); diff --git a/libgomp/testsuite/libgomp.oacc-c-c++-common/update-1-2.c b/libgomp/testsuite/libgomp.oacc-c-c++-common/update-1-2.c index c7e7257a873..82c31925063 100644 --- a/libgomp/testsuite/libgomp.oacc-c-c++-common/update-1-2.c +++ b/libgomp/testsuite/libgomp.oacc-c-c++-common/update-1-2.c @@ -13,6 +13,7 @@ int main (int argc, char **argv) { int N = 8; + int NDIV2 = N / 2; float *a, *b, *c; float *d_a, *d_b, *d_c; int i; @@ -242,7 +243,7 @@ main (int argc, char **argv) a[i] = 6.0; } -#pragma acc update device (a[0:N >> 1]) +#pragma acc update device (a[0:NDIV2]) #pragma acc parallel present (a[0:N], b[0:N]) { @@ -254,7 +255,7 @@ main (int argc, char **argv) #pragma acc update self (a[0:N], b[0:N]) - for (i = 0; i < (N >> 1); i++) + for (i = 0; i < NDIV2; i++) { if (a[i] != 6.0) abort (); @@ -263,7 +264,7 @@ main (int argc, char **argv) abort (); } - for (i = (N >> 1); i < N; i++) + for (i = NDIV2; i < N; i++) { if (a[i] != 5.0) abort (); @@ -278,5 +279,83 @@ main (int argc, char **argv) if (!acc_is_present (&b[0], (N * sizeof (float)))) abort (); + for (i = 0; i < N; i++) + { + a[i] = 0.0; + } + +#pragma acc update device (a[0:4]) + +#pragma acc parallel present (a[0:N]) + { + int ii; + + for (ii = 0; ii < N; ii++) + a[ii] = a[ii] + 1.0; + } + +#pragma acc update self (a[4:4]) + + for (i = 0; i < NDIV2; i++) + { + if (a[i] != 0.0) + abort (); + } + + for (i = NDIV2; i < N; i++) + { + if (a[i] != 6.0) + abort (); + } + +#pragma acc update self (a[0:4]) + + for (i = 0; i < NDIV2; i++) + { + if (a[i] != 1.0) + abort (); + } + + for (i = NDIV2; i < N; i++) + { + if (a[i] != 6.0) + abort (); + } + + a[2] = 9; + a[3] = 9; + a[4] = 9; + a[5] = 9; + +#pragma acc update device (a[2:4]) + +#pragma acc parallel present (a[0:N]) + { + int ii; + + for (ii = 0; ii < N; ii++) + a[ii] = a[ii] + 1.0; + } + +#pragma acc update self (a[2:4]) + + for (i = 0; i < 2; i++) + { + if (a[i] != 1.0) + abort (); + } + + for (i = 2; i < 6; i++) + { + if (a[i] != 10.0) + abort (); + } + + for (i = 6; i < N; i++) + { + if (a[i] != 6.0) + abort (); + } + return 0; } diff --git a/libgomp/testsuite/libgomp.oacc-c-c++-common/update-1.c b/libgomp/testsuite/libgomp.oacc-c-c++-common/update-1.c index dff139f03cc..1b2a46072d6 100644 --- a/libgomp/testsuite/libgomp.oacc-c-c++-common/update-1.c +++ b/libgomp/testsuite/libgomp.oacc-c-c++-common/update-1.c @@ -11,6 +11,7 @@ int main (int argc, char **argv) { int N = 8; + int NDIV2 = N / 2; float *a, *b, *c; float *d_a, *d_b, *d_c; int i; @@ -109,7 +110,7 @@ main (int argc, char **argv) b[ii] = a[ii]; } -#pragma acc update self (a[0:N], b[0:N]) +#pragma acc update host (a[0:N], b[0:N]) for (i = 0; i < N; i++) { @@ -240,7 +241,7 @@ main (int argc, char **argv) a[i] = 6.0; } -#pragma acc update device (a[0:N >> 1]) +#pragma acc update device (a[0:NDIV2]) #pragma acc parallel present (a[0:N], b[0:N]) { @@ -252,7 +253,7 @@ main (int argc, char **argv) #pragma acc update host (a[0:N], b[0:N]) - for (i = 0; i < (N >> 1); i++) + for (i = 0; i < NDIV2; i++) { if (a[i] != 6.0) abort (); @@ -261,7 +262,7 @@ main (int argc, char **argv) abort (); } - for (i = (N >> 1); i < N; i++) + for (i = NDIV2; i < N; i++) { if (a[i] != 5.0) abort (); @@ -276,5 +277,83 @@ main (int argc, char **argv) if (!acc_is_present (&b[0], (N * sizeof (float)))) abort (); + for (i = 0; i < N; i++) + { + a[i] = 0.0; + } + +#pragma acc update device (a[0:4]) + +#pragma acc parallel present (a[0:N]) + { + int ii; + + for (ii = 0; ii < N; ii++) + a[ii] = a[ii] + 1.0; + } + +#pragma acc update host (a[4:4]) + + for (i = 0; i < NDIV2; i++) + { + if (a[i] != 0.0) + abort (); + } + + for (i = NDIV2; i < N; i++) + { + if (a[i] != 6.0) + abort (); + } + +#pragma acc update host (a[0:4]) + + for (i = 0; i < NDIV2; i++) + { + if (a[i] != 1.0) + abort (); + } + + for (i = NDIV2; i < N; i++) + { + if (a[i] != 6.0) + abort (); + } + + a[2] = 9; + a[3] = 9; + a[4] = 9; + a[5] = 9; + +#pragma acc update device (a[2:4]) + +#pragma acc parallel present (a[0:N]) + { + int ii; + + for (ii = 0; ii < N; ii++) + a[ii] = a[ii] + 1.0; + } + +#pragma acc update host (a[2:4]) + + for (i = 0; i < 2; i++) + { + if (a[i] != 1.0) + abort (); + } + + for (i = 2; i < 6; i++) + { + if (a[i] != 10.0) + abort (); + } + + for (i = 6; i < N; i++) + { + if (a[i] != 6.0) + abort (); + } + return 0; } diff --git a/libgomp/testsuite/libgomp.oacc-fortran/update-1.f90 b/libgomp/testsuite/libgomp.oacc-fortran/update-1.f90 new file mode 100644 index 00000000000..4e1d2c01278 --- /dev/null +++ b/libgomp/testsuite/libgomp.oacc-fortran/update-1.f90 @@ -0,0 +1,242 @@ +! { dg-do run } +! { dg-skip-if "" { *-*-* } { "*" } { "-DACC_MEM_SHARED=0" } } + +program update + use openacc + implicit none + integer, parameter :: N = 8 + integer, parameter :: NDIV2 = N / 2 + real :: a(N), b(N) + integer i + + do i = 1, N + a(i) = 3.0 + b(i) = 0.0 + end do + + !$acc enter data copyin (a, b) + + !$acc parallel present (a, b) + do i = 1, N + b(i) = a(i) + end do + !$acc end parallel + + !$acc update host (a, b) + + do i = 1, N + if (a(i) .ne. 3.0) call abort + if (b(i) .ne. 3.0) call abort + end do + + if (acc_is_present (a) .neqv. .TRUE.) call abort + if (acc_is_present (b) .neqv. .TRUE.) call abort + + do i = 1, N + a(i) = 5.0 + b(i) = 1.0 + end do + + !$acc update device (a, b) + + !$acc parallel present (a, b) + do i = 1, N + b(i) = a(i) + end do + !$acc end parallel + + !$acc update host (a, b) + + do i = 1, N + if (a(i) .ne. 5.0) call abort + if (b(i) .ne. 5.0) call abort + end do + + if (acc_is_present (a) .neqv. .TRUE.) call abort + if (acc_is_present (b) .neqv. .TRUE.) call abort + + !$acc parallel present (a, b) + do i = 1, N + b(i) = a(i) + end do + !$acc end parallel + + !$acc update host (a, b) + + do i = 1, N + if (a(i) .ne. 5.0) call abort + if (b(i) .ne. 5.0) call abort + end do + + if (acc_is_present (a) .neqv. .TRUE.) call abort + if (acc_is_present (b) .neqv. .TRUE.) call abort + + do i = 1, N + a(i) = 6.0 + b(i) = 0.0 + end do + + !$acc update device (a, b) + + do i = 1, N + a(i) = 9.0 + end do + + !$acc parallel present (a, b) + do i = 1, N + b(i) = a(i) + end do + !$acc end parallel + + !$acc update host (a, b) + + do i = 1, N + if (a(i) .ne. 6.0) call abort + if (b(i) .ne. 6.0) call abort + end do + + if (acc_is_present (a) .neqv. .TRUE.) call abort + if (acc_is_present (b) .neqv. .TRUE.) call abort + + do i = 1, N + a(i) = 7.0 + b(i) = 2.0 + end do + + !$acc update device (a, b) + + do i = 1, N + a(i) = 9.0 + end do + + !$acc parallel present (a, b) + do i = 1, N + b(i) = a(i) + end do + !$acc end parallel + + !$acc update host (a, b) + + do i = 1, N + if (a(i) .ne. 7.0) call abort + if (b(i) .ne. 7.0) call abort + end do + + do i = 1, N + a(i) = 9.0 + end do + + !$acc update device (a) + + !$acc parallel present (a, b) + do i = 1, N + b(i) = a(i) + end do + !$acc end parallel + + !$acc update host (a, b) + + do i = 1, N + if (a(i) .ne. 9.0) call abort + if (b(i) .ne. 9.0) call abort + end do + + if (acc_is_present (a) .neqv. .TRUE.) call abort + if (acc_is_present (b) .neqv. .TRUE.) call abort + + do i = 1, N + a(i) = 5.0 + end do + + !$acc update device (a) + + do i = 1, N + a(i) = 6.0 + end do + + !$acc update device (a(1:NDIV2)) + + !$acc parallel present (a, b) + do i = 1, N + b(i) = a(i) + end do + !$acc end parallel + + !$acc update host (a, b) + + do i = 1, NDIV2 + if (a(i) .ne. 6.0) call abort + if (b(i) .ne. 6.0) call abort + end do + + do i = NDIV2 + 1, N + if (a(i) .ne. 5.0) call abort + if (b(i) .ne. 5.0) call abort + end do + + if (acc_is_present (a) .neqv. .TRUE.) call abort + if (acc_is_present (b) .neqv. .TRUE.) call abort + + do i = 1, N + a(i) = 0.0 + end do + + !$acc update device (a(1:4)) + + !$acc parallel present (a) + do i = 1, N + a(i) = a(i) + 1.0 + end do + !$acc end parallel + + !$acc update host (a(5:N)) + + do i = 1, NDIV2 + if (a(i) .ne. 0.0) call abort + end do + + do i = NDIV2 + 1, N + if (a(i) .ne. 6.0) call abort + end do + + !$acc update host (a(1:4)) + + do i = 1, NDIV2 + if (a(i) .ne. 1.0) call abort + end do + + do i = NDIV2 + 1, N + if (a(i) .ne. 6.0) call abort + end do + + a(3) = 9 + a(4) = 9 + a(5) = 9 + a(6) = 9 + + !$acc update device (a(3:6)) + + !$acc parallel present (a(1:N)) + do i = 1, N + a(i) = a(i) + 1.0 + end do + !$acc end parallel + + !$acc update host (a(3:6)) + + do i = 1, 2 + if (a(i) .ne. 1.0) call abort + end do + + do i = 3, 6 + if (a(i) .ne. 10.0) call abort + end do + + do i = 7, N + if (a(i) .ne. 6.0) call abort + end do + + !$acc exit data delete (a, b) + +end program + diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog index dbbd16099da..09b58655300 100644 --- a/libstdc++-v3/ChangeLog +++ b/libstdc++-v3/ChangeLog @@ -1,3 +1,8 @@ +2016-04-06 Eric Botcazou <ebotcazou@adacore.com> + + * src/Makefile.am (libstdc++-symbols.ver): Remove useless /dev/null. + * src/Makefile.in: Regenerate. + 2016-02-24 Jonathan Wakely <jwakely@redhat.com> PR libstdc++/69939 diff --git a/libstdc++-v3/src/Makefile.am b/libstdc++-v3/src/Makefile.am index a5f48b22c6d..fb0ec9a23c6 100644 --- a/libstdc++-v3/src/Makefile.am +++ b/libstdc++-v3/src/Makefile.am @@ -227,7 +227,7 @@ libstdc++-symbols.ver: ${glibcxx_srcdir}/$(SYMVER_FILE) \ chmod +w $@.tmp if test "x$(port_specific_symbol_files)" != x; then \ if grep '^# Appended to version file.' \ - $(port_specific_symbol_files) /dev/null > /dev/null 2>&1; then \ + $(port_specific_symbol_files) > /dev/null 2>&1; then \ cat $(port_specific_symbol_files) >> $@.tmp; \ else \ sed -n '1,/DO NOT DELETE/p' $@.tmp > tmp.top; \ diff --git a/libstdc++-v3/src/Makefile.in b/libstdc++-v3/src/Makefile.in index 176879194b2..5221a5d5c29 100644 --- a/libstdc++-v3/src/Makefile.in +++ b/libstdc++-v3/src/Makefile.in @@ -938,7 +938,7 @@ compatibility-condvar.o: compatibility-condvar.cc @ENABLE_SYMVERS_TRUE@ chmod +w $@.tmp @ENABLE_SYMVERS_TRUE@ if test "x$(port_specific_symbol_files)" != x; then \ @ENABLE_SYMVERS_TRUE@ if grep '^# Appended to version file.' \ -@ENABLE_SYMVERS_TRUE@ $(port_specific_symbol_files) /dev/null > /dev/null 2>&1; then \ +@ENABLE_SYMVERS_TRUE@ $(port_specific_symbol_files) > /dev/null 2>&1; then \ @ENABLE_SYMVERS_TRUE@ cat $(port_specific_symbol_files) >> $@.tmp; \ @ENABLE_SYMVERS_TRUE@ else \ @ENABLE_SYMVERS_TRUE@ sed -n '1,/DO NOT DELETE/p' $@.tmp > tmp.top; \ |