diff options
| author | clyon <clyon@138bc75d-0d04-0410-961f-82ee72b054a4> | 2014-11-03 15:39:32 +0000 |
|---|---|---|
| committer | clyon <clyon@138bc75d-0d04-0410-961f-82ee72b054a4> | 2014-11-03 15:39:32 +0000 |
| commit | 53f02ba9e2f9c3c84b085408706eda99625ce2d1 (patch) | |
| tree | 1503ec2602940b42f75718e185a46d6edee94389 | |
| parent | 22fc8281bfb4e05bf989a410a1cd5c85b7edbbb1 (diff) | |
| download | gcc-53f02ba9e2f9c3c84b085408706eda99625ce2d1.tar.gz | |
Merge branches/gcc-4_8-branch rev 216856
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@217046 138bc75d-0d04-0410-961f-82ee72b054a4
151 files changed, 3605 insertions, 735 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a7f5cbe955a..8d74c362b74 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,570 @@ +2014-10-29 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/aarch64/aarch64.c (aarch64_madd_needs_nop): Restore + recog state after aarch64_prev_real_insn call. + +2014-10-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config.gcc (aarch64*-*-*): Define TARGET_FIX_ERR_A53_835769_DEFAULT + if asked. + * configure.ac: Add --enable-fix-cortex-a53-835769 option. + * configure: Regenerate. + * config/aarch64/aarch64.c (aarch64_override_options): Handle + TARGET_FIX_ERR_A53_835769_DEFAULT. + * config/aarch64/aarch64.opt (mfix-cortex-a53-835769): Set Init value + to 2. + * doc/install.texi: Document --enable-fix-cortex-a53-835769 option. + +2014-10-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/aarch64/aarch64.opt (mfix-cortex-a53-835769): New option. + * config/aarch64/aarch64.h (ADJUST_INSN_LENGTH): Define. + (FINAL_PRESCAN_INSN): Likewise. + * config/aarch64/aarch64.h (is_mem_p): New function. + (has_memory_op): Likewise. + (aarch64_prev_real_insn): Likewise. + (is_madd_op): Likewise. + (dep_between_memop_and_curr): Likewise. + (aarch64_madd_needs_nop): Likewise. + (aarch64_final_prescan_insn): Likewise. + * doc/invoke.texi (Document new option). + +2014-10-15 Eric Botcazou <ebotcazou@adacore.com> + + * stor-layout.c (self_referential_size): Do not promote arguments. + +2014-10-12 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + Backport from mainline r215880 + 2014-10-03 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): + Issue a warning message when vec_lvsl or vec_lvsr is used with a + little endian target. + + Backport from mainline r215882 + 2014-10-03 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * altivec.md (altivec_lvsl): New define_expand. + (altivec_lvsl_direct): Rename define_insn from altivec_lvsl. + (altivec_lvsr): New define_expand. + (altivec_lvsr_direct): Rename define_insn from altivec_lvsr. + * rs6000.c (rs6000_expand_builtin): Change to use + altivec_lvs[lr]_direct; remove commented-out code. + +2014-10-09 Uros Bizjak <ubizjak@gmail.com> + + Backport from mainline + 2014-10-09 Uros Bizjak <ubizjak@gmail.com> + + PR rtl-optimization/57003 + * regcprop.c (copyprop_hardreg_forward_1): If ksvd.ignore_set_reg, + also check CALL_INSN_FUNCTION_USAGE for clobbers again after + killing regs_invalidated_by_call. + +2014-10-08 Oleg Endo <olegendo@gcc.gnu.org> + + Backport from mainline + 2014-10-08 Oleg Endo <olegendo@gcc.gnu.org> + + PR target/52941 + * config/sh/sync.md (atomic_exchangesi_hard, atomic_exchange<mode>_hard, + atomic_fetch_<fetchop_name>si_hard, + atomic_fetch_<fetchop_name><mode>_hard, atomic_fetch_nandsi_hard, + atomic_fetch_nand<mode>_hard, atomic_<fetchop_name>_fetchsi_hard, + atomic_<fetchop_name>_fetch<mode>_hard, atomic_nand_fetchsi_hard, + atomic_nand_fetch<mode>_hard): Add missing set of T_REG. + +2014-10-02 Martin Jambor <mjambor@suse.cz> + + PR tree-optimization/63375 + * tree-sra.c (build_access_from_expr_1): Disqualify volatile + references. + +2014-10-01 Jakub Jelinek <jakub@redhat.com> + + PR debug/63342 + * dwarf2out.c (loc_list_from_tree): Handle TARGET_MEM_REF and + SSA_NAME. + + PR target/63428 + * config/i386/i386.c (expand_vec_perm_pshufb): Fix up rperm[0] + argument to avx2_permv2ti. + +2014-10-01 Uros Bizjak <ubizjak@gmail.com> + + Backport from mainline + 2014-09-30 Uros Bizjak <ubizjak@gmail.com> + + * config/i386/i386.md (fmodxf3): Enable for flag_finite_math_only only. + (fmod<mode>3): Ditto. + (fpremxf4_i387): Ditto. + (reminderxf3): Ditto. + (reminder<mode>3): Ditto. + (fprem1xf4_i387): Ditto. + +2014-09-30 Jakub Jelinek <jakub@redhat.com> + + PR inline-asm/63282 + * ifcvt.c (dead_or_predicable): Don't call redirect_jump_1 + or invert_jump_1 if jump isn't any_condjump_p. + +2014-09-29 Charles Baylis <charles.baylis@linaro.org> + + Backport from mainline r212303 + PR target/49423 + * config/arm/arm-protos.h (arm_legitimate_address_p, + arm_is_constant_pool_ref): Add prototypes. + * config/arm/arm.c (arm_legitimate_address_p): Remove static. + (arm_is_constant_pool_ref) New function. + * config/arm/arm.md (unaligned_loadhis, arm_zero_extendhisi2_v6, + arm_zero_extendqisi2_v6): Use Uh constraint for memory operand. + (arm_extendhisi2, arm_extendhisi2_v6): Use Uh constraint for memory + operand and remove pool_range and neg_pool_range attributes. + (arm_extendqihi_insn, arm_extendqisi, arm_extendqisi_v6): Remove + pool_range and neg_pool_range attributes. + * config/arm/constraints.md (Uh): New constraint. (Uq): Don't allow + constant pool references. + +2014-09-28 John David Anglin <danglin@gcc.gnu.org> + + * config/pa/pa.c (pa_output_function_epilogue): Only update + last_address when a nonnote insn is found. + +2014-09-25 Oleg Endo <olegendo@gcc.gnu.org> + + Backport from mainline + 2014-09-25 Nick Clifton <nickc@redhat.com> + 2014-09-25 Oleg Endo <olegendo@gcc.gnu.org> + + PR target/62218 + * config/sh/sync.md (atomic_fetch_nand<mode>_soft_imask, + atomic_test_and_set_soft_imask): Fix typo in instruction sequence. + +2014-09-25 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + Backport from mainline r215559 + 2014-09-25 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + PR target/63335 + * config/rs6000/rs6000-c.c (altivec_build_resolved_builtin): + Exclude VSX_BUILTIN_XVCMPGEDP_P from special handling. + +2014-09-25 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/63341 + * tree-vectorizer.h (vect_create_data_ref_ptr, + vect_create_addr_base_for_vector_ref): Add another tree argument + defaulting to NULL_TREE. + * tree-vect-data-refs.c (vect_create_data_ref_ptr): Add byte_offset + argument, pass it down to vect_create_addr_base_for_vector_ref. + (vect_create_addr_base_for_vector_ref): Add byte_offset argument, + add that to base_offset too if non-NULL. + * tree-vect-stmts.c (vectorizable_load): Add byte_offset variable, + for dr_explicit_realign_optimized set it to vector byte size + - 1 instead of setting offset, pass byte_offset down to + vect_create_data_ref_ptr. + +2014-09-23 Michael Meissner <meissner@linux.vnet.ibm.com> + + Back port from trunk: + 2014-09-23 Michael Meissner <meissner@linux.vnet.ibm.com> + + * config/rs6000/rs6000.md (f32_vsx): New mode attributes to + refine the constraints used on 32/64-bit floating point moves. + (f32_av): Likewise. + (f64_vsx): Likewise. + (f64_dm): Likewise. + (f64_av): Likewise. + (BOOL_REGS_OUTPUT): Use wt constraint for TImode instead of wa. + (BOOL_REGS_OP1): Likewise. + (BOOL_REGS_OP2): Likewise. + (BOOL_REGS_UNARY): Likewise. + (mov<mode>_hardfloat, SFmode/SDmode): Tighten down constraints for + 32/64-bit floating point moves. Do not use wa, instead use ww/ws + for moves involving VSX registers. Do not use constraints that + target VSX registers for decimal types. + (mov<mode>_hardfloat32, DFmode/DDmode): Likewise. + (mov<mode>_hardfloat64, DFmode/DDmode): Likewise. + +2014-09-19 Michael Meissner <meissner@linux.vnet.ibm.com> + + Back port from trunk: + 2014-09-19 Michael Meissner <meissner@linux.vnet.ibm.com> + + * config/rs6000/predicates.md (fusion_gpr_mem_load): Move testing + for base_reg_operand to be common between LO_SUM and PLUS. + (fusion_gpr_mem_combo): New predicate to match a fused address + that combines the addis and memory offset address. + + * config/rs6000/rs6000-protos.h (fusion_gpr_load_p): Change + calling signature. + (emit_fusion_gpr_load): Likewise. + + * config/rs6000/rs6000.c (fusion_gpr_load_p): Change calling + signature to pass each argument separately, rather than + using an operands array. Rewrite the insns found by peephole2 to + be a single insn, rather than hoping the insns will still be + together when the peephole pass is done. Drop being called via a + normal peephole. + (emit_fusion_gpr_load): Change calling signature to be called from + the fusion_gpr_load_<mode> insns with a combined memory address + instead of the peephole pass passing the addis and offset + separately. + + * config/rs6000/rs6000.md (UNSPEC_FUSION_GPR): New unspec for GPR + fusion. + (power8 fusion peephole): Drop support for doing power8 via a + normal peephole that was created by the peephole2 pass. + (power8 fusion peephole2): Create a new insn with the fused + address, so that the fused operation is kept together after + register allocation is done. + (fusion_gpr_load_<mode>): Likewise. + +2014-09-17 Jakub Jelinek <jakub@redhat.com> + + PR debug/63284 + * tree-cfgcleanup.c (fixup_noreturn_call): Don't split block + if there are only debug stmts after the noreturn call, instead + remove the debug stmts. + +2014-09-10 Michael Meissner <meissner@linux.vnet.ibm.com> + + * config/rs6000/vsx.md (vsx_fmav4sf4): Use correct constraints for + V2DF, V4SF, DF, and DI modes. + (vsx_fmav2df2): Likewise. + (vsx_float_fix_<mode>2): Likewise. + (vsx_reduc_<VEC_reduc_name>_v2df_scalar): Likewise. + +2014-09-10 Alan Modra <amodra@gmail.com> + + PR debug/60655 + * dwarf2out.c (mem_loc_descriptor <PLUS>): Return NULL if addend + can't be output. + +2014-09-09 Richard Biener <rguenther@suse.de> + + Backport from mainline + 2014-06-11 Richard Biener <rguenther@suse.de> + + PR tree-optimization/61452 + * tree-ssa-sccvn.c (visit_phi): Remove pointless setting of + expr and has_constants in case we found a leader. + (simplify_binary_expression): Always valueize operands first. + (simplify_unary_expression): Likewise. + +2014-09-09 Richard Biener <rguenther@suse.de> + + Backport from mainline + 2014-05-05 Richard Biener <rguenther@suse.de> + + PR middle-end/61010 + * fold-const.c (fold_binary_loc): Consistently avoid + canonicalizing X & CST away from a CST that is the mask + of a mode. + + 2014-05-28 Richard Biener <rguenther@suse.de> + + PR middle-end/61045 + * fold-const.c (fold_comparison): When folding + X +- C1 CMP Y +- C2 to X CMP Y +- C2 +- C1 also ensure + the sign of the remaining constant operand stays the same. + + 2014-08-11 Richard Biener <rguenther@suse.de> + + PR tree-optimization/62075 + * tree-vect-slp.c (vect_detect_hybrid_slp_stmts): Properly + handle uses in patterns. + +2014-09-09 James Greenhalgh <james.greenhalgh@arm.com> + + Backport from mainline. + 2014-09-09 James Greenhalgh <james.greenhalgh@arm.com> + + * doc/invoke.texi (-march): Use GNU/Linux rather than Linux. + (-mtune): Likewise. + (-mcpu): Likewise. + +2014-09-08 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/60196 + PR tree-optimization/63189 + Backported from mainline + 2013-09-17 Cong Hou <congh@google.com> + + * tree-vect-patterns.c (vect_recog_dot_prod_pattern): Fix a bug + when checking the dot production pattern. The type of rhs operand + of multiply is now checked correctly. + +2014-09-08 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2014-08-06 Vladimir Makarov <vmakarov@redhat.com> + + PR debug/61923 + * haifa-sched.c (advance_one_cycle): Fix dump. + (schedule_block): Don't advance cycle if we are already at the + beginning of the cycle. + +2014-09-03 Martin Jambor <mjambor@suse.cz> + + PR ipa/62015 + * ipa-cp.c (intersect_aggregates_with_edge): Handle impermissible + pass-trough jump functions correctly. + +2014-09-03 Martin Jambor <mjambor@suse.cz> + + PR ipa/61986 + * ipa-cp.c (find_aggregate_values_for_callers_subset): Chain + created replacements in ascending order of offsets. + (known_aggs_to_agg_replacement_list): Likewise. + +2014-09-01 Marek Polacek <polacek@redhat.com> + + Backport from mainline + 2014-08-21 Marek Polacek <polacek@redhat.com> + + PR c/61271 + * expr.c (is_aligning_offset): Remove logical not. + +2014-09-01 Marek Polacek <polacek@redhat.com> + + Backport from mainline + 2014-08-19 Marek Polacek <polacek@redhat.com> + + PR c/61271 + * cgraphunit.c (handle_alias_pairs): Fix condition. + +2014-08-30 John David Anglin <danglin@gcc.gnu.org> + + * config/pa/pa.c (pa_assemble_integer): Don't add PLABEL relocation + prefix to function labels when generating fast indirect calls. + +2014-08-26 Joel Sherrill <joel.sherrill@oarcorp.com> + + * doc/invoke.texi: -fno-cxa-atexit should be -fno-use-cxa-atexit. + +2014-08-26 Marek Polacek <polacek@redhat.com> + + Backport from mainline + 2014-08-26 Marek Polacek <polacek@redhat.com> + + PR c/61271 + * tree-vectorizer.h (LOOP_REQUIRES_VERSIONING_FOR_ALIGNMENT, + LOOP_REQUIRES_VERSIONING_FOR_ALIAS): Wrap in parens. + +2014-08-24 Oleg Endo <olegendo@gcc.gnu.org> + + Backport from mainline + 2014-08-24 Oleg Endo <olegendo@gcc.gnu.org> + + PR target/61996 + * config/sh/sh.opt (musermode): Allow negative form. + * config/sh/sh.c (sh_option_override): Disable TARGET_USERMODE for + targets that don't support it. + * doc/invoke.texi (SH Options): Rename sh-*-linux* to sh*-*-linux*. + Document -mno-usermode option. + +2014-08-23 John David Anglin <danglin@gcc.gnu.org> + + PR target/62038 + * config/pa/pa.c (pa_output_function_epilogue): Don't set + last_address when the current function is a thunk. + (pa_asm_output_mi_thunk): When we don't have named sections or they + are not being used, check that thunk can reach the stub table with a + short branch. + +2014-08-22 Michael Meissner <meissner@linux.vnet.ibm.com> + + Backport fro mainline + 2014-08-22 Michael Meissner <meissner@linux.vnet.ibm.com> + + PR target/62195 + * doc/md.texi (Machine Constraints): Update PowerPC wi constraint + documentation to state it is only for VSX operations. + + * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Make wi + constraint only active if VSX. + + * config/rs6000/rs6000.md (lfiwax): Use wj constraint instead of + wi cosntraint for ISA 2.07 lxsiwax/lxsiwzx instructions. + (lfiwzx): Likewise. + +2014-08-15 Tom de Vries <tom@codesourcery.com> + + Backport from mainline: + 2014-08-14 Tom de Vries <tom@codesourcery.com> + + PR rtl-optimization/62004 + PR rtl-optimization/62030 + * ifcvt.c (rtx_interchangeable_p): New function. + (noce_try_move, noce_process_if_block): Use rtx_interchangeable_p. + + 2014-08-05 Richard Biener <rguenther@suse.de> + + * emit-rtl.h (mem_attrs_eq_p): Declare. + * emit-rtl.c (mem_attrs_eq_p): Export. + +2014-08-16 John David Anglin <danglin@gcc.gnu.org> + + Backport from trunk: + 2014-04-06 John David Anglin <danglin@gcc.gnu.org> + + PR debug/55794 + * config/pa/pa.c (pa_output_function_epilogue): Skip address and code + size accounting for thunks. + (pa_asm_output_mi_thunk): Use final_start_function() and + final_end_function() to output function start and end directives. + +2014-08-15 Oleg Endo <olegendo@gcc.gnu.org> + + Backport from mainline: + 2014-08-15 Oleg Endo <olegendo@gcc.gnu.org> + + * doc/invoke.texi (SH options): Document missing processor variant + options. Remove references to Hitachi. Undocument deprecated mspace + option. + +2014-08-13 Felix Yang <fei.yang0953@gmail.com> + + PR tree-optimization/62073 + * tree-vect-loop.c (vect_is_simple_reduction_1): Check that DEF1 has + a basic block. + +2014-08-13 Thomas Preud'homme <thomas.preudhomme@arm.com> + + Backport from mainline + 2014-08-12 Thomas Preud'homme <thomas.preudhomme@arm.com> + + PR middle-end/62103 + * gimple-fold.c (fold_ctor_reference): Don't fold in presence of + bitfields, that is when size doesn't match the size of type or the + size of the constructor. + +2014-08-12 Michael Meissner <meissner@linux.vnet.ibm.com> + + Backport patch from mainline + 2014-08-11 Michael Meissner <meissner@linux.vnet.ibm.com> + + * config/rs6000/constraints.md (wh constraint): New constraint, + for FP registers if direct move is available. + (wi constraint): New constraint, for VSX/FP registers that can + handle 64-bit integers. + (wj constraint): New constraint for VSX/FP registers that can + handle 64-bit integers for direct moves. + (wk constraint): New constraint for VSX/FP registers that can + handle 64-bit doubles for direct moves. + (wy constraint): Make documentation match implementation. + + * config/rs6000/rs6000.c (struct rs6000_reg_addr): Add + scalar_in_vmx_p field to simplify tests of whether SFmode or + DFmode can go in the Altivec registers. + (rs6000_hard_regno_mode_ok): Use scalar_in_vmx_p field. + (rs6000_setup_reg_addr_masks): Likewise. + (rs6000_debug_print_mode): Add debug support for scalar_in_vmx_p + field, and wh/wi/wj/wk constraints. + (rs6000_init_hard_regno_mode_ok): Setup scalar_in_vmx_p field, and + the wh/wi/wj/wk constraints. + (rs6000_preferred_reload_class): If SFmode/DFmode can go in the + upper registers, prefer VSX registers unless the operation is a + memory operation with REG+OFFSET addressing. + + * config/rs6000/vsx.md (VSr mode attribute): Add support for + DImode. Change SFmode to use ww constraint instead of d to allow + SF registers in the upper registers. + (VSr2): Likewise. + (VSr3): Likewise. + (VSr5): Fix thinko in comment. + (VSa): New mode attribute that is an alternative to wa, that + returns the VSX register class that a mode can go in, but may not + be the preferred register class. + (VS_64dm): New mode attribute for appropriate register classes for + referencing 64-bit elements of vectors for direct moves and normal + moves. + (VS_64reg): Likewise. + (vsx_mov<mode>): Change wa constraint to <VSa> to limit the + register allocator to only registers the data type can handle. + (vsx_le_perm_load_<mode>): Likewise. + (vsx_le_perm_store_<mode>): Likewise. + (vsx_xxpermdi2_le_<mode>): Likewise. + (vsx_xxpermdi4_le_<mode>): Likewise. + (vsx_lxvd2x2_le_<mode>): Likewise. + (vsx_lxvd2x4_le_<mode>): Likewise. + (vsx_stxvd2x2_le_<mode>): Likewise. + (vsx_add<mode>3): Likewise. + (vsx_sub<mode>3): Likewise. + (vsx_mul<mode>3): Likewise. + (vsx_div<mode>3): Likewise. + (vsx_tdiv<mode>3_internal): Likewise. + (vsx_fre<mode>2): Likewise. + (vsx_neg<mode>2): Likewise. + (vsx_abs<mode>2): Likewise. + (vsx_nabs<mode>2): Likewise. + (vsx_smax<mode>3): Likewise. + (vsx_smin<mode>3): Likewise. + (vsx_sqrt<mode>2): Likewise. + (vsx_rsqrte<mode>2): Likewise. + (vsx_tsqrt<mode>2_internal): Likewise. + (vsx_fms<mode>4): Likewise. + (vsx_nfma<mode>4): Likewise. + (vsx_eq<mode>): Likewise. + (vsx_gt<mode>): Likewise. + (vsx_ge<mode>): Likewise. + (vsx_eq<mode>_p): Likewise. + (vsx_gt<mode>_p): Likewise. + (vsx_ge<mode>_p): Likewise. + (vsx_xxsel<mode>): Likewise. + (vsx_xxsel<mode>_uns): Likewise. + (vsx_copysign<mode>3): Likewise. + (vsx_float<VSi><mode>2): Likewise. + (vsx_floatuns<VSi><mode>2): Likewise. + (vsx_fix_trunc<mode><VSi>2): Likewise. + (vsx_fixuns_trunc<mode><VSi>2): Likewise. + (vsx_x<VSv>r<VSs>i): Likewise. + (vsx_x<VSv>r<VSs>ic): Likewise. + (vsx_btrunc<mode>2): Likewise. + (vsx_b2trunc<mode>2): Likewise. + (vsx_floor<mode>2): Likewise. + (vsx_ceil<mode>2): Likewise. + (vsx_<VS_spdp_insn>): Likewise. + (vsx_xscvspdp): Likewise. + (vsx_xvcvspuxds): Likewise. + (vsx_float_fix_<mode>2): Likewise. + (vsx_set_<mode>): Likewise. + (vsx_extract_<mode>_internal1): Likewise. + (vsx_extract_<mode>_internal2): Likewise. + (vsx_extract_<mode>_load): Likewise. + (vsx_extract_<mode>_store): Likewise. + (vsx_splat_<mode>): Likewise. + (vsx_xxspltw_<mode>): Likewise. + (vsx_xxspltw_<mode>_direct): Likewise. + (vsx_xxmrghw_<mode>): Likewise. + (vsx_xxmrglw_<mode>): Likewise. + (vsx_xxsldwi_<mode>): Likewise. + (vsx_xscvdpspn): Tighten constraints to only use register classes + the types use. + (vsx_xscvspdpn): Likewise. + (vsx_xscvdpspn_scalar): Likewise. + + * config/rs6000/rs6000.h (enum rs6000_reg_class_enum): Add wh, wi, + wj, and wk constraints. + (GPR_REG_CLASS_P): New helper macro for register classes targeting + general purpose registers. + + * config/rs6000/rs6000.md (f32_dm): Use wh constraint for SDmode + direct moves. + (zero_extendsidi2_lfiwz): Use wj constraint for direct move of + DImode instead of wm. Use wk constraint for direct move of DFmode + instead of wm. + (extendsidi2_lfiwax): Likewise. + (lfiwax): Likewise. + (lfiwzx): Likewise. + (movdi_internal64): Likewise. + + * doc/md.texi (PowerPC and IBM RS6000): Document wh, wi, wj, and + wk constraints. Make the wy constraint documentation match them + implementation. + 2014-08-01 Thomas Preud'homme <thomas.preudhomme@arm.com> Backport from mainline diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index fb37762b343..bc560ac589b 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20140811 +20141030 diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog index eea52d22a0e..2f39ad5dbe1 100644 --- a/gcc/ada/ChangeLog +++ b/gcc/ada/ChangeLog @@ -1,3 +1,20 @@ +2014-10-13 Eric Botcazou <ebotcazou@adacore.com> + Alan Modra <amodra@gmail.com> + + PR ada/63225 + * uintp.adb (Vector_To_Uint): Move from here to... + * uintp.ads (UI_Vector): Make public. + (Vector_To_Uint): ...here. + +2014-08-12 Joel Sherrill <joel.sherrill@oarcorp.com> + + * socket.c: For RTEMS, use correct prototype of gethostbyname_r(). + * gsocket.h Add include of <unistd.h> on RTEMS. + +2014-08-11 Joel Sherrill <joel.sherrill@oarcorp.com> + + * s-osinte-rtems.adb: Correct formatting of line in license block. + 2014-05-22 Release Manager * GCC 4.8.3 released. diff --git a/gcc/ada/gsocket.h b/gcc/ada/gsocket.h index e21d7142701..1d9235f4ad8 100644 --- a/gcc/ada/gsocket.h +++ b/gcc/ada/gsocket.h @@ -183,6 +183,11 @@ #include <sys/time.h> #endif +#if defined(__rtems__) +#include <unistd.h> +/* Required, for read(), write(), and close() */ +#endif + /* * RTEMS has these .h files but not until you have built and installed RTEMS. * When building a C/C++ toolset, you also build the newlib C library, so the diff --git a/gcc/ada/s-osinte-rtems.adb b/gcc/ada/s-osinte-rtems.adb index de21785941a..9f01128c918 100644 --- a/gcc/ada/s-osinte-rtems.adb +++ b/gcc/ada/s-osinte-rtems.adb @@ -22,7 +22,7 @@ -- You should have received a copy of the GNU General Public License and -- -- a copy of the GCC Runtime Library Exception along with this program; -- -- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -- --- <http://www.gnu.org/licenses/>. +-- <http://www.gnu.org/licenses/>. -- -- -- -- GNARL was developed by the GNARL team at Florida State University. It is -- -- now maintained by Ada Core Technologies Inc. in cooperation with Florida -- diff --git a/gcc/ada/socket.c b/gcc/ada/socket.c index 18999b394ea..e65845628a1 100644 --- a/gcc/ada/socket.c +++ b/gcc/ada/socket.c @@ -212,7 +212,7 @@ __gnat_gethostbyname (const char *name, struct hostent *rh; int ri; -#if defined(__linux__) || defined(__GLIBC__) +#if defined(__linux__) || defined(__GLIBC__) || defined(__rtems__) (void) gethostbyname_r (name, ret, buf, buflen, &rh, h_errnop); #else rh = gethostbyname_r (name, ret, buf, buflen, h_errnop); diff --git a/gcc/ada/uintp.adb b/gcc/ada/uintp.adb index bc014666224..7618898af95 100644 --- a/gcc/ada/uintp.adb +++ b/gcc/ada/uintp.adb @@ -171,22 +171,6 @@ package body Uintp is -- If Discard_Quotient is True, Quotient is set to No_Uint -- If Discard_Remainder is True, Remainder is set to No_Uint - function Vector_To_Uint - (In_Vec : UI_Vector; - Negative : Boolean) return Uint; - -- Functions that calculate values in UI_Vectors, call this function to - -- create and return the Uint value. In_Vec contains the multiple precision - -- (Base) representation of a non-negative value. Leading zeroes are - -- permitted. Negative is set if the desired result is the negative of the - -- given value. The result will be either the appropriate directly - -- represented value, or a table entry in the proper canonical format is - -- created and returned. - -- - -- Note that Init_Operand puts a signed value in the result vector, but - -- Vector_To_Uint is always presented with a non-negative value. The - -- processing of signs is something that is done by the caller before - -- calling Vector_To_Uint. - ------------ -- Direct -- ------------ diff --git a/gcc/ada/uintp.ads b/gcc/ada/uintp.ads index dcf85a07f37..d76d2852704 100644 --- a/gcc/ada/uintp.ads +++ b/gcc/ada/uintp.ads @@ -90,6 +90,18 @@ package Uintp is Uint_Minus_80 : constant Uint; Uint_Minus_128 : constant Uint; + type UI_Vector is array (Pos range <>) of Int; + -- Vector containing the integer values of a Uint value + + -- Note: An earlier version of this package used pointers of arrays of Ints + -- (dynamically allocated) for the Uint type. The change leads to a few + -- less natural idioms used throughout this code, but eliminates all uses + -- of the heap except for the table package itself. For example, Uint + -- parameters are often converted to UI_Vectors for internal manipulation. + -- This is done by creating the local UI_Vector using the function N_Digits + -- on the Uint to find the size needed for the vector, and then calling + -- Init_Operand to copy the values out of the table into the vector. + ----------------- -- Subprograms -- ----------------- @@ -252,6 +264,22 @@ package Uintp is -- function is used for capacity checks, and it can be one bit off -- without affecting its usage. + function Vector_To_Uint + (In_Vec : UI_Vector; + Negative : Boolean) return Uint; + -- Functions that calculate values in UI_Vectors, call this function to + -- create and return the Uint value. In_Vec contains the multiple precision + -- (Base) representation of a non-negative value. Leading zeroes are + -- permitted. Negative is set if the desired result is the negative of the + -- given value. The result will be either the appropriate directly + -- represented value, or a table entry in the proper canonical format is + -- created and returned. + -- + -- Note that Init_Operand puts a signed value in the result vector, but + -- Vector_To_Uint is always presented with a non-negative value. The + -- processing of signs is something that is done by the caller before + -- calling Vector_To_Uint. + --------------------- -- Output Routines -- --------------------- @@ -494,18 +522,6 @@ private -- UI_Vector is defined for this purpose and some internal subprograms -- used for converting from one to the other are defined. - type UI_Vector is array (Pos range <>) of Int; - -- Vector containing the integer values of a Uint value - - -- Note: An earlier version of this package used pointers of arrays of Ints - -- (dynamically allocated) for the Uint type. The change leads to a few - -- less natural idioms used throughout this code, but eliminates all uses - -- of the heap except for the table package itself. For example, Uint - -- parameters are often converted to UI_Vectors for internal manipulation. - -- This is done by creating the local UI_Vector using the function N_Digits - -- on the Uint to find the size needed for the vector, and then calling - -- Init_Operand to copy the values out of the table into the vector. - type Uint_Entry is record Length : Pos; -- Length of entry in Udigits table in digits (i.e. in words) diff --git a/gcc/cgraphunit.c b/gcc/cgraphunit.c index 7fa8055878c..7dd2c1d5595 100644 --- a/gcc/cgraphunit.c +++ b/gcc/cgraphunit.c @@ -1097,7 +1097,7 @@ handle_alias_pairs (void) /* We use local aliases for C++ thunks to force the tailcall to bind locally. This is a hack - to keep it working do the following (which is not strictly correct). */ - && (! TREE_CODE (target_node->symbol.decl) == FUNCTION_DECL + && (TREE_CODE (target_node->symbol.decl) != FUNCTION_DECL || ! DECL_VIRTUAL_P (target_node->symbol.decl)) && ! lookup_attribute ("weakref", DECL_ATTRIBUTES (p->decl))) { diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index f19045d0792..7e7f1c3d573 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -300,6 +300,8 @@ aarch64_builtin_vectorized_function (tree fndecl, extern void aarch64_split_combinev16qi (rtx operands[3]); extern void aarch64_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel); +extern bool aarch64_madd_needs_nop (rtx); +extern void aarch64_final_prescan_insn (rtx); extern bool aarch64_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel); #endif /* GCC_AARCH64_PROTOS_H */ diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 9f9570e3edf..ddf5f929b3e 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -5109,6 +5109,15 @@ aarch64_override_options (void) aarch64_tune = selected_tune->core; aarch64_tune_params = selected_tune->tune; + if (aarch64_fix_a53_err835769 == 2) + { +#ifdef TARGET_FIX_ERR_A53_835769_DEFAULT + aarch64_fix_a53_err835769 = 1; +#else + aarch64_fix_a53_err835769 = 0; +#endif + } + aarch64_override_options_after_change (); } @@ -6305,6 +6314,148 @@ aarch64_mangle_type (const_tree type) return NULL; } + +/* Return true iff X is a MEM rtx. */ + +static int +is_mem_p (rtx *x, void *data ATTRIBUTE_UNUSED) +{ + return MEM_P (*x); +} + + +/* Return true if mem_insn contains a MEM RTX somewhere in it. */ + +static bool +has_memory_op (rtx mem_insn) +{ + rtx pattern = PATTERN (mem_insn); + return for_each_rtx (&pattern, is_mem_p, NULL); +} + + +/* Find the first rtx before insn that will generate an assembly + instruction. */ + +static rtx +aarch64_prev_real_insn (rtx insn) +{ + if (!insn) + return NULL; + + do + { + insn = prev_real_insn (insn); + } + while (insn && recog_memoized (insn) < 0); + + return insn; +} + +/* Return true iff t1 is the type of a multiply-accumulate instruction. */ + +static bool +is_madd_op (enum attr_type t1) +{ + unsigned int i; + /* A number of these may be AArch32 only. */ + enum attr_type mlatypes[] = { + TYPE_MLA, TYPE_MLAS, TYPE_SMLAD, TYPE_SMLADX, TYPE_SMLAL, TYPE_SMLALD, + TYPE_SMLALS, TYPE_SMLALXY, TYPE_SMLAWX, TYPE_SMLAWY, TYPE_SMLAXY, + TYPE_SMMLA, TYPE_UMLAL, TYPE_UMLALS,TYPE_SMLSD, TYPE_SMLSDX, TYPE_SMLSLD + }; + + for (i = 0; i < sizeof (mlatypes) / sizeof (enum attr_type); i++) + { + if (t1 == mlatypes[i]) + return true; + } + + return false; +} + + +/* Check if there is a register dependency between a load and the insn + for which we hold recog_data. */ + +static bool +dep_between_memop_and_curr (rtx memop) +{ + rtx load_reg; + int opno; + + gcc_assert (GET_CODE (memop) == SET); + + if (!REG_P (SET_DEST (memop))) + return false; + + load_reg = SET_DEST (memop); + for (opno = 1; opno < recog_data.n_operands; opno++) + { + rtx operand = recog_data.operand[opno]; + if (REG_P (operand) + && reg_overlap_mentioned_p (load_reg, operand)) + return true; + + } + return false; +} + + + +/* When working around the Cortex-A53 erratum 835769, + given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate + instruction and has a preceding memory instruction such that a NOP + should be inserted between them. */ + +bool +aarch64_madd_needs_nop (rtx insn) +{ + enum attr_type attr_type; + rtx prev; + rtx body; + + if (!aarch64_fix_a53_err835769) + return false; + + if (recog_memoized (insn) < 0) + return false; + + attr_type = get_attr_type (insn); + if (!is_madd_op (attr_type)) + return false; + + prev = aarch64_prev_real_insn (insn); + /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN. + Restore recog state to INSN to avoid state corruption. */ + extract_constrain_insn_cached (insn); + + if (!prev || !has_memory_op (prev)) + return false; + + body = single_set (prev); + + /* If the previous insn is a memory op and there is no dependency between + it and the madd, emit a nop between them. If we know it's a memop but + body is NULL, return true to be safe. */ + if (GET_MODE (recog_data.operand[0]) == DImode + && (!body || !dep_between_memop_and_curr (body))) + return true; + + return false; + +} + +/* Implement FINAL_PRESCAN_INSN. */ + +void +aarch64_final_prescan_insn (rtx insn) +{ + if (aarch64_madd_needs_nop (insn)) + fprintf (asm_out_file, "\tnop // between mem op and mult-accumulate\n"); +} + + /* Return the equivalent letter for size. */ static char sizetochar (int size) diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 26ab9d55124..dd101d17536 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -471,6 +471,18 @@ enum target_cpus (TARGET_CPU_cortexa53 | (AARCH64_CPU_DEFAULT_FLAGS << 6)) #endif +/* If inserting NOP before a mult-accumulate insn remember to adjust the + length so that conditional branching code is updated appropriately. */ +#define ADJUST_INSN_LENGTH(insn, length) \ + do \ + { \ + if (aarch64_madd_needs_nop (insn)) \ + length += 4; \ + } while (0) + +#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ + aarch64_final_prescan_insn (INSN); \ + /* The processor for which instructions should be scheduled. */ extern enum aarch64_processor aarch64_tune; diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt index 35182489d79..f7c70bf8f08 100644 --- a/gcc/config/aarch64/aarch64.opt +++ b/gcc/config/aarch64/aarch64.opt @@ -67,6 +67,10 @@ mgeneral-regs-only Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Generate code which uses only the general registers +mfix-cortex-a53-835769 +Target Report Var(aarch64_fix_a53_err835769) Init(2) +Workaround for ARM Cortex-A53 Erratum number 835769 + mlittle-endian Target Report RejectNegative InverseMask(BIG_END) Assume target CPU is configured as little endian diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 8a8e36dac4e..e7da7fc8007 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -56,6 +56,7 @@ extern int arm_split_constant (RTX_CODE, enum machine_mode, rtx, extern int legitimate_pic_operand_p (rtx); extern rtx legitimize_pic_address (rtx, enum machine_mode, rtx); extern rtx legitimize_tls_address (rtx, rtx); +extern bool arm_legitimate_address_p (enum machine_mode, rtx, bool); extern int arm_legitimate_address_outer_p (enum machine_mode, rtx, RTX_CODE, int); extern int thumb_legitimate_offset_p (enum machine_mode, HOST_WIDE_INT); extern bool arm_legitimize_reload_address (rtx *, enum machine_mode, int, int, @@ -285,4 +286,6 @@ extern bool arm_autoinc_modes_ok_p (enum machine_mode, enum arm_auto_incmodes); extern void arm_emit_eabi_attribute (const char *, int, int); +extern bool arm_is_constant_pool_ref (rtx); + #endif /* ! GCC_ARM_PROTOS_H */ diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 81a5e6b1593..80891343bdd 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -82,7 +82,6 @@ static rtx arm_legitimize_address (rtx, rtx, enum machine_mode); static reg_class_t arm_preferred_reload_class (rtx, reg_class_t); static rtx thumb_legitimize_address (rtx, rtx, enum machine_mode); inline static int thumb1_index_register_rtx_p (rtx, int); -static bool arm_legitimate_address_p (enum machine_mode, rtx, bool); static int thumb_far_jump_used_p (void); static bool thumb_force_lr_save (void); static unsigned arm_size_return_regs (void); @@ -28544,4 +28543,13 @@ arm_asan_shadow_offset (void) return (unsigned HOST_WIDE_INT) 1 << 29; } +/* return TRUE if x is a reference to a value in a constant pool */ +extern bool +arm_is_constant_pool_ref (rtx x) +{ + return (MEM_P (x) + && GET_CODE (XEXP (x, 0)) == SYMBOL_REF + && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0))); +} + #include "gt-arm.h" diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 452fe5f997e..aff783833a0 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -4440,7 +4440,7 @@ (define_insn "unaligned_loadhis" [(set (match_operand:SI 0 "s_register_operand" "=l,r") (sign_extend:SI - (unspec:HI [(match_operand:HI 1 "memory_operand" "Uw,m")] + (unspec:HI [(match_operand:HI 1 "memory_operand" "Uw,Uh")] UNSPEC_UNALIGNED_LOAD)))] "unaligned_access && TARGET_32BIT" "ldr%(sh%)\t%0, %1\t@ unaligned" @@ -5239,7 +5239,7 @@ (define_insn "*arm_zero_extendhisi2_v6" [(set (match_operand:SI 0 "s_register_operand" "=r,r") - (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] + (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,Uh")))] "TARGET_ARM && arm_arch6" "@ uxth%?\\t%0, %1 @@ -5333,7 +5333,7 @@ (define_insn "*arm_zero_extendqisi2_v6" [(set (match_operand:SI 0 "s_register_operand" "=r,r") - (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,Uh")))] "TARGET_ARM && arm_arch6" "@ uxtb%(%)\\t%0, %1 @@ -5567,31 +5567,27 @@ (define_insn "*arm_extendhisi2" [(set (match_operand:SI 0 "s_register_operand" "=r,r") - (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,Uh")))] "TARGET_ARM && arm_arch4 && !arm_arch6" "@ # ldr%(sh%)\\t%0, %1" [(set_attr "length" "8,4") (set_attr "type" "alu_shift_reg,load_byte") - (set_attr "predicable" "yes") - (set_attr "pool_range" "*,256") - (set_attr "neg_pool_range" "*,244")] + (set_attr "predicable" "yes")] ) ;; ??? Check Thumb-2 pool range (define_insn "*arm_extendhisi2_v6" [(set (match_operand:SI 0 "s_register_operand" "=r,r") - (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,Uh")))] "TARGET_32BIT && arm_arch6" "@ sxth%?\\t%0, %1 ldr%(sh%)\\t%0, %1" [(set_attr "type" "extend,load_byte") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") - (set_attr "pool_range" "*,256") - (set_attr "neg_pool_range" "*,244")] + (set_attr "predicable_short_it" "no")] ) (define_insn "*arm_extendhisi2addsi" @@ -5634,9 +5630,7 @@ "TARGET_ARM && arm_arch4" "ldr%(sb%)\\t%0, %1" [(set_attr "type" "load_byte") - (set_attr "predicable" "yes") - (set_attr "pool_range" "256") - (set_attr "neg_pool_range" "244")] + (set_attr "predicable" "yes")] ) (define_expand "extendqisi2" @@ -5676,9 +5670,7 @@ ldr%(sb%)\\t%0, %1" [(set_attr "length" "8,4") (set_attr "type" "alu_shift_reg,load_byte") - (set_attr "predicable" "yes") - (set_attr "pool_range" "*,256") - (set_attr "neg_pool_range" "*,244")] + (set_attr "predicable" "yes")] ) (define_insn "*arm_extendqisi_v6" @@ -5690,9 +5682,7 @@ sxtb%?\\t%0, %1 ldr%(sb%)\\t%0, %1" [(set_attr "type" "extend,load_byte") - (set_attr "predicable" "yes") - (set_attr "pool_range" "*,256") - (set_attr "neg_pool_range" "*,244")] + (set_attr "predicable" "yes")] ) (define_insn "*arm_extendqisi2addsi" diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index d7b9cb99808..40c8b1530b3 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -36,7 +36,7 @@ ;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py ;; The following memory constraints have been used: -;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us +;; in ARM/Thumb-2 state: Q, Uh, Ut, Uv, Uy, Un, Um, Us ;; in ARM state: Uq ;; in Thumb state: Uu, Uw @@ -342,6 +342,12 @@ An address valid for loading/storing register exclusive" (match_operand 0 "mem_noofs_operand")) +(define_memory_constraint "Uh" + "@internal + An address suitable for byte and half-word loads which does not point inside a constant pool" + (and (match_code "mem") + (match_test "arm_legitimate_address_p (GET_MODE (op), XEXP (op, 0), false) && !arm_is_constant_pool_ref (op)"))) + (define_memory_constraint "Ut" "@internal In ARM/Thumb-2 state an address valid for loading/storing opaque structure @@ -388,7 +394,8 @@ (and (match_code "mem") (match_test "TARGET_ARM && arm_legitimate_address_outer_p (GET_MODE (op), XEXP (op, 0), - SIGN_EXTEND, 0)"))) + SIGN_EXTEND, 0) + && !arm_is_constant_pool_ref (op)"))) (define_memory_constraint "Q" "@internal diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 5e84e53fb13..73f8a44a209 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -38811,8 +38811,8 @@ expand_vec_perm_pshufb (struct expand_vec_perm_d *d) op0 = gen_lowpart (V4DImode, d->op0); op1 = gen_lowpart (V4DImode, d->op1); rperm[0] - = GEN_INT (((d->perm[0] & (nelt / 2)) ? 1 : 0) - || ((d->perm[nelt / 2] & (nelt / 2)) ? 2 : 0)); + = GEN_INT ((d->perm[0] / (nelt / 2)) + | ((d->perm[nelt / 2] / (nelt / 2)) * 16)); emit_insn (gen_avx2_permv2ti (target, op0, op1, rperm[0])); return true; } diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index d5055943f13..24e93f9f41a 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -13516,7 +13516,8 @@ (set (reg:CCFP FPSR_REG) (unspec:CCFP [(match_dup 2) (match_dup 3)] UNSPEC_C2_FLAG))] - "TARGET_USE_FANCY_MATH_387" + "TARGET_USE_FANCY_MATH_387 + && flag_finite_math_only" "fprem" [(set_attr "type" "fpspc") (set_attr "mode" "XF")]) @@ -13525,7 +13526,8 @@ [(use (match_operand:XF 0 "register_operand")) (use (match_operand:XF 1 "general_operand")) (use (match_operand:XF 2 "general_operand"))] - "TARGET_USE_FANCY_MATH_387" + "TARGET_USE_FANCY_MATH_387 + && flag_finite_math_only" { rtx label = gen_label_rtx (); @@ -13548,7 +13550,8 @@ [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "general_operand")) (use (match_operand:MODEF 2 "general_operand"))] - "TARGET_USE_FANCY_MATH_387" + "TARGET_USE_FANCY_MATH_387 + && flag_finite_math_only" { rtx (*gen_truncxf) (rtx, rtx); @@ -13587,7 +13590,8 @@ (set (reg:CCFP FPSR_REG) (unspec:CCFP [(match_dup 2) (match_dup 3)] UNSPEC_C2_FLAG))] - "TARGET_USE_FANCY_MATH_387" + "TARGET_USE_FANCY_MATH_387 + && flag_finite_math_only" "fprem1" [(set_attr "type" "fpspc") (set_attr "mode" "XF")]) @@ -13596,7 +13600,8 @@ [(use (match_operand:XF 0 "register_operand")) (use (match_operand:XF 1 "general_operand")) (use (match_operand:XF 2 "general_operand"))] - "TARGET_USE_FANCY_MATH_387" + "TARGET_USE_FANCY_MATH_387 + && flag_finite_math_only" { rtx label = gen_label_rtx (); @@ -13619,7 +13624,8 @@ [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "general_operand")) (use (match_operand:MODEF 2 "general_operand"))] - "TARGET_USE_FANCY_MATH_387" + "TARGET_USE_FANCY_MATH_387 + && flag_finite_math_only" { rtx (*gen_truncxf) (rtx, rtx); diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c index 7603858340d..47fd47f196d 100644 --- a/gcc/config/pa/pa.c +++ b/gcc/config/pa/pa.c @@ -3237,7 +3237,12 @@ pa_assemble_integer (rtx x, unsigned int size, int aligned_p) && aligned_p && function_label_operand (x, VOIDmode)) { - fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file); + fputs (size == 8? "\t.dword\t" : "\t.word\t", asm_out_file); + + /* We don't want an OPD when generating fast indirect calls. */ + if (!TARGET_FAST_INDIRECT_CALLS) + fputs ("P%", asm_out_file); + output_addr_const (asm_out_file, x); fputc ('\n', asm_out_file); return true; @@ -4160,8 +4165,7 @@ static void pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) { rtx insn = get_last_insn (); - - last_address = 0; + bool extra_nop; /* pa_expand_epilogue does the dirty work now. We just need to output the assembler directives which denote the end @@ -4185,26 +4189,36 @@ pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) if (insn && GET_CODE (insn) == CALL_INSN) { fputs ("\tnop\n", file); - last_address += 4; + extra_nop = true; } + else + extra_nop = false; fputs ("\t.EXIT\n\t.PROCEND\n", file); if (TARGET_SOM && TARGET_GAS) { - /* We done with this subspace except possibly for some additional + /* We are done with this subspace except possibly for some additional debug information. Forget that we are in this subspace to ensure that the next function is output in its own subspace. */ in_section = NULL; cfun->machine->in_nsubspa = 2; } + /* Thunks do their own insn accounting. */ + if (cfun->is_thunk) + return; + if (INSN_ADDRESSES_SET_P ()) { + last_address = extra_nop ? 4 : 0; insn = get_last_nonnote_insn (); - last_address += INSN_ADDRESSES (INSN_UID (insn)); - if (INSN_P (insn)) - last_address += insn_default_length (insn); + if (insn) + { + last_address += INSN_ADDRESSES (INSN_UID (insn)); + if (INSN_P (insn)) + last_address += insn_default_length (insn); + } last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1) & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)); } @@ -8270,8 +8284,7 @@ pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta, xoperands[1] = XEXP (DECL_RTL (thunk_fndecl), 0); xoperands[2] = GEN_INT (delta); - ASM_OUTPUT_LABEL (file, XSTR (xoperands[1], 0)); - fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n"); + final_start_function (emit_barrier (), file, 1); /* Output the thunk. We know that the function is in the same translation unit (i.e., the same space) as the thunk, and that @@ -8301,12 +8314,16 @@ pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta, || ((DECL_SECTION_NAME (thunk_fndecl) == DECL_SECTION_NAME (function)) && last_address < 262132))) + /* In this case, we need to be able to reach the start of + the stub table even though the function is likely closer + and can be jumped to directly. */ || (targetm_common.have_named_sections && DECL_SECTION_NAME (thunk_fndecl) == NULL && DECL_SECTION_NAME (function) == NULL - && last_address < 262132) + && total_code_bytes < MAX_PCREL17F_OFFSET) + /* Likewise. */ || (!targetm_common.have_named_sections - && last_address < 262132)))) + && total_code_bytes < MAX_PCREL17F_OFFSET)))) { if (!val_14) output_asm_insn ("addil L'%2,%%r26", xoperands); @@ -8477,16 +8494,7 @@ pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta, } } - fprintf (file, "\t.EXIT\n\t.PROCEND\n"); - - if (TARGET_SOM && TARGET_GAS) - { - /* We done with this subspace except possibly for some additional - debug information. Forget that we are in this subspace to ensure - that the next function is output in its own subspace. */ - in_section = NULL; - cfun->machine->in_nsubspa = 2; - } + final_end_function (); if (TARGET_SOM && flag_pic && TREE_PUBLIC (function)) { diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 6abb4feb5eb..47a4610b78a 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -2297,7 +2297,31 @@ "dststt %0,%1,%2" [(set_attr "type" "vecsimple")]) -(define_insn "altivec_lvsl" +(define_expand "altivec_lvsl" + [(use (match_operand:V16QI 0 "register_operand" "")) + (use (match_operand:V16QI 1 "memory_operand" ""))] + "TARGET_ALTIVEC" +{ + if (VECTOR_ELT_ORDER_BIG) + emit_insn (gen_altivec_lvsl_direct (operands[0], operands[1])); + else + { + int i; + rtx mask, perm[16], constv, vperm; + mask = gen_reg_rtx (V16QImode); + emit_insn (gen_altivec_lvsl_direct (mask, operands[1])); + for (i = 0; i < 16; ++i) + perm[i] = GEN_INT (i); + constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm)); + constv = force_reg (V16QImode, constv); + vperm = gen_rtx_UNSPEC (V16QImode, gen_rtvec (3, mask, mask, constv), + UNSPEC_VPERM); + emit_insn (gen_rtx_SET (VOIDmode, operands[0], vperm)); + } + DONE; +}) + +(define_insn "altivec_lvsl_direct" [(set (match_operand:V16QI 0 "register_operand" "=v") (unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "Z")] UNSPEC_LVSL))] @@ -2305,7 +2329,31 @@ "lvsl %0,%y1" [(set_attr "type" "vecload")]) -(define_insn "altivec_lvsr" +(define_expand "altivec_lvsr" + [(use (match_operand:V16QI 0 "register_operand" "")) + (use (match_operand:V16QI 1 "memory_operand" ""))] + "TARGET_ALTIVEC" +{ + if (VECTOR_ELT_ORDER_BIG) + emit_insn (gen_altivec_lvsr_direct (operands[0], operands[1])); + else + { + int i; + rtx mask, perm[16], constv, vperm; + mask = gen_reg_rtx (V16QImode); + emit_insn (gen_altivec_lvsr_direct (mask, operands[1])); + for (i = 0; i < 16; ++i) + perm[i] = GEN_INT (i); + constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm)); + constv = force_reg (V16QImode, constv); + vperm = gen_rtx_UNSPEC (V16QImode, gen_rtvec (3, mask, mask, constv), + UNSPEC_VPERM); + emit_insn (gen_rtx_SET (VOIDmode, operands[0], vperm)); + } + DONE; +}) + +(define_insn "altivec_lvsr_direct" [(set (match_operand:V16QI 0 "register_operand" "=v") (unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "Z")] UNSPEC_LVSR))] diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 4467b9e3d8b..1724d28f7bc 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -65,6 +65,20 @@ (define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]" "If -mmfpgpr was used, a floating point register or NO_REGS.") +(define_register_constraint "wh" "rs6000_constraints[RS6000_CONSTRAINT_wh]" + "Floating point register if direct moves are available, or NO_REGS.") + +;; At present, DImode is not allowed in the Altivec registers. If in the +;; future it is allowed, wi/wj can be set to VSX_REGS instead of FLOAT_REGS. +(define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]" + "FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.") + +(define_register_constraint "wj" "rs6000_constraints[RS6000_CONSTRAINT_wj]" + "FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.") + +(define_register_constraint "wk" "rs6000_constraints[RS6000_CONSTRAINT_wk]" + "FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.") + (define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]" "Floating point register if the LFIWAX instruction is enabled or NO_REGS.") @@ -98,7 +112,7 @@ "Floating point register if the STFIWX instruction is enabled or NO_REGS.") (define_register_constraint "wy" "rs6000_constraints[RS6000_CONSTRAINT_wy]" - "VSX vector register to hold scalar float values or NO_REGS.") + "FP or VSX register to perform ISA 2.07 float ops or NO_REGS.") (define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]" "Floating point register if the LFIWZX instruction is enabled or NO_REGS.") diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 0659e066eee..6ee392d837f 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -1795,7 +1795,7 @@ (define_predicate "fusion_gpr_mem_load" (match_code "mem,sign_extend,zero_extend") { - rtx addr; + rtx addr, base, offset; /* Handle sign/zero extend. */ if (GET_CODE (op) == ZERO_EXTEND @@ -1825,24 +1825,79 @@ } addr = XEXP (op, 0); + if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM) + return 0; + + base = XEXP (addr, 0); + if (!base_reg_operand (base, GET_MODE (base))) + return 0; + + offset = XEXP (addr, 1); + if (GET_CODE (addr) == PLUS) + return satisfies_constraint_I (offset); + + else if (GET_CODE (addr) == LO_SUM) { - rtx base = XEXP (addr, 0); - rtx offset = XEXP (addr, 1); + if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64)) + return small_toc_ref (offset, GET_MODE (offset)); - return (base_reg_operand (base, GET_MODE (base)) - && satisfies_constraint_I (offset)); + else if (TARGET_ELF && !TARGET_POWERPC64) + return CONSTANT_P (offset); } - else if (GET_CODE (addr) == LO_SUM) + return 0; +}) + +;; Match a GPR load (lbz, lhz, lwz, ld) that uses a combined address in the +;; memory field with both the addis and the memory offset. Sign extension +;; is not handled here, since lha and lwa are not fused. +(define_predicate "fusion_gpr_mem_combo" + (match_code "mem,zero_extend") +{ + rtx addr, base, offset; + + /* Handle zero extend. */ + if (GET_CODE (op) == ZERO_EXTEND) { - rtx base = XEXP (addr, 0); - rtx offset = XEXP (addr, 1); + op = XEXP (op, 0); + mode = GET_MODE (op); + } + + if (!MEM_P (op)) + return 0; - if (!base_reg_operand (base, GET_MODE (base))) + switch (mode) + { + case QImode: + case HImode: + case SImode: + break; + + case DImode: + if (!TARGET_POWERPC64) return 0; + break; - else if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64)) + default: + return 0; + } + + addr = XEXP (op, 0); + if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM) + return 0; + + base = XEXP (addr, 0); + if (!fusion_gpr_addis (base, GET_MODE (base))) + return 0; + + offset = XEXP (addr, 1); + if (GET_CODE (addr) == PLUS) + return satisfies_constraint_I (offset); + + else if (GET_CODE (addr) == LO_SUM) + { + if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64)) return small_toc_ref (offset, GET_MODE (offset)); else if (TARGET_ELF && !TARGET_POWERPC64) diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index 9cb6387b9ed..3009f1ea80e 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -4126,7 +4126,8 @@ altivec_build_resolved_builtin (tree *args, int n, argument) is reversed. Patch the arguments here before building the resolved CALL_EXPR. */ if (desc->code == ALTIVEC_BUILTIN_VEC_VCMPGE_P - && desc->overloaded_code != ALTIVEC_BUILTIN_VCMPGEFP_P) + && desc->overloaded_code != ALTIVEC_BUILTIN_VCMPGEFP_P + && desc->overloaded_code != VSX_BUILTIN_XVCMPGEDP_P) { tree t; t = args[2], args[2] = args[1], args[1] = t; @@ -4184,6 +4185,14 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, if (TARGET_DEBUG_BUILTIN) fprintf (stderr, "altivec_resolve_overloaded_builtin, code = %4d, %s\n", (int)fcode, IDENTIFIER_POINTER (DECL_NAME (fndecl))); + + /* vec_lvsl and vec_lvsr are deprecated for use with LE element order. */ + if (fcode == ALTIVEC_BUILTIN_VEC_LVSL && !VECTOR_ELT_ORDER_BIG) + warning (OPT_Wdeprecated, "vec_lvsl is deprecated for little endian; use \ +assignment for unaligned loads and stores"); + else if (fcode == ALTIVEC_BUILTIN_VEC_LVSR && !VECTOR_ELT_ORDER_BIG) + warning (OPT_Wdeprecated, "vec_lvsr is deprecated for little endian; use \ +assignment for unaligned loads and stores"); /* For now treat vec_splats and vec_promote as the same. */ if (fcode == ALTIVEC_BUILTIN_VEC_SPLATS diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 02d2c3bd727..5db8b28fec5 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -79,9 +79,9 @@ extern int mems_ok_for_quad_peep (rtx, rtx); extern bool gpr_or_gpr_p (rtx, rtx); extern bool direct_move_p (rtx, rtx); extern bool quad_load_store_p (rtx, rtx); -extern bool fusion_gpr_load_p (rtx *, bool); +extern bool fusion_gpr_load_p (rtx, rtx, rtx, rtx); extern void expand_fusion_gpr_load (rtx *); -extern const char *emit_fusion_gpr_load (rtx *); +extern const char *emit_fusion_gpr_load (rtx, rtx); extern enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, enum reg_class); extern enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class, diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index b40218da009..9589d411136 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -369,6 +369,7 @@ struct rs6000_reg_addr { enum insn_code reload_gpr_vsx; /* INSN to move from GPR to VSX. */ enum insn_code reload_vsx_gpr; /* INSN to move from VSX to GPR. */ addr_mask_type addr_mask[(int)N_RELOAD_REG]; /* Valid address masks. */ + bool scalar_in_vmx_p; /* Scalar value can go in VMX. */ }; static struct rs6000_reg_addr reg_addr[NUM_MACHINE_MODES]; @@ -1704,8 +1705,7 @@ rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode) asked for it. */ if (TARGET_VSX && VSX_REGNO_P (regno) && (VECTOR_MEM_VSX_P (mode) - || (TARGET_VSX_SCALAR_FLOAT && mode == SFmode) - || (TARGET_VSX_SCALAR_DOUBLE && (mode == DFmode || mode == DImode)) + || reg_addr[mode].scalar_in_vmx_p || (TARGET_VSX_TIMODE && mode == TImode) || (TARGET_VADDUQM && mode == V1TImode))) { @@ -1714,10 +1714,7 @@ rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode) if (ALTIVEC_REGNO_P (regno)) { - if (mode == SFmode && !TARGET_UPPER_REGS_SF) - return 0; - - if ((mode == DFmode || mode == DImode) && !TARGET_UPPER_REGS_DF) + if (GET_MODE_SIZE (mode) != 16 && !reg_addr[mode].scalar_in_vmx_p) return 0; return ALTIVEC_REGNO_P (last_regno); @@ -1897,14 +1894,16 @@ rs6000_debug_print_mode (ssize_t m) if (rs6000_vector_unit[m] != VECTOR_NONE || rs6000_vector_mem[m] != VECTOR_NONE || (reg_addr[m].reload_store != CODE_FOR_nothing) - || (reg_addr[m].reload_load != CODE_FOR_nothing)) + || (reg_addr[m].reload_load != CODE_FOR_nothing) + || reg_addr[m].scalar_in_vmx_p) { fprintf (stderr, - " Vector-arith=%-10s Vector-mem=%-10s Reload=%c%c", + " Vector-arith=%-10s Vector-mem=%-10s Reload=%c%c Upper=%c", rs6000_debug_vector_unit (rs6000_vector_unit[m]), rs6000_debug_vector_unit (rs6000_vector_mem[m]), (reg_addr[m].reload_store != CODE_FOR_nothing) ? 's' : '*', - (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*'); + (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*', + (reg_addr[m].scalar_in_vmx_p) ? 'y' : 'n'); } fputs ("\n", stderr); @@ -2021,6 +2020,10 @@ rs6000_debug_reg_global (void) "wd reg_class = %s\n" "wf reg_class = %s\n" "wg reg_class = %s\n" + "wh reg_class = %s\n" + "wi reg_class = %s\n" + "wj reg_class = %s\n" + "wk reg_class = %s\n" "wl reg_class = %s\n" "wm reg_class = %s\n" "wr reg_class = %s\n" @@ -2040,6 +2043,10 @@ rs6000_debug_reg_global (void) reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wh]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wj]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wk]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]], @@ -2324,6 +2331,8 @@ rs6000_setup_reg_addr_masks (void) for (m = 0; m < NUM_MACHINE_MODES; ++m) { + enum machine_mode m2 = (enum machine_mode)m; + /* SDmode is special in that we want to access it only via REG+REG addressing on power7 and above, since we want to use the LFIWZX and STFIWZX instructions to load it. */ @@ -2358,13 +2367,12 @@ rs6000_setup_reg_addr_masks (void) if (TARGET_UPDATE && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR) - && GET_MODE_SIZE (m) <= 8 - && !VECTOR_MODE_P (m) - && !COMPLEX_MODE_P (m) + && GET_MODE_SIZE (m2) <= 8 + && !VECTOR_MODE_P (m2) + && !COMPLEX_MODE_P (m2) && !indexed_only_p - && !(TARGET_E500_DOUBLE && GET_MODE_SIZE (m) == 8) - && !(m == DFmode && TARGET_UPPER_REGS_DF) - && !(m == SFmode && TARGET_UPPER_REGS_SF)) + && !(TARGET_E500_DOUBLE && GET_MODE_SIZE (m2) == 8) + && !reg_addr[m2].scalar_in_vmx_p) { addr_mask |= RELOAD_REG_PRE_INCDEC; @@ -2595,37 +2603,44 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) f - Register class to use with traditional SFmode instructions. v - Altivec register. wa - Any VSX register. + wc - Reserved to represent individual CR bits (used in LLVM). wd - Preferred register class for V2DFmode. wf - Preferred register class for V4SFmode. wg - Float register for power6x move insns. + wh - FP register for direct move instructions. + wi - FP or VSX register to hold 64-bit integers for VSX insns. + wj - FP or VSX register to hold 64-bit integers for direct moves. + wk - FP or VSX register to hold 64-bit doubles for direct moves. wl - Float register if we can do 32-bit signed int loads. wm - VSX register for ISA 2.07 direct move operations. + wn - always NO_REGS. wr - GPR if 64-bit mode is permitted. ws - Register class to do ISA 2.06 DF operations. + wt - VSX register for TImode in VSX registers. wu - Altivec register for ISA 2.07 VSX SF/SI load/stores. wv - Altivec register for ISA 2.06 VSX DF/DI load/stores. - wt - VSX register for TImode in VSX registers. ww - Register class to do SF conversions in with VSX operations. wx - Float register if we can do 32-bit int stores. wy - Register class to do ISA 2.07 SF operations. wz - Float register if we can do 32-bit unsigned int loads. */ if (TARGET_HARD_FLOAT && TARGET_FPRS) - rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; + rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; /* SFmode */ if (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT) - rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; + rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; /* DFmode */ if (TARGET_VSX) { rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS; - rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; - rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; + rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */ + rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */ + rs6000_constraints[RS6000_CONSTRAINT_wi] = FLOAT_REGS; /* DImode */ if (TARGET_VSX_TIMODE) - rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; + rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; /* TImode */ - if (TARGET_UPPER_REGS_DF) + if (TARGET_UPPER_REGS_DF) /* DFmode */ { rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; @@ -2639,19 +2654,26 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) if (TARGET_ALTIVEC) rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS; - if (TARGET_MFPGPR) + if (TARGET_MFPGPR) /* DFmode */ rs6000_constraints[RS6000_CONSTRAINT_wg] = FLOAT_REGS; if (TARGET_LFIWAX) - rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS; + rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS; /* DImode */ if (TARGET_DIRECT_MOVE) - rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS; + { + rs6000_constraints[RS6000_CONSTRAINT_wh] = FLOAT_REGS; + rs6000_constraints[RS6000_CONSTRAINT_wj] /* DImode */ + = rs6000_constraints[RS6000_CONSTRAINT_wi]; + rs6000_constraints[RS6000_CONSTRAINT_wk] /* DFmode */ + = rs6000_constraints[RS6000_CONSTRAINT_ws]; + rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS; + } if (TARGET_POWERPC64) rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS; - if (TARGET_P8_VECTOR && TARGET_UPPER_REGS_SF) + if (TARGET_P8_VECTOR && TARGET_UPPER_REGS_SF) /* SFmode */ { rs6000_constraints[RS6000_CONSTRAINT_wu] = ALTIVEC_REGS; rs6000_constraints[RS6000_CONSTRAINT_wy] = VSX_REGS; @@ -2666,10 +2688,10 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS; if (TARGET_STFIWX) - rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS; + rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS; /* DImode */ if (TARGET_LFIWZX) - rs6000_constraints[RS6000_CONSTRAINT_wz] = FLOAT_REGS; + rs6000_constraints[RS6000_CONSTRAINT_wz] = FLOAT_REGS; /* DImode */ /* Set up the reload helper and direct move functions. */ if (TARGET_VSX || TARGET_ALTIVEC) @@ -2692,10 +2714,11 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_di_load; if (TARGET_VSX && TARGET_UPPER_REGS_DF) { - reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store; - reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load; - reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store; - reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load; + reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store; + reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load; + reg_addr[DFmode].scalar_in_vmx_p = true; + reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store; + reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load; } if (TARGET_P8_VECTOR) { @@ -2703,6 +2726,8 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_di_load; reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_di_store; reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_di_load; + if (TARGET_UPPER_REGS_SF) + reg_addr[SFmode].scalar_in_vmx_p = true; } if (TARGET_VSX_TIMODE) { @@ -2759,10 +2784,11 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_si_load; if (TARGET_VSX && TARGET_UPPER_REGS_DF) { - reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store; - reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load; - reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store; - reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load; + reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store; + reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load; + reg_addr[DFmode].scalar_in_vmx_p = true; + reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store; + reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load; } if (TARGET_P8_VECTOR) { @@ -2770,6 +2796,8 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_si_load; reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_si_store; reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_si_load; + if (TARGET_UPPER_REGS_SF) + reg_addr[SFmode].scalar_in_vmx_p = true; } if (TARGET_VSX_TIMODE) { @@ -2810,6 +2838,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) for (m = 0; m < NUM_MACHINE_MODES; ++m) { + enum machine_mode m2 = (enum machine_mode)m; int reg_size2 = reg_size; /* TFmode/TDmode always takes 2 registers, even in VSX. */ @@ -2818,7 +2847,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) reg_size2 = UNITS_PER_FP_WORD; rs6000_class_max_nregs[m][c] - = (GET_MODE_SIZE (m) + reg_size2 - 1) / reg_size2; + = (GET_MODE_SIZE (m2) + reg_size2 - 1) / reg_size2; } } @@ -13782,8 +13811,8 @@ rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, case ALTIVEC_BUILTIN_MASK_FOR_LOAD: case ALTIVEC_BUILTIN_MASK_FOR_STORE: { - int icode = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr - : (int) CODE_FOR_altivec_lvsl); + int icode = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct + : (int) CODE_FOR_altivec_lvsl_direct); enum machine_mode tmode = insn_data[icode].operand[0].mode; enum machine_mode mode = insn_data[icode].operand[1].mode; tree arg; @@ -13811,7 +13840,6 @@ rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) target = gen_reg_rtx (tmode); - /*pat = gen_altivec_lvsr (target, op);*/ pat = GEN_FCN (icode) (target, op); if (!pat) return 0; @@ -17232,7 +17260,14 @@ rs6000_preferred_reload_class (rtx x, enum reg_class rclass) prefer Altivec loads.. */ if (rclass == VSX_REGS) { - if (GET_MODE_SIZE (mode) <= 8) + if (MEM_P (x) && reg_addr[mode].scalar_in_vmx_p) + { + rtx addr = XEXP (x, 0); + if (rs6000_legitimate_offset_address_p (mode, addr, false, true) + || legitimate_lo_sum_address_p (mode, addr, false)) + return FLOAT_REGS; + } + else if (GET_MODE_SIZE (mode) <= 8 && !reg_addr[mode].scalar_in_vmx_p) return FLOAT_REGS; if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode) @@ -32797,25 +32832,14 @@ rs6000_split_logical (rtx operands[3], /* Return true if the peephole2 can combine a load involving a combination of an addis instruction and a load with an offset that can be fused together on - a power8. - - The operands are: - operands[0] register set with addis - operands[1] value set via addis - operands[2] target register being loaded - operands[3] D-form memory reference using operands[0]. - - In addition, we are passed a boolean that is true if this is a peephole2, - and we can use see if the addis_reg is dead after the insn and can be - replaced by the target register. */ + a power8. */ bool -fusion_gpr_load_p (rtx *operands, bool peep2_p) +fusion_gpr_load_p (rtx addis_reg, /* register set via addis. */ + rtx addis_value, /* addis value. */ + rtx target, /* target register that is loaded. */ + rtx mem) /* bottom part of the memory addr. */ { - rtx addis_reg = operands[0]; - rtx addis_value = operands[1]; - rtx target = operands[2]; - rtx mem = operands[3]; rtx addr; rtx base_reg; @@ -32829,9 +32853,6 @@ fusion_gpr_load_p (rtx *operands, bool peep2_p) if (!fusion_gpr_addis (addis_value, GET_MODE (addis_value))) return false; - if (!fusion_gpr_mem_load (mem, GET_MODE (mem))) - return false; - /* Allow sign/zero extension. */ if (GET_CODE (mem) == ZERO_EXTEND || (GET_CODE (mem) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN)) @@ -32840,22 +32861,22 @@ fusion_gpr_load_p (rtx *operands, bool peep2_p) if (!MEM_P (mem)) return false; + if (!fusion_gpr_mem_load (mem, GET_MODE (mem))) + return false; + addr = XEXP (mem, 0); /* either PLUS or LO_SUM. */ if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM) return false; /* Validate that the register used to load the high value is either the - register being loaded, or we can safely replace its use in a peephole2. + register being loaded, or we can safely replace its use. - If this is a peephole2, we assume that there are 2 instructions in the - peephole (addis and load), so we want to check if the target register was - not used in the memory address and the register to hold the addis result - is dead after the peephole. */ + This function is only called from the peephole2 pass and we assume that + there are 2 instructions in the peephole (addis and load), so we want to + check if the target register was not used in the memory address and the + register to hold the addis result is dead after the peephole. */ if (REGNO (addis_reg) != REGNO (target)) { - if (!peep2_p) - return false; - if (reg_mentioned_p (target, mem)) return false; @@ -32896,9 +32917,6 @@ expand_fusion_gpr_load (rtx *operands) enum machine_mode extend_mode = target_mode; enum machine_mode ptr_mode = Pmode; enum rtx_code extend = UNKNOWN; - rtx addis_reg = ((ptr_mode == target_mode) - ? target - : simplify_subreg (ptr_mode, target, target_mode, 0)); if (GET_CODE (orig_mem) == ZERO_EXTEND || (TARGET_P8_FUSION_SIGN && GET_CODE (orig_mem) == SIGN_EXTEND)) @@ -32915,13 +32933,14 @@ expand_fusion_gpr_load (rtx *operands) gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM); offset = XEXP (orig_addr, 1); - new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_reg, offset); - new_mem = change_address (orig_mem, target_mode, new_addr); + new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset); + new_mem = replace_equiv_address_nv (orig_mem, new_addr); if (extend != UNKNOWN) new_mem = gen_rtx_fmt_e (ZERO_EXTEND, extend_mode, new_mem); - emit_insn (gen_rtx_SET (VOIDmode, addis_reg, addis_value)); + new_mem = gen_rtx_UNSPEC (extend_mode, gen_rtvec (1, new_mem), + UNSPEC_FUSION_GPR); emit_insn (gen_rtx_SET (VOIDmode, target, new_mem)); if (extend == SIGN_EXTEND) @@ -32940,55 +32959,40 @@ expand_fusion_gpr_load (rtx *operands) } /* Return a string to fuse an addis instruction with a gpr load to the same - register that we loaded up the addis instruction. The code is complicated, - so we call output_asm_insn directly, and just return "". + register that we loaded up the addis instruction. The address that is used + is the logical address that was formed during peephole2: + (lo_sum (high) (low-part)) - The operands are: - operands[0] register set with addis (must be same reg as target). - operands[1] value set via addis - operands[2] target register being loaded - operands[3] D-form memory reference using operands[0]. */ + The code is complicated, so we call output_asm_insn directly, and just + return "". */ const char * -emit_fusion_gpr_load (rtx *operands) +emit_fusion_gpr_load (rtx target, rtx mem) { - rtx addis_reg = operands[0]; - rtx addis_value = operands[1]; - rtx target = operands[2]; - rtx mem = operands[3]; + rtx addis_value; rtx fuse_ops[10]; rtx addr; rtx load_offset; const char *addis_str = NULL; const char *load_str = NULL; - const char *extend_insn = NULL; const char *mode_name = NULL; char insn_template[80]; enum machine_mode mode; const char *comment_str = ASM_COMMENT_START; - bool sign_p = false; - gcc_assert (REG_P (addis_reg) && REG_P (target)); - gcc_assert (REGNO (addis_reg) == REGNO (target)); - - if (*comment_str == ' ') - comment_str++; - - /* Allow sign/zero extension. */ if (GET_CODE (mem) == ZERO_EXTEND) mem = XEXP (mem, 0); - else if (GET_CODE (mem) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN) - { - sign_p = true; - mem = XEXP (mem, 0); - } + gcc_assert (REG_P (target) && MEM_P (mem)); + + if (*comment_str == ' ') + comment_str++; - gcc_assert (MEM_P (mem)); addr = XEXP (mem, 0); if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM) gcc_unreachable (); + addis_value = XEXP (addr, 0); load_offset = XEXP (addr, 1); /* Now emit the load instruction to the same register. */ @@ -32998,29 +33002,22 @@ emit_fusion_gpr_load (rtx *operands) case QImode: mode_name = "char"; load_str = "lbz"; - extend_insn = "extsb %0,%0"; break; case HImode: mode_name = "short"; load_str = "lhz"; - extend_insn = "extsh %0,%0"; break; case SImode: mode_name = "int"; load_str = "lwz"; - extend_insn = "extsw %0,%0"; break; case DImode: - if (TARGET_POWERPC64) - { - mode_name = "long"; - load_str = "ld"; - } - else - gcc_unreachable (); + gcc_assert (TARGET_POWERPC64); + mode_name = "long"; + load_str = "ld"; break; default: @@ -33164,14 +33161,6 @@ emit_fusion_gpr_load (rtx *operands) else fatal_insn ("Unable to generate load offset for fusion", load_offset); - /* Handle sign extension. The peephole2 pass generates this as a separate - insn, but we handle it just in case it got reattached. */ - if (sign_p) - { - gcc_assert (extend_insn != NULL); - output_asm_insn (extend_insn, fuse_ops); - } - return ""; } diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 90a93f71f4a..a408e3e9218 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1438,6 +1438,10 @@ enum r6000_reg_class_enum { RS6000_CONSTRAINT_wd, /* VSX register for V2DF */ RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */ + RS6000_CONSTRAINT_wh, /* FPR register for direct moves. */ + RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */ + RS6000_CONSTRAINT_wj, /* FPR/VSX register for DImode direct moves. */ + RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct moves. */ RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */ RS6000_CONSTRAINT_wm, /* VSX register for direct move */ RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */ @@ -1462,6 +1466,9 @@ extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; #define VSX_REG_CLASS_P(CLASS) \ ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS) +/* Return whether a given register class targets general purpose registers. */ +#define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS) + /* Given an rtx X being reloaded into a reg required to be in class CLASS, return the class of reg to actually use. In general this is just CLASS; but on some machines diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index bff4cef5fa0..d31ae4c377f 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -134,6 +134,7 @@ UNSPEC_UNPACK_128BIT UNSPEC_PACK_128BIT UNSPEC_LSQ + UNSPEC_FUSION_GPR ]) ;; @@ -317,7 +318,24 @@ (define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")]) ; Definitions for 32-bit fpr direct move -(define_mode_attr f32_dm [(SF "wn") (SD "wm")]) +; At present, the decimal modes are not allowed in the traditional altivec +; registers, so restrict the constraints to just the traditional FPRs. +(define_mode_attr f32_dm [(SF "wn") (SD "wh")]) + +; Definitions for 32-bit VSX +(define_mode_attr f32_vsx [(SF "ww") (SD "wn")]) + +; Definitions for 32-bit use of altivec registers +(define_mode_attr f32_av [(SF "wu") (SD "wn")]) + +; Definitions for 64-bit VSX +(define_mode_attr f64_vsx [(DF "ws") (DD "wn")]) + +; Definitions for 64-bit direct move +(define_mode_attr f64_dm [(DF "wk") (DD "wh")]) + +; Definitions for 64-bit use of altivec registers +(define_mode_attr f64_av [(DF "wv") (DD "wn")]) ; These modes do not fit in integer registers in 32-bit mode. ; but on e500v2, the gpr are 64 bit registers @@ -424,7 +442,7 @@ ;; either. ;; Mode attribute for boolean operation register constraints for output -(define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wa,v") +(define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wt,v") (PTI "&r,r,r") (V16QI "wa,v,&?r,?r,?r") (V8HI "wa,v,&?r,?r,?r") @@ -435,7 +453,7 @@ (V1TI "wa,v,&?r,?r,?r")]) ;; Mode attribute for boolean operation register constraints for operand1 -(define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wa,v") +(define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wt,v") (PTI "r,0,r") (V16QI "wa,v,r,0,r") (V8HI "wa,v,r,0,r") @@ -446,7 +464,7 @@ (V1TI "wa,v,r,0,r")]) ;; Mode attribute for boolean operation register constraints for operand2 -(define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wa,v") +(define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wt,v") (PTI "r,r,0") (V16QI "wa,v,r,r,0") (V8HI "wa,v,r,r,0") @@ -459,7 +477,7 @@ ;; Mode attribute for boolean operation register constraints for operand1 ;; for one_cmpl. To simplify things, we repeat the constraint where 0 ;; is used for operand1 or operand2 -(define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wa,v") +(define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wt,v") (PTI "r,0,0") (V16QI "wa,v,r,0,0") (V8HI "wa,v,r,0,0") @@ -566,7 +584,7 @@ "") (define_insn "*zero_extendsidi2_lfiwzx" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wz,!wu") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wj,!wz,!wu") (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))] "TARGET_POWERPC64 && TARGET_LFIWZX" "@ @@ -736,7 +754,7 @@ "") (define_insn "*extendsidi2_lfiwax" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wl,!wu") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wj,!wl,!wu") (sign_extend:DI (match_operand:SI 1 "lwa_operand" "Y,r,r,Z,Z")))] "TARGET_POWERPC64 && TARGET_LFIWAX" "@ @@ -5614,7 +5632,7 @@ ; We don't define lfiwax/lfiwzx with the normal definition, because we ; don't want to support putting SImode in FPR registers. (define_insn "lfiwax" - [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm") + [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj") (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")] UNSPEC_LFIWAX))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX" @@ -5694,7 +5712,7 @@ (set_attr "type" "fpload")]) (define_insn "lfiwzx" - [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm") + [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj") (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")] UNSPEC_LFIWZX))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX" @@ -9210,8 +9228,8 @@ }") (define_insn "mov<mode>_hardfloat" - [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,wa,wa,<f32_lr>,<f32_sm>,wu,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r") - (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,wa,j,<f32_lm>,<f32_sr>,Z,wu,r,<f32_dm>,r,h,0,G,Fn"))] + [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,<f32_vsx>,<f32_vsx>,<f32_lr>,<f32_sm>,<f32_av>,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r") + (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,<f32_vsx>,j,<f32_lm>,<f32_sr>,Z,<f32_av>,r,<f32_dm>,r, h, 0, G,Fn"))] "(gpc_reg_operand (operands[0], <MODE>mode) || gpc_reg_operand (operands[1], <MODE>mode)) && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)" @@ -9422,8 +9440,8 @@ ;; reloading. (define_insn "*mov<mode>_hardfloat32" - [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,!r,!r,!r") - (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,G,H,F"))] + [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_vsx>,<f64_vsx>,Y,r,!r,!r,!r,!r") + (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,<f64_vsx>,j,r,Y,r,G,H,F"))] "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && (gpc_reg_operand (operands[0], <MODE>mode) || gpc_reg_operand (operands[1], <MODE>mode))" @@ -9491,8 +9509,8 @@ ; ld/std require word-aligned displacements -> 'Y' constraint. ; List Y->r and r->Y before r->r for reload. (define_insn "*mov<mode>_hardfloat64" - [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wm") - (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wm,r"))] + [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_vsx>,<f64_vsx>,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,<f64_dm>") + (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,<f64_vsx>,j,r,Y,r,r,h,0,G,H,F,wg,r,<f64_dm>,r"))] "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && (gpc_reg_operand (operands[0], <MODE>mode) || gpc_reg_operand (operands[1], <MODE>mode))" @@ -10272,8 +10290,8 @@ { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) (define_insn "*movdi_internal64" - [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wm") - (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wm,r"))] + [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wj,?*wi") + (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wj,r,O"))] "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode) || gpc_reg_operand (operands[1], DImode))" @@ -10293,7 +10311,8 @@ mftgpr %0,%1 mffgpr %0,%1 mfvsrd %0,%x1 - mtvsrd %x0,%1" + mtvsrd %x0,%1 + xxlxor %x0,%x0,%x0" [(set_attr_alternative "type" [(if_then_else (match_test "update_indexed_address_mem (operands[0], VOIDmode)") @@ -10334,8 +10353,9 @@ (const_string "mftgpr") (const_string "mffgpr") (const_string "mftgpr") - (const_string "mffgpr")]) - (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4")]) + (const_string "mffgpr") + (const_string "vecsimple")]) + (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4,4")]) ;; immediate value valid for a single instruction hiding in a const_double (define_insn "" @@ -15751,22 +15771,9 @@ ;; a GPR. The addis instruction must be adjacent to the load, and use the same ;; register that is being loaded. The fused ops must be physically adjacent. -;; We use define_peephole for the actual addis/load, and the register used to -;; hold the addis value must be the same as the register being loaded. We use -;; define_peephole2 to change the register used for addis to be the register -;; being loaded, since we can look at whether it is dead after the load insn. - -(define_peephole - [(set (match_operand:P 0 "base_reg_operand" "") - (match_operand:P 1 "fusion_gpr_addis" "")) - (set (match_operand:INT1 2 "base_reg_operand" "") - (match_operand:INT1 3 "fusion_gpr_mem_load" ""))] - "TARGET_P8_FUSION && fusion_gpr_load_p (operands, false)" -{ - return emit_fusion_gpr_load (operands); -} - [(set_attr "type" "load") - (set_attr "length" "8")]) +;; Find cases where the addis that feeds into a load instruction is either used +;; once or is the same as the target register, and replace it with the fusion +;; insn (define_peephole2 [(set (match_operand:P 0 "base_reg_operand" "") @@ -15774,15 +15781,28 @@ (set (match_operand:INT1 2 "base_reg_operand" "") (match_operand:INT1 3 "fusion_gpr_mem_load" ""))] "TARGET_P8_FUSION - && (REGNO (operands[0]) != REGNO (operands[2]) - || GET_CODE (operands[3]) == SIGN_EXTEND) - && fusion_gpr_load_p (operands, true)" + && fusion_gpr_load_p (operands[0], operands[1], operands[2], + operands[3])" [(const_int 0)] { expand_fusion_gpr_load (operands); DONE; }) +;; Fusion insn, created by the define_peephole2 above (and eventually by +;; reload) + +(define_insn "fusion_gpr_load_<mode>" + [(set (match_operand:INT1 0 "base_reg_operand" "=&b") + (unspec:INT1 [(match_operand:INT1 1 "fusion_gpr_mem_combo" "")] + UNSPEC_FUSION_GPR))] + "TARGET_P8_FUSION" +{ + return emit_fusion_gpr_load (operands[0], operands[1]); +} + [(set_attr "type" "load") + (set_attr "length" "8")]) + ;; Miscellaneous ISA 2.06 (power7) instructions (define_insn "addg6s" diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index d7839f5f5e1..432dfe14f43 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -86,19 +86,26 @@ (V4SF "wf") (V2DI "wd") (V2DF "wd") + (DI "wi") (DF "ws") - (SF "d") + (SF "ww") (V1TI "v") (TI "wt")]) -;; Map the register class used for float<->int conversions +;; Map the register class used for float<->int conversions (floating point side) +;; VSr2 is the preferred register class, VSr3 is any register class that will +;; hold the data (define_mode_attr VSr2 [(V2DF "wd") (V4SF "wf") - (DF "ws")]) + (DF "ws") + (SF "ww") + (DI "wi")]) (define_mode_attr VSr3 [(V2DF "wa") (V4SF "wa") - (DF "ws")]) + (DF "ws") + (SF "ww") + (DI "wi")]) ;; Map the register class for sp<->dp float conversions, destination (define_mode_attr VSr4 [(SF "ws") @@ -106,12 +113,27 @@ (V2DF "wd") (V4SF "v")]) -;; Map the register class for sp<->dp float conversions, destination +;; Map the register class for sp<->dp float conversions, source (define_mode_attr VSr5 [(SF "ws") (DF "f") (V2DF "v") (V4SF "wd")]) +;; The VSX register class that a type can occupy, even if it is not the +;; preferred register class (VSr is the preferred register class that will get +;; allocated first). +(define_mode_attr VSa [(V16QI "wa") + (V8HI "wa") + (V4SI "wa") + (V4SF "wa") + (V2DI "wa") + (V2DF "wa") + (DI "wi") + (DF "ws") + (SF "ww") + (V1TI "wa") + (TI "wt")]) + ;; Same size integer type for floating point data (define_mode_attr VSi [(V4SF "v4si") (V2DF "v2di") @@ -207,6 +229,16 @@ (V2DF "V4DF") (V1TI "V2TI")]) +;; Map register class for 64-bit element in 128-bit vector for direct moves +;; to/from gprs +(define_mode_attr VS_64dm [(V2DF "wk") + (V2DI "wj")]) + +;; Map register class for 64-bit element in 128-bit vector for normal register +;; to register moves +(define_mode_attr VS_64reg [(V2DF "ws") + (V2DI "wi")]) + ;; Constants for creating unspecs (define_c_enum "unspec" [UNSPEC_VSX_CONCAT @@ -235,7 +267,7 @@ ;; The patterns for LE permuted loads and stores come before the general ;; VSX moves so they match first. (define_insn_and_split "*vsx_le_perm_load_<mode>" - [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=wa") + [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=<VSa>") (match_operand:VSX_LE 1 "memory_operand" "Z"))] "!BYTES_BIG_ENDIAN && TARGET_VSX" "#" @@ -258,7 +290,7 @@ (set_attr "length" "8")]) (define_insn_and_split "*vsx_le_perm_load_<mode>" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=<VSa>") (match_operand:VSX_W 1 "memory_operand" "Z"))] "!BYTES_BIG_ENDIAN && TARGET_VSX" "#" @@ -350,7 +382,7 @@ (define_insn "*vsx_le_perm_store_<mode>" [(set (match_operand:VSX_LE 0 "memory_operand" "=Z") - (match_operand:VSX_LE 1 "vsx_register_operand" "+wa"))] + (match_operand:VSX_LE 1 "vsx_register_operand" "+<VSa>"))] "!BYTES_BIG_ENDIAN && TARGET_VSX" "#" [(set_attr "type" "vecstore") @@ -395,7 +427,7 @@ (define_insn "*vsx_le_perm_store_<mode>" [(set (match_operand:VSX_W 0 "memory_operand" "=Z") - (match_operand:VSX_W 1 "vsx_register_operand" "+wa"))] + (match_operand:VSX_W 1 "vsx_register_operand" "+<VSa>"))] "!BYTES_BIG_ENDIAN && TARGET_VSX" "#" [(set_attr "type" "vecstore") @@ -585,8 +617,8 @@ (define_insn "*vsx_mov<mode>" - [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=Z,<VSr>,<VSr>,?Z,?wa,?wa,wQ,?&r,??Y,??r,??r,<VSr>,?wa,*r,v,wZ, v") - (match_operand:VSX_M 1 "input_operand" "<VSr>,Z,<VSr>,wa,Z,wa,r,wQ,r,Y,r,j,j,j,W,v,wZ"))] + [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=Z,<VSr>,<VSr>,?Z,?<VSa>,?<VSa>,wQ,?&r,??Y,??r,??r,<VSr>,?<VSa>,*r,v,wZ, v") + (match_operand:VSX_M 1 "input_operand" "<VSr>,Z,<VSr>,<VSa>,Z,<VSa>,r,wQ,r,Y,r,j,j,j,W,v,wZ"))] "VECTOR_MEM_VSX_P (<MODE>mode) && (register_operand (operands[0], <MODE>mode) || register_operand (operands[1], <MODE>mode))" @@ -688,36 +720,36 @@ ;; instructions are now combined with the insn for the traditional floating ;; point unit. (define_insn "*vsx_add<mode>3" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (plus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (plus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvadd<VSs> %x0,%x1,%x2" [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "*vsx_sub<mode>3" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (minus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (minus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvsub<VSs> %x0,%x1,%x2" [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "*vsx_mul<mode>3" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (mult:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (mult:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvmul<VSs> %x0,%x1,%x2" [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_mul>")]) (define_insn "*vsx_div<mode>3" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (div:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (div:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvdiv<VSs> %x0,%x1,%x2" [(set_attr "type" "<VStype_div>") @@ -753,8 +785,8 @@ (define_insn "*vsx_tdiv<mode>3_internal" [(set (match_operand:CCFP 0 "cc_reg_operand" "=x,x") - (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa") - (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,wa")] + (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,<VSa>") + (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,<VSa>")] UNSPEC_VSX_TDIV))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "x<VSv>tdiv<VSs> %0,%x1,%x2" @@ -762,8 +794,8 @@ (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "vsx_fre<mode>2" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")] UNSPEC_FRES))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvre<VSs> %x0,%x1" @@ -771,60 +803,60 @@ (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "*vsx_neg<mode>2" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (neg:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (neg:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvneg<VSs> %x0,%x1" [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "*vsx_abs<mode>2" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (abs:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (abs:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvabs<VSs> %x0,%x1" [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "vsx_nabs<mode>2" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") (neg:VSX_F (abs:VSX_F - (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa"))))] + (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>"))))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvnabs<VSs> %x0,%x1" [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "vsx_smax<mode>3" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (smax:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (smax:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvmax<VSs> %x0,%x1,%x2" [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "*vsx_smin<mode>3" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (smin:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (smin:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvmin<VSs> %x0,%x1,%x2" [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "*vsx_sqrt<mode>2" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (sqrt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (sqrt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvsqrt<VSs> %x0,%x1" [(set_attr "type" "<VStype_sqrt>") (set_attr "fp_type" "<VSfptype_sqrt>")]) (define_insn "*vsx_rsqrte<mode>2" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")] UNSPEC_RSQRT))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvrsqrte<VSs> %x0,%x1" @@ -859,7 +891,7 @@ (define_insn "*vsx_tsqrt<mode>2_internal" [(set (match_operand:CCFP 0 "cc_reg_operand" "=x,x") - (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")] + (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,<VSa>")] UNSPEC_VSX_TSQRT))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "x<VSv>tsqrt<VSs> %0,%x1" @@ -872,11 +904,11 @@ ;; multiply. (define_insn "*vsx_fmav4sf4" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=ws,ws,?wa,?wa,v") + [(set (match_operand:V4SF 0 "vsx_register_operand" "=wf,wf,?wa,?wa,v") (fma:V4SF - (match_operand:V4SF 1 "vsx_register_operand" "%ws,ws,wa,wa,v") - (match_operand:V4SF 2 "vsx_register_operand" "ws,0,wa,0,v") - (match_operand:V4SF 3 "vsx_register_operand" "0,ws,0,wa,v")))] + (match_operand:V4SF 1 "vsx_register_operand" "%wf,wf,wa,wa,v") + (match_operand:V4SF 2 "vsx_register_operand" "wf,0,wa,0,v") + (match_operand:V4SF 3 "vsx_register_operand" "0,wf,0,wa,v")))] "VECTOR_UNIT_VSX_P (V4SFmode)" "@ xvmaddasp %x0,%x1,%x2 @@ -887,11 +919,11 @@ [(set_attr "type" "vecfloat")]) (define_insn "*vsx_fmav2df4" - [(set (match_operand:V2DF 0 "vsx_register_operand" "=ws,ws,?wa,?wa") + [(set (match_operand:V2DF 0 "vsx_register_operand" "=wd,wd,?wa,?wa") (fma:V2DF - (match_operand:V2DF 1 "vsx_register_operand" "%ws,ws,wa,wa") - (match_operand:V2DF 2 "vsx_register_operand" "ws,0,wa,0") - (match_operand:V2DF 3 "vsx_register_operand" "0,ws,0,wa")))] + (match_operand:V2DF 1 "vsx_register_operand" "%wd,wd,wa,wa") + (match_operand:V2DF 2 "vsx_register_operand" "wd,0,wa,0") + (match_operand:V2DF 3 "vsx_register_operand" "0,wd,0,wa")))] "VECTOR_UNIT_VSX_P (V2DFmode)" "@ xvmaddadp %x0,%x1,%x2 @@ -901,12 +933,12 @@ [(set_attr "type" "vecdouble")]) (define_insn "*vsx_fms<mode>4" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,<VSr>,?wa,?wa") + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,<VSr>,?<VSa>,?<VSa>") (fma:VSX_F - (match_operand:VSX_F 1 "vsx_register_operand" "%<VSr>,<VSr>,wa,wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,0,wa,0") + (match_operand:VSX_F 1 "vsx_register_operand" "%<VSr>,<VSr>,<VSa>,<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,0,<VSa>,0") (neg:VSX_F - (match_operand:VSX_F 3 "vsx_register_operand" "0,<VSr>,0,wa"))))] + (match_operand:VSX_F 3 "vsx_register_operand" "0,<VSr>,0,<VSa>"))))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "@ xvmsuba<VSs> %x0,%x1,%x2 @@ -916,12 +948,12 @@ [(set_attr "type" "<VStype_mul>")]) (define_insn "*vsx_nfma<mode>4" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,<VSr>,?wa,?wa") + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,<VSr>,?<VSa>,?<VSa>") (neg:VSX_F (fma:VSX_F - (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSr>,wa,wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,0,wa,0") - (match_operand:VSX_F 3 "vsx_register_operand" "0,<VSr>,0,wa"))))] + (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSr>,<VSa>,<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,0,<VSa>,0") + (match_operand:VSX_F 3 "vsx_register_operand" "0,<VSr>,0,<VSa>"))))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "@ xvnmadda<VSs> %x0,%x1,%x2 @@ -966,27 +998,27 @@ ;; Vector conditional expressions (no scalar version for these instructions) (define_insn "vsx_eq<mode>" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (eq:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (eq:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvcmpeq<VSs> %x0,%x1,%x2" [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "vsx_gt<mode>" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (gt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (gt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvcmpgt<VSs> %x0,%x1,%x2" [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "*vsx_ge<mode>" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (ge:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (ge:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvcmpge<VSs> %x0,%x1,%x2" [(set_attr "type" "<VStype_simple>") @@ -997,10 +1029,10 @@ (define_insn "*vsx_eq_<mode>_p" [(set (reg:CC 74) (unspec:CC - [(eq:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?wa"))] + [(eq:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?<VSa>"))] UNSPEC_PREDICATE)) - (set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") + (set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") (eq:VSX_F (match_dup 1) (match_dup 2)))] "VECTOR_UNIT_VSX_P (<MODE>mode)" @@ -1010,10 +1042,10 @@ (define_insn "*vsx_gt_<mode>_p" [(set (reg:CC 74) (unspec:CC - [(gt:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?wa"))] + [(gt:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?<VSa>"))] UNSPEC_PREDICATE)) - (set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") + (set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") (gt:VSX_F (match_dup 1) (match_dup 2)))] "VECTOR_UNIT_VSX_P (<MODE>mode)" @@ -1023,10 +1055,10 @@ (define_insn "*vsx_ge_<mode>_p" [(set (reg:CC 74) (unspec:CC - [(ge:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?wa"))] + [(ge:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?<VSa>"))] UNSPEC_PREDICATE)) - (set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") + (set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") (ge:VSX_F (match_dup 1) (match_dup 2)))] "VECTOR_UNIT_VSX_P (<MODE>mode)" @@ -1035,33 +1067,33 @@ ;; Vector select (define_insn "*vsx_xxsel<mode>" - [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa") + [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?<VSa>") (if_then_else:VSX_L - (ne:CC (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,wa") + (ne:CC (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,<VSa>") (match_operand:VSX_L 4 "zero_constant" "")) - (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,wa") - (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,wa")))] + (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,<VSa>") + (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_MEM_VSX_P (<MODE>mode)" "xxsel %x0,%x3,%x2,%x1" [(set_attr "type" "vecperm")]) (define_insn "*vsx_xxsel<mode>_uns" - [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa") + [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?<VSa>") (if_then_else:VSX_L - (ne:CCUNS (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,wa") + (ne:CCUNS (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,<VSa>") (match_operand:VSX_L 4 "zero_constant" "")) - (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,wa") - (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,wa")))] + (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,<VSa>") + (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_MEM_VSX_P (<MODE>mode)" "xxsel %x0,%x3,%x2,%x1" [(set_attr "type" "vecperm")]) ;; Copy sign (define_insn "vsx_copysign<mode>3" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") (unspec:VSX_F - [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")] + [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")] UNSPEC_COPYSIGN))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvcpsgn<VSs> %x0,%x2,%x1" @@ -1074,7 +1106,7 @@ ;; in rs6000.md so don't test VECTOR_UNIT_VSX_P, just test against VSX. ;; Don't use vsx_register_operand here, use gpc_reg_operand to match rs6000.md. (define_insn "vsx_float<VSi><mode>2" - [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=<VSr>,?wa") + [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=<VSr>,?<VSa>") (float:VSX_B (match_operand:<VSI> 1 "gpc_reg_operand" "<VSr2>,<VSr3>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "x<VSv>cvsx<VSc><VSs> %x0,%x1" @@ -1082,7 +1114,7 @@ (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "vsx_floatuns<VSi><mode>2" - [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=<VSr>,?wa") + [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=<VSr>,?<VSa>") (unsigned_float:VSX_B (match_operand:<VSI> 1 "gpc_reg_operand" "<VSr2>,<VSr3>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "x<VSv>cvux<VSc><VSs> %x0,%x1" @@ -1091,7 +1123,7 @@ (define_insn "vsx_fix_trunc<mode><VSi>2" [(set (match_operand:<VSI> 0 "gpc_reg_operand" "=<VSr2>,?<VSr3>") - (fix:<VSI> (match_operand:VSX_B 1 "gpc_reg_operand" "<VSr>,wa")))] + (fix:<VSI> (match_operand:VSX_B 1 "gpc_reg_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "x<VSv>cv<VSs>sx<VSc>s %x0,%x1" [(set_attr "type" "<VStype_simple>") @@ -1099,7 +1131,7 @@ (define_insn "vsx_fixuns_trunc<mode><VSi>2" [(set (match_operand:<VSI> 0 "gpc_reg_operand" "=<VSr2>,?<VSr3>") - (unsigned_fix:<VSI> (match_operand:VSX_B 1 "gpc_reg_operand" "<VSr>,wa")))] + (unsigned_fix:<VSI> (match_operand:VSX_B 1 "gpc_reg_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "x<VSv>cv<VSs>ux<VSc>s %x0,%x1" [(set_attr "type" "<VStype_simple>") @@ -1107,8 +1139,8 @@ ;; Math rounding functions (define_insn "vsx_x<VSv>r<VSs>i" - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa") - (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")] + [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,<VSa>")] UNSPEC_VSX_ROUND_I))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "x<VSv>r<VSs>i %x0,%x1" @@ -1116,8 +1148,8 @@ (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "vsx_x<VSv>r<VSs>ic" - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa") - (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")] + [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,<VSa>")] UNSPEC_VSX_ROUND_IC))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "x<VSv>r<VSs>ic %x0,%x1" @@ -1125,16 +1157,16 @@ (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "vsx_btrunc<mode>2" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (fix:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (fix:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvr<VSs>iz %x0,%x1" [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "*vsx_b2trunc<mode>2" - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa") - (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")] + [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,<VSa>")] UNSPEC_FRIZ))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "x<VSv>r<VSs>iz %x0,%x1" @@ -1142,8 +1174,8 @@ (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "vsx_floor<mode>2" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")] UNSPEC_FRIM))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvr<VSs>im %x0,%x1" @@ -1151,8 +1183,8 @@ (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "vsx_ceil<mode>2" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")] UNSPEC_FRIP))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvr<VSs>ip %x0,%x1" @@ -1167,8 +1199,8 @@ ;; scalar single precision instructions internally use the double format. ;; Prefer the altivec registers, since we likely will need to do a vperm (define_insn "vsx_<VS_spdp_insn>" - [(set (match_operand:<VS_spdp_res> 0 "vsx_register_operand" "=<VSr4>,?wa") - (unspec:<VS_spdp_res> [(match_operand:VSX_SPDP 1 "vsx_register_operand" "<VSr5>,wa")] + [(set (match_operand:<VS_spdp_res> 0 "vsx_register_operand" "=<VSr4>,?<VSa>") + (unspec:<VS_spdp_res> [(match_operand:VSX_SPDP 1 "vsx_register_operand" "<VSr5>,<VSa>")] UNSPEC_VSX_CVSPDP))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "<VS_spdp_insn> %x0,%x1" @@ -1176,8 +1208,8 @@ ;; xscvspdp, represent the scalar SF type as V4SF (define_insn "vsx_xscvspdp" - [(set (match_operand:DF 0 "vsx_register_operand" "=ws,?wa") - (unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")] + [(set (match_operand:DF 0 "vsx_register_operand" "=ws") + (unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa")] UNSPEC_VSX_CVSPDP))] "VECTOR_UNIT_VSX_P (V4SFmode)" "xscvspdp %x0,%x1" @@ -1204,7 +1236,7 @@ ;; ISA 2.07 xscvdpspn/xscvspdpn that does not raise an error on signalling NaNs (define_insn "vsx_xscvdpspn" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=ws,?wa") + [(set (match_operand:V4SF 0 "vsx_register_operand" "=ww,?ww") (unspec:V4SF [(match_operand:DF 1 "vsx_register_operand" "wd,wa")] UNSPEC_VSX_CVDPSPN))] "TARGET_XSCVDPSPN" @@ -1212,16 +1244,16 @@ [(set_attr "type" "fp")]) (define_insn "vsx_xscvspdpn" - [(set (match_operand:DF 0 "vsx_register_operand" "=ws,?wa") - (unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")] + [(set (match_operand:DF 0 "vsx_register_operand" "=ws,?ws") + (unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wf,wa")] UNSPEC_VSX_CVSPDPN))] "TARGET_XSCVSPDPN" "xscvspdpn %x0,%x1" [(set_attr "type" "fp")]) (define_insn "vsx_xscvdpspn_scalar" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "f")] + [(set (match_operand:V4SF 0 "vsx_register_operand" "=wf,?wa") + (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "ww,ww")] UNSPEC_VSX_CVDPSPN))] "TARGET_XSCVDPSPN" "xscvdpspn %x0,%x1" @@ -1309,10 +1341,10 @@ ;; since the xsrdpiz instruction does not truncate the value if the floating ;; point value is < LONG_MIN or > LONG_MAX. (define_insn "*vsx_float_fix_<mode>2" - [(set (match_operand:VSX_DF 0 "vsx_register_operand" "=<VSr>,?wa") + [(set (match_operand:VSX_DF 0 "vsx_register_operand" "=<VSr>,?<VSa>") (float:VSX_DF (fix:<VSI> - (match_operand:VSX_DF 1 "vsx_register_operand" "<VSr>,?wa"))))] + (match_operand:VSX_DF 1 "vsx_register_operand" "<VSr>,?<VSa>"))))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && VECTOR_UNIT_VSX_P (<MODE>mode) && flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ" @@ -1325,10 +1357,10 @@ ;; Build a V2DF/V2DI vector from two scalars (define_insn "vsx_concat_<mode>" - [(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSr>,?wa") + [(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSr>,?<VSa>") (vec_concat:VSX_D - (match_operand:<VS_scalar> 1 "vsx_register_operand" "ws,wa") - (match_operand:<VS_scalar> 2 "vsx_register_operand" "ws,wa")))] + (match_operand:<VS_scalar> 1 "vsx_register_operand" "<VS_64reg>,<VSa>") + (match_operand:<VS_scalar> 2 "vsx_register_operand" "<VS_64reg>,<VSa>")))] "VECTOR_MEM_VSX_P (<MODE>mode)" { if (BYTES_BIG_ENDIAN) @@ -1359,18 +1391,18 @@ ;; xxpermdi for little endian loads and stores. We need several of ;; these since the form of the PARALLEL differs by mode. (define_insn "*vsx_xxpermdi2_le_<mode>" - [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=wa") + [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=<VSa>") (vec_select:VSX_LE - (match_operand:VSX_LE 1 "vsx_register_operand" "wa") + (match_operand:VSX_LE 1 "vsx_register_operand" "<VSa>") (parallel [(const_int 1) (const_int 0)])))] "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)" "xxpermdi %x0,%x1,%x1,2" [(set_attr "type" "vecperm")]) (define_insn "*vsx_xxpermdi4_le_<mode>" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=<VSa>") (vec_select:VSX_W - (match_operand:VSX_W 1 "vsx_register_operand" "wa") + (match_operand:VSX_W 1 "vsx_register_operand" "<VSa>") (parallel [(const_int 2) (const_int 3) (const_int 0) (const_int 1)])))] "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)" @@ -1408,7 +1440,7 @@ ;; lxvd2x for little endian loads. We need several of ;; these since the form of the PARALLEL differs by mode. (define_insn "*vsx_lxvd2x2_le_<mode>" - [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=wa") + [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=<VSa>") (vec_select:VSX_LE (match_operand:VSX_LE 1 "memory_operand" "Z") (parallel [(const_int 1) (const_int 0)])))] @@ -1417,7 +1449,7 @@ [(set_attr "type" "vecload")]) (define_insn "*vsx_lxvd2x4_le_<mode>" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=<VSa>") (vec_select:VSX_W (match_operand:VSX_W 1 "memory_operand" "Z") (parallel [(const_int 2) (const_int 3) @@ -1459,7 +1491,7 @@ (define_insn "*vsx_stxvd2x2_le_<mode>" [(set (match_operand:VSX_LE 0 "memory_operand" "=Z") (vec_select:VSX_LE - (match_operand:VSX_LE 1 "vsx_register_operand" "wa") + (match_operand:VSX_LE 1 "vsx_register_operand" "<VSa>") (parallel [(const_int 1) (const_int 0)])))] "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)" "stxvd2x %x1,%y0" @@ -1468,7 +1500,7 @@ (define_insn "*vsx_stxvd2x4_le_<mode>" [(set (match_operand:VSX_W 0 "memory_operand" "=Z") (vec_select:VSX_W - (match_operand:VSX_W 1 "vsx_register_operand" "wa") + (match_operand:VSX_W 1 "vsx_register_operand" "<VSa>") (parallel [(const_int 2) (const_int 3) (const_int 0) (const_int 1)])))] "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)" @@ -1520,11 +1552,12 @@ ;; Set the element of a V2DI/VD2F mode (define_insn "vsx_set_<mode>" - [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,?wa") - (unspec:VSX_D [(match_operand:VSX_D 1 "vsx_register_operand" "wd,wa") - (match_operand:<VS_scalar> 2 "vsx_register_operand" "ws,wa") - (match_operand:QI 3 "u5bit_cint_operand" "i,i")] - UNSPEC_VSX_SET))] + [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,?<VSa>") + (unspec:VSX_D + [(match_operand:VSX_D 1 "vsx_register_operand" "wd,<VSa>") + (match_operand:<VS_scalar> 2 "vsx_register_operand" "<VS_64reg>,<VSa>") + (match_operand:QI 3 "u5bit_cint_operand" "i,i")] + UNSPEC_VSX_SET))] "VECTOR_MEM_VSX_P (<MODE>mode)" { int idx_first = BYTES_BIG_ENDIAN ? 0 : 1; @@ -1589,7 +1622,7 @@ (define_insn_and_split "vsx_extract_v4sf" [(set (match_operand:SF 0 "vsx_register_operand" "=f,f") (vec_select:SF - (match_operand:V4SF 1 "vsx_register_operand" "wa,wa") + (match_operand:V4SF 1 "vsx_register_operand" "<VSa>,<VSa>") (parallel [(match_operand:QI 2 "u5bit_cint_operand" "O,i")]))) (clobber (match_scratch:V4SF 3 "=X,0"))] "VECTOR_UNIT_VSX_P (V4SFmode)" @@ -1772,9 +1805,9 @@ ;; V2DF/V2DI splat (define_insn "vsx_splat_<mode>" - [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,wd,wd,?wa,?wa,?wa") + [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,wd,wd,?<VSa>,?<VSa>,?<VSa>") (vec_duplicate:VSX_D - (match_operand:<VS_scalar> 1 "splat_input_operand" "ws,f,Z,wa,wa,Z")))] + (match_operand:<VS_scalar> 1 "splat_input_operand" "<VS_64reg>,f,Z,<VSa>,<VSa>,Z")))] "VECTOR_MEM_VSX_P (<MODE>mode)" "@ xxpermdi %x0,%x1,%x1,0 @@ -1787,10 +1820,10 @@ ;; V4SF/V4SI splat (define_insn "vsx_xxspltw_<mode>" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?wa") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?<VSa>") (vec_duplicate:VSX_W (vec_select:<VS_scalar> - (match_operand:VSX_W 1 "vsx_register_operand" "wf,wa") + (match_operand:VSX_W 1 "vsx_register_operand" "wf,<VSa>") (parallel [(match_operand:QI 2 "u5bit_cint_operand" "i,i")]))))] "VECTOR_MEM_VSX_P (<MODE>mode)" @@ -1803,8 +1836,8 @@ [(set_attr "type" "vecperm")]) (define_insn "vsx_xxspltw_<mode>_direct" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?wa") - (unspec:VSX_W [(match_operand:VSX_W 1 "vsx_register_operand" "wf,wa") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?<VSa>") + (unspec:VSX_W [(match_operand:VSX_W 1 "vsx_register_operand" "wf,<VSa>") (match_operand:QI 2 "u5bit_cint_operand" "i,i")] UNSPEC_VSX_XXSPLTW))] "VECTOR_MEM_VSX_P (<MODE>mode)" @@ -1813,11 +1846,11 @@ ;; V4SF/V4SI interleave (define_insn "vsx_xxmrghw_<mode>" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?wa") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?<VSa>") (vec_select:VSX_W (vec_concat:<VS_double> - (match_operand:VSX_W 1 "vsx_register_operand" "wf,wa") - (match_operand:VSX_W 2 "vsx_register_operand" "wf,wa")) + (match_operand:VSX_W 1 "vsx_register_operand" "wf,<VSa>") + (match_operand:VSX_W 2 "vsx_register_operand" "wf,<VSa>")) (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))] "VECTOR_MEM_VSX_P (<MODE>mode)" @@ -1830,11 +1863,11 @@ [(set_attr "type" "vecperm")]) (define_insn "vsx_xxmrglw_<mode>" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?wa") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?<VSa>") (vec_select:VSX_W (vec_concat:<VS_double> - (match_operand:VSX_W 1 "vsx_register_operand" "wf,wa") - (match_operand:VSX_W 2 "vsx_register_operand" "wf,?wa")) + (match_operand:VSX_W 1 "vsx_register_operand" "wf,<VSa>") + (match_operand:VSX_W 2 "vsx_register_operand" "wf,?<VSa>")) (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))] "VECTOR_MEM_VSX_P (<MODE>mode)" @@ -1848,9 +1881,9 @@ ;; Shift left double by word immediate (define_insn "vsx_xxsldwi_<mode>" - [(set (match_operand:VSX_L 0 "vsx_register_operand" "=wa") - (unspec:VSX_L [(match_operand:VSX_L 1 "vsx_register_operand" "wa") - (match_operand:VSX_L 2 "vsx_register_operand" "wa") + [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSa>") + (unspec:VSX_L [(match_operand:VSX_L 1 "vsx_register_operand" "<VSa>") + (match_operand:VSX_L 2 "vsx_register_operand" "<VSa>") (match_operand:QI 3 "u5bit_cint_operand" "i")] UNSPEC_VSX_SLDWI))] "VECTOR_MEM_VSX_P (<MODE>mode)" @@ -1931,7 +1964,7 @@ ;; to the top element of the V2DF array without doing an extract. (define_insn_and_split "*vsx_reduc_<VEC_reduc_name>_v2df_scalar" - [(set (match_operand:DF 0 "vfloat_operand" "=&ws,&?wa,ws,?wa") + [(set (match_operand:DF 0 "vfloat_operand" "=&ws,&?ws,ws,?ws") (vec_select:DF (VEC_reduc:V2DF (vec_concat:V2DF diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c index 9ecaa926dda..e818a799b4d 100644 --- a/gcc/config/sh/sh.c +++ b/gcc/config/sh/sh.c @@ -808,6 +808,12 @@ sh_option_override (void) targetm.asm_out.aligned_op.di = NULL; targetm.asm_out.unaligned_op.di = NULL; } + + /* User/priviledged mode is supported only on SH3*, SH4* and SH5*. + Disable it for everything else. */ + if (! (TARGET_SH3 || TARGET_SH5) && TARGET_USERMODE) + TARGET_USERMODE = false; + if (TARGET_SH1) { if (! strcmp (sh_div_str, "call-div1")) diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt index 8a6788eb3d1..8fdd7e38546 100644 --- a/gcc/config/sh/sh.opt +++ b/gcc/config/sh/sh.opt @@ -343,7 +343,7 @@ Target RejectNegative Joined UInteger Var(sh_multcost) Init(-1) Cost to assume for a multiply insn musermode -Target Report RejectNegative Var(TARGET_USERMODE) +Target Var(TARGET_USERMODE) Don't generate privileged-mode only code; implies -mno-inline-ic_invalidate if the inline code would not work in user mode. ;; We might want to enable this by default for TARGET_HARD_SH4, because diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md index cf135ac09fb..17a34e7f9b0 100644 --- a/gcc/config/sh/sync.md +++ b/gcc/config/sh/sync.md @@ -466,6 +466,7 @@ (set (mem:SI (match_dup 1)) (unspec:SI [(match_operand:SI 2 "arith_operand" "rI08")] UNSPEC_ATOMIC)) + (set (reg:SI T_REG) (const_int 1)) (clobber (reg:SI R0_REG))] "TARGET_ATOMIC_HARD_LLCS || (TARGET_SH4A_ARCH && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)" @@ -484,6 +485,7 @@ (set (mem:QIHI (match_dup 1)) (unspec:QIHI [(match_operand:QIHI 2 "register_operand" "r")] UNSPEC_ATOMIC)) + (set (reg:SI T_REG) (const_int 1)) (clobber (reg:SI R0_REG)) (clobber (match_scratch:SI 3 "=&r")) (clobber (match_scratch:SI 4 "=1"))] @@ -617,6 +619,7 @@ [(FETCHOP:SI (mem:SI (match_dup 1)) (match_operand:SI 2 "<fetchop_predicate>" "<fetchop_constraint>"))] UNSPEC_ATOMIC)) + (set (reg:SI T_REG) (const_int 1)) (clobber (reg:SI R0_REG))] "TARGET_ATOMIC_HARD_LLCS || (TARGET_SH4A_ARCH && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)" @@ -637,6 +640,7 @@ [(FETCHOP:QIHI (mem:QIHI (match_dup 1)) (match_operand:QIHI 2 "<fetchop_predicate>" "<fetchop_constraint>"))] UNSPEC_ATOMIC)) + (set (reg:SI T_REG) (const_int 1)) (clobber (reg:SI R0_REG)) (clobber (match_scratch:SI 3 "=&r")) (clobber (match_scratch:SI 4 "=1"))] @@ -784,6 +788,7 @@ [(not:SI (and:SI (mem:SI (match_dup 1)) (match_operand:SI 2 "logical_operand" "rK08")))] UNSPEC_ATOMIC)) + (set (reg:SI T_REG) (const_int 1)) (clobber (reg:SI R0_REG))] "TARGET_ATOMIC_HARD_LLCS || (TARGET_SH4A_ARCH && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)" @@ -805,6 +810,7 @@ [(not:QIHI (and:QIHI (mem:QIHI (match_dup 1)) (match_operand:QIHI 2 "logical_operand" "rK08")))] UNSPEC_ATOMIC)) + (set (reg:SI T_REG) (const_int 1)) (clobber (reg:SI R0_REG)) (clobber (match_scratch:SI 3 "=&r")) (clobber (match_scratch:SI 4 "=1"))] @@ -903,7 +909,7 @@ " and %0,%3" "\n" " not %3,%3" "\n" " mov.<bwl> %3,@%1" "\n" - " stc %4,sr"; + " ldc %4,sr"; } [(set_attr "length" "20")]) @@ -960,7 +966,8 @@ (set (mem:SI (match_dup 1)) (unspec:SI [(FETCHOP:SI (mem:SI (match_dup 1)) (match_dup 2))] - UNSPEC_ATOMIC))] + UNSPEC_ATOMIC)) + (set (reg:SI T_REG) (const_int 1))] "TARGET_ATOMIC_HARD_LLCS || (TARGET_SH4A_ARCH && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)" { @@ -980,6 +987,7 @@ (unspec:QIHI [(FETCHOP:QIHI (mem:QIHI (match_dup 1)) (match_dup 2))] UNSPEC_ATOMIC)) + (set (reg:SI T_REG) (const_int 1)) (clobber (reg:SI R0_REG)) (clobber (match_scratch:SI 3 "=&r")) (clobber (match_scratch:SI 4 "=1"))] @@ -1124,7 +1132,8 @@ (set (mem:SI (match_dup 1)) (unspec:SI [(not:SI (and:SI (mem:SI (match_dup 1)) (match_dup 2)))] - UNSPEC_ATOMIC))] + UNSPEC_ATOMIC)) + (set (reg:SI T_REG) (const_int 1))] "TARGET_ATOMIC_HARD_LLCS || (TARGET_SH4A_ARCH && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)" { @@ -1145,6 +1154,7 @@ (unspec:QIHI [(not:QIHI (and:QIHI (mem:QIHI (match_dup 1)) (match_dup 2)))] UNSPEC_ATOMIC)) + (set (reg:SI T_REG) (const_int 1)) (clobber (reg:SI R0_REG)) (clobber (match_scratch:SI 3 "=&r")) (clobber (match_scratch:SI 4 "=1"))] @@ -1353,7 +1363,7 @@ " ldc r0,sr" "\n" " mov.b @%0,r0" "\n" " mov.b %1,@%0" "\n" - " stc %2,sr" "\n" + " ldc %2,sr" "\n" " tst r0,r0"; } [(set_attr "length" "16")]) diff --git a/gcc/configure b/gcc/configure index d731769987a..01767dca0f1 100755 --- a/gcc/configure +++ b/gcc/configure @@ -910,6 +910,7 @@ with_plugin_ld enable_gnu_indirect_function enable_initfini_array enable_comdat +enable_fix_cortex_a53_835769 enable_gnu_unique_object enable_linker_build_id with_long_double_128 @@ -1619,6 +1620,14 @@ Optional Features: glibc systems --enable-initfini-array use .init_array/.fini_array sections --enable-comdat enable COMDAT group support + + --enable-fix-cortex-a53-835769 + enable workaround for AArch64 Cortex-A53 erratum + 835769 by default + --disable-fix-cortex-a53-835769 + disable workaround for AArch64 Cortex-A53 erratum + 835769 by default + --enable-gnu-unique-object enable the use of the @gnu_unique_object ELF extension on glibc systems @@ -17839,7 +17848,7 @@ else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF -#line 17841 "configure" +#line 17850 "configure" #include "confdefs.h" #if HAVE_DLFCN_H @@ -17945,7 +17954,7 @@ else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF -#line 17947 "configure" +#line 17956 "configure" #include "confdefs.h" #if HAVE_DLFCN_H @@ -23797,6 +23806,28 @@ _ACEOF $as_echo "$gcc_cv_lto_plugin" >&6; } case "$target" in + + aarch64*-*-*) + # Enable default workaround for AArch64 Cortex-A53 erratum 835769. + # Check whether --enable-fix-cortex-a53-835769 was given. +if test "${enable_fix_cortex_a53_835769+set}" = set; then : + enableval=$enable_fix_cortex_a53_835769; + case $enableval in + yes) + tm_defines="${tm_defines} TARGET_FIX_ERR_A53_835769_DEFAULT=1" + ;; + no) + ;; + *) + as_fn_error "'$enableval' is an invalid value for --enable-fix-cortex-a53-835769.\ + Valid choices are 'yes' and 'no'." "$LINENO" 5 + ;; + + esac + +fi + + ;; # All TARGET_ABI_OSF targets. alpha*-*-linux* | alpha*-*-*bsd*) { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for explicit relocation support" >&5 diff --git a/gcc/configure.ac b/gcc/configure.ac index ac5863d8a92..ef349a4a688 100644 --- a/gcc/configure.ac +++ b/gcc/configure.ac @@ -3443,6 +3443,32 @@ AC_DEFINE_UNQUOTED(HAVE_LTO_PLUGIN, $gcc_cv_lto_plugin, AC_MSG_RESULT($gcc_cv_lto_plugin) case "$target" in + + aarch64*-*-*) + # Enable default workaround for AArch64 Cortex-A53 erratum 835769. + AC_ARG_ENABLE(fix-cortex-a53-835769, + [ +AS_HELP_STRING([--enable-fix-cortex-a53-835769], + [enable workaround for AArch64 Cortex-A53 erratum 835769 by default]) +AS_HELP_STRING([--disable-fix-cortex-a53-835769], + [disable workaround for AArch64 Cortex-A53 erratum 835769 by default]) + ], + [ + case $enableval in + yes) + tm_defines="${tm_defines} TARGET_FIX_ERR_A53_835769_DEFAULT=1" + ;; + no) + ;; + *) + AC_MSG_ERROR(['$enableval' is an invalid value for --enable-fix-cortex-a53-835769.\ + Valid choices are 'yes' and 'no'.]) + ;; + + esac + ], + []) + ;; # All TARGET_ABI_OSF targets. alpha*-*-linux* | alpha*-*-*bsd*) gcc_GAS_CHECK_FEATURE([explicit relocation support], diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 82e61f5f6b7..917e5cfdd20 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,23 @@ +2014-10-15 Jason Merrill <jason@redhat.com> + + PR c++/63455 + Revert: + * parser.c (cp_parser_abort_tentative_parse): Make sure we haven't + committed to this tentative parse. + + PR c++/63415 + * pt.c (value_dependent_expression_p) [CONSTRUCTOR]: Check the type. + (iterative_hash_template_arg): Likewise. + + PR c++/56710 + * semantics.c (finish_member_declaration): Don't push closure + members. + + PR c++/58624 + * pt.c (tsubst_copy_and_build) [VAR_DECL]: Use TLS wrapper. + * semantics.c (finish_id_expression): Don't call TLS wrapper in a + template. + 2014-08-07 Jason Merrill <jason@redhat.com> PR c++/61959 diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c index affe2df0c47..a84bc59cef2 100644 --- a/gcc/cp/parser.c +++ b/gcc/cp/parser.c @@ -23779,8 +23779,6 @@ cp_parser_commit_to_tentative_parse (cp_parser* parser) static void cp_parser_abort_tentative_parse (cp_parser* parser) { - gcc_assert (parser->context->status != CP_PARSER_STATUS_KIND_COMMITTED - || errorcount > 0); cp_parser_simulate_error (parser); /* Now, pretend that we want to see if the construct was successfully parsed. */ diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index c03af2e93e0..eadb0786f9a 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -1571,6 +1571,7 @@ iterative_hash_template_arg (tree arg, hashval_t val) case CONSTRUCTOR: { tree field, value; + iterative_hash_template_arg (TREE_TYPE (arg), val); FOR_EACH_CONSTRUCTOR_ELT (CONSTRUCTOR_ELTS (arg), i, field, value) { val = iterative_hash_template_arg (field, val); @@ -14499,6 +14500,16 @@ tsubst_copy_and_build (tree t, case PARM_DECL: { tree r = tsubst_copy (t, args, complain, in_decl); + if (TREE_CODE (r) == VAR_DECL + && !processing_template_decl + && !cp_unevaluated_operand + && DECL_THREAD_LOCAL_P (r)) + { + if (tree wrap = get_tls_wrapper_fn (r)) + /* Replace an evaluated use of the thread_local variable with + a call to its wrapper. */ + r = build_cxx_call (wrap, 0, NULL, tf_warning_or_error); + } if (TREE_CODE (TREE_TYPE (t)) != REFERENCE_TYPE) /* If the original type was a reference, we'll be wrapped in @@ -19816,6 +19827,8 @@ value_dependent_expression_p (tree expression) { unsigned ix; tree val; + if (dependent_type_p (TREE_TYPE (expression))) + return true; FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (expression), ix, val) if (value_dependent_expression_p (val)) return true; diff --git a/gcc/cp/semantics.c b/gcc/cp/semantics.c index 9825dbe6aa4..30ec7fcf565 100644 --- a/gcc/cp/semantics.c +++ b/gcc/cp/semantics.c @@ -2735,8 +2735,10 @@ finish_member_declaration (tree decl) /*friend_p=*/0); } } - /* Enter the DECL into the scope of the class. */ - else if (pushdecl_class_level (decl)) + /* Enter the DECL into the scope of the class, if the class + isn't a closure (whose fields are supposed to be unnamed). */ + else if (CLASSTYPE_LAMBDA_EXPR (current_class_type) + || pushdecl_class_level (decl)) { if (TREE_CODE (decl) == USING_DECL) { @@ -3343,6 +3345,7 @@ finish_id_expression (tree id_expression, tree wrap; if (TREE_CODE (decl) == VAR_DECL && !cp_unevaluated_operand + && !processing_template_decl && DECL_THREAD_LOCAL_P (decl) && (wrap = get_tls_wrapper_fn (decl))) { diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index 672d78365f2..2c3dace8b41 100644 --- a/gcc/doc/install.texi +++ b/gcc/doc/install.texi @@ -2982,6 +2982,8 @@ information have to. @ifhtml @itemize @item +@uref{#aarch64x-x-x,,aarch64*-*-*} +@item @uref{#alpha-x-x,,alpha*-*-*} @item @uref{#alpha-dec-osf51,,alpha*-dec-osf5.1} @@ -3124,6 +3126,18 @@ information have to. <!-- -------- host/target specific issues start here ---------------- --> <hr /> @end html + +@heading @anchor{aarch64x-x-x}aarch64*-*-* +To enable a workaround for the Cortex-A53 erratum number 835769 by default +(for all CPUs regardless of -mcpu option given) at configure time use the +@option{--enable-fix-cortex-a53-835769} option. This will enable the fix by +default and can be explicitly disabled during during compilation by passing the +@option{-mno-fix-cortex-a53-835769} option. Conversely, +@option{--disable-fix-cortex-a53-835769} will disable the workaround by +default. The workaround is disabled by default if neither of +@option{--enable-fix-cortex-a53-835769} or +@option{--disable-fix-cortex-a53-835769} is given at configure time. + @heading @anchor{alpha-x-x}alpha*-*-* This section contains general configuration information for all diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index f9843598a62..705a0965869 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -475,6 +475,7 @@ Objective-C and Objective-C++ Dialects}. -mstrict-align @gol -momit-leaf-frame-pointer -mno-omit-leaf-frame-pointer @gol -mtls-dialect=desc -mtls-dialect=traditional @gol +-mfix-cortex-a53-835769 -mno-fix-cortex-a53-835769 @gol -march=@var{name} -mcpu=@var{name} -mtune=@var{name}} @emph{Adapteva Epiphany Options} @@ -10939,6 +10940,14 @@ of TLS variables. This is the default. Use traditional TLS as the thread-local storage mechanism for dynamic accesses of TLS variables. +@item -mfix-cortex-a53-835769 +@itemx -mno-fix-cortex-a53-835769 +@opindex -mfix-cortex-a53-835769 +@opindex -mno-fix-cortex-a53-835769 +Enable or disable the workaround for the ARM Cortex-A53 erratum number 835769. +This will involve inserting a NOP instruction between memory instructions and +64-bit integer multiply-accumulate instructions. + @item -march=@var{name} @opindex march Specify the name of the target architecture, optionally suffixed by one or @@ -11282,8 +11291,8 @@ architecture together with the optional CRC32 extensions. @option{-march=native} causes the compiler to auto-detect the architecture of the build computer. At present, this feature is only supported on -Linux, and not all architectures are recognized. If the auto-detect is -unsuccessful the option has no effect. +GNU/Linux, and not all architectures are recognized. If the auto-detect +is unsuccessful the option has no effect. @item -mtune=@var{name} @opindex mtune @@ -11328,7 +11337,7 @@ this option may change in future GCC versions as CPU models come and go. @option{-mtune=native} causes the compiler to auto-detect the CPU of the build computer. At present, this feature is only supported on -Linux, and not all architectures are recognized. If the auto-detect is +GNU/Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. @item -mcpu=@var{name} @@ -11349,8 +11358,8 @@ See @option{-mtune} for more information. @option{-mcpu=native} causes the compiler to auto-detect the CPU of the build computer. At present, this feature is only supported on -Linux, and not all architectures are recognized. If the auto-detect is -unsuccessful the option has no effect. +GNU/Linux, and not all architectures are recognized. If the auto-detect +is unsuccessful the option has no effect. @item -mfpu=@var{name} @opindex mfpu @@ -12501,7 +12510,7 @@ are compatible with as many systems and code bases as possible. @item -mkernel @opindex mkernel Enable kernel development mode. The @option{-mkernel} option sets -@option{-static}, @option{-fno-common}, @option{-fno-cxa-atexit}, +@option{-static}, @option{-fno-common}, @option{-fno-use-cxa-atexit}, @option{-fno-exceptions}, @option{-fno-non-call-exceptions}, @option{-fapple-kext}, @option{-fno-weak} and @option{-fno-rtti} where applicable. This mode also sets @option{-mno-altivec}, @@ -18729,6 +18738,72 @@ single-precision mode by default. @opindex m4 Generate code for the SH4. +@item -m4-100 +@opindex m4-100 +Generate code for SH4-100. + +@item -m4-100-nofpu +@opindex m4-100-nofpu +Generate code for SH4-100 in such a way that the +floating-point unit is not used. + +@item -m4-100-single +@opindex m4-100-single +Generate code for SH4-100 assuming the floating-point unit is in +single-precision mode by default. + +@item -m4-100-single-only +@opindex m4-100-single-only +Generate code for SH4-100 in such a way that no double-precision +floating-point operations are used. + +@item -m4-200 +@opindex m4-200 +Generate code for SH4-200. + +@item -m4-200-nofpu +@opindex m4-200-nofpu +Generate code for SH4-200 without in such a way that the +floating-point unit is not used. + +@item -m4-200-single +@opindex m4-200-single +Generate code for SH4-200 assuming the floating-point unit is in +single-precision mode by default. + +@item -m4-200-single-only +@opindex m4-200-single-only +Generate code for SH4-200 in such a way that no double-precision +floating-point operations are used. + +@item -m4-300 +@opindex m4-300 +Generate code for SH4-300. + +@item -m4-300-nofpu +@opindex m4-300-nofpu +Generate code for SH4-300 without in such a way that the +floating-point unit is not used. + +@item -m4-300-single +@opindex m4-300-single +Generate code for SH4-300 in such a way that no double-precision +floating-point operations are used. + +@item -m4-300-single-only +@opindex m4-300-single-only +Generate code for SH4-300 in such a way that no double-precision +floating-point operations are used. + +@item -m4-340 +@opindex m4-340 +Generate code for SH4-340 (no MMU, no FPU). + +@item -m4-500 +@opindex m4-500 +Generate code for SH4-500 (no FPU). Passes @option{-isa=sh4-nofpu} to the +assembler. + @item -m4a-nofpu @opindex m4a-nofpu Generate code for the SH4al-dsp, or for a SH4a in such a way that the @@ -18754,6 +18829,33 @@ Same as @option{-m4a-nofpu}, except that it implicitly passes @option{-dsp} to the assembler. GCC doesn't generate any DSP instructions at the moment. +@item -m5-32media +@opindex m5-32media +Generate 32-bit code for SHmedia. + +@item -m5-32media-nofpu +@opindex m5-32media-nofpu +Generate 32-bit code for SHmedia in such a way that the +floating-point unit is not used. + +@item -m5-64media +@opindex m5-64media +Generate 64-bit code for SHmedia. + +@item -m5-64media-nofpu +@opindex m5-64media-nofpu +Generate 64-bit code for SHmedia in such a way that the +floating-point unit is not used. + +@item -m5-compact +@opindex m5-compact +Generate code for SHcompact. + +@item -m5-compact-nofpu +@opindex m5-compact-nofpu +Generate code for SHcompact in such a way that the +floating-point unit is not used. + @item -mb @opindex mb Compile code for the processor in big-endian mode. @@ -18787,16 +18889,12 @@ Enable the use of bit manipulation instructions on SH2A. Enable the use of the instruction @code{fmovd}. Check @option{-mdalign} for alignment constraints. -@item -mhitachi -@opindex mhitachi -Comply with the calling conventions defined by Renesas. - @item -mrenesas -@opindex mhitachi +@opindex mrenesas Comply with the calling conventions defined by Renesas. @item -mno-renesas -@opindex mhitachi +@opindex mno-renesas Comply with the calling conventions defined for GCC before the Renesas conventions were available. This option is the default for all targets of the SH toolchain. @@ -18804,12 +18902,12 @@ targets of the SH toolchain. @item -mnomacsave @opindex mnomacsave Mark the @code{MAC} register as call-clobbered, even if -@option{-mhitachi} is given. +@option{-mrenesas} is given. @item -mieee @itemx -mno-ieee @opindex mieee -@opindex mnoieee +@opindex mno-ieee Control the IEEE compliance of floating-point comparisons, which affects the handling of cases where the result of a comparison is unordered. By default @option{-mieee} is implicitly enabled. If @option{-ffinite-math-only} is @@ -18849,14 +18947,14 @@ separated list. For details on the atomic built-in functions see @item none Disable compiler generated atomic sequences and emit library calls for atomic -operations. This is the default if the target is not @code{sh-*-linux*}. +operations. This is the default if the target is not @code{sh*-*-linux*}. @item soft-gusa Generate GNU/Linux compatible gUSA software atomic sequences for the atomic built-in functions. The generated atomic sequences require additional support from the interrupt/exception handling code of the system and are only suitable for SH3* and SH4* single-core systems. This option is enabled by default when -the target is @code{sh-*-linux*} and SH3* or SH4*. When the target is SH4A, +the target is @code{sh*-*-linux*} and SH3* or SH4*. When the target is SH4A, this option will also partially utilize the hardware atomic instructions @code{movli.l} and @code{movco.l} to create more efficient code, unless @samp{strict} is specified. @@ -18875,7 +18973,7 @@ setting @code{SR.IMASK = 1111}. This model works only when the program runs in privileged mode and is only suitable for single-core systems. Additional support from the interrupt/exception handling code of the system is not required. This model is enabled by default when the target is -@code{sh-*-linux*} and SH1* or SH2*. +@code{sh*-*-linux*} and SH1* or SH2*. @item hard-llcs Generate hardware atomic sequences using the @code{movli.l} and @code{movco.l} @@ -18910,21 +19008,20 @@ that are implied by the @code{tas.b} instruction. On multi-core SH4A processors the @code{tas.b} instruction must be used with caution since it can result in data corruption for certain cache configurations. -@item -mspace -@opindex mspace -Optimize for space instead of speed. Implied by @option{-Os}. - @item -mprefergot @opindex mprefergot When generating position-independent code, emit function calls using the Global Offset Table instead of the Procedure Linkage Table. @item -musermode +@itemx -mno-usermode @opindex musermode -Don't generate privileged mode only code. This option -implies @option{-mno-inline-ic_invalidate} -if the inlined code would not work in user mode. -This is the default when the target is @code{sh-*-linux*}. +@opindex mno-usermode +Don't allow (allow) the compiler generating privileged mode code. Specifying +@option{-musermode} also implies @option{-mno-inline-ic_invalidate} if the +inlined code would not work in user mode. @option{-musermode} is the default +when the target is @code{sh*-*-linux*}. If the target is SH1* or SH2* +@option{-musermode} has no effect, since there is no user mode. @item -multcost=@var{number} @opindex multcost=@var{number} diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 5e932d36541..8254ff5e1be 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -2078,6 +2078,18 @@ VSX vector register to hold vector float data or NO_REGS. @item wg If @option{-mmfpgpr} was used, a floating point register or NO_REGS. +@item wh +Floating point register if direct moves are available, or NO_REGS. + +@item wi +FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS. + +@item wj +FP or VSX register to hold 64-bit integers for direct moves or NO_REGS. + +@item wk +FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS. + @item wl Floating point register if the LFIWAX instruction is enabled or NO_REGS. @@ -2109,7 +2121,7 @@ FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS. Floating point register if the STFIWX instruction is enabled or NO_REGS. @item wy -VSX vector register to hold scalar float values or NO_REGS. +FP or VSX register to perform ISA 2.07 float ops or NO_REGS. @item wz Floating point register if the LFIWZX instruction is enabled or NO_REGS. diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c index 77771c09b64..c68453e984b 100644 --- a/gcc/dwarf2out.c +++ b/gcc/dwarf2out.c @@ -12234,7 +12234,7 @@ mem_loc_descriptor (rtx rtl, enum machine_mode mode, op1 = mem_loc_descriptor (XEXP (rtl, 1), mode, mem_mode, VAR_INIT_STATUS_INITIALIZED); if (op1 == 0) - break; + return NULL; add_loc_descr (&mem_loc_result, op1); add_loc_descr (&mem_loc_result, new_loc_descr (DW_OP_plus, 0, 0)); @@ -13882,6 +13882,10 @@ loc_list_from_tree (tree loc, int want_address) have_address = 1; break; + case TARGET_MEM_REF: + case SSA_NAME: + return NULL; + case COMPOUND_EXPR: return loc_list_from_tree (TREE_OPERAND (loc, 1), want_address); diff --git a/gcc/emit-rtl.c b/gcc/emit-rtl.c index b5278bf4318..1cac5181341 100644 --- a/gcc/emit-rtl.c +++ b/gcc/emit-rtl.c @@ -263,7 +263,7 @@ mem_attrs_htab_hash (const void *x) /* Return true if the given memory attributes are equal. */ -static bool +bool mem_attrs_eq_p (const struct mem_attrs *p, const struct mem_attrs *q) { return (p->alias == q->alias diff --git a/gcc/emit-rtl.h b/gcc/emit-rtl.h index 726809097e7..81bb3344b58 100644 --- a/gcc/emit-rtl.h +++ b/gcc/emit-rtl.h @@ -20,6 +20,9 @@ along with GCC; see the file COPYING3. If not see #ifndef GCC_EMIT_RTL_H #define GCC_EMIT_RTL_H +/* Return whether two MEM_ATTRs are equal. */ +bool mem_attrs_eq_p (const struct mem_attrs *, const struct mem_attrs *); + /* Set the alias set of MEM to SET. */ extern void set_mem_alias_set (rtx, alias_set_type); diff --git a/gcc/expr.c b/gcc/expr.c index 01697e99ac8..f83a7d0d448 100644 --- a/gcc/expr.c +++ b/gcc/expr.c @@ -10603,7 +10603,7 @@ is_aligning_offset (const_tree offset, const_tree exp) || !host_integerp (TREE_OPERAND (offset, 1), 1) || compare_tree_int (TREE_OPERAND (offset, 1), BIGGEST_ALIGNMENT / BITS_PER_UNIT) <= 0 - || !exact_log2 (tree_low_cst (TREE_OPERAND (offset, 1), 1) + 1) < 0) + || exact_log2 (tree_low_cst (TREE_OPERAND (offset, 1), 1) + 1) < 0) return 0; /* Look at the first operand of BIT_AND_EXPR and strip any conversion. diff --git a/gcc/fold-const.c b/gcc/fold-const.c index 57ba334f3b6..a775f2713c1 100644 --- a/gcc/fold-const.c +++ b/gcc/fold-const.c @@ -9217,7 +9217,7 @@ fold_comparison (location_t loc, enum tree_code code, tree type, /* Transform comparisons of the form X +- C1 CMP Y +- C2 to X CMP Y +- C2 +- C1 for signed X, Y. This is valid if the resulting offset is smaller in absolute value than the - original one. */ + original one and has the same sign. */ if (TYPE_OVERFLOW_UNDEFINED (TREE_TYPE (arg0)) && (TREE_CODE (arg0) == PLUS_EXPR || TREE_CODE (arg0) == MINUS_EXPR) && (TREE_CODE (TREE_OPERAND (arg0, 1)) == INTEGER_CST @@ -9236,32 +9236,35 @@ fold_comparison (location_t loc, enum tree_code code, tree type, "a comparison"); /* Put the constant on the side where it doesn't overflow and is - of lower absolute value than before. */ + of lower absolute value and of same sign than before. */ cst = int_const_binop (TREE_CODE (arg0) == TREE_CODE (arg1) ? MINUS_EXPR : PLUS_EXPR, const2, const1); if (!TREE_OVERFLOW (cst) - && tree_int_cst_compare (const2, cst) == tree_int_cst_sgn (const2)) + && tree_int_cst_compare (const2, cst) == tree_int_cst_sgn (const2) + && tree_int_cst_sgn (cst) == tree_int_cst_sgn (const2)) { fold_overflow_warning (warnmsg, WARN_STRICT_OVERFLOW_COMPARISON); return fold_build2_loc (loc, code, type, - variable1, - fold_build2_loc (loc, - TREE_CODE (arg1), TREE_TYPE (arg1), - variable2, cst)); + variable1, + fold_build2_loc (loc, TREE_CODE (arg1), + TREE_TYPE (arg1), + variable2, cst)); } cst = int_const_binop (TREE_CODE (arg0) == TREE_CODE (arg1) ? MINUS_EXPR : PLUS_EXPR, const1, const2); if (!TREE_OVERFLOW (cst) - && tree_int_cst_compare (const1, cst) == tree_int_cst_sgn (const1)) + && tree_int_cst_compare (const1, cst) == tree_int_cst_sgn (const1) + && tree_int_cst_sgn (cst) == tree_int_cst_sgn (const1)) { fold_overflow_warning (warnmsg, WARN_STRICT_OVERFLOW_COMPARISON); return fold_build2_loc (loc, code, type, - fold_build2_loc (loc, TREE_CODE (arg0), TREE_TYPE (arg0), - variable1, cst), - variable2); + fold_build2_loc (loc, TREE_CODE (arg0), + TREE_TYPE (arg0), + variable1, cst), + variable2); } } @@ -11222,7 +11225,6 @@ fold_binary_loc (location_t loc, { double_int c1, c2, c3, msk; int width = TYPE_PRECISION (type), w; - bool try_simplify = true; c1 = tree_to_double_int (TREE_OPERAND (arg0, 1)); c2 = tree_to_double_int (arg1); @@ -11259,20 +11261,7 @@ fold_binary_loc (location_t loc, } } - /* If X is a tree of the form (Y * K1) & K2, this might conflict - with that optimization from the BIT_AND_EXPR optimizations. - This could end up in an infinite recursion. */ - if (TREE_CODE (TREE_OPERAND (arg0, 0)) == MULT_EXPR - && TREE_CODE (TREE_OPERAND (TREE_OPERAND (arg0, 0), 1)) - == INTEGER_CST) - { - tree t = TREE_OPERAND (TREE_OPERAND (arg0, 0), 1); - double_int masked = mask_with_tz (type, c3, tree_to_double_int (t)); - - try_simplify = (masked != c1); - } - - if (try_simplify && c3 != c1) + if (c3 != c1) return fold_build2_loc (loc, BIT_IOR_EXPR, type, fold_build2_loc (loc, BIT_AND_EXPR, type, TREE_OPERAND (arg0, 0), @@ -11662,16 +11651,25 @@ fold_binary_loc (location_t loc, && TREE_CODE (arg0) == MULT_EXPR && TREE_CODE (TREE_OPERAND (arg0, 1)) == INTEGER_CST) { + double_int darg1 = tree_to_double_int (arg1); double_int masked - = mask_with_tz (type, tree_to_double_int (arg1), + = mask_with_tz (type, darg1, tree_to_double_int (TREE_OPERAND (arg0, 1))); if (masked.is_zero ()) return omit_two_operands_loc (loc, type, build_zero_cst (type), arg0, arg1); - else if (masked != tree_to_double_int (arg1)) - return fold_build2_loc (loc, code, type, op0, - double_int_to_tree (type, masked)); + else if (masked != darg1) + { + /* Avoid the transform if arg1 is a mask of some + mode which allows further optimizations. */ + int pop = darg1.popcount (); + if (!(pop >= BITS_PER_UNIT + && exact_log2 (pop) != -1 + && double_int::mask (pop) == darg1)) + return fold_build2_loc (loc, code, type, op0, + double_int_to_tree (type, masked)); + } } /* For constants M and N, if M == (1LL << cst) - 1 && (N & M) == M, diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index 22e84cf8dd0..b5dfcf1fa47 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,21 @@ +2014-10-10 Jakub Jelinek <jakub@redhat.com> + + PR fortran/59488 + * trans-openmp.c (gfc_omp_predetermined_sharing): Return + OMP_CLAUSE_DEFAULT_SHARED for parameters or vtables. + +2014-09-03 Marek Polacek <polacek@redhat.com> + + Backport from trunk + PR fortran/62270 + * interface.c (compare_parameter): Fix condition. + +2014-08-21 Thomas Koenig <tkoenig@gcc.gnu.org> + + Backport from trunk + PR fortran/62214 + * gfortran.dg/array_assignment_5.f90: New test. + 2014-08-10 Thomas Koenig <tkoenig@gcc.gnu.org> Backport from trunk diff --git a/gcc/fortran/frontend-passes.c b/gcc/fortran/frontend-passes.c index 27729324cb7..7bbdac81b9e 100644 --- a/gcc/fortran/frontend-passes.c +++ b/gcc/fortran/frontend-passes.c @@ -874,6 +874,10 @@ optimize_binop_array_assignment (gfc_code *c, gfc_expr **rhs, bool seen_op) return true; break; + case INTRINSIC_CONCAT: + /* Do not do string concatenations. */ + break; + default: /* Binary operators. */ if (optimize_binop_array_assignment (c, &e->value.op.op1, true)) diff --git a/gcc/fortran/interface.c b/gcc/fortran/interface.c index 725cd8a4b76..e38bb1f5d0b 100644 --- a/gcc/fortran/interface.c +++ b/gcc/fortran/interface.c @@ -1923,7 +1923,7 @@ compare_parameter (gfc_symbol *formal, gfc_expr *actual, /* F2008, 12.5.2.5; IR F08/0073. */ if (formal->ts.type == BT_CLASS && actual->expr_type != EXPR_NULL && ((CLASS_DATA (formal)->attr.class_pointer - && !formal->attr.intent == INTENT_IN) + && formal->attr.intent != INTENT_IN) || CLASS_DATA (formal)->attr.allocatable)) { if (actual->ts.type != BT_CLASS) diff --git a/gcc/fortran/trans-openmp.c b/gcc/fortran/trans-openmp.c index 988dea92f58..53a78f08875 100644 --- a/gcc/fortran/trans-openmp.c +++ b/gcc/fortran/trans-openmp.c @@ -115,6 +115,16 @@ gfc_omp_predetermined_sharing (tree decl) if (GFC_DECL_RESULT (decl) && ! DECL_HAS_VALUE_EXPR_P (decl)) return OMP_CLAUSE_DEFAULT_SHARED; + /* These are either array or derived parameters, or vtables. + In the former cases, the OpenMP standard doesn't consider them to be + variables at all (they can't be redefined), but they can nevertheless appear + in parallel/task regions and for default(none) purposes treat them as shared. + For vtables likely the same handling is desirable. */ + if (TREE_CODE (decl) == VAR_DECL + && TREE_READONLY (decl) + && TREE_STATIC (decl)) + return OMP_CLAUSE_DEFAULT_SHARED; + return OMP_CLAUSE_DEFAULT_UNSPECIFIED; } diff --git a/gcc/gimple-fold.c b/gcc/gimple-fold.c index f8593501435..592909f4def 100644 --- a/gcc/gimple-fold.c +++ b/gcc/gimple-fold.c @@ -2957,8 +2957,8 @@ fold_ctor_reference (tree type, tree ctor, unsigned HOST_WIDE_INT offset, result. */ if (!AGGREGATE_TYPE_P (TREE_TYPE (ctor)) && !offset /* VIEW_CONVERT_EXPR is defined only for matching sizes. */ - && operand_equal_p (TYPE_SIZE (type), - TYPE_SIZE (TREE_TYPE (ctor)), 0)) + && !compare_tree_int (TYPE_SIZE (type), size) + && !compare_tree_int (TYPE_SIZE (TREE_TYPE (ctor)), size)) { ret = canonicalize_constructor_val (unshare_expr (ctor), from_decl); ret = fold_unary (VIEW_CONVERT_EXPR, type, ret); diff --git a/gcc/haifa-sched.c b/gcc/haifa-sched.c index c4591bfe35b..28934c5d9e8 100644 --- a/gcc/haifa-sched.c +++ b/gcc/haifa-sched.c @@ -2931,7 +2931,7 @@ advance_one_cycle (void) { advance_state (curr_state); if (sched_verbose >= 6) - fprintf (sched_dump, ";;\tAdvanced a state.\n"); + fprintf (sched_dump, ";;\tAdvance the current state.\n"); } /* Update register pressure after scheduling INSN. */ @@ -5964,6 +5964,7 @@ schedule_block (basic_block *target_bb, state_t init_state) modulo_insns_scheduled = 0; ls.modulo_epilogue = false; + ls.first_cycle_insn_p = true; /* Loop until all the insns in BB are scheduled. */ while ((*current_sched_info->schedule_more_p) ()) @@ -6034,7 +6035,6 @@ schedule_block (basic_block *target_bb, state_t init_state) if (must_backtrack) goto do_backtrack; - ls.first_cycle_insn_p = true; ls.shadows_only_p = false; cycle_issued_insns = 0; ls.can_issue_more = issue_rate; @@ -6321,11 +6321,13 @@ schedule_block (basic_block *target_bb, state_t init_state) break; } } + ls.first_cycle_insn_p = true; } if (ls.modulo_epilogue) success = true; end_schedule: - advance_one_cycle (); + if (!ls.first_cycle_insn_p) + advance_one_cycle (); perform_replacements_new_cycle (); if (modulo_ii > 0) { diff --git a/gcc/ifcvt.c b/gcc/ifcvt.c index e3353a5f26b..70a84d25775 100644 --- a/gcc/ifcvt.c +++ b/gcc/ifcvt.c @@ -294,6 +294,28 @@ block_fallthru (basic_block bb) return (e) ? e->dest : NULL_BLOCK; } + +/* Return true if RTXs A and B can be safely interchanged. */ + +static bool +rtx_interchangeable_p (const_rtx a, const_rtx b) +{ + if (!rtx_equal_p (a, b)) + return false; + + if (GET_CODE (a) != MEM) + return true; + + /* A dead type-unsafe memory reference is legal, but a live type-unsafe memory + reference is not. Interchanging a dead type-unsafe memory reference with + a live type-safe one creates a live type-unsafe memory reference, in other + words, it makes the program illegal. + We check here conservatively whether the two memory references have equal + memory attributes. */ + + return mem_attrs_eq_p (get_mem_attrs (a), get_mem_attrs (b)); +} + /* Go through a bunch of insns, converting them to conditional execution format if possible. Return TRUE if all of the non-note @@ -1014,6 +1036,9 @@ noce_try_move (struct noce_if_info *if_info) || (rtx_equal_p (if_info->a, XEXP (cond, 1)) && rtx_equal_p (if_info->b, XEXP (cond, 0)))) { + if (!rtx_interchangeable_p (if_info->a, if_info->b)) + return FALSE; + y = (code == EQ) ? if_info->a : if_info->b; /* Avoid generating the move if the source is the destination. */ @@ -2483,7 +2508,7 @@ noce_process_if_block (struct noce_if_info *if_info) if (! insn_b || insn_b != last_active_insn (else_bb, FALSE) || (set_b = single_set (insn_b)) == NULL_RTX - || ! rtx_equal_p (x, SET_DEST (set_b))) + || ! rtx_interchangeable_p (x, SET_DEST (set_b))) return FALSE; } else @@ -2496,7 +2521,7 @@ noce_process_if_block (struct noce_if_info *if_info) || BLOCK_FOR_INSN (insn_b) != BLOCK_FOR_INSN (if_info->cond_earliest) || !NONJUMP_INSN_P (insn_b) || (set_b = single_set (insn_b)) == NULL_RTX - || ! rtx_equal_p (x, SET_DEST (set_b)) + || ! rtx_interchangeable_p (x, SET_DEST (set_b)) || ! noce_operand_ok (SET_SRC (set_b)) || reg_overlap_mentioned_p (x, SET_SRC (set_b)) || modified_between_p (SET_SRC (set_b), insn_b, jump) @@ -2562,7 +2587,7 @@ noce_process_if_block (struct noce_if_info *if_info) /* Look and see if A and B are really the same. Avoid creating silly cmove constructs that no one will fix up later. */ - if (rtx_equal_p (a, b)) + if (rtx_interchangeable_p (a, b)) { /* If we have an INSN_B, we don't have to create any new rtl. Just move the instruction that we already have. If we don't have an @@ -4246,6 +4271,9 @@ dead_or_predicable (basic_block test_bb, basic_block merge_bb, old_dest = JUMP_LABEL (jump); if (other_bb != new_dest) { + if (!any_condjump_p (jump)) + goto cancel; + if (JUMP_P (BB_END (dest_edge->src))) new_dest_label = JUMP_LABEL (BB_END (dest_edge->src)); else if (new_dest == EXIT_BLOCK_PTR) diff --git a/gcc/ipa-cp.c b/gcc/ipa-cp.c index bd45575cba6..b7db0cc129d 100644 --- a/gcc/ipa-cp.c +++ b/gcc/ipa-cp.c @@ -2904,6 +2904,11 @@ intersect_aggregates_with_edge (struct cgraph_edge *cs, int index, intersect_with_agg_replacements (cs->caller, src_idx, &inter, 0); } + else + { + inter.release (); + return vNULL; + } } else { @@ -2919,6 +2924,11 @@ intersect_aggregates_with_edge (struct cgraph_edge *cs, int index, else intersect_with_plats (src_plats, &inter, 0); } + else + { + inter.release (); + return vNULL; + } } } else if (jfunc->type == IPA_JF_ANCESTOR @@ -3002,7 +3012,8 @@ find_aggregate_values_for_callers_subset (struct cgraph_node *node, vec<cgraph_edge_p> callers) { struct ipa_node_params *dest_info = IPA_NODE_REF (node); - struct ipa_agg_replacement_value *res = NULL; + struct ipa_agg_replacement_value *res; + struct ipa_agg_replacement_value **tail = &res; struct cgraph_edge *cs; int i, j, count = ipa_get_param_count (dest_info); @@ -3046,14 +3057,15 @@ find_aggregate_values_for_callers_subset (struct cgraph_node *node, v->offset = item->offset; v->value = item->value; v->by_ref = plats->aggs_by_ref; - v->next = res; - res = v; + *tail = v; + tail = &v->next; } next_param: if (inter.exists ()) inter.release (); } + *tail = NULL; return res; } @@ -3062,7 +3074,8 @@ find_aggregate_values_for_callers_subset (struct cgraph_node *node, static struct ipa_agg_replacement_value * known_aggs_to_agg_replacement_list (vec<ipa_agg_jump_function_t> known_aggs) { - struct ipa_agg_replacement_value *res = NULL; + struct ipa_agg_replacement_value *res; + struct ipa_agg_replacement_value **tail = &res; struct ipa_agg_jump_function *aggjf; struct ipa_agg_jf_item *item; int i, j; @@ -3076,9 +3089,10 @@ known_aggs_to_agg_replacement_list (vec<ipa_agg_jump_function_t> known_aggs) v->offset = item->offset; v->value = item->value; v->by_ref = aggjf->by_ref; - v->next = res; - res = v; + *tail = v; + tail = &v->next; } + *tail = NULL; return res; } diff --git a/gcc/regcprop.c b/gcc/regcprop.c index 8bfb64e40cb..5b785116aad 100644 --- a/gcc/regcprop.c +++ b/gcc/regcprop.c @@ -1039,7 +1039,17 @@ copyprop_hardreg_forward_1 (basic_block bb, struct value_data *vd) but instead among CLOBBERs on the CALL_INSN, we could wrongly assume the value in it is still live. */ if (ksvd.ignore_set_reg) - note_stores (PATTERN (insn), kill_clobbered_value, vd); + { + note_stores (PATTERN (insn), kill_clobbered_value, vd); + for (exp = CALL_INSN_FUNCTION_USAGE (insn); + exp; + exp = XEXP (exp, 1)) + { + rtx x = XEXP (exp, 0); + if (GET_CODE (x) == CLOBBER) + kill_value (SET_DEST (x), vd); + } + } } /* Notice stores. */ diff --git a/gcc/stor-layout.c b/gcc/stor-layout.c index 3381fcfd52e..24cad6c889a 100644 --- a/gcc/stor-layout.c +++ b/gcc/stor-layout.c @@ -234,12 +234,7 @@ self_referential_size (tree size) param_type = TREE_TYPE (ref); param_decl = build_decl (input_location, PARM_DECL, param_name, param_type); - if (targetm.calls.promote_prototypes (NULL_TREE) - && INTEGRAL_TYPE_P (param_type) - && TYPE_PRECISION (param_type) < TYPE_PRECISION (integer_type_node)) - DECL_ARG_TYPE (param_decl) = integer_type_node; - else - DECL_ARG_TYPE (param_decl) = param_type; + DECL_ARG_TYPE (param_decl) = param_type; DECL_ARTIFICIAL (param_decl) = 1; TREE_READONLY (param_decl) = 1; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index d55ac28b2dc..65c98a7f1da 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,211 @@ +2014-10-29 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * gcc.target/aarch64/madd_after_asm_1.c: New test. + +2014-10-15 Eric Botcazou <ebotcazou@adacore.com> + + * gnat.dg/opt41.adb: New test. + * gnat.dg/opt41_pkg.ad[sb]: New helper. + +2014-10-12 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + Backport from mainline r215880 + 2014-10-03 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * g++.dg/ext/altivec-2.C: Compile with -Wno-deprecated to avoid + failing with the new warning message. + * gcc.dg/vmx/3c-01a.c: Likewise. + * gcc.dg/vmx/ops-long-1.c: Likewise. + * gcc.dg/vmx/ops.c: Likewise. + * gcc.target/powerpc/altivec-20.c: Likewise. + * gcc.target/powerpc/altivec-6.c: Likewise. + * gcc.target/powerpc/altivec-vec-merge.c: Likewise. + * gcc.target/powerpc/vsx-builtin-8.c: Likewise. + * gcc.target/powerpc/warn-lvsl-lvsr.c: New test. + + Backport from mainline r215882 + 2014-10-03 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * gcc.target/powerpc/lvsl-lvsr.c: New test. + + Backport from mainline r216017 + 2014-10-08 Pat Haugen <pthaugen@us.ibm.com> + + * gcc.dg/vmx/3c-01a.c: Add default options from vmx.exp. + * gcc.dg/vmx/ops.c: Likewise. + * gcc.dg/vmx/ops-long-1.c: Likewise. + +2014-10-10 Jakub Jelinek <jakub@redhat.com> + + PR fortran/59488 + * gfortran.dg/gomp/pr59488-1.f90: New test. + * gfortran.dg/gomp/pr59488-2.f90: New test. + +2014-10-01 Jakub Jelinek <jakub@redhat.com> + + PR debug/63342 + * gcc.dg/pr63342.c: New test. + + PR target/63428 + * gcc.dg/torture/vshuf-4.inc: Move test 122 from EXPTESTS + to test 24 in TESTS. + +2014-10-01 Uros Bizjak <ubizjak@gmail.com> + + Backport from mainline + 2013-11-07 Joseph Myers <joseph@codesourcery.com> + + * lib/target-supports.exp + (check_effective_target_fenv_exceptions): New function. + +2014-09-30 Jakub Jelinek <jakub@redhat.com> + + PR inline-asm/63282 + * gcc.c-torture/compile/pr63282.c: New test. + +2014-09-26 Jakub Jelinek <jakub@redhat.com> + + * g++.dg/compat/struct-layout-1_generate.c: Add -Wno-abi + to default options. + +2014-09-25 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + Backport from mainline r215559 + 2014-09-25 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + PR target/63335 + * gcc.target/powerpc/pr63335.c: New test. + +2014-09-25 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/63341 + * gcc.dg/vect/pr63341-1.c: New test. + * gcc.dg/vect/pr63341-2.c: New test. + +2014-09-18 Joseph Myers <joseph@codesourcery.com> + + * gcc.dg/torture/float128-exact-underflow.c: New test. + +2014-09-17 Jakub Jelinek <jakub@redhat.com> + + PR debug/63284 + * gcc.dg/pr63284.c: New test. + +2014-09-09 Richard Biener <rguenther@suse.de> + + Backport from mainline + 2014-06-11 Richard Biener <rguenther@suse.de> + + PR tree-optimization/61452 + * gcc.dg/torture/pr61452.c: New testcase. + +2014-09-09 Richard Biener <rguenther@suse.de> + + Backport from mainline + 2014-05-05 Richard Biener <rguenther@suse.de> + + PR middle-end/61010 + * gcc.dg/torture/pr61010.c: New testcase. + + 2014-05-28 Richard Biener <rguenther@suse.de> + + PR middle-end/61045 + * gcc.dg/pr61045.c: New testcase. + + 2014-08-11 Richard Biener <rguenther@suse.de> + + PR tree-optimization/62075 + * gcc.dg/vect/pr62075.c: New testcase. + +2014-09-08 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/60196 + PR tree-optimization/63189 + * gcc.dg/vect/pr63189.c: New test. + * gcc.dg/vect/pr60196-1.c: New test. + * gcc.dg/vect/pr60196-2.c: New test. + + Backported from mainline + 2013-09-17 Cong Hou <congh@google.com> + + * gcc.dg/vect/vect-reduc-dot-s16c.c: Add a test case with dot product + on two arrays with short and int types. This should not be recognized + as a dot product pattern. + +2014-09-08 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2014-08-06 Vladimir Makarov <vmakarov@redhat.com> + + PR debug/61923 + * gcc.target/i386/pr61923.c: New test. + +2014-09-06 John David Anglin <danglin@gcc.gnu.org> + + PR testsuite/56194 + * g++.dg/init/const9.C: Skip scan-assembler-not "rodata" on hppa*-*-*. + +2014-09-03 Marek Polacek <polacek@redhat.com> + + Backport from mainline + 2014-09-02 Marek Polacek <polacek@redhat.com> + + PR fortran/62270 + * gfortran.dg/pointer_intent_7.f90: Adjust dg-error. + +2014-09-03 Martin Jambor <mjambor@suse.cz> + + PR ipa/62015 + * g++.dg/ipa/pr62015.C: New test. + +2014-09-03 Martin Jambor <mjambor@suse.cz> + + PR ipa/61986 + * gcc.dg/ipa/pr61986.c: New test. + +2014-08-26 Dominik Vogt <vogt@linux.vnet.ibm.com> + + * gfortran.dg/bessel_7.f90: Bump allowed precision to avoid + failure on s390*-*-linux-gnu. + +2014-08-24 Oleg Endo <olegendo@gcc.gnu.org> + + Backport from mainline + 2014-08-24 Oleg Endo <olegendo@gcc.gnu.org> + + PR target/61996 + * gcc.target/sh/pr61996.c: New. + +2014-08-21 Thomas Koenig <tkoenig@gcc.gnu.org> + + Backport from trunk + PR fortran/62214 + * gfortran.dg/array_assignment_5.f90: New test. + +2014-08-15 Tom de Vries <tom@codesourcery.com> + + Backport from mainline: + 2014-08-14 Tom de Vries <tom@codesourcery.com> + + PR rtl-optimization/62004 + PR rtl-optimization/62030 + * gcc.dg/pr62004.c: New test. + * gcc.dg/pr62030.c: Same. + * gcc.target/mips/pr62030-octeon.c: Same. + +2014-08-13 Felix Yang <fei.yang0953@gmail.com> + + PR tree-optimization/62073 + * gcc.dg/vect/pr62073.c: New test. + +2014-08-13 Thomas Preud'homme <thomas.preudhomme@arm.com> + + Backport from mainline + 2014-08-12 Thomas Preud'homme <thomas.preudhomme@arm.com> + + PR middle-end/62103 + * gcc.c-torture/execute/bitfld-6.c: New test. + 2014-08-10 Thomas Koenig <tkoenig@gcc.gnu.org> Backport from trunk diff --git a/gcc/testsuite/g++.dg/compat/struct-layout-1_generate.c b/gcc/testsuite/g++.dg/compat/struct-layout-1_generate.c index 2cf08946e36..2884c25f337 100644 --- a/gcc/testsuite/g++.dg/compat/struct-layout-1_generate.c +++ b/gcc/testsuite/g++.dg/compat/struct-layout-1_generate.c @@ -1,5 +1,5 @@ /* Structure layout test generator. - Copyright (C) 2004, 2005, 2007, 2008, 2009, 2011, 2012 + Copyright (C) 2004-2014 Free Software Foundation, Inc. Contributed by Jakub Jelinek <jakub@redhat.com>. @@ -44,7 +44,7 @@ along with GCC; see the file COPYING3. If not see #endif const char *dg_options[] = { -"/* { dg-options \"%s-I%s\" } */\n", +"/* { dg-options \"%s-I%s -Wno-abi\" } */\n", "/* { dg-options \"%s-I%s -mno-mmx -Wno-abi\" { target i?86-*-* x86_64-*-* } } */\n", "/* { dg-options \"%s-I%s -fno-common\" { target hppa*-*-hpux* powerpc*-*-darwin* *-*-mingw32* *-*-cygwin* } } */\n", "/* { dg-options \"%s-I%s -mno-mmx -fno-common -Wno-abi\" { target i?86-*-darwin* x86_64-*-darwin* i?86-*-mingw32* x86_64-*-mingw32* i?86-*-cygwin* } } */\n", diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-initlist8.C b/gcc/testsuite/g++.dg/cpp0x/constexpr-initlist8.C new file mode 100644 index 00000000000..3d859a8524d --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-initlist8.C @@ -0,0 +1,7 @@ +// PR c++/63415 +// { dg-do compile { target c++11 } } + +template <typename T> +struct A { + static constexpr int value = int(T{}); +}; diff --git a/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-names1.C b/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-names1.C new file mode 100644 index 00000000000..df2b03705ae --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-names1.C @@ -0,0 +1,9 @@ +// PR c++/56710 +// { dg-options "-std=c++11 -Wall" } + +int main() +{ + int t = 0; + return [&]() -> int {int __t; __t = t; return __t; }(); + return [&t]() -> int {int __t; __t = t; return __t; }(); +} diff --git a/gcc/testsuite/g++.dg/ext/altivec-2.C b/gcc/testsuite/g++.dg/ext/altivec-2.C index eb8a92942bc..e14e6f800f7 100644 --- a/gcc/testsuite/g++.dg/ext/altivec-2.C +++ b/gcc/testsuite/g++.dg/ext/altivec-2.C @@ -1,6 +1,6 @@ /* { dg-do compile { target powerpc*-*-* } } */ /* { dg-require-effective-target powerpc_altivec_ok } */ -/* { dg-options "-maltivec -Wall -Wno-unused-but-set-variable" } */ +/* { dg-options "-maltivec -Wall -Wno-unused-but-set-variable -Wno-deprecated" } */ /* This test checks if AltiVec builtins accept const-qualified arguments. */ diff --git a/gcc/testsuite/g++.dg/ext/stmtexpr16.C b/gcc/testsuite/g++.dg/ext/stmtexpr16.C new file mode 100644 index 00000000000..ddce40c050d --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/stmtexpr16.C @@ -0,0 +1,10 @@ +// PR c++/63455 +// { dg-options "-std=gnu++11" } + +int main() +{ + int x = 0; + + // without '+0', gcc 4.6 gives a different error (no ICE though) + decltype(({ int y = x; y; })+0) v1 = 0; +} diff --git a/gcc/testsuite/g++.dg/init/const9.C b/gcc/testsuite/g++.dg/init/const9.C index ba1dfd4bc46..d733e953332 100644 --- a/gcc/testsuite/g++.dg/init/const9.C +++ b/gcc/testsuite/g++.dg/init/const9.C @@ -1,5 +1,5 @@ // PR c++/55893 -// { dg-final { scan-assembler-not "rodata" } } +// { dg-final { scan-assembler-not "rodata" { target { ! hppa*-*-* } } } } struct foo { diff --git a/gcc/testsuite/g++.dg/ipa/pr62015.C b/gcc/testsuite/g++.dg/ipa/pr62015.C new file mode 100644 index 00000000000..950b46e759b --- /dev/null +++ b/gcc/testsuite/g++.dg/ipa/pr62015.C @@ -0,0 +1,55 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -std=c++11" } */ + + +extern "C" int printf(const char *fmt, ...); +extern "C" void abort(void); + +struct Side { + enum _Value { Left, Right, Invalid }; + + constexpr Side() : _value(Invalid) {} + constexpr Side(_Value value) : _value(value) {} + operator _Value() const { return (_Value)_value; } + + private: + char _value; +}; + +struct A { + void init(); + void adjust(Side side, bool final); + void move(Side side); +}; + +void A::init() +{ + adjust(Side::Invalid, false); +} + +static void __attribute__((noinline)) +check (int v, int final) +{ + if (v != 0) + abort(); +} + + +__attribute__((noinline)) +void A::adjust(Side side, bool final) +{ + check ((int)side, final); +} + +void A::move(Side side) +{ + adjust(side, false); + adjust(side, true); +} + +int main() +{ + A t; + t.move(Side::Left); + return 0; +} diff --git a/gcc/testsuite/g++.dg/rtti/dyncast7.C b/gcc/testsuite/g++.dg/rtti/dyncast7.C new file mode 100644 index 00000000000..deb43976630 --- /dev/null +++ b/gcc/testsuite/g++.dg/rtti/dyncast7.C @@ -0,0 +1,28 @@ +// I think this dynamic_cast has undefined behavior when destroying E::o +// because we're the F period of destruction has started and ap doesn't +// point to the object currently being destroyed--but the reasonable +// options are success or failure, not SEGV. + +// { dg-do run } + +extern "C" void abort(); + +struct A { virtual ~A(); }; +struct B { virtual ~B() { } }; +struct C : B, A { }; +struct E : virtual B { A o; }; +struct F : virtual C, virtual E { }; + +A* ap; +C* cp; + +A::~A() { + C* cp2 = dynamic_cast<C*>(ap); + if (cp2 != cp && cp2 != 0) + abort(); +} + +int main() { + F f; + ap = cp = &f; +} diff --git a/gcc/testsuite/g++.dg/tls/thread_local10.C b/gcc/testsuite/g++.dg/tls/thread_local10.C new file mode 100644 index 00000000000..48c1b861c78 --- /dev/null +++ b/gcc/testsuite/g++.dg/tls/thread_local10.C @@ -0,0 +1,23 @@ +// PR c++/58624 + +// { dg-do run { target c++11 } } +// { dg-add-options tls } +// { dg-require-effective-target tls_runtime } + +int i; + +template <typename> struct A +{ + static thread_local int s; + + A () { i = s; } +}; + +int f() { return 42; } +template <typename T> thread_local int A<T>::s = f(); + +int main () { + A<void> a; + if (i != 42) + __builtin_abort(); +} diff --git a/gcc/testsuite/gcc.c-torture/compile/pr63282.c b/gcc/testsuite/gcc.c-torture/compile/pr63282.c new file mode 100644 index 00000000000..cb23278d50d --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/pr63282.c @@ -0,0 +1,13 @@ +/* PR inline-asm/63282 */ + +void bar (void); + +void +foo (void) +{ + asm volatile goto ("" : : : : a, b); +a: + bar (); +b: + return; +} diff --git a/gcc/testsuite/gcc.c-torture/execute/bitfld-6.c b/gcc/testsuite/gcc.c-torture/execute/bitfld-6.c new file mode 100644 index 00000000000..50927dc1d53 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/execute/bitfld-6.c @@ -0,0 +1,23 @@ +union U +{ + const int a; + unsigned b : 20; +}; + +static union U u = { 0x12345678 }; + +/* Constant folding used to fail to account for endianness when folding a + union. */ + +int +main (void) +{ +#ifdef __BYTE_ORDER__ +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + return u.b - 0x45678; +#else + return u.b - 0x12345; +#endif +#endif + return 0; +} diff --git a/gcc/testsuite/gcc.dg/ipa/pr61986.c b/gcc/testsuite/gcc.dg/ipa/pr61986.c new file mode 100644 index 00000000000..8d2f658b87c --- /dev/null +++ b/gcc/testsuite/gcc.dg/ipa/pr61986.c @@ -0,0 +1,48 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +int a, b, c; + +struct S +{ + int f0; + int f1; +} d; + +static int fn2 (struct S); +void fn3 (struct S); + +void +fn1 (struct S p) +{ + struct S h = { 0, 0 }; + fn3 (p); + fn2 (h); +} + +int +fn2 (struct S p) +{ + struct S j = { 0, 0 }; + fn3 (p); + fn2 (j); + return 0; +} + +void +fn3 (struct S p) +{ + for (; b; a++) + c = p.f0; + fn1 (d); +} + +void +fn4 () +{ + for (;;) + { + struct S f = { 0, 0 }; + fn1 (f); + } +} diff --git a/gcc/testsuite/gcc.dg/pr61045.c b/gcc/testsuite/gcc.dg/pr61045.c new file mode 100644 index 00000000000..1808cdc259f --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr61045.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-fstrict-overflow" } */ + +int main () +{ + int a = 0; + int b = __INT_MAX__; + int t = (a - 2) > (b - 1); + if (t != 0) + __builtin_abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/pr62004.c b/gcc/testsuite/gcc.dg/pr62004.c new file mode 100644 index 00000000000..c994a411b3b --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr62004.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-tree-tail-merge" } */ + +struct node +{ + struct node *next; + struct node *prev; +}; + +struct node node; + +struct head +{ + struct node *first; +}; + +struct head heads[5]; + +int k = 2; + +struct head *head = &heads[2]; + +int +main () +{ + struct node *p; + + node.next = (void*)0; + + node.prev = (void *)head; + + head->first = &node; + + struct node *n = head->first; + + struct head *h = &heads[k]; + + heads[2].first = n->next; + + if ((void*)n->prev == (void *)h) + p = h->first; + else + /* Dead tbaa-unsafe load from ((struct node *)&heads[2])->next. */ + p = n->prev->next; + + return !(p == (void*)0); +} diff --git a/gcc/testsuite/gcc.dg/pr62030.c b/gcc/testsuite/gcc.dg/pr62030.c new file mode 100644 index 00000000000..b8baf934354 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr62030.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +extern void abort (void); + +struct node +{ + struct node *next; + struct node *prev; +}; + +struct node node; + +struct head +{ + struct node *first; +}; + +struct head heads[5]; + +int k = 2; + +struct head *head = &heads[2]; + +static int __attribute__((noinline)) +foo (void) +{ + node.prev = (void *)head; + head->first = &node; + + struct node *n = head->first; + struct head *h = &heads[k]; + struct node *next = n->next; + + if (n->prev == (void *)h) + h->first = next; + else + n->prev->next = next; + + n->next = h->first; + return n->next == &node; +} + +int +main (void) +{ + if (foo ()) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/pr63284.c b/gcc/testsuite/gcc.dg/pr63284.c new file mode 100644 index 00000000000..dc7fc28b87e --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr63284.c @@ -0,0 +1,42 @@ +/* PR debug/63284 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -fcompare-debug" } */ + +int a[10], *b, *d, c, f; +int fn2 (void); +void fn3 (void); +void fn4 (int); + +static int +fn1 (int x) +{ + int e = a[0]; + if (e) + return 1; + if (b) + switch (x) + { + case 1: + if (d) + e = fn2 (); + else + fn3 (); + break; + case 0: + if (d) + { + fn3 (); + if (c) + fn4 (1); + } + else + fn4 (0); + } + return e; +} + +void +fn6 (void) +{ + f = fn1 (0); +} diff --git a/gcc/testsuite/gcc.dg/pr63342.c b/gcc/testsuite/gcc.dg/pr63342.c new file mode 100644 index 00000000000..499d508c13f --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr63342.c @@ -0,0 +1,26 @@ +/* PR debug/63342 */ +/* { dg-do compile } */ +/* { dg-options "-g -O2" } */ +/* { dg-additional-options "-fpic" { target fpic } } */ + +static __thread double u[9], v[9]; + +void +foo (double **p, double **q) +{ + *p = u; + *q = v; +} + +double +bar (double x) +{ + int i; + double s = 0.0; + for (i = 0; i < 9; i++) + { + double a = x + v[i]; + s += u[i] * a * a; + } + return s; +} diff --git a/gcc/testsuite/gcc.dg/torture/float128-exact-underflow.c b/gcc/testsuite/gcc.dg/torture/float128-exact-underflow.c new file mode 100644 index 00000000000..ea11f26e22d --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/float128-exact-underflow.c @@ -0,0 +1,41 @@ +/* Test that exact underflow in __float128 signals the underflow + exception if trapping is enabled, but does not raise the flag + otherwise. */ + +/* { dg-do run { target i?86-*-*gnu* x86_64-*-*gnu* } } */ +/* { dg-options "-D_GNU_SOURCE" } */ +/* { dg-require-effective-target fenv_exceptions } */ + +#include <fenv.h> +#include <setjmp.h> +#include <signal.h> +#include <stdlib.h> + +volatile sig_atomic_t caught_sigfpe; +sigjmp_buf buf; + +static void +handle_sigfpe (int sig) +{ + caught_sigfpe = 1; + siglongjmp (buf, 1); +} + +int +main (void) +{ + volatile __float128 a = 0x1p-16382q, b = 0x1p-2q; + volatile __float128 r; + r = a * b; + if (fetestexcept (FE_UNDERFLOW)) + abort (); + if (r != 0x1p-16384q) + abort (); + feenableexcept (FE_UNDERFLOW); + signal (SIGFPE, handle_sigfpe); + if (sigsetjmp (buf, 1) == 0) + r = a * b; + if (!caught_sigfpe) + abort (); + exit (0); +} diff --git a/gcc/testsuite/gcc.dg/torture/pr61010.c b/gcc/testsuite/gcc.dg/torture/pr61010.c new file mode 100644 index 00000000000..ed5653982cb --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr61010.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ + +int main (void) +{ + int a = 0; + unsigned b = (a * 64 & 192) | 63U; + return 0; +} diff --git a/gcc/testsuite/gcc.dg/torture/pr61452.c b/gcc/testsuite/gcc.dg/torture/pr61452.c new file mode 100644 index 00000000000..a62de30fd84 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr61452.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ + +int a, b; +short c, d; +char e, f; + +int +fn1 (int p1, char p2) +{ + return p1 || p2 ? 0 : p2; +} + +void +fn2 () +{ + for (; a;) + { + int g; + g = c = e; + for (; a;) + b = fn1 (g = d = e, g); + f = g; + } +} + +int +main () +{ + fn2 (); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/torture/vshuf-4.inc b/gcc/testsuite/gcc.dg/torture/vshuf-4.inc index c50fa8e9dd5..d0cb7387ca3 100644 --- a/gcc/testsuite/gcc.dg/torture/vshuf-4.inc +++ b/gcc/testsuite/gcc.dg/torture/vshuf-4.inc @@ -23,7 +23,8 @@ T (19, 3, 2, 1, 0) \ T (20, 0, 4, 1, 5) \ T (21, 2, 6, 3, 7) \ T (22, 1, 2, 3, 0) \ -T (23, 2, 1, 0, 3) +T (23, 2, 1, 0, 3) \ +T (24, 2, 5, 6, 3) #define EXPTESTS \ T (116, 1, 2, 4, 3) \ T (117, 7, 3, 3, 0) \ @@ -31,7 +32,6 @@ T (118, 5, 3, 2, 7) \ T (119, 0, 3, 5, 6) \ T (120, 0, 0, 1, 5) \ T (121, 4, 6, 2, 1) \ -T (122, 2, 5, 6, 3) \ T (123, 4, 6, 3, 2) \ T (124, 4, 7, 5, 6) \ T (125, 0, 4, 2, 4) \ diff --git a/gcc/testsuite/gcc.dg/vect/pr60196-1.c b/gcc/testsuite/gcc.dg/vect/pr60196-1.c new file mode 100644 index 00000000000..10ed4afebdf --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr60196-1.c @@ -0,0 +1,34 @@ +/* PR tree-optimization/63189 */ +/* { dg-additional-options "-fwrapv" } */ +/* { dg-do run } */ + +#include "tree-vect.h" + +__attribute__((noinline, noclone)) static int +bar (const short *a, int len) +{ + int x; + int x1 = 0; + + for (x = 0; x < len; x++) + x1 += x * a[x]; + return x1; +} + +__attribute__((noinline, noclone)) void +foo (void) +{ + short stuff[9] = {1, 1, 1, 1, 1, 1, 1, 1, 1 }; + if (bar (stuff, 9) != 36) + abort (); +} + +int +main () +{ + check_vect (); + foo (); + return 0; +} + +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr60196-2.c b/gcc/testsuite/gcc.dg/vect/pr60196-2.c new file mode 100644 index 00000000000..b2059c20cd5 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr60196-2.c @@ -0,0 +1,33 @@ +/* PR tree-optimization/63189 */ +/* { dg-do run } */ + +#include "tree-vect.h" + +static const short a[8] = {1, 1, 1, 1, 1, 1, 1, 1 }; +static const unsigned char b[8] = {0, 0, 0, 0, 0, 0, 0, 0 }; + +__attribute__((noinline, noclone)) static int +bar (void) +{ + int sum = 0, i; + for (i = 0; i < 8; ++i) + sum += a[i] * b[i]; + return sum; +} + +__attribute__((noinline, noclone)) void +foo (void) +{ + if (bar () != 0) + abort (); +} + +int +main () +{ + check_vect (); + foo (); + return 0; +} + +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr62073.c b/gcc/testsuite/gcc.dg/vect/pr62073.c new file mode 100644 index 00000000000..15f2ad66b0c --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr62073.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O1" } */ + +struct S0 +{ + int f7; +}; +struct S0 g_50; +int g_70; +int g_76; + +int foo (long long p_56, int * p_57) +{ + int *l_77; + int l_101; + + for (; g_70;) + { + int **l_78 = &l_77; + if (g_50.f7) + continue; + *l_78 = 0; + } + for (g_76 = 1; g_76 >= 0; g_76--) + { + int *l_90; + for (l_101 = 4; l_101 >= 0; l_101--) + if (l_101) + *l_90 = 0; + else + { + int **l_113 = &l_77; + *l_113 = p_57; + } + } + + return *l_77; +} + +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr62075.c b/gcc/testsuite/gcc.dg/vect/pr62075.c new file mode 100644 index 00000000000..798490e8752 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr62075.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ + +int a[16][2]; +struct A +{ + int b[16][2]; + int c[16][1]; +}; + +void +foo (struct A *x) +{ + int i; + for (i = 0; i < 16; ++i) + { + x->b[i][0] = a[i][0]; + x->c[i][0] = 0 != a[i][0]; + x->b[i][1] = a[i][1]; + } +} + +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr63189.c b/gcc/testsuite/gcc.dg/vect/pr63189.c new file mode 100644 index 00000000000..da6fba4b1b3 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr63189.c @@ -0,0 +1,26 @@ +/* PR tree-optimization/63189 */ +/* { dg-do run } */ + +#include "tree-vect.h" + +short int d[16] = { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 }; + +__attribute__((noinline, noclone)) void +foo (void) +{ + int j, s = 0; + for (j = 0; j < 8; j++) + s += d[j] * j; + if (s != 7) + abort (); +} + +int +main () +{ + check_vect (); + foo (); + return 0; +} + +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr63341-1.c b/gcc/testsuite/gcc.dg/vect/pr63341-1.c new file mode 100644 index 00000000000..4aece7bbd24 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr63341-1.c @@ -0,0 +1,32 @@ +/* PR tree-optimization/63341 */ +/* { dg-do run } */ + +#include "tree-vect.h" + +typedef union U { unsigned short s; unsigned char c; } __attribute__((packed)) U; +struct S { char e __attribute__((aligned (64))); U s[32]; }; +struct S t = {0, {{1}, {2}, {3}, {4}, {5}, {6}, {7}, {8}, + {9}, {10}, {11}, {12}, {13}, {14}, {15}, {16}, + {17}, {18}, {19}, {20}, {21}, {22}, {23}, {24}, + {25}, {26}, {27}, {28}, {29}, {30}, {31}, {32}}}; +unsigned short d[32] = { 1 }; + +__attribute__((noinline, noclone)) void +foo () +{ + int i; + for (i = 0; i < 32; i++) + d[i] = t.s[i].s; + if (__builtin_memcmp (d, t.s, sizeof d)) + abort (); +} + +int +main () +{ + check_vect (); + foo (); + return 0; +} + +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr63341-2.c b/gcc/testsuite/gcc.dg/vect/pr63341-2.c new file mode 100644 index 00000000000..4e7d2bb1f5a --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr63341-2.c @@ -0,0 +1,35 @@ +/* PR tree-optimization/63341 */ +/* { dg-do run } */ + +#include "tree-vect.h" + +typedef union U { unsigned short s; unsigned char c; } __attribute__((packed)) U; +struct S { char e __attribute__((aligned (64))); U s[32]; }; +struct S t = {0, {{0x5010}, {0x5111}, {0x5212}, {0x5313}, {0x5414}, {0x5515}, {0x5616}, {0x5717}, + {0x5818}, {0x5919}, {0x5a1a}, {0x5b1b}, {0x5c1c}, {0x5d1d}, {0x5e1e}, {0x5f1f}, + {0x6020}, {0x6121}, {0x6222}, {0x6323}, {0x6424}, {0x6525}, {0x6626}, {0x6727}, + {0x6828}, {0x6929}, {0x6a2a}, {0x6b2b}, {0x6c2c}, {0x6d2d}, {0x6e2e}, {0x6f2f}}}; +unsigned short d[32] = { 1 }; + +__attribute__((noinline, noclone)) void +foo () +{ + int i; + for (i = 0; i < 32; i++) + d[i] = t.s[i].s + 4; + for (i = 0; i < 32; i++) + if (d[i] != t.s[i].s + 4) + abort (); + else + asm volatile ("" : : : "memory"); +} + +int +main () +{ + check_vect (); + foo (); + return 0; +} + +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vmx/3c-01a.c b/gcc/testsuite/gcc.dg/vmx/3c-01a.c index 2499ca66598..56f3c8708b8 100644 --- a/gcc/testsuite/gcc.dg/vmx/3c-01a.c +++ b/gcc/testsuite/gcc.dg/vmx/3c-01a.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mno-vsx -Wno-deprecated" } */ #include <altivec.h> typedef const volatile unsigned int _1; typedef const unsigned int _2; diff --git a/gcc/testsuite/gcc.dg/vmx/ops-long-1.c b/gcc/testsuite/gcc.dg/vmx/ops-long-1.c index 5471706790a..bceb4fc8dae 100644 --- a/gcc/testsuite/gcc.dg/vmx/ops-long-1.c +++ b/gcc/testsuite/gcc.dg/vmx/ops-long-1.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mno-vsx -Wno-deprecated" } */ /* Checks from the original ops.c that pass pointers to long or unsigned long for operations that support that in released versions diff --git a/gcc/testsuite/gcc.dg/vmx/ops.c b/gcc/testsuite/gcc.dg/vmx/ops.c index b39ad1d6569..21801ca237a 100644 --- a/gcc/testsuite/gcc.dg/vmx/ops.c +++ b/gcc/testsuite/gcc.dg/vmx/ops.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mno-vsx -Wno-deprecated" } */ #include <altivec.h> #include <stdlib.h> extern char * *var_char_ptr; diff --git a/gcc/testsuite/gcc.target/aarch64/madd_after_asm_1.c b/gcc/testsuite/gcc.target/aarch64/madd_after_asm_1.c new file mode 100644 index 00000000000..523941d4792 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/madd_after_asm_1.c @@ -0,0 +1,14 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -mfix-cortex-a53-835769" } */ + +int +test (int a, double b, int c, int d, int e) +{ + double result; + __asm__ __volatile ("// %0, %1" + : "=w" (result) + : "0" (b) + : /* No clobbers */ + ); + return c * d + e; +} diff --git a/gcc/testsuite/gcc.target/i386/pr61923.c b/gcc/testsuite/gcc.target/i386/pr61923.c new file mode 100644 index 00000000000..458158cc6dc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr61923.c @@ -0,0 +1,36 @@ +/* PR debug/61923 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -fcompare-debug" } */ + +typedef struct +{ + struct + { + struct + { + char head; + } tickets; + }; +} arch_spinlock_t; +struct ext4_map_blocks +{ + int m_lblk; + int m_len; + int m_flags; +}; +int ext4_da_map_blocks_ei_0; +void fn1 (int p1, struct ext4_map_blocks *p2) +{ + int ret; + if (p2->m_flags) + { + ext4_da_map_blocks_ei_0++; + arch_spinlock_t *lock; + switch (sizeof *&lock->tickets.head) + case 1: + asm("" : "+m"(*&lock->tickets.head) : ""(0)); + __asm__(""); + ret = 0; + } + fn2 (p2->m_lblk, p2->m_len); +} diff --git a/gcc/testsuite/gcc.target/mips/pr62030-octeon.c b/gcc/testsuite/gcc.target/mips/pr62030-octeon.c new file mode 100644 index 00000000000..5e3d3b3b635 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/pr62030-octeon.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-options "-march=octeon" } */ + +extern void abort (void); + +struct node +{ + struct node *next; + struct node *prev; +}; + +struct node node; + +struct head +{ + struct node *first; +}; + +struct head heads[5]; + +int k = 2; + +struct head *head = &heads[2]; + +static int __attribute__((noinline)) +foo (void) +{ + node.prev = (void *)head; + head->first = &node; + + struct node *n = head->first; + struct head *h = &heads[k]; + struct node *next = n->next; + + if (n->prev == (void *)h) + h->first = next; + else + n->prev->next = next; + + n->next = h->first; + return n->next == &node; +} + +int +main (void) +{ + if (foo ()) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-20.c b/gcc/testsuite/gcc.target/powerpc/altivec-20.c index b2c29a979d9..1af8ed7dc54 100644 --- a/gcc/testsuite/gcc.target/powerpc/altivec-20.c +++ b/gcc/testsuite/gcc.target/powerpc/altivec-20.c @@ -1,5 +1,5 @@ /* { dg-do compile { target powerpc_altivec_ok } } */ -/* { dg-options "-maltivec -mcpu=G5 -O2" } */ +/* { dg-options "-maltivec -mcpu=G5 -O2 -Wno-deprecated" } */ #include <altivec.h> diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-6.c b/gcc/testsuite/gcc.target/powerpc/altivec-6.c index 51d411688fb..29856fd0794 100644 --- a/gcc/testsuite/gcc.target/powerpc/altivec-6.c +++ b/gcc/testsuite/gcc.target/powerpc/altivec-6.c @@ -1,6 +1,6 @@ /* { dg-do compile { target powerpc*-*-* } } */ /* { dg-require-effective-target powerpc_altivec_ok } */ -/* { dg-options "-maltivec -O0 -Wall" } */ +/* { dg-options "-maltivec -O0 -Wall -Wno-deprecated" } */ #include <altivec.h> diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c b/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c index 3689f97490c..b1ed8b86491 100644 --- a/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c +++ b/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c @@ -1,7 +1,7 @@ /* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */ /* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */ /* { dg-require-effective-target powerpc_altivec_ok } */ -/* { dg-options "-maltivec -O2" } */ +/* { dg-options "-maltivec -O2 -Wno-deprecated" } */ #include <altivec.h> diff --git a/gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c b/gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c new file mode 100644 index 00000000000..71dd0a24ae1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c @@ -0,0 +1,21 @@ +/* Test expected code generation for lvsl and lvsr on little endian. + Note that lvsl and lvsr are each produced once, but the filename + causes them to appear twice in the file. */ + +/* { dg-do compile { target { powerpc64le-*-* } } } */ +/* { dg-options "-O0 -Wno-deprecated" } */ +/* { dg-final { scan-assembler-times "lvsl" 2 } } */ +/* { dg-final { scan-assembler-times "lvsr" 2 } } */ +/* { dg-final { scan-assembler-times "lxvd2x" 2 } } */ +/* { dg-final { scan-assembler-times "vperm" 2 } } */ + + +#include <altivec.h> + +float f[20]; + +void foo () +{ + vector unsigned char a = vec_lvsl (4, f); + vector unsigned char b = vec_lvsr (8, f); +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr63335.c b/gcc/testsuite/gcc.target/powerpc/pr63335.c new file mode 100644 index 00000000000..931a8b6e99e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr63335.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { powerpc64*-*-* } } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx" } */ + +#include <altivec.h> + +void abort (void); + +vector double vec = (vector double) {99.0, 99.0}; + +int main() { + + int actual = vec_all_nge(vec, vec); + if ( actual != 0) + abort(); + + actual = vec_all_nle(vec, vec); + if ( actual != 0) + abort(); + + actual = vec_any_nge(vec, vec); + if ( actual != 0) + abort(); + + actual = vec_any_nle(vec, vec); + if ( actual != 0) + abort(); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c index 836b3851cad..934cdad250c 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ -/* { dg-options "-O3 -mcpu=power7" } */ +/* { dg-options "-O3 -mcpu=power7 -Wno-deprecated" } */ /* Test the various load/store varients. */ diff --git a/gcc/testsuite/gcc.target/powerpc/warn-lvsl-lvsr.c b/gcc/testsuite/gcc.target/powerpc/warn-lvsl-lvsr.c new file mode 100644 index 00000000000..bf889aaa22b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/warn-lvsl-lvsr.c @@ -0,0 +1,14 @@ +/* Test for deprecation messages on use of lvsl and lvsr for little endian. */ + +/* { dg-do compile { target { powerpc64le-*-* } } } */ +/* { dg-options "-O0 -Wdeprecated" } */ + +#include <altivec.h> + +float f[20]; + +void foo () +{ + vector unsigned char a = vec_lvsl (4, f); /* { dg-warning "vec_lvsl is deprecated for little endian; use assignment for unaligned loads and stores" } */ + vector unsigned char b = vec_lvsr (8, f); /* { dg-warning "vec_lvsr is deprecated for little endian; use assignment for unaligned loads and stores" } */ +} diff --git a/gcc/testsuite/gcc.target/sh/pr61996.c b/gcc/testsuite/gcc.target/sh/pr61996.c new file mode 100644 index 00000000000..51a5f929d55 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/pr61996.c @@ -0,0 +1,12 @@ +/* Check that the option -musermode has no effect on targets that do not + support user/privileged mode and that it does not interfere with option + -matomic-model=soft-imask. */ +/* { dg-do compile } */ +/* { dg-options "-matomic-model=soft-imask" } */ +/* { dg-skip-if "" { "sh*-*-*" } { "*"} { "-m1*" "-m2*" } } */ + +int +test (void) +{ + return 0; +} diff --git a/gcc/testsuite/gfortran.dg/array_assignment_5.f90 b/gcc/testsuite/gfortran.dg/array_assignment_5.f90 new file mode 100644 index 00000000000..6d585270cea --- /dev/null +++ b/gcc/testsuite/gfortran.dg/array_assignment_5.f90 @@ -0,0 +1,16 @@ +! { dg-do run } +! { dg-options "-ffrontend-optimize" } +! PR 62214 - this used to give the wrong result. +! Original test case by Oliver Fuhrer +PROGRAM test + IMPLICIT NONE + CHARACTER(LEN=20) :: fullNames(2) + CHARACTER(LEN=255) :: pathName + CHARACTER(LEN=5) :: fileNames(2) + + pathName = "/dir1/dir2/" + fileNames = (/ "file1", "file2" /) + fullNames = SPREAD(TRIM(pathName),1,2) // fileNames + if (fullNames(1) /= '/dir1/dir2/file1' .or. & + & fullnames(2) /= '/dir1/dir2/file2') call abort +END PROGRAM test diff --git a/gcc/testsuite/gfortran.dg/bessel_7.f90 b/gcc/testsuite/gfortran.dg/bessel_7.f90 index 7e63ed1e859..c6b5f7407f7 100644 --- a/gcc/testsuite/gfortran.dg/bessel_7.f90 +++ b/gcc/testsuite/gfortran.dg/bessel_7.f90 @@ -16,7 +16,7 @@ implicit none real,parameter :: values(*) = [0.0, 0.5, 1.0, 0.9, 1.8,2.0,3.0,4.0,4.25,8.0,34.53, 475.78] real,parameter :: myeps(size(values)) = epsilon(0.0) & - * [2, 3, 4, 5, 8, 2, 12, 6, 7, 6, 36, 168 ] + * [2, 3, 4, 5, 8, 2, 13, 6, 7, 6, 36, 168 ] ! The following is sufficient for me - the values above are a bit ! more tolerant ! * [0, 0, 0, 3, 3, 0, 9, 0, 2, 1, 22, 130 ] diff --git a/gcc/testsuite/gfortran.dg/gomp/pr59488-1.f90 b/gcc/testsuite/gfortran.dg/gomp/pr59488-1.f90 new file mode 100644 index 00000000000..9db17dd2769 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/gomp/pr59488-1.f90 @@ -0,0 +1,13 @@ +! PR fortran/59488 +! { dg-do compile } +! { dg-options "-fopenmp" } + + implicit none + integer, parameter :: p(2) = (/ 11, 12 /) + integer :: r + + !$omp parallel do default(none) + do r = 1, 2 + print *, p(r) + end do +end diff --git a/gcc/testsuite/gfortran.dg/gomp/pr59488-2.f90 b/gcc/testsuite/gfortran.dg/gomp/pr59488-2.f90 new file mode 100644 index 00000000000..38f157b81ad --- /dev/null +++ b/gcc/testsuite/gfortran.dg/gomp/pr59488-2.f90 @@ -0,0 +1,16 @@ +! PR fortran/59488 +! { dg-do compile } +! { dg-options "-fopenmp" } + + implicit none + type t + integer :: s1, s2, s3 + end type + integer :: r + type(t), parameter :: u = t(1, 2, 3) + + !$omp parallel do default(none) + do r = 1, 2 + print *, u + end do +end diff --git a/gcc/testsuite/gfortran.dg/pointer_intent_7.f90 b/gcc/testsuite/gfortran.dg/pointer_intent_7.f90 index c09eb2b5ffa..5387ace8c19 100644 --- a/gcc/testsuite/gfortran.dg/pointer_intent_7.f90 +++ b/gcc/testsuite/gfortran.dg/pointer_intent_7.f90 @@ -23,7 +23,7 @@ contains call bar2 (c) call bar3 (c) call bar2p (b) ! { dg-error "INTENT\\(IN\\) in pointer association context \\(actual argument to INTENT = OUT/INOUT" } - call bar3p (b) ! { dg-error "INTENT\\(IN\\) in pointer association context \\(actual argument to INTENT = OUT/INOUT" } + call bar3p (b) ! { dg-error "Actual argument to .n. at \\(1\\) must be polymorphic" } call bar2p (c) ! { dg-error "INTENT\\(IN\\) in pointer association context \\(actual argument to INTENT = OUT/INOUT" } call bar3p (c) ! { dg-error "INTENT\\(IN\\) in pointer association context \\(actual argument to INTENT = OUT/INOUT" } end subroutine diff --git a/gcc/testsuite/gnat.dg/opt41.adb b/gcc/testsuite/gnat.dg/opt41.adb new file mode 100644 index 00000000000..21660431c50 --- /dev/null +++ b/gcc/testsuite/gnat.dg/opt41.adb @@ -0,0 +1,15 @@ +-- { dg-do run } +-- { dg-options "-Os" } + +with Ada.Strings.Unbounded; use Ada.Strings.Unbounded; +with Opt41_Pkg; use Opt41_Pkg; + +procedure Opt41 is + R : Rec := (Five, To_Unbounded_String ("CONFIG")); + SP : String_Access := new String'(To_String (Rec_Write (R))); + RP : Rec_Ptr := new Rec'(Rec_Read (SP)); +begin + if RP.D /= R.D then + raise Program_Error; + end if; +end; diff --git a/gcc/testsuite/gnat.dg/opt41_pkg.adb b/gcc/testsuite/gnat.dg/opt41_pkg.adb new file mode 100644 index 00000000000..c43c1bfdf04 --- /dev/null +++ b/gcc/testsuite/gnat.dg/opt41_pkg.adb @@ -0,0 +1,53 @@ +with Ada.Streams; use Ada.Streams;
+
+package body Opt41_Pkg is
+
+ type Wstream is new Root_Stream_Type with record
+ S : Unbounded_String;
+ end record;
+
+ procedure Read (Stream : in out Wstream;
+ Item : out Stream_Element_Array;
+ Last : out Stream_Element_Offset) is null;
+
+ procedure Write (Stream : in out Wstream; Item : Stream_Element_Array) is
+ begin
+ for J in Item'Range loop
+ Append (Stream.S, Character'Val (Item (J)));
+ end loop;
+ end Write;
+
+ function Rec_Write (R : Rec) return Unbounded_String is
+ S : aliased Wstream;
+ begin
+ Rec'Output (S'Access, R);
+ return S.S;
+ end Rec_Write;
+
+ type Rstream is new Root_Stream_Type with record
+ S : String_Access;
+ Idx : Integer := 1;
+ end record;
+
+ procedure Write (Stream : in out Rstream; Item : Stream_Element_Array) is null;
+
+ procedure Read (Stream : in out Rstream;
+ Item : out Stream_Element_Array;
+ Last : out Stream_Element_Offset) is
+ begin
+ Last := Stream_Element_Offset'Min
+ (Item'Last, Item'First + Stream_Element_Offset (Stream.S'Last - Stream.Idx));
+ for I in Item'First .. Last loop
+ Item (I) := Stream_Element (Character'Pos (Stream.S (Stream.Idx)));
+ Stream.Idx := Stream.Idx + 1;
+ end loop;
+ end Read;
+
+ function Rec_Read (Str : String_Access) return Rec is
+ S : aliased Rstream;
+ begin
+ S.S := Str;
+ return Rec'Input (S'Access);
+ end Rec_Read;
+
+end Opt41_Pkg;
diff --git a/gcc/testsuite/gnat.dg/opt41_pkg.ads b/gcc/testsuite/gnat.dg/opt41_pkg.ads new file mode 100644 index 00000000000..e73bc931927 --- /dev/null +++ b/gcc/testsuite/gnat.dg/opt41_pkg.ads @@ -0,0 +1,28 @@ +with Ada.Strings.Unbounded; use Ada.Strings.Unbounded;
+
+package Opt41_Pkg is
+
+ type Enum is (One, Two, Three, Four, Five, Six);
+
+ type Rec (D : Enum) is record
+ case D is
+ when One =>
+ I : Integer;
+ when Two | Five | Six =>
+ S : Unbounded_String;
+ case D is
+ when Two => B : Boolean;
+ when others => null;
+ end case;
+ when others =>
+ null;
+ end case;
+ end record;
+
+ type Rec_Ptr is access all Rec;
+
+ function Rec_Write (R : Rec) return Unbounded_String;
+
+ function Rec_Read (Str : String_Access) return Rec;
+
+end Opt41_Pkg;
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index befd224291c..f8e633744b8 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -5526,3 +5526,40 @@ proc check_effective_target_aarch64_large { } { return 0 } } + +# Return 1 if <fenv.h> is available with all the standard IEEE +# exceptions and floating-point exceptions are raised by arithmetic +# operations. (If the target requires special options for "inexact" +# exceptions, those need to be specified in the testcases.) + +proc check_effective_target_fenv_exceptions {} { + return [check_runtime fenv_exceptions { + #include <fenv.h> + #include <stdlib.h> + #ifndef FE_DIVBYZERO + # error Missing FE_DIVBYZERO + #endif + #ifndef FE_INEXACT + # error Missing FE_INEXACT + #endif + #ifndef FE_INVALID + # error Missing FE_INVALID + #endif + #ifndef FE_OVERFLOW + # error Missing FE_OVERFLOW + #endif + #ifndef FE_UNDERFLOW + # error Missing FE_UNDERFLOW + #endif + volatile float a = 0.0f, r; + int + main (void) + { + r = a / a; + if (fetestexcept (FE_INVALID)) + exit (0); + else + abort (); + } + } "-std=gnu99"] +} diff --git a/gcc/tree-cfgcleanup.c b/gcc/tree-cfgcleanup.c index aeb5e4e8cfb..cd3e6e39672 100644 --- a/gcc/tree-cfgcleanup.c +++ b/gcc/tree-cfgcleanup.c @@ -498,7 +498,20 @@ fixup_noreturn_call (gimple stmt) /* First split basic block if stmt is not last. */ if (stmt != gsi_stmt (gsi_last_bb (bb))) - split_block (bb, stmt); + { + if (stmt == gsi_stmt (gsi_last_nondebug_bb (bb))) + { + /* Don't split if there are only debug stmts + after stmt, that can result in -fcompare-debug + failures. Remove the debug stmts instead, + they should be all unreachable anyway. */ + gimple_stmt_iterator gsi = gsi_for_stmt (stmt); + for (gsi_next (&gsi); !gsi_end_p (gsi); ) + gsi_remove (&gsi, true); + } + else + split_block (bb, stmt); + } changed |= remove_fallthru_edge (bb->succs); diff --git a/gcc/tree-sra.c b/gcc/tree-sra.c index 43b2ce683cb..644861d7f21 100644 --- a/gcc/tree-sra.c +++ b/gcc/tree-sra.c @@ -1030,6 +1030,11 @@ build_access_from_expr_1 (tree expr, gimple stmt, bool write) "component."); return NULL; } + if (TREE_THIS_VOLATILE (expr)) + { + disqualify_base_of_expr (expr, "part of a volatile reference."); + return NULL; + } switch (TREE_CODE (expr)) { diff --git a/gcc/tree-ssa-sccvn.c b/gcc/tree-ssa-sccvn.c index 5dce65afe85..b2afbcdfea0 100644 --- a/gcc/tree-ssa-sccvn.c +++ b/gcc/tree-ssa-sccvn.c @@ -3015,33 +3015,12 @@ visit_phi (gimple phi) /* If all value numbered to the same value, the phi node has that value. */ if (allsame) - { - if (is_gimple_min_invariant (sameval)) - { - VN_INFO (PHI_RESULT (phi))->has_constants = true; - VN_INFO (PHI_RESULT (phi))->expr = sameval; - } - else - { - VN_INFO (PHI_RESULT (phi))->has_constants = false; - VN_INFO (PHI_RESULT (phi))->expr = sameval; - } - - if (TREE_CODE (sameval) == SSA_NAME) - return visit_copy (PHI_RESULT (phi), sameval); - - return set_ssa_val_to (PHI_RESULT (phi), sameval); - } + return set_ssa_val_to (PHI_RESULT (phi), sameval); /* Otherwise, see if it is equivalent to a phi node in this block. */ result = vn_phi_lookup (phi); if (result) - { - if (TREE_CODE (result) == SSA_NAME) - changed = visit_copy (PHI_RESULT (phi), result); - else - changed = set_ssa_val_to (PHI_RESULT (phi), result); - } + changed = set_ssa_val_to (PHI_RESULT (phi), result); else { vn_phi_insert (phi, PHI_RESULT (phi)); @@ -3142,24 +3121,18 @@ simplify_binary_expression (gimple stmt) catch those with constants. The goal here is to simultaneously combine constants between expressions, but avoid infinite expansion of expressions during simplification. */ - if (TREE_CODE (op0) == SSA_NAME) - { - if (VN_INFO (op0)->has_constants + op0 = vn_valueize (op0); + if (TREE_CODE (op0) == SSA_NAME + && (VN_INFO (op0)->has_constants || TREE_CODE_CLASS (code) == tcc_comparison - || code == COMPLEX_EXPR) - op0 = valueize_expr (vn_get_expr_for (op0)); - else - op0 = vn_valueize (op0); - } + || code == COMPLEX_EXPR)) + op0 = valueize_expr (vn_get_expr_for (op0)); - if (TREE_CODE (op1) == SSA_NAME) - { - if (VN_INFO (op1)->has_constants - || code == COMPLEX_EXPR) - op1 = valueize_expr (vn_get_expr_for (op1)); - else - op1 = vn_valueize (op1); - } + op1 = vn_valueize (op1); + if (TREE_CODE (op1) == SSA_NAME + && (VN_INFO (op1)->has_constants + || code == COMPLEX_EXPR)) + op1 = valueize_expr (vn_get_expr_for (op1)); /* Pointer plus constant can be represented as invariant address. Do so to allow further propatation, see also tree forwprop. */ @@ -3217,27 +3190,31 @@ simplify_unary_expression (gimple stmt) return NULL_TREE; orig_op0 = op0; - if (VN_INFO (op0)->has_constants) - op0 = valueize_expr (vn_get_expr_for (op0)); - else if (CONVERT_EXPR_CODE_P (code) - || code == REALPART_EXPR - || code == IMAGPART_EXPR - || code == VIEW_CONVERT_EXPR - || code == BIT_FIELD_REF) + op0 = vn_valueize (op0); + if (TREE_CODE (op0) == SSA_NAME) { - /* We want to do tree-combining on conversion-like expressions. - Make sure we feed only SSA_NAMEs or constants to fold though. */ - tree tem = valueize_expr (vn_get_expr_for (op0)); - if (UNARY_CLASS_P (tem) - || BINARY_CLASS_P (tem) - || TREE_CODE (tem) == VIEW_CONVERT_EXPR - || TREE_CODE (tem) == SSA_NAME - || TREE_CODE (tem) == CONSTRUCTOR - || is_gimple_min_invariant (tem)) - op0 = tem; + if (VN_INFO (op0)->has_constants) + op0 = valueize_expr (vn_get_expr_for (op0)); + else if (CONVERT_EXPR_CODE_P (code) + || code == REALPART_EXPR + || code == IMAGPART_EXPR + || code == VIEW_CONVERT_EXPR + || code == BIT_FIELD_REF) + { + /* We want to do tree-combining on conversion-like expressions. + Make sure we feed only SSA_NAMEs or constants to fold though. */ + tree tem = valueize_expr (vn_get_expr_for (op0)); + if (UNARY_CLASS_P (tem) + || BINARY_CLASS_P (tem) + || TREE_CODE (tem) == VIEW_CONVERT_EXPR + || TREE_CODE (tem) == SSA_NAME + || TREE_CODE (tem) == CONSTRUCTOR + || is_gimple_min_invariant (tem)) + op0 = tem; + } } - /* Avoid folding if nothing changed, but remember the expression. */ + /* Avoid folding if nothing changed. */ if (op0 == orig_op0) return NULL_TREE; diff --git a/gcc/tree-vect-data-refs.c b/gcc/tree-vect-data-refs.c index 2fe2abbb47f..cfca2adf4e2 100644 --- a/gcc/tree-vect-data-refs.c +++ b/gcc/tree-vect-data-refs.c @@ -3575,6 +3575,9 @@ vect_get_new_vect_var (tree type, enum vect_var_kind var_kind, const char *name) is as follows: if LOOP=i_loop: &in (relative to i_loop) if LOOP=j_loop: &in+i*2B (relative to j_loop) + BYTE_OFFSET: Optional, defaulted to NULL. If supplied, it is added to the + initial address. Unlike OFFSET, which is number of elements to + be added, BYTE_OFFSET is measured in bytes. Output: 1. Return an SSA_NAME whose value is the address of the memory location of @@ -3588,7 +3591,8 @@ tree vect_create_addr_base_for_vector_ref (gimple stmt, gimple_seq *new_stmt_list, tree offset, - struct loop *loop) + struct loop *loop, + tree byte_offset) { stmt_vec_info stmt_info = vinfo_for_stmt (stmt); struct data_reference *dr = STMT_VINFO_DATA_REF (stmt_info); @@ -3650,6 +3654,16 @@ vect_create_addr_base_for_vector_ref (gimple stmt, base_offset = force_gimple_operand (base_offset, &seq, false, tmp); gimple_seq_add_seq (new_stmt_list, seq); } + if (byte_offset) + { + tree tmp = create_tmp_var (sizetype, "offset"); + + byte_offset = fold_convert (sizetype, byte_offset); + base_offset = fold_build2 (PLUS_EXPR, sizetype, + base_offset, byte_offset); + base_offset = force_gimple_operand (base_offset, &seq, false, tmp); + gimple_seq_add_seq (new_stmt_list, seq); + } /* base + base_offset */ if (loop_vinfo) @@ -3714,6 +3728,10 @@ vect_create_addr_base_for_vector_ref (gimple stmt, 5. BSI: location where the new stmts are to be placed if there is no loop 6. ONLY_INIT: indicate if ap is to be updated in the loop, or remain pointing to the initial address. + 7. BYTE_OFFSET (optional, defaults to NULL): a byte offset to be added + to the initial address accessed by the data-ref in STMT. This is + similar to OFFSET, but OFFSET is counted in elements, while BYTE_OFFSET + in bytes. Output: 1. Declare a new ptr to vector_type, and have it point to the base of the @@ -3727,6 +3745,8 @@ vect_create_addr_base_for_vector_ref (gimple stmt, initial_address = &a[init]; if OFFSET is supplied: initial_address = &a[init + OFFSET]; + if BYTE_OFFSET is supplied: + initial_address = &a[init] + BYTE_OFFSET; Return the initial_address in INITIAL_ADDRESS. @@ -3744,7 +3764,7 @@ tree vect_create_data_ref_ptr (gimple stmt, tree aggr_type, struct loop *at_loop, tree offset, tree *initial_address, gimple_stmt_iterator *gsi, gimple *ptr_incr, - bool only_init, bool *inv_p) + bool only_init, bool *inv_p, tree byte_offset) { const char *base_name; stmt_vec_info stmt_info = vinfo_for_stmt (stmt); @@ -3903,10 +3923,10 @@ vect_create_data_ref_ptr (gimple stmt, tree aggr_type, struct loop *at_loop, /* (2) Calculate the initial address of the aggregate-pointer, and set the aggregate-pointer to point to it before the loop. */ - /* Create: (&(base[init_val+offset]) in the loop preheader. */ + /* Create: (&(base[init_val+offset]+byte_offset) in the loop preheader. */ new_temp = vect_create_addr_base_for_vector_ref (stmt, &new_stmt_list, - offset, loop); + offset, loop, byte_offset); if (new_stmt_list) { if (pe) diff --git a/gcc/tree-vect-loop.c b/gcc/tree-vect-loop.c index 3b2c51a9719..1c6cb5838a0 100644 --- a/gcc/tree-vect-loop.c +++ b/gcc/tree-vect-loop.c @@ -2205,7 +2205,8 @@ vect_is_simple_reduction_1 (loop_vec_info loop_info, gimple phi, } def1 = SSA_NAME_DEF_STMT (op1); - if (flow_bb_inside_loop_p (loop, gimple_bb (def_stmt)) + if (gimple_bb (def1) + && flow_bb_inside_loop_p (loop, gimple_bb (def_stmt)) && loop->inner && flow_bb_inside_loop_p (loop->inner, gimple_bb (def1)) && is_gimple_assign (def1)) diff --git a/gcc/tree-vect-slp.c b/gcc/tree-vect-slp.c index ddf351ba732..1cce19f68d6 100644 --- a/gcc/tree-vect-slp.c +++ b/gcc/tree-vect-slp.c @@ -1837,7 +1837,10 @@ vect_detect_hybrid_slp_stmts (slp_tree node) && (stmt_vinfo = vinfo_for_stmt (use_stmt)) && !STMT_SLP_TYPE (stmt_vinfo) && (STMT_VINFO_RELEVANT (stmt_vinfo) - || VECTORIZABLE_CYCLE_DEF (STMT_VINFO_DEF_TYPE (stmt_vinfo))) + || VECTORIZABLE_CYCLE_DEF (STMT_VINFO_DEF_TYPE (stmt_vinfo)) + || (STMT_VINFO_IN_PATTERN_P (stmt_vinfo) + && STMT_VINFO_RELATED_STMT (stmt_vinfo) + && !STMT_SLP_TYPE (vinfo_for_stmt (STMT_VINFO_RELATED_STMT (stmt_vinfo))))) && !(gimple_code (use_stmt) == GIMPLE_PHI && STMT_VINFO_DEF_TYPE (stmt_vinfo) == vect_reduction_def)) diff --git a/gcc/tree-vect-stmts.c b/gcc/tree-vect-stmts.c index 361c312d891..1fcf7260102 100644 --- a/gcc/tree-vect-stmts.c +++ b/gcc/tree-vect-stmts.c @@ -4319,6 +4319,7 @@ vectorizable_load (gimple stmt, gimple_stmt_iterator *gsi, gimple *vec_stmt, int i, j, group_size; tree msq = NULL_TREE, lsq; tree offset = NULL_TREE; + tree byte_offset = NULL_TREE; tree realignment_token = NULL_TREE; gimple phi = NULL; vec<tree> dr_chain = vNULL; @@ -4934,7 +4935,8 @@ vectorizable_load (gimple stmt, gimple_stmt_iterator *gsi, gimple *vec_stmt, if (alignment_support_scheme == dr_explicit_realign_optimized) { phi = SSA_NAME_DEF_STMT (msq); - offset = size_int (TYPE_VECTOR_SUBPARTS (vectype) - 1); + byte_offset = size_binop (MINUS_EXPR, TYPE_SIZE_UNIT (vectype), + size_one_node); } } else @@ -4955,7 +4957,8 @@ vectorizable_load (gimple stmt, gimple_stmt_iterator *gsi, gimple *vec_stmt, if (j == 0) dataref_ptr = vect_create_data_ref_ptr (first_stmt, aggr_type, at_loop, offset, &dummy, gsi, - &ptr_incr, false, &inv_p); + &ptr_incr, false, &inv_p, + byte_offset); else dataref_ptr = bump_vector_ptr (dataref_ptr, ptr_incr, gsi, stmt, TYPE_SIZE_UNIT (aggr_type)); diff --git a/gcc/tree-vectorizer.h b/gcc/tree-vectorizer.h index 7807ed7afb0..fcd4b8191b0 100644 --- a/gcc/tree-vectorizer.h +++ b/gcc/tree-vectorizer.h @@ -324,9 +324,9 @@ typedef struct _loop_vec_info { #define LOOP_VINFO_OPERANDS_SWAPPED(L) (L)->operands_swapped #define LOOP_REQUIRES_VERSIONING_FOR_ALIGNMENT(L) \ -(L)->may_misalign_stmts.length () > 0 +((L)->may_misalign_stmts.length () > 0) #define LOOP_REQUIRES_VERSIONING_FOR_ALIAS(L) \ -(L)->may_alias_ddrs.length () > 0 +((L)->may_alias_ddrs.length () > 0) #define NITERS_KNOWN_P(n) \ (host_integerp ((n),0) \ @@ -939,7 +939,8 @@ extern tree vect_check_gather (gimple, loop_vec_info, tree *, tree *, extern bool vect_analyze_data_refs (loop_vec_info, bb_vec_info, int *); extern tree vect_create_data_ref_ptr (gimple, tree, struct loop *, tree, tree *, gimple_stmt_iterator *, - gimple *, bool, bool *); + gimple *, bool, bool *, + tree = NULL_TREE); extern tree bump_vector_ptr (tree, gimple, gimple_stmt_iterator *, gimple, tree); extern tree vect_create_destination_var (tree, tree); extern bool vect_grouped_store_supported (tree, unsigned HOST_WIDE_INT); @@ -957,7 +958,8 @@ extern void vect_record_grouped_load_vectors (gimple, vec<tree> ); extern int vect_get_place_in_interleaving_chain (gimple, gimple); extern tree vect_get_new_vect_var (tree, enum vect_var_kind, const char *); extern tree vect_create_addr_base_for_vector_ref (gimple, gimple_seq *, - tree, struct loop *); + tree, struct loop *, + tree = NULL_TREE); /* In tree-vect-loop.c. */ /* FORNOW: Used in tree-parloops.c. */ diff --git a/libada/ChangeLog b/libada/ChangeLog index 5ecdfc92dfb..60dddfec84e 100644 --- a/libada/ChangeLog +++ b/libada/ChangeLog @@ -1,3 +1,7 @@ +2014-08-12 Joel Sherrill <joel.sherrill@oarcorp.com> + + * Makefile.in: Add CFLAGS_FOR_TARGET to GNATLIBCFLAGS_FOR_C. + 2014-05-22 Release Manager * GCC 4.8.3 released. diff --git a/libada/Makefile.in b/libada/Makefile.in index 983a5422040..ca02e8db2cb 100644 --- a/libada/Makefile.in +++ b/libada/Makefile.in @@ -60,7 +60,7 @@ CFLAGS=-g PICFLAG = @PICFLAG@ GNATLIBFLAGS= -W -Wall -gnatpg -nostdinc GNATLIBCFLAGS= -g -O2 -GNATLIBCFLAGS_FOR_C = -W -Wall $(GNATLIBCFLAGS) \ +GNATLIBCFLAGS_FOR_C = -W -Wall $(GNATLIBCFLAGS) $(CFLAGS_FOR_TARGET) \ -fexceptions -DIN_RTS @have_getipinfo@ host_subdir = @host_subdir@ diff --git a/libcpp/ChangeLog b/libcpp/ChangeLog index de755ce7569..42cdc5c357b 100644 --- a/libcpp/ChangeLog +++ b/libcpp/ChangeLog @@ -1,3 +1,14 @@ +2014-10-12 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + Backport from mainline r215873 + 2014-10-03 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * lex.c (search_line_fast): Add new version to be used for Power8 + and later targets when Altivec is enabled. Restrict the existing + Altivec version to big-endian systems so that lvsr is not used on + little endian, where it is deprecated. Remove LE-specific code + from the now-BE-only version. + 2014-05-22 Release Manager * GCC 4.8.3 released. diff --git a/libcpp/lex.c b/libcpp/lex.c index 335d2b3e4fd..9f95ee0c2dc 100644 --- a/libcpp/lex.c +++ b/libcpp/lex.c @@ -515,9 +515,111 @@ init_vectorized_lexer (void) search_line_fast = impl; } -#elif (GCC_VERSION >= 4005) && defined(__ALTIVEC__) +#elif defined(_ARCH_PWR8) && defined(__ALTIVEC__) -/* A vection of the fast scanner using AltiVec vectorized byte compares. */ +/* A vection of the fast scanner using AltiVec vectorized byte compares + and VSX unaligned loads (when VSX is available). This is otherwise + the same as the pre-GCC 5 version. */ + +static const uchar * +search_line_fast (const uchar *s, const uchar *end ATTRIBUTE_UNUSED) +{ + typedef __attribute__((altivec(vector))) unsigned char vc; + + const vc repl_nl = { + '\n', '\n', '\n', '\n', '\n', '\n', '\n', '\n', + '\n', '\n', '\n', '\n', '\n', '\n', '\n', '\n' + }; + const vc repl_cr = { + '\r', '\r', '\r', '\r', '\r', '\r', '\r', '\r', + '\r', '\r', '\r', '\r', '\r', '\r', '\r', '\r' + }; + const vc repl_bs = { + '\\', '\\', '\\', '\\', '\\', '\\', '\\', '\\', + '\\', '\\', '\\', '\\', '\\', '\\', '\\', '\\' + }; + const vc repl_qm = { + '?', '?', '?', '?', '?', '?', '?', '?', + '?', '?', '?', '?', '?', '?', '?', '?', + }; + const vc zero = { 0 }; + + vc data, t; + + /* Main loop processing 16 bytes at a time. */ + do + { + vc m_nl, m_cr, m_bs, m_qm; + + data = *((const vc *)s); + s += 16; + + m_nl = (vc) __builtin_vec_cmpeq(data, repl_nl); + m_cr = (vc) __builtin_vec_cmpeq(data, repl_cr); + m_bs = (vc) __builtin_vec_cmpeq(data, repl_bs); + m_qm = (vc) __builtin_vec_cmpeq(data, repl_qm); + t = (m_nl | m_cr) | (m_bs | m_qm); + + /* T now contains 0xff in bytes for which we matched one of the relevant + characters. We want to exit the loop if any byte in T is non-zero. + Below is the expansion of vec_any_ne(t, zero). */ + } + while (!__builtin_vec_vcmpeq_p(/*__CR6_LT_REV*/3, t, zero)); + + /* Restore s to to point to the 16 bytes we just processed. */ + s -= 16; + + { +#define N (sizeof(vc) / sizeof(long)) + + union { + vc v; + /* Statically assert that N is 2 or 4. */ + unsigned long l[(N == 2 || N == 4) ? N : -1]; + } u; + unsigned long l, i = 0; + + u.v = t; + + /* Find the first word of T that is non-zero. */ + switch (N) + { + case 4: + l = u.l[i++]; + if (l != 0) + break; + s += sizeof(unsigned long); + l = u.l[i++]; + if (l != 0) + break; + s += sizeof(unsigned long); + case 2: + l = u.l[i++]; + if (l != 0) + break; + s += sizeof(unsigned long); + l = u.l[i]; + } + + /* L now contains 0xff in bytes for which we matched one of the + relevant characters. We can find the byte index by finding + its bit index and dividing by 8. */ +#ifdef __BIG_ENDIAN__ + l = __builtin_clzl(l) >> 3; +#else + l = __builtin_ctzl(l) >> 3; +#endif + return s + l; + +#undef N + } +} + +#elif (GCC_VERSION >= 4005) && defined(__ALTIVEC__) && defined (__BIG_ENDIAN__) + +/* A vection of the fast scanner using AltiVec vectorized byte compares. + This cannot be used for little endian because vec_lvsl/lvsr are + deprecated for little endian and the code won't work properly. */ /* ??? Unfortunately, attribute(target("altivec")) is not yet supported, so we can't compile this function without -maltivec on the command line (or implied by some other switch). */ @@ -559,13 +661,8 @@ search_line_fast (const uchar *s, const uchar *end ATTRIBUTE_UNUSED) beginning with all ones and shifting in zeros according to the mis-alignment. The LVSR instruction pulls the exact shift we want from the address. */ -#ifdef __BIG_ENDIAN__ mask = __builtin_vec_lvsr(0, s); mask = __builtin_vec_perm(zero, ones, mask); -#else - mask = __builtin_vec_lvsl(0, s); - mask = __builtin_vec_perm(ones, zero, mask); -#endif data &= mask; /* While altivec loads mask addresses, we still need to align S so @@ -629,11 +726,7 @@ search_line_fast (const uchar *s, const uchar *end ATTRIBUTE_UNUSED) /* L now contains 0xff in bytes for which we matched one of the relevant characters. We can find the byte index by finding its bit index and dividing by 8. */ -#ifdef __BIG_ENDIAN__ l = __builtin_clzl(l) >> 3; -#else - l = __builtin_ctzl(l) >> 3; -#endif return s + l; #undef N diff --git a/libffi/ChangeLog b/libffi/ChangeLog index ffab7e6321d..0b4a3726d81 100644 --- a/libffi/ChangeLog +++ b/libffi/ChangeLog @@ -1,3 +1,9 @@ +2014-09-11 Jakub Jelinek <jakub@redhat.com> + + * src/powerpc/linux64.S: Emit .note.GNU-stack even when + POWERPC64 is not defined. + * src/powerpc/linux64_closure.S: Likewise. Also test _CALL_ELF == 2. + 2014-05-22 Release Manager * GCC 4.8.3 released. diff --git a/libffi/src/powerpc/linux64.S b/libffi/src/powerpc/linux64.S index c4d01d8e3f7..d2acb7007b0 100644 --- a/libffi/src/powerpc/linux64.S +++ b/libffi/src/powerpc/linux64.S @@ -254,7 +254,8 @@ ffi_call_LINUX64: .align 3 .LEFDE1: -# if (defined __ELF__ && defined __linux__) || _CALL_ELF == 2 +#endif + +#if (defined __ELF__ && defined __linux__) || _CALL_ELF == 2 .section .note.GNU-stack,"",@progbits -# endif #endif diff --git a/libffi/src/powerpc/linux64_closure.S b/libffi/src/powerpc/linux64_closure.S index 46a9ddfcd6b..1d80a39490b 100644 --- a/libffi/src/powerpc/linux64_closure.S +++ b/libffi/src/powerpc/linux64_closure.S @@ -381,7 +381,8 @@ ffi_closure_LINUX64: .align 3 .LEFDE1: -# if defined __ELF__ && defined __linux__ +#endif + +#if (defined __ELF__ && defined __linux__) || _CALL_ELF == 2 .section .note.GNU-stack,"",@progbits -# endif #endif diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog index 530597813c5..44979791f99 100644 --- a/libgcc/ChangeLog +++ b/libgcc/ChangeLog @@ -1,3 +1,14 @@ +2014-10-26 John David Anglin <danglin@gcc.gnu.org> + + * config/pa/linux-unwind.h (pa32_read_access_ok): New function. + (pa32_fallback_frame_state): Use pa32_read_access_ok to check if + memory read accesses are ok. + +2014-09-18 Joseph Myers <joseph@codesourcery.com> + + * config/i386/sfp-machine.h (FP_TRAPPING_EXCEPTIONS): Treat clear + bits not set bits as indicating trapping exceptions. + 2014-05-22 Release Manager * GCC 4.8.3 released. diff --git a/libgcc/config/i386/sfp-machine.h b/libgcc/config/i386/sfp-machine.h index b19d94b6192..27b42a108a0 100644 --- a/libgcc/config/i386/sfp-machine.h +++ b/libgcc/config/i386/sfp-machine.h @@ -59,7 +59,7 @@ void __sfp_handle_exceptions (int); __sfp_handle_exceptions (_fex); \ } while (0); -#define FP_TRAPPING_EXCEPTIONS ((_fcw >> FP_EX_SHIFT) & FP_EX_ALL) +#define FP_TRAPPING_EXCEPTIONS ((~_fcw >> FP_EX_SHIFT) & FP_EX_ALL) #define FP_ROUNDMODE (_fcw & FP_RND_MASK) #endif diff --git a/libgcc/config/pa/linux-unwind.h b/libgcc/config/pa/linux-unwind.h index aacea0e9ab5..8bcc8b948df 100644 --- a/libgcc/config/pa/linux-unwind.h +++ b/libgcc/config/pa/linux-unwind.h @@ -32,6 +32,17 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #include <signal.h> #include <sys/ucontext.h> +/* Return TRUE if read access to *P is allowed. */ + +static inline long +pa32_read_access_ok (void *p) +{ + long ret; + + __asm__ ("proberi (%1),3,%0" : "=r" (ret) : "r" (p) :); + return ret; +} + /* Unfortunately, because of various bugs and changes to the kernel, we have several cases to deal with. @@ -48,7 +59,12 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see tell us how to locate the sigcontext structure. Note that with a 2.4 64-bit kernel, the signal context is not properly - passed back to userspace so the unwind will not work correctly. */ + passed back to userspace so the unwind will not work correctly. + + There is also a bug in various glibc versions. The (CONTEXT)->ra + for the outermost frame is not marked as undefined, so we need to + check whether read access is allowed for all the accesses used in + searching for the signal trampoline. */ #define MD_FALLBACK_FRAME_STATE_FOR pa32_fallback_frame_state @@ -73,14 +89,17 @@ pa32_fallback_frame_state (struct _Unwind_Context *context, e4008200 be,l 0x100(%sr2, %r0), %sr0, %r31 08000240 nop */ - if (pc[0] == 0x34190000 || pc[0] == 0x34190002) + if (pa32_read_access_ok (pc) + && (pc[0] == 0x34190000 || pc[0] == 0x34190002)) off = 4*4; - else if (pc[4] == 0x34190000 || pc[4] == 0x34190002) + else if (pa32_read_access_ok (&pc[4]) + && (pc[4] == 0x34190000 || pc[4] == 0x34190002)) { pc += 4; off = 10 * 4; } - else if (pc[5] == 0x34190000 || pc[5] == 0x34190002) + else if (pa32_read_access_ok (&pc[5]) + && (pc[5] == 0x34190000 || pc[5] == 0x34190002)) { pc += 5; off = 10 * 4; @@ -96,13 +115,16 @@ pa32_fallback_frame_state (struct _Unwind_Context *context, word boundary and we can then determine the frame offset. */ sp = (unsigned long)context->ra; pc = (unsigned int *)sp; - if ((pc[0] == 0x34190000 || pc[0] == 0x34190002) && (sp & 4)) + if ((sp & 4) + && pa32_read_access_ok (pc) + && (pc[0] == 0x34190000 || pc[0] == 0x34190002)) off = 5 * 4; else return _URC_END_OF_STACK; } - if (pc[1] != 0x3414015a + if (!pa32_read_access_ok (&pc[3]) + || pc[1] != 0x3414015a || pc[2] != 0xe4008200 || pc[3] != 0x08000240) return _URC_END_OF_STACK; diff --git a/libgfortran/ChangeLog b/libgfortran/ChangeLog index a0868cd72cd..97a4fb1b199 100644 --- a/libgfortran/ChangeLog +++ b/libgfortran/ChangeLog @@ -1,3 +1,22 @@ +2014-10-20 Janne Blomqvist <jb@gcc.gnu.org> + + PR libfortran/63589 + * configure.ac: Check for strtok_r. + * runtime/main.c (gfstrtok_r): Fallback implementation of + strtok_r. + (find_addr2line): Use strtok_r to split PATH. + * config.h.in: Regenerated. + * configure: Regenerated. + +2014-08-20 Steven G. Kargl <kargl@gcc.gnu.org> + + PR libgfortran/62188 + * m4/bessel.m4: Avoid indexing off the end of an array. + * generated/bessel_r10.c: Regenerated. + * generated/bessel_r16.c: Ditto. + * generated/bessel_r4.c: Ditto. + * generated/bessel_r8.c: Ditto. + 2014-07-31 Janne Blomqvist <jb@gcc.gnu.org> Backport from mainline diff --git a/libgfortran/config.h.in b/libgfortran/config.h.in index fb5026fc0da..a391e95b0e1 100644 --- a/libgfortran/config.h.in +++ b/libgfortran/config.h.in @@ -711,6 +711,9 @@ /* Define to 1 if you have the `strtof' function. */ #undef HAVE_STRTOF +/* Define to 1 if you have the `strtok_r' function. */ +#undef HAVE_STRTOK_R + /* Define to 1 if you have the `strtold' function. */ #undef HAVE_STRTOLD diff --git a/libgfortran/configure b/libgfortran/configure index ee99e6c89a5..d26b379db8a 100755 --- a/libgfortran/configure +++ b/libgfortran/configure @@ -2595,6 +2595,7 @@ as_fn_append ac_func_list " umask" as_fn_append ac_func_list " getegid" as_fn_append ac_func_list " secure_getenv" as_fn_append ac_func_list " __secure_getenv" +as_fn_append ac_func_list " strtok_r" as_fn_append ac_header_list " math.h" # Check that the precious variables saved in the cache have kept the same # value. @@ -12339,7 +12340,7 @@ else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF -#line 12342 "configure" +#line 12343 "configure" #include "confdefs.h" #if HAVE_DLFCN_H @@ -12445,7 +12446,7 @@ else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF -#line 12448 "configure" +#line 12449 "configure" #include "confdefs.h" #if HAVE_DLFCN_H @@ -16561,6 +16562,8 @@ done + + # Check strerror_r, cannot be above as versions with two and three arguments exist ac_save_CFLAGS="$CFLAGS" diff --git a/libgfortran/configure.ac b/libgfortran/configure.ac index 7d97fed1b0b..bdb71ff3d20 100644 --- a/libgfortran/configure.ac +++ b/libgfortran/configure.ac @@ -267,7 +267,7 @@ alarm access fork execl wait setmode execve pipe dup2 close \ strcasestr getrlimit gettimeofday stat fstat lstat getpwuid vsnprintf dup \ getcwd localtime_r gmtime_r getpwuid_r ttyname_r clock_gettime \ readlink getgid getpid getppid getuid geteuid umask getegid \ -secure_getenv __secure_getenv) +secure_getenv __secure_getenv strtok_r) # Check strerror_r, cannot be above as versions with two and three arguments exist LIBGFOR_CHECK_STRERROR_R diff --git a/libgfortran/generated/bessel_r10.c b/libgfortran/generated/bessel_r10.c index 44da8478a8c..e926d5c9e69 100644 --- a/libgfortran/generated/bessel_r10.c +++ b/libgfortran/generated/bessel_r10.c @@ -162,7 +162,7 @@ bessel_yn_r10 (gfc_array_r10 * const restrict ret, int n1, int n2, x2rev = GFC_REAL_10_LITERAL(2.)/x; - for (i = 2; i <= n1+n2; i++) + for (i = 2; i <= n2 - n1; i++) { #if defined(GFC_REAL_10_INFINITY) if (unlikely (last2 == -GFC_REAL_10_INFINITY)) diff --git a/libgfortran/generated/bessel_r16.c b/libgfortran/generated/bessel_r16.c index d0ad50a9ff0..c0ee468ca96 100644 --- a/libgfortran/generated/bessel_r16.c +++ b/libgfortran/generated/bessel_r16.c @@ -166,7 +166,7 @@ bessel_yn_r16 (gfc_array_r16 * const restrict ret, int n1, int n2, x2rev = GFC_REAL_16_LITERAL(2.)/x; - for (i = 2; i <= n1+n2; i++) + for (i = 2; i <= n2 - n1; i++) { #if defined(GFC_REAL_16_INFINITY) if (unlikely (last2 == -GFC_REAL_16_INFINITY)) diff --git a/libgfortran/generated/bessel_r4.c b/libgfortran/generated/bessel_r4.c index 5fe486bb77e..eedfc1fc0c5 100644 --- a/libgfortran/generated/bessel_r4.c +++ b/libgfortran/generated/bessel_r4.c @@ -162,7 +162,7 @@ bessel_yn_r4 (gfc_array_r4 * const restrict ret, int n1, int n2, x2rev = GFC_REAL_4_LITERAL(2.)/x; - for (i = 2; i <= n1+n2; i++) + for (i = 2; i <= n2 - n1; i++) { #if defined(GFC_REAL_4_INFINITY) if (unlikely (last2 == -GFC_REAL_4_INFINITY)) diff --git a/libgfortran/generated/bessel_r8.c b/libgfortran/generated/bessel_r8.c index 2150042cef3..8e71cb9bc13 100644 --- a/libgfortran/generated/bessel_r8.c +++ b/libgfortran/generated/bessel_r8.c @@ -162,7 +162,7 @@ bessel_yn_r8 (gfc_array_r8 * const restrict ret, int n1, int n2, x2rev = GFC_REAL_8_LITERAL(2.)/x; - for (i = 2; i <= n1+n2; i++) + for (i = 2; i <= n2 - n1; i++) { #if defined(GFC_REAL_8_INFINITY) if (unlikely (last2 == -GFC_REAL_8_INFINITY)) diff --git a/libgfortran/m4/bessel.m4 b/libgfortran/m4/bessel.m4 index bfdbf9a81e7..41adade7321 100644 --- a/libgfortran/m4/bessel.m4 +++ b/libgfortran/m4/bessel.m4 @@ -163,7 +163,7 @@ bessel_yn_r'rtype_kind` ('rtype` * const restrict ret, int n1, int n2, x2rev = GFC_REAL_'rtype_kind`_LITERAL(2.)/x; - for (i = 2; i <= n1+n2; i++) + for (i = 2; i <= n2 - n1; i++) { #if defined('rtype_name`_INFINITY) if (unlikely (last2 == -'rtype_name`_INFINITY)) diff --git a/libgfortran/runtime/main.c b/libgfortran/runtime/main.c index d774cfb8ae1..32033ba3e90 100644 --- a/libgfortran/runtime/main.c +++ b/libgfortran/runtime/main.c @@ -153,6 +153,16 @@ full_exe_path (void) } +#ifndef HAVE_STRTOK_R +static char* +gfstrtok_r (char *str, const char *delim, + char **saveptr __attribute__ ((unused))) +{ + return strtok (str, delim); +} +#define strtok_r gfstrtok_r +#endif + char *addr2line_path; /* Find addr2line and store the path. */ @@ -161,30 +171,32 @@ void find_addr2line (void) { #ifdef HAVE_ACCESS -#define A2L_LEN 10 +#define A2L_LEN 11 char *path = secure_getenv ("PATH"); if (!path) return; + char *tp = strdup (path); + if (!tp) + return; size_t n = strlen (path); - char ap[n + 1 + A2L_LEN]; - size_t ai = 0; - for (size_t i = 0; i < n; i++) + char *ap = xmalloc (n + A2L_LEN); + char *saveptr; + for (char *str = tp;; str = NULL) { - if (path[i] != ':') - ap[ai++] = path[i]; - else + char *token = strtok_r (str, ":", &saveptr); + if (!token) + break; + size_t toklen = strlen (token); + memcpy (ap, token, toklen); + memcpy (ap + toklen, "/addr2line", A2L_LEN); + if (access (ap, R_OK|X_OK) == 0) { - ap[ai++] = '/'; - memcpy (ap + ai, "addr2line", A2L_LEN); - if (access (ap, R_OK|X_OK) == 0) - { - addr2line_path = strdup (ap); - return; - } - else - ai = 0; + addr2line_path = strdup (ap); + break; } } + free (tp); + free (ap); #endif } diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog index 9c8408d8d09..22edbcfc40b 100644 --- a/libstdc++-v3/ChangeLog +++ b/libstdc++-v3/ChangeLog @@ -1,3 +1,56 @@ +2014-10-15 Jason Merrill <jason@redhat.com> + + * libsupc++/dyncast.cc (__dynamic_cast): Handle mid-destruction + dynamic_cast more gracefully. + +2014-10-14 Kai Tietz <ktietz@redhat.com> + + PR libstdc++/57440 + * config/os/mingw32/os_defines.h (_GTHREAD_USE_MUTEX_INIT_FUNC): + Define to avoid leak. + * config/os/mingw32-w64/os_defines.h: Likewise. + +2014-10-03 Jonathan Wakely <jwakely@redhat.com> + + PR libstdc++/63449 + * doc/xml/manual/containers.xml: Remove outdated section. Update + std::list notes. + * doc/html/*: Regenerate. + +2014-10-01 Jonathan Wakely <jwakely@redhat.com> + + * doc/xml/manual/status_cxx2011.xml: Corrections. + * doc/html/manual/status.html: Regenerate. + +2014-08-28 Samuel Bronson <naesten@gmail.com> + + Backport r212453 from trunk + 2014-07-11 Samuel Bronson <naesten@gmail.com> + Matthias Klose <doko@ubuntu.com> + + PR libstdc++/58962 + * python/libstdcxx/v6/printers.py: Port to Python 2+3 + (imap): New compat function. + (izip): Likewise. + (Iterator): New mixin to allow writing iterators in Python 3 style + regardless of which version we're running on. + [Python3] (long) New compat alias for "int". + * testsuite/lib/gdb-test.exp: Port to Python 2+3 (print syntax) + + Backport r210625 from trunk + 2014-05-19 Jonathan Wakely <jwakely@redhat.com> + + * python/libstdcxx/v6/printers.py: Use Python3 raise syntax. + +2014-08-26 John David Anglin <danglin@gcc.gnu.org> + + * config/abi/post/hppa-linux-gnu/baseline_symbols.txt: Update. + +2014-08-26 Jonathan Wakely <jwakely@redhat.com> + + * doc/xml/manual/status_cxx2011.xml: Correct status table. + * doc/html/manual/*: Regenerate. + 2014-08-04 Jonathan Wakely <jwakely@redhat.com> Backported from mainline diff --git a/libstdc++-v3/config/abi/post/hppa-linux-gnu/baseline_symbols.txt b/libstdc++-v3/config/abi/post/hppa-linux-gnu/baseline_symbols.txt index 28b4a7a1b67..aa325cc8e49 100644 --- a/libstdc++-v3/config/abi/post/hppa-linux-gnu/baseline_symbols.txt +++ b/libstdc++-v3/config/abi/post/hppa-linux-gnu/baseline_symbols.txt @@ -400,6 +400,7 @@ FUNC:_ZNKSt15basic_streambufIwSt11char_traitsIwEE5pbaseEv@@GLIBCXX_3.4 FUNC:_ZNKSt15basic_streambufIwSt11char_traitsIwEE6getlocEv@@GLIBCXX_3.4 FUNC:_ZNKSt15basic_stringbufIcSt11char_traitsIcESaIcEE3strEv@@GLIBCXX_3.4 FUNC:_ZNKSt15basic_stringbufIwSt11char_traitsIwESaIwEE3strEv@@GLIBCXX_3.4 +FUNC:_ZNKSt17bad_function_call4whatEv@@GLIBCXX_3.4.18 FUNC:_ZNKSt18basic_stringstreamIcSt11char_traitsIcESaIcEE3strEv@@GLIBCXX_3.4 FUNC:_ZNKSt18basic_stringstreamIcSt11char_traitsIcESaIcEE5rdbufEv@@GLIBCXX_3.4 FUNC:_ZNKSt18basic_stringstreamIwSt11char_traitsIwESaIwEE3strEv@@GLIBCXX_3.4 @@ -587,6 +588,8 @@ FUNC:_ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt FUNC:_ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewm@@GLIBCXX_3.4 FUNC:_ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewx@@GLIBCXX_3.4 FUNC:_ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewy@@GLIBCXX_3.4 +FUNC:_ZNKSt8__detail20_Prime_rehash_policy11_M_next_bktEj@@GLIBCXX_3.4.18 +FUNC:_ZNKSt8__detail20_Prime_rehash_policy14_M_need_rehashEjjj@@GLIBCXX_3.4.18 FUNC:_ZNKSt8bad_cast4whatEv@@GLIBCXX_3.4.9 FUNC:_ZNKSt8ios_base7failure4whatEv@@GLIBCXX_3.4 FUNC:_ZNKSt8messagesIcE18_M_convert_to_charERKSs@@GLIBCXX_3.4 @@ -1204,6 +1207,7 @@ FUNC:_ZNSt11range_errorD2Ev@@GLIBCXX_3.4.15 FUNC:_ZNSt11regex_errorD0Ev@@GLIBCXX_3.4.15 FUNC:_ZNSt11regex_errorD1Ev@@GLIBCXX_3.4.15 FUNC:_ZNSt11regex_errorD2Ev@@GLIBCXX_3.4.15 +FUNC:_ZNSt11this_thread11__sleep_forENSt6chrono8durationIxSt5ratioILx1ELx1EEEENS1_IxS2_ILx1ELx1000000000EEEE@@GLIBCXX_3.4.18 FUNC:_ZNSt12__basic_fileIcE2fdEv@@GLIBCXX_3.4 FUNC:_ZNSt12__basic_fileIcE4fileEv@@GLIBCXX_3.4.1 FUNC:_ZNSt12__basic_fileIcE4openEPKcSt13_Ios_Openmodei@@GLIBCXX_3.4 @@ -1471,6 +1475,11 @@ FUNC:_ZNSt13basic_ostreamIwSt11char_traitsIwEElsEs@@GLIBCXX_3.4 FUNC:_ZNSt13basic_ostreamIwSt11char_traitsIwEElsEt@@GLIBCXX_3.4 FUNC:_ZNSt13basic_ostreamIwSt11char_traitsIwEElsEx@@GLIBCXX_3.4 FUNC:_ZNSt13basic_ostreamIwSt11char_traitsIwEElsEy@@GLIBCXX_3.4 +FUNC:_ZNSt13random_device14_M_init_pretr1ERKSs@@GLIBCXX_3.4.18 +FUNC:_ZNSt13random_device16_M_getval_pretr1Ev@@GLIBCXX_3.4.18 +FUNC:_ZNSt13random_device7_M_finiEv@@GLIBCXX_3.4.18 +FUNC:_ZNSt13random_device7_M_initERKSs@@GLIBCXX_3.4.18 +FUNC:_ZNSt13random_device9_M_getvalEv@@GLIBCXX_3.4.18 FUNC:_ZNSt13runtime_errorC1ERKSs@@GLIBCXX_3.4 FUNC:_ZNSt13runtime_errorC2ERKSs@@GLIBCXX_3.4 FUNC:_ZNSt13runtime_errorD0Ev@@GLIBCXX_3.4 @@ -1900,6 +1909,8 @@ FUNC:_ZNSt6__norm15_List_node_base7reverseEv@@GLIBCXX_3.4.9 FUNC:_ZNSt6__norm15_List_node_base8transferEPS0_S1_@@GLIBCXX_3.4.9 FUNC:_ZNSt6__norm15_List_node_base9_M_unhookEv@@GLIBCXX_3.4.14 FUNC:_ZNSt6chrono12system_clock3nowEv@@GLIBCXX_3.4.11 +FUNC:_ZNSt6chrono3_V212steady_clock3nowEv@@GLIBCXX_3.4.19 +FUNC:_ZNSt6chrono3_V212system_clock3nowEv@@GLIBCXX_3.4.19 FUNC:_ZNSt6gslice8_IndexerC1EjRKSt8valarrayIjES4_@@GLIBCXX_3.4 FUNC:_ZNSt6gslice8_IndexerC2EjRKSt8valarrayIjES4_@@GLIBCXX_3.4 FUNC:_ZNSt6locale11_M_coalesceERKS_S1_i@@GLIBCXX_3.4 @@ -2436,6 +2447,7 @@ FUNC:__cxa_guard_acquire@@CXXABI_1.3 FUNC:__cxa_guard_release@@CXXABI_1.3 FUNC:__cxa_pure_virtual@@CXXABI_1.3 FUNC:__cxa_rethrow@@CXXABI_1.3 +FUNC:__cxa_thread_atexit@@CXXABI_1.3.7 FUNC:__cxa_throw@@CXXABI_1.3 FUNC:__cxa_tm_cleanup@@CXXABI_TM_1 FUNC:__cxa_vec_cctor@@CXXABI_1.3 @@ -2482,6 +2494,7 @@ OBJECT:0:CXXABI_1.3.3 OBJECT:0:CXXABI_1.3.4 OBJECT:0:CXXABI_1.3.5 OBJECT:0:CXXABI_1.3.6 +OBJECT:0:CXXABI_1.3.7 OBJECT:0:CXXABI_TM_1 OBJECT:0:GLIBCXX_3.4 OBJECT:0:GLIBCXX_3.4.1 @@ -2493,6 +2506,8 @@ OBJECT:0:GLIBCXX_3.4.14 OBJECT:0:GLIBCXX_3.4.15 OBJECT:0:GLIBCXX_3.4.16 OBJECT:0:GLIBCXX_3.4.17 +OBJECT:0:GLIBCXX_3.4.18 +OBJECT:0:GLIBCXX_3.4.19 OBJECT:0:GLIBCXX_3.4.2 OBJECT:0:GLIBCXX_3.4.3 OBJECT:0:GLIBCXX_3.4.4 @@ -2992,6 +3007,8 @@ OBJECT:1:_ZNSt21__numeric_limits_base9is_iec559E@@GLIBCXX_3.4 OBJECT:1:_ZNSt21__numeric_limits_base9is_moduloE@@GLIBCXX_3.4 OBJECT:1:_ZNSt21__numeric_limits_base9is_signedE@@GLIBCXX_3.4 OBJECT:1:_ZNSt6chrono12system_clock12is_monotonicE@@GLIBCXX_3.4.11 +OBJECT:1:_ZNSt6chrono3_V212steady_clock9is_steadyE@@GLIBCXX_3.4.19 +OBJECT:1:_ZNSt6chrono3_V212system_clock9is_steadyE@@GLIBCXX_3.4.19 OBJECT:1:_ZSt10adopt_lock@@GLIBCXX_3.4.11 OBJECT:1:_ZSt10defer_lock@@GLIBCXX_3.4.11 OBJECT:1:_ZSt11try_to_lock@@GLIBCXX_3.4.11 diff --git a/libstdc++-v3/config/os/mingw32-w64/os_defines.h b/libstdc++-v3/config/os/mingw32-w64/os_defines.h index ad764361a45..920d7cf095f 100644 --- a/libstdc++-v3/config/os/mingw32-w64/os_defines.h +++ b/libstdc++-v3/config/os/mingw32-w64/os_defines.h @@ -78,4 +78,7 @@ #define _GLIBCXX_LLP64 1 #endif +// See libstdc++/59807 +#define _GTHREAD_USE_MUTEX_INIT_FUNC 1 + #endif diff --git a/libstdc++-v3/config/os/mingw32/os_defines.h b/libstdc++-v3/config/os/mingw32/os_defines.h index df3a1cb1704..900291dd2ec 100644 --- a/libstdc++-v3/config/os/mingw32/os_defines.h +++ b/libstdc++-v3/config/os/mingw32/os_defines.h @@ -75,4 +75,7 @@ #define _GLIBCXX_LLP64 1 #endif +// See libstdc++/59807 +#define _GTHREAD_USE_MUTEX_INIT_FUNC 1 + #endif diff --git a/libstdc++-v3/doc/html/index.html b/libstdc++-v3/doc/html/index.html index 787112d9299..8125acd5f4e 100644 --- a/libstdc++-v3/doc/html/index.html +++ b/libstdc++-v3/doc/html/index.html @@ -43,7 +43,7 @@ </a></span></dt><dd><dl><dt><span class="section"><a href="manual/localization.html#std.localization.locales">Locales</a></span></dt><dd><dl><dt><span class="section"><a href="manual/localization.html#std.localization.locales.locale">locale</a></span></dt><dd><dl><dt><span class="section"><a href="manual/localization.html#locales.locale.req">Requirements</a></span></dt><dt><span class="section"><a href="manual/localization.html#locales.locale.design">Design</a></span></dt><dt><span class="section"><a href="manual/localization.html#locales.locale.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="manual/localization.html#locale.impl.c">Interacting with "C" locales</a></span></dt></dl></dd><dt><span class="section"><a href="manual/localization.html#locales.locale.future">Future</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="manual/facets.html">Facets</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#std.localization.facet.ctype">ctype</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#facet.ctype.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#idm269999753024">Specializations</a></span></dt></dl></dd><dt><span class="section"><a href="manual/facets.html#facet.ctype.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="manual/facets.html#std.localization.facet.codecvt">codecvt</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#facet.codecvt.req">Requirements</a></span></dt><dt><span class="section"><a href="manual/facets.html#facet.codecvt.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#codecvt.design.wchar_t_size"><span class="type">wchar_t</span> Size</a></span></dt><dt><span class="section"><a href="manual/facets.html#codecvt.design.unicode">Support for Unicode</a></span></dt><dt><span class="section"><a href="manual/facets.html#codecvt.design.issues">Other Issues</a></span></dt></dl></dd><dt><span class="section"><a href="manual/facets.html#facet.codecvt.impl">Implementation</a></span></dt><dt><span class="section"><a href="manual/facets.html#facet.codecvt.use">Use</a></span></dt><dt><span class="section"><a href="manual/facets.html#facet.codecvt.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="manual/facets.html#manual.localization.facet.messages">messages</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#facet.messages.req">Requirements</a></span></dt><dt><span class="section"><a href="manual/facets.html#facet.messages.design">Design</a></span></dt><dt><span class="section"><a href="manual/facets.html#facet.messages.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#messages.impl.models">Models</a></span></dt><dt><span class="section"><a href="manual/facets.html#messages.impl.gnu">The GNU Model</a></span></dt></dl></dd><dt><span class="section"><a href="manual/facets.html#facet.messages.use">Use</a></span></dt><dt><span class="section"><a href="manual/facets.html#facet.messages.future">Future</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="chapter"><a href="manual/containers.html">9. Containers -</a></span></dt><dd><dl><dt><span class="section"><a href="manual/containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="manual/containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="manual/containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd><dt><span class="section"><a href="manual/containers.html#containers.sequences.vector">vector</a></span></dt><dd><dl><dt><span class="section"><a href="manual/containers.html#sequences.vector.management">Space Overhead Management</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="manual/associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="manual/associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="manual/associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="manual/associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="manual/associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="manual/unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="manual/unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="manual/unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="manual/containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="manual/containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="manual/iterators.html">10. +</a></span></dt><dd><dl><dt><span class="section"><a href="manual/containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="manual/containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="manual/containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="manual/associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="manual/associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="manual/associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="manual/associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="manual/associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="manual/unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="manual/unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="manual/unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="manual/containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="manual/containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="manual/iterators.html">10. Iterators </a></span></dt><dd><dl><dt><span class="section"><a href="manual/iterators.html#std.iterators.predefined">Predefined</a></span></dt><dd><dl><dt><span class="section"><a href="manual/iterators.html#iterators.predefined.vs_pointers">Iterators vs. Pointers</a></span></dt><dt><span class="section"><a href="manual/iterators.html#iterators.predefined.end">One Past the End</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="manual/algorithms.html">11. @@ -162,4 +162,4 @@ Support for C++11 dialect. </a></span></dt><dt><span class="appendix"><a href="manual/appendix_gpl.html">D. <acronym class="acronym">GNU</acronym> General Public License version 3 - </a></span></dt><dt><span class="appendix"><a href="manual/appendix_gfdl.html">E. GNU Free Documentation License</a></span></dt></dl></dd></dl></dd><dt><span class="book"><a href="bk02.html"></a></span></dt><dd><dl><dt><span class="article"><a href="api.html">The GNU C++ Library API Reference</a></span></dt></dl></dd><dt><span class="book"><a href="bk03.html"></a></span></dt><dd><dl><dt><span class="article"><a href="faq.html">Frequently Asked Questions</a></span></dt></dl></dd></dl></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"> </td><td width="20%" align="center"> </td><td width="40%" align="right"> <a accesskey="n" href="manual/index.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top"> </td><td width="20%" align="center"> </td><td width="40%" align="right" valign="top"> The GNU C++ Library Manual</td></tr></table></div></body></html>
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GNU Free Documentation License</a></span></dt></dl></dd></dl></dd><dt><span class="book"><a href="bk02.html"></a></span></dt><dd><dl><dt><span class="article"><a href="api.html">The GNU C++ Library API Reference</a></span></dt></dl></dd><dt><span class="book"><a href="bk03.html"></a></span></dt><dd><dl><dt><span class="article"><a href="faq.html">Frequently Asked Questions</a></span></dt></dl></dd></dl></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"> </td><td width="20%" align="center"> </td><td width="40%" align="right"> <a accesskey="n" href="manual/index.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top"> </td><td width="20%" align="center"> </td><td width="40%" align="right" valign="top"> The GNU C++ Library Manual</td></tr></table></div></body></html> diff --git a/libstdc++-v3/doc/html/manual/abi.html b/libstdc++-v3/doc/html/manual/abi.html index 337cf81fe0f..0f51eee4df9 100644 --- a/libstdc++-v3/doc/html/manual/abi.html +++ b/libstdc++-v3/doc/html/manual/abi.html @@ -96,7 +96,7 @@ compatible. definitions, where the version definition is the maximum for a particular release. Labels are cumulative. If a particular release is not listed, it has the same version labels as the preceding - release.</p><p>This corresponds to the mapfile: gcc/libgcc-std.ver</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>GCC 3.0.0: GCC_3.0</p></li><li class="listitem"><p>GCC 3.3.0: GCC_3.3</p></li><li class="listitem"><p>GCC 3.3.1: GCC_3.3.1</p></li><li class="listitem"><p>GCC 3.3.2: GCC_3.3.2</p></li><li class="listitem"><p>GCC 3.3.4: GCC_3.3.4</p></li><li class="listitem"><p>GCC 3.4.0: GCC_3.4</p></li><li class="listitem"><p>GCC 3.4.2: GCC_3.4.2</p></li><li class="listitem"><p>GCC 3.4.4: GCC_3.4.4</p></li><li class="listitem"><p>GCC 4.0.0: GCC_4.0.0</p></li><li class="listitem"><p>GCC 4.1.0: GCC_4.1.0</p></li><li class="listitem"><p>GCC 4.2.0: GCC_4.2.0</p></li><li class="listitem"><p>GCC 4.3.0: GCC_4.3.0</p></li><li class="listitem"><p>GCC 4.4.0: GCC_4.4.0</p></li><li class="listitem"><p>GCC 4.5.0: GCC_4.5.0</p></li><li class="listitem"><p>GCC 4.6.0: GCC_4.6.0</p></li><li class="listitem"><p>GCC 4.7.0: GCC_4.7.0</p></li></ul></div></li><li class="listitem"><p> + release.</p><p>This corresponds to the mapfile: gcc/libgcc-std.ver</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>GCC 3.0.0: GCC_3.0</p></li><li class="listitem"><p>GCC 3.3.0: GCC_3.3</p></li><li class="listitem"><p>GCC 3.3.1: GCC_3.3.1</p></li><li class="listitem"><p>GCC 3.3.2: GCC_3.3.2</p></li><li class="listitem"><p>GCC 3.3.4: GCC_3.3.4</p></li><li class="listitem"><p>GCC 3.4.0: GCC_3.4</p></li><li class="listitem"><p>GCC 3.4.2: GCC_3.4.2</p></li><li class="listitem"><p>GCC 3.4.4: GCC_3.4.4</p></li><li class="listitem"><p>GCC 4.0.0: GCC_4.0.0</p></li><li class="listitem"><p>GCC 4.1.0: GCC_4.1.0</p></li><li class="listitem"><p>GCC 4.2.0: GCC_4.2.0</p></li><li class="listitem"><p>GCC 4.3.0: GCC_4.3.0</p></li><li class="listitem"><p>GCC 4.4.0: GCC_4.4.0</p></li><li class="listitem"><p>GCC 4.5.0: GCC_4.5.0</p></li><li class="listitem"><p>GCC 4.6.0: GCC_4.6.0</p></li><li class="listitem"><p>GCC 4.7.0: GCC_4.7.0</p></li><li class="listitem"><p>GCC 4.8.0: GCC_4.8.0</p></li></ul></div></li><li class="listitem"><p> Release versioning on the libstdc++.so binary, implemented in the same way as the libgcc_s.so binary above. Listed is the filename: <code class="constant">DT_SONAME</code> can be deduced from @@ -111,7 +111,7 @@ compatible. has the same filename and <code class="constant">DT_SONAME</code> as the preceding release. </p><p>It is versioned as follows: - </p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>GCC 3.0.0: libstdc++.so.3.0.0</p></li><li class="listitem"><p>GCC 3.0.1: libstdc++.so.3.0.1</p></li><li class="listitem"><p>GCC 3.0.2: libstdc++.so.3.0.2</p></li><li class="listitem"><p>GCC 3.0.3: libstdc++.so.3.0.2 (See Note 1)</p></li><li class="listitem"><p>GCC 3.0.4: libstdc++.so.3.0.4</p></li><li class="listitem"><p>GCC 3.1.0: libstdc++.so.4.0.0 <span class="emphasis"><em>(Incompatible with previous)</em></span></p></li><li class="listitem"><p>GCC 3.1.1: libstdc++.so.4.0.1</p></li><li class="listitem"><p>GCC 3.2.0: libstdc++.so.5.0.0 <span class="emphasis"><em>(Incompatible with previous)</em></span></p></li><li class="listitem"><p>GCC 3.2.1: libstdc++.so.5.0.1</p></li><li class="listitem"><p>GCC 3.2.2: libstdc++.so.5.0.2</p></li><li class="listitem"><p>GCC 3.2.3: libstdc++.so.5.0.3 (See Note 2)</p></li><li class="listitem"><p>GCC 3.3.0: libstdc++.so.5.0.4</p></li><li class="listitem"><p>GCC 3.3.1: libstdc++.so.5.0.5</p></li><li class="listitem"><p>GCC 3.4.0: libstdc++.so.6.0.0 <span class="emphasis"><em>(Incompatible with previous)</em></span></p></li><li class="listitem"><p>GCC 3.4.1: libstdc++.so.6.0.1</p></li><li class="listitem"><p>GCC 3.4.2: libstdc++.so.6.0.2</p></li><li class="listitem"><p>GCC 3.4.3: libstdc++.so.6.0.3</p></li><li class="listitem"><p>GCC 4.0.0: libstdc++.so.6.0.4</p></li><li class="listitem"><p>GCC 4.0.1: libstdc++.so.6.0.5</p></li><li class="listitem"><p>GCC 4.0.2: libstdc++.so.6.0.6</p></li><li class="listitem"><p>GCC 4.0.3: libstdc++.so.6.0.7</p></li><li class="listitem"><p>GCC 4.1.0: libstdc++.so.6.0.7</p></li><li class="listitem"><p>GCC 4.1.1: libstdc++.so.6.0.8</p></li><li class="listitem"><p>GCC 4.2.0: libstdc++.so.6.0.9</p></li><li class="listitem"><p>GCC 4.2.1: libstdc++.so.6.0.9 (See Note 3)</p></li><li class="listitem"><p>GCC 4.2.2: libstdc++.so.6.0.9</p></li><li class="listitem"><p>GCC 4.3.0: libstdc++.so.6.0.10</p></li><li class="listitem"><p>GCC 4.4.0: libstdc++.so.6.0.11</p></li><li class="listitem"><p>GCC 4.4.1: libstdc++.so.6.0.12</p></li><li class="listitem"><p>GCC 4.4.2: libstdc++.so.6.0.13</p></li><li class="listitem"><p>GCC 4.5.0: libstdc++.so.6.0.14</p></li><li class="listitem"><p>GCC 4.6.0: libstdc++.so.6.0.15</p></li><li class="listitem"><p>GCC 4.6.1: libstdc++.so.6.0.16</p></li><li class="listitem"><p>GCC 4.7.0: libstdc++.so.6.0.17</p></li><li class="listitem"><p>GCC 4.8.0: libstdc++.so.6.0.18</p></li></ul></div><p> + </p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>GCC 3.0.0: libstdc++.so.3.0.0</p></li><li class="listitem"><p>GCC 3.0.1: libstdc++.so.3.0.1</p></li><li class="listitem"><p>GCC 3.0.2: libstdc++.so.3.0.2</p></li><li class="listitem"><p>GCC 3.0.3: libstdc++.so.3.0.2 (See Note 1)</p></li><li class="listitem"><p>GCC 3.0.4: libstdc++.so.3.0.4</p></li><li class="listitem"><p>GCC 3.1.0: libstdc++.so.4.0.0 <span class="emphasis"><em>(Incompatible with previous)</em></span></p></li><li class="listitem"><p>GCC 3.1.1: libstdc++.so.4.0.1</p></li><li class="listitem"><p>GCC 3.2.0: libstdc++.so.5.0.0 <span class="emphasis"><em>(Incompatible with previous)</em></span></p></li><li class="listitem"><p>GCC 3.2.1: libstdc++.so.5.0.1</p></li><li class="listitem"><p>GCC 3.2.2: libstdc++.so.5.0.2</p></li><li class="listitem"><p>GCC 3.2.3: libstdc++.so.5.0.3 (See Note 2)</p></li><li class="listitem"><p>GCC 3.3.0: libstdc++.so.5.0.4</p></li><li class="listitem"><p>GCC 3.3.1: libstdc++.so.5.0.5</p></li><li class="listitem"><p>GCC 3.4.0: libstdc++.so.6.0.0 <span class="emphasis"><em>(Incompatible with previous)</em></span></p></li><li class="listitem"><p>GCC 3.4.1: libstdc++.so.6.0.1</p></li><li class="listitem"><p>GCC 3.4.2: libstdc++.so.6.0.2</p></li><li class="listitem"><p>GCC 3.4.3: libstdc++.so.6.0.3</p></li><li class="listitem"><p>GCC 4.0.0: libstdc++.so.6.0.4</p></li><li class="listitem"><p>GCC 4.0.1: libstdc++.so.6.0.5</p></li><li class="listitem"><p>GCC 4.0.2: libstdc++.so.6.0.6</p></li><li class="listitem"><p>GCC 4.0.3: libstdc++.so.6.0.7</p></li><li class="listitem"><p>GCC 4.1.0: libstdc++.so.6.0.7</p></li><li class="listitem"><p>GCC 4.1.1: libstdc++.so.6.0.8</p></li><li class="listitem"><p>GCC 4.2.0: libstdc++.so.6.0.9</p></li><li class="listitem"><p>GCC 4.2.1: libstdc++.so.6.0.9 (See Note 3)</p></li><li class="listitem"><p>GCC 4.2.2: libstdc++.so.6.0.9</p></li><li class="listitem"><p>GCC 4.3.0: libstdc++.so.6.0.10</p></li><li class="listitem"><p>GCC 4.4.0: libstdc++.so.6.0.11</p></li><li class="listitem"><p>GCC 4.4.1: libstdc++.so.6.0.12</p></li><li class="listitem"><p>GCC 4.4.2: libstdc++.so.6.0.13</p></li><li class="listitem"><p>GCC 4.5.0: libstdc++.so.6.0.14</p></li><li class="listitem"><p>GCC 4.6.0: libstdc++.so.6.0.15</p></li><li class="listitem"><p>GCC 4.6.1: libstdc++.so.6.0.16</p></li><li class="listitem"><p>GCC 4.7.0: libstdc++.so.6.0.17</p></li><li class="listitem"><p>GCC 4.8.0: libstdc++.so.6.0.18</p></li><li class="listitem"><p>GCC 4.8.3: libstdc++.so.6.0.19</p></li></ul></div><p> Note 1: Error should be libstdc++.so.3.0.3. </p><p> Note 2: Not strictly required. @@ -129,7 +129,7 @@ compatible. GLIBCPP_3.2 for symbols that were introduced in the GCC 3.2.0 release.) If a particular release is not listed, it has the same version labels as the preceding release. - </p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>GCC 3.0.0: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.0.1: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.0.2: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.0.3: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.0.4: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.1.0: GLIBCPP_3.1, CXXABI_1</p></li><li class="listitem"><p>GCC 3.1.1: GLIBCPP_3.1, CXXABI_1</p></li><li class="listitem"><p>GCC 3.2.0: GLIBCPP_3.2, CXXABI_1.2</p></li><li class="listitem"><p>GCC 3.2.1: GLIBCPP_3.2.1, CXXABI_1.2</p></li><li class="listitem"><p>GCC 3.2.2: GLIBCPP_3.2.2, CXXABI_1.2</p></li><li class="listitem"><p>GCC 3.2.3: GLIBCPP_3.2.2, CXXABI_1.2</p></li><li class="listitem"><p>GCC 3.3.0: GLIBCPP_3.2.2, CXXABI_1.2.1</p></li><li class="listitem"><p>GCC 3.3.1: GLIBCPP_3.2.3, CXXABI_1.2.1</p></li><li class="listitem"><p>GCC 3.3.2: GLIBCPP_3.2.3, CXXABI_1.2.1</p></li><li class="listitem"><p>GCC 3.3.3: GLIBCPP_3.2.3, CXXABI_1.2.1</p></li><li class="listitem"><p>GCC 3.4.0: GLIBCXX_3.4, CXXABI_1.3</p></li><li class="listitem"><p>GCC 3.4.1: GLIBCXX_3.4.1, CXXABI_1.3</p></li><li class="listitem"><p>GCC 3.4.2: GLIBCXX_3.4.2</p></li><li class="listitem"><p>GCC 3.4.3: GLIBCXX_3.4.3</p></li><li class="listitem"><p>GCC 4.0.0: GLIBCXX_3.4.4, CXXABI_1.3.1</p></li><li class="listitem"><p>GCC 4.0.1: GLIBCXX_3.4.5</p></li><li class="listitem"><p>GCC 4.0.2: GLIBCXX_3.4.6</p></li><li class="listitem"><p>GCC 4.0.3: GLIBCXX_3.4.7</p></li><li class="listitem"><p>GCC 4.1.1: GLIBCXX_3.4.8</p></li><li class="listitem"><p>GCC 4.2.0: GLIBCXX_3.4.9</p></li><li class="listitem"><p>GCC 4.3.0: GLIBCXX_3.4.10, CXXABI_1.3.2</p></li><li class="listitem"><p>GCC 4.4.0: GLIBCXX_3.4.11, CXXABI_1.3.3</p></li><li class="listitem"><p>GCC 4.4.1: GLIBCXX_3.4.12, CXXABI_1.3.3</p></li><li class="listitem"><p>GCC 4.4.2: GLIBCXX_3.4.13, CXXABI_1.3.3</p></li><li class="listitem"><p>GCC 4.5.0: GLIBCXX_3.4.14, CXXABI_1.3.4</p></li><li class="listitem"><p>GCC 4.6.0: GLIBCXX_3.4.15, CXXABI_1.3.5</p></li><li class="listitem"><p>GCC 4.6.1: GLIBCXX_3.4.16, CXXABI_1.3.5</p></li><li class="listitem"><p>GCC 4.7.0: GLIBCXX_3.4.17, CXXABI_1.3.6</p></li><li class="listitem"><p>GCC 4.8.0: GLIBCXX_3.4.18, CXXABI_1.3.7</p></li></ul></div></li><li class="listitem"><p>Incremental bumping of a compiler pre-defined macro, + </p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>GCC 3.0.0: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.0.1: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.0.2: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.0.3: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.0.4: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.1.0: GLIBCPP_3.1, CXXABI_1</p></li><li class="listitem"><p>GCC 3.1.1: GLIBCPP_3.1, CXXABI_1</p></li><li class="listitem"><p>GCC 3.2.0: GLIBCPP_3.2, CXXABI_1.2</p></li><li class="listitem"><p>GCC 3.2.1: GLIBCPP_3.2.1, CXXABI_1.2</p></li><li class="listitem"><p>GCC 3.2.2: GLIBCPP_3.2.2, CXXABI_1.2</p></li><li class="listitem"><p>GCC 3.2.3: GLIBCPP_3.2.2, CXXABI_1.2</p></li><li class="listitem"><p>GCC 3.3.0: GLIBCPP_3.2.2, CXXABI_1.2.1</p></li><li class="listitem"><p>GCC 3.3.1: GLIBCPP_3.2.3, CXXABI_1.2.1</p></li><li class="listitem"><p>GCC 3.3.2: GLIBCPP_3.2.3, CXXABI_1.2.1</p></li><li class="listitem"><p>GCC 3.3.3: GLIBCPP_3.2.3, CXXABI_1.2.1</p></li><li class="listitem"><p>GCC 3.4.0: GLIBCXX_3.4, CXXABI_1.3</p></li><li class="listitem"><p>GCC 3.4.1: GLIBCXX_3.4.1, CXXABI_1.3</p></li><li class="listitem"><p>GCC 3.4.2: GLIBCXX_3.4.2</p></li><li class="listitem"><p>GCC 3.4.3: GLIBCXX_3.4.3</p></li><li class="listitem"><p>GCC 4.0.0: GLIBCXX_3.4.4, CXXABI_1.3.1</p></li><li class="listitem"><p>GCC 4.0.1: GLIBCXX_3.4.5</p></li><li class="listitem"><p>GCC 4.0.2: GLIBCXX_3.4.6</p></li><li class="listitem"><p>GCC 4.0.3: GLIBCXX_3.4.7</p></li><li class="listitem"><p>GCC 4.1.1: GLIBCXX_3.4.8</p></li><li class="listitem"><p>GCC 4.2.0: GLIBCXX_3.4.9</p></li><li class="listitem"><p>GCC 4.3.0: GLIBCXX_3.4.10, CXXABI_1.3.2</p></li><li class="listitem"><p>GCC 4.4.0: GLIBCXX_3.4.11, CXXABI_1.3.3</p></li><li class="listitem"><p>GCC 4.4.1: GLIBCXX_3.4.12, CXXABI_1.3.3</p></li><li class="listitem"><p>GCC 4.4.2: GLIBCXX_3.4.13, CXXABI_1.3.3</p></li><li class="listitem"><p>GCC 4.5.0: GLIBCXX_3.4.14, CXXABI_1.3.4</p></li><li class="listitem"><p>GCC 4.6.0: GLIBCXX_3.4.15, CXXABI_1.3.5</p></li><li class="listitem"><p>GCC 4.6.1: GLIBCXX_3.4.16, CXXABI_1.3.5</p></li><li class="listitem"><p>GCC 4.7.0: GLIBCXX_3.4.17, CXXABI_1.3.6</p></li><li class="listitem"><p>GCC 4.8.0: GLIBCXX_3.4.18, CXXABI_1.3.7</p></li><li class="listitem"><p>GCC 4.8.3: GLIBCXX_3.4.19, CXXABI_1.3.7</p></li></ul></div></li><li class="listitem"><p>Incremental bumping of a compiler pre-defined macro, __GXX_ABI_VERSION. This macro is defined as the version of the compiler v3 ABI, with g++ 3.0 being version 100. This macro will be automatically defined whenever g++ is used (the curious can diff --git a/libstdc++-v3/doc/html/manual/containers.html b/libstdc++-v3/doc/html/manual/containers.html index 6c84f020b37..e1de388e8a3 100644 --- a/libstdc++-v3/doc/html/manual/containers.html +++ b/libstdc++-v3/doc/html/manual/containers.html @@ -7,9 +7,10 @@ </th><td width="20%" align="right"> <a accesskey="n" href="associative.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.containers"></a>Chapter 9. Containers <a id="idm269999493408" class="indexterm"></a> -</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd><dt><span class="section"><a href="containers.html#containers.sequences.vector">vector</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.vector.management">Space Overhead Management</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.containers.sequences"></a>Sequences</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="containers.sequences.list"></a>list</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="sequences.list.size"></a>list::size() is O(n)</h4></div></div></div><p> - Yes it is, and that's okay. This is a decision that we preserved - when we imported SGI's STL implementation. The following is +</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.containers.sequences"></a>Sequences</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="containers.sequences.list"></a>list</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="sequences.list.size"></a>list::size() is O(n)</h4></div></div></div><p> + Yes it is, and that was okay until the 2011 edition of the C++ standard. + In future GCC will change it to O(1) but O(N) was a decision that we + preserved when we imported SGI's STL implementation. The following is quoted from <a class="link" href="http://www.sgi.com/tech/stl/FAQ.html" target="_top">their FAQ</a>: </p><div class="blockquote"><blockquote class="blockquote"><p> The size() member function, for list and slist, takes time @@ -41,14 +42,4 @@ </p><pre class="programlisting"> if (L.empty()) ... - </pre></blockquote></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="containers.sequences.vector"></a>vector</h3></div></div></div><p> - </p><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="sequences.vector.management"></a>Space Overhead Management</h4></div></div></div><p> - In <a class="link" href="http://gcc.gnu.org/ml/libstdc++/2002-04/msg00105.html" target="_top">this - message to the list</a>, Daniel Kostecky announced work on an - alternate form of <code class="code">std::vector</code> that would support - hints on the number of elements to be over-allocated. The design - was also described, along with possible implementation choices. - </p><p> - The first two alpha releases were announced <a class="link" href="http://gcc.gnu.org/ml/libstdc++/2002-07/msg00048.html" target="_top">here</a> - and <a class="link" href="http://gcc.gnu.org/ml/libstdc++/2002-07/msg00111.html" target="_top">here</a>. - </p></div></div></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="facets.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="std_contents.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="associative.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Facets </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Associative</td></tr></table></div></body></html>
\ No newline at end of file + </pre></blockquote></div></div></div></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="facets.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="std_contents.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="associative.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Facets </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Associative</td></tr></table></div></body></html> diff --git a/libstdc++-v3/doc/html/manual/index.html b/libstdc++-v3/doc/html/manual/index.html index 8f9861b286f..dc8cfc43ae3 100644 --- a/libstdc++-v3/doc/html/manual/index.html +++ b/libstdc++-v3/doc/html/manual/index.html @@ -24,7 +24,7 @@ </a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales">Locales</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales.locale">locale</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locales.locale.req">Requirements</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.design">Design</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locale.impl.c">Interacting with "C" locales</a></span></dt></dl></dd><dt><span class="section"><a href="localization.html#locales.locale.future">Future</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="facets.html">Facets</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#std.localization.facet.ctype">ctype</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.ctype.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#idm269999753024">Specializations</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.ctype.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#std.localization.facet.codecvt">codecvt</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.codecvt.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#codecvt.design.wchar_t_size"><span class="type">wchar_t</span> Size</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.unicode">Support for Unicode</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.issues">Other Issues</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.codecvt.impl">Implementation</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#manual.localization.facet.messages">messages</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.messages.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.design">Design</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#messages.impl.models">Models</a></span></dt><dt><span class="section"><a href="facets.html#messages.impl.gnu">The GNU Model</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.messages.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.future">Future</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="chapter"><a href="containers.html">9. Containers -</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd><dt><span class="section"><a href="containers.html#containers.sequences.vector">vector</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.vector.management">Space Overhead Management</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="iterators.html">10. +</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="iterators.html">10. Iterators </a></span></dt><dd><dl><dt><span class="section"><a href="iterators.html#std.iterators.predefined">Predefined</a></span></dt><dd><dl><dt><span class="section"><a href="iterators.html#iterators.predefined.vs_pointers">Iterators vs. Pointers</a></span></dt><dt><span class="section"><a href="iterators.html#iterators.predefined.end">One Past the End</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="algorithms.html">11. @@ -160,4 +160,4 @@ Support for C++11 dialect. </a></dt></dl></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="../index.html">Prev</a> </td><td width="20%" align="center"> </td><td width="40%" align="right"> <a accesskey="n" href="intro.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">The GNU C++ Library </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Part I. Introduction -</td></tr></table></div></body></html>
\ No newline at end of file +</td></tr></table></div></body></html> diff --git a/libstdc++-v3/doc/html/manual/status.html b/libstdc++-v3/doc/html/manual/status.html index b14e331fbfc..a0d247f901e 100644 --- a/libstdc++-v3/doc/html/manual/status.html +++ b/libstdc++-v3/doc/html/manual/status.html @@ -165,7 +165,8 @@ particular release. <code class="code">set_new_handler</code> is not thread-safe. </td></tr><tr><td align="left">18.7</td><td align="left">Type identification</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">18.7.1</td><td align="left">Class type_info</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">18.7.2</td><td align="left">Class bad_cast</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">18.7.3</td><td align="left">Class bad_typeid</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">18.8</td><td align="left">Exception handling</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">18.8.1</td><td align="left">Class exception</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">18.8.2</td><td align="left">Class bad_exception</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">18.8.3</td><td align="left">Abnormal termination</td><td align="left">Partial</td><td align="left">Missing <code class="code">get_terminate</code>. <code class="code">set_terminate</code> is not thread-safe. - </td></tr><tr><td align="left">18.8.4</td><td align="left"><code class="code">uncaught_exception</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">18.8.5</td><td align="left">Exception Propagation</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">18.8.6</td><td align="left"><code class="code">nested_exception</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">18.9</td><td align="left">Initializer lists</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">18.9.1</td><td align="left">Initializer list constructors</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">18.9.2</td><td align="left">Initializer list access</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">18.9.3</td><td align="left">Initializer list range access</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">18.10</td><td align="left">Other runtime support</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left"> + </td></tr><tr><td align="left">18.8.4</td><td align="left"><code class="code">uncaught_exception</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">18.8.5</td><td align="left">Exception Propagation</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">18.8.6</td><td align="left"><code class="code">nested_exception</code></td><td align="left">Partial</td><td align="left">Follows an earlier C++0x draft, not the final specification. + </td></tr><tr><td align="left">18.9</td><td align="left">Initializer lists</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">18.9.1</td><td align="left">Initializer list constructors</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">18.9.2</td><td align="left">Initializer list access</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">18.9.3</td><td align="left">Initializer list range access</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">18.10</td><td align="left">Other runtime support</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left"> <span class="emphasis"><em>19</em></span> </td><td colspan="3" align="left"> <span class="emphasis"><em>Diagnostics</em></span> @@ -173,7 +174,7 @@ particular release. <span class="emphasis"><em>20</em></span> </td><td colspan="3" align="left"> <span class="emphasis"><em>General utilities</em></span> - </td></tr><tr><td align="left">20.1</td><td align="left">General</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.2</td><td align="left">Utility components</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.2.1</td><td align="left">Operators</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.2.2</td><td align="left">Swap</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.2.3</td><td align="left"><code class="code">forward</code> and <code class="code">move</code> helpers</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.2.4</td><td align="left">Function template <code class="code">declval</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.3</td><td align="left">Pairs</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.3.1</td><td align="left">In general</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.3.2</td><td align="left">Class template <code class="code">pair</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.3.3</td><td align="left">Specialized algorithms</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.3.4</td><td align="left">Tuple-like access to <code class="code">pair</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.3.5</td><td align="left">Piecewise construction</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.4</td><td align="left">Tuples</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.4.1</td><td align="left">In general</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.4.2</td><td align="left">Class template <code class="code">tuple</code></td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.4.2.1</td><td align="left">Construction</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.4.2.2</td><td align="left">Assignment</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.4.2.3</td><td align="left">Swap</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.4.2.4</td><td align="left">Tuple creation functions</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.4.2.5</td><td align="left">Tuple helper classes</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.4.2.6</td><td align="left">Element access</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.4.2.7</td><td align="left">Relational operators</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.4.2.8</td><td align="left">Tuple traits</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.4.2.9</td><td align="left">Tuple specialized algorithms</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.5</td><td align="left">Class template <code class="code">bitset</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.5.1</td><td align="left"><code class="code">bitset</code> constructors</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.5.2</td><td align="left"><code class="code">bitset</code> members</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.5.3</td><td align="left"><code class="code">bitset</code> hash support</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.5.4</td><td align="left"><code class="code">bitset</code> operators</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.6</td><td align="left">Memory</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.6.1</td><td align="left">In general</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.6.2</td><td align="left">Header <code class="code"><memory></code> synopsis</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.6.3</td><td align="left">Pointer traits</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">20.6.4</td><td align="left">Pointer safety</td><td align="left">Partial</td><td align="left"> </td></tr><tr bgcolor="#C8B0B0"><td align="left">20.6.5</td><td align="left">Align</td><td align="left">N</td><td align="left"> </td></tr><tr><td align="left">20.6.6</td><td align="left">Allocator argument tag</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.6.7</td><td align="left"><code class="code">uses_allocator</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.6.8</td><td align="left">Allocator traits</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.6.9</td><td align="left">The default allocator</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.6.10</td><td align="left">Raw storage iterator</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.6.11</td><td align="left">Temporary buffers</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.6.12</td><td align="left">Specialized algorithms</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.6.12.1</td><td align="left"><code class="code">addressof</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.6.12.2</td><td align="left"><code class="code">uninitialized_copy</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.6.12.3</td><td align="left"><code class="code">uninitialized_fill</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.6.12.4</td><td align="left"><code class="code">uninitialized_fill_n</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.6.13</td><td align="left">C library</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.7</td><td align="left">Smart pointers</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.7.1</td><td align="left">Class template <code class="code">unique_ptr</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.7.2</td><td align="left">Shared-ownership pointers</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.7.2.1</td><td align="left">Class <code class="code">bad_weak_ptr</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.7.2.2</td><td align="left">Class template <code class="code">shared_ptr</code></td><td align="left">Y</td><td align="left"> + </td></tr><tr><td align="left">20.1</td><td align="left">General</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.2</td><td align="left">Utility components</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.2.1</td><td align="left">Operators</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.2.2</td><td align="left">Swap</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.2.3</td><td align="left"><code class="code">forward</code> and <code class="code">move</code> helpers</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.2.4</td><td align="left">Function template <code class="code">declval</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.3</td><td align="left">Pairs</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.3.1</td><td align="left">In general</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.3.2</td><td align="left">Class template <code class="code">pair</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.3.3</td><td align="left">Specialized algorithms</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.3.4</td><td align="left">Tuple-like access to <code class="code">pair</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.3.5</td><td align="left">Piecewise construction</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.4</td><td align="left">Tuples</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.4.1</td><td align="left">In general</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.4.2</td><td align="left">Class template <code class="code">tuple</code></td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.4.2.1</td><td align="left">Construction</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.4.2.2</td><td align="left">Assignment</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.4.2.3</td><td align="left">Swap</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.4.2.4</td><td align="left">Tuple creation functions</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.4.2.5</td><td align="left">Tuple helper classes</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.4.2.6</td><td align="left">Element access</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.4.2.7</td><td align="left">Relational operators</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.4.2.8</td><td align="left">Tuple traits</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.4.2.9</td><td align="left">Tuple specialized algorithms</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.5</td><td align="left">Class template <code class="code">bitset</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.5.1</td><td align="left"><code class="code">bitset</code> constructors</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.5.2</td><td align="left"><code class="code">bitset</code> members</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.5.3</td><td align="left"><code class="code">bitset</code> hash support</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.5.4</td><td align="left"><code class="code">bitset</code> operators</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.6</td><td align="left">Memory</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.6.1</td><td align="left">In general</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.6.2</td><td align="left">Header <code class="code"><memory></code> synopsis</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.6.3</td><td align="left">Pointer traits</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">20.6.4</td><td align="left">Pointer safety</td><td align="left">Partial</td><td align="left"> </td></tr><tr bgcolor="#C8B0B0"><td align="left">20.6.5</td><td align="left">Align</td><td align="left">N</td><td align="left"> </td></tr><tr><td align="left">20.6.6</td><td align="left">Allocator argument tag</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.6.7</td><td align="left"><code class="code">uses_allocator</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.6.8</td><td align="left">Allocator traits</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.6.9</td><td align="left">The default allocator</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.6.10</td><td align="left">Raw storage iterator</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.6.11</td><td align="left">Temporary buffers</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.6.12</td><td align="left">Specialized algorithms</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.6.12.1</td><td align="left"><code class="code">addressof</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.6.12.2</td><td align="left"><code class="code">uninitialized_copy</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.6.12.3</td><td align="left"><code class="code">uninitialized_fill</code></td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">20.6.12.4</td><td align="left"><code class="code">uninitialized_fill_n</code></td><td align="left">Partial</td><td align="left">Returns <code class="code">void</code>.</td></tr><tr><td align="left">20.6.13</td><td align="left">C library</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.7</td><td align="left">Smart pointers</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">20.7.1</td><td align="left">Class template <code class="code">unique_ptr</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.7.2</td><td align="left">Shared-ownership pointers</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.7.2.1</td><td align="left">Class <code class="code">bad_weak_ptr</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">20.7.2.2</td><td align="left">Class template <code class="code">shared_ptr</code></td><td align="left">Y</td><td align="left"> <p> Uses code from <a class="link" href="http://www.boost.org/libs/smart_ptr/shared_ptr.htm" target="_top">boost::shared_ptr</a>. @@ -187,22 +188,26 @@ particular release. <span class="emphasis"><em>21</em></span> </td><td colspan="3" align="left"> <span class="emphasis"><em>Strings</em></span> - </td></tr><tr><td align="left">21.1</td><td align="left">General</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">21.2</td><td align="left">Character traits</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">21.2.1</td><td align="left">Character traits requirements</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">21.2.2</td><td align="left">traits typedefs</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">21.2.3</td><td align="left"><code class="code">char_traits</code> specializations</td><td align="left"> </td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">21.2.3.1</td><td align="left">struct <code class="code">char_traits<char></code></td><td align="left">Partial</td><td align="left">Missing constexpr</td></tr><tr bgcolor="#B0B0B0"><td align="left">21.2.3.2</td><td align="left">struct <code class="code">char_traits<char16_t></code></td><td align="left">Partial</td><td align="left">Missing constexpr</td></tr><tr><td align="left">21.2.3.3</td><td align="left">struct <code class="code">char_traits<char32_t></code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">21.2.3.4</td><td align="left">struct <code class="code">char_traits<wchar_t></code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">21.3</td><td align="left">String classes</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">21.4</td><td align="left">Class template <code class="code">basic_string</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">21.5</td><td align="left">Numeric Conversions</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">21.6</td><td align="left">Hash support</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">21.7</td><td align="left">Null-terminated sequence utilities</td><td align="left">Partial</td><td align="left">C library dependency. + </td></tr><tr><td align="left">21.1</td><td align="left">General</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">21.2</td><td align="left">Character traits</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">21.2.1</td><td align="left">Character traits requirements</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">21.2.2</td><td align="left">traits typedefs</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">21.2.3</td><td align="left"><code class="code">char_traits</code> specializations</td><td align="left"> </td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">21.2.3.1</td><td align="left">struct <code class="code">char_traits<char></code></td><td align="left">Partial</td><td align="left">Missing constexpr</td></tr><tr bgcolor="#B0B0B0"><td align="left">21.2.3.2</td><td align="left">struct <code class="code">char_traits<char16_t></code></td><td align="left">Partial</td><td align="left">Missing constexpr</td></tr><tr><td align="left">21.2.3.3</td><td align="left">struct <code class="code">char_traits<char32_t></code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">21.2.3.4</td><td align="left">struct <code class="code">char_traits<wchar_t></code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">21.3</td><td align="left">String classes</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">21.4</td><td align="left">Class template <code class="code">basic_string</code></td><td align="left">Partial</td><td align="left">Non-conforming Copy-On-Write implementation. + Missing <code class="code">getline</code> overloads for rvalue streams. + </td></tr><tr><td align="left">21.5</td><td align="left">Numeric Conversions</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">21.6</td><td align="left">Hash support</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">21.7</td><td align="left">Null-terminated sequence utilities</td><td align="left">Partial</td><td align="left">C library dependency. Missing <code class="filename"><cuchar></code> </td></tr><tr><td align="left"> <span class="emphasis"><em>22</em></span> </td><td colspan="3" align="left"> <span class="emphasis"><em>Localization</em></span> - </td></tr><tr><td align="left">22.1</td><td align="left">General</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.2</td><td align="left">Header <code class="code"><locale></code> synopsis</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.3</td><td align="left">Locales</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">22.3.1</td><td align="left">Class <code class="code">locale</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.3.2</td><td align="left"><code class="code">locale</code> globals</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.3.3</td><td align="left">Convenience interfaces</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">22.3.3.1</td><td align="left">Character classification</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.3.3.2</td><td align="left">Conversions</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">22.3.3.2.1</td><td align="left">Character conversions</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#C8B0B0"><td align="left">22.3.3.2.2</td><td align="left"><code class="code">string</code> conversions</td><td align="left">N</td><td align="left"> </td></tr><tr bgcolor="#C8B0B0"><td align="left">22.3.3.2.3</td><td align="left">Buffer conversions</td><td align="left">N</td><td align="left"> </td></tr><tr><td align="left">22.4</td><td align="left">Standard <code class="code">locale</code> categories</td><td align="left"> </td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">22.4.1</td><td align="left">The <code class="code">ctype</code> category</td><td align="left">Partial</td><td align="left">Missing <code class="code">codecvt<char16_t></code> and - <code class="code">codecvt<char32_t></code></td></tr><tr><td align="left">22.4.2</td><td align="left">The numeric category</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">22.4.2.1</td><td align="left"><code class="code">num_get</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.4.2.2</td><td align="left"><code class="code">num_put</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.4.3</td><td align="left">The numeric punctuation facet</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.4.4</td><td align="left">The collate category</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.4.5</td><td align="left">The time category</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">22.4.5.1</td><td align="left">Class template <code class="code">time_get</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.4.5.2</td><td align="left">Class template <code class="code">time_get_byname</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.4.5.3</td><td align="left">Class template <code class="code">time_put</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.4.5.3</td><td align="left">Class template <code class="code">time_put_byname</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.4.6</td><td align="left">The monetary category</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">22.4.6.1</td><td align="left">Class template <code class="code">money_get</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.4.6.2</td><td align="left">Class template <code class="code">money_put</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.4.6.3</td><td align="left">Class template <code class="code">money_punct</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.4.6.4</td><td align="left">Class template <code class="code">money_punct_byname</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.4.7</td><td align="left">The message retrieval category</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.4.8</td><td align="left">Program-defined facets</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#C8B0B0"><td align="left">22.5</td><td align="left">Standard code conversion facets</td><td align="left">N</td><td align="left"> </td></tr><tr><td align="left">22.6</td><td align="left">C Library Locales</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left"> + </td></tr><tr><td align="left">22.1</td><td align="left">General</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.2</td><td align="left">Header <code class="code"><locale></code> synopsis</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.3</td><td align="left">Locales</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">22.3.1</td><td align="left">Class <code class="code">locale</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.3.2</td><td align="left"><code class="code">locale</code> globals</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.3.3</td><td align="left">Convenience interfaces</td><td align="left"> </td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">22.3.3.1</td><td align="left">Character classification</td><td align="left">Partial</td><td align="left">Missing <code class="code">isblank</code>.</td></tr><tr><td align="left">22.3.3.2</td><td align="left">Conversions</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">22.3.3.2.1</td><td align="left">Character conversions</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#C8B0B0"><td align="left">22.3.3.2.2</td><td align="left"><code class="code">string</code> conversions</td><td align="left">N</td><td align="left"> </td></tr><tr bgcolor="#C8B0B0"><td align="left">22.3.3.2.3</td><td align="left">Buffer conversions</td><td align="left">N</td><td align="left"> </td></tr><tr><td align="left">22.4</td><td align="left">Standard <code class="code">locale</code> categories</td><td align="left"> </td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">22.4.1</td><td align="left">The <code class="code">ctype</code> category</td><td align="left">Partial</td><td align="left">Missing <code class="code">codecvt<char16_t></code> and + <code class="code">codecvt<char32_t></code></td></tr><tr><td align="left">22.4.2</td><td align="left">The numeric category</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">22.4.2.1</td><td align="left"><code class="code">num_get</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.4.2.2</td><td align="left"><code class="code">num_put</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.4.3</td><td align="left">The numeric punctuation facet</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.4.4</td><td align="left">The collate category</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.4.5</td><td align="left">The time category</td><td align="left"> </td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">22.4.5.1</td><td align="left">Class template <code class="code">time_get</code></td><td align="left">Partial</td><td align="left">Missing <code class="code">get</code> and <code class="code">do_get</code></td></tr><tr bgcolor="#B0B0B0"><td align="left">22.4.5.2</td><td align="left">Class template <code class="code">time_get_byname</code></td><td align="left">Partial</td><td align="left">Likewise</td></tr><tr><td align="left">22.4.5.3</td><td align="left">Class template <code class="code">time_put</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.4.5.3</td><td align="left">Class template <code class="code">time_put_byname</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.4.6</td><td align="left">The monetary category</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">22.4.6.1</td><td align="left">Class template <code class="code">money_get</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.4.6.2</td><td align="left">Class template <code class="code">money_put</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.4.6.3</td><td align="left">Class template <code class="code">money_punct</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.4.6.4</td><td align="left">Class template <code class="code">money_punct_byname</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.4.7</td><td align="left">The message retrieval category</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">22.4.8</td><td align="left">Program-defined facets</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#C8B0B0"><td align="left">22.5</td><td align="left">Standard code conversion facets</td><td align="left">N</td><td align="left"> </td></tr><tr><td align="left">22.6</td><td align="left">C Library Locales</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left"> <span class="emphasis"><em>23</em></span> </td><td colspan="3" align="left"> <span class="emphasis"><em>Containers</em></span> </td></tr><tr><td align="left">23.1</td><td align="left">General</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">23.2</td><td align="left">Container requirements</td><td align="left"> </td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">23.2.1</td><td align="left">General container requirements</td><td align="left">Partial</td><td align="left">Only <code class="code">vector</code> and <code class="code">forward_list</code> meet the requirements relating to allocator use and propagation.</td></tr><tr><td align="left">23.2.2</td><td align="left">Container data races</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">23.2.3</td><td align="left">Sequence containers</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">23.2.4</td><td align="left">Associative containers</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">23.2.5</td><td align="left">Unordered associative containers</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">23.3</td><td align="left">Sequence containers</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">23.3.2</td><td align="left">Class template <code class="code">array</code></td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">23.3.3</td><td align="left">Class template <code class="code">deque</code></td><td align="left">Partial</td><td align="left"><code class="code">insert</code> and <code class="code">erase</code> members do not - take <code class="code">const_iterator</code> arguments (N2350).</td></tr><tr><td align="left">23.3.4</td><td align="left">Class template <code class="code">forward_list</code></td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">23.3.5</td><td align="left">Class template <code class="code">list</code></td><td align="left">Partial</td><td align="left"><code class="code">insert</code> and <code class="code">erase</code> members do not - take <code class="code">const_iterator</code> arguments (N2350).</td></tr><tr bgcolor="#B0B0B0"><td align="left">23.3.6</td><td align="left">Class template <code class="code">vector</code></td><td align="left">Partial</td><td align="left"><code class="code">insert</code> and <code class="code">erase</code> members do not + take <code class="code">const_iterator</code> arguments (N2350).</td></tr><tr><td align="left">23.3.4</td><td align="left">Class template <code class="code">forward_list</code></td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">23.3.5</td><td align="left">Class template <code class="code">list</code></td><td align="left">Partial</td><td align="left">O(N) size. + <code class="code">insert</code> and <code class="code">erase</code> members do not + take <code class="code">const_iterator</code> arguments (N2350). + </td></tr><tr bgcolor="#B0B0B0"><td align="left">23.3.6</td><td align="left">Class template <code class="code">vector</code></td><td align="left">Partial</td><td align="left"><code class="code">insert</code> and <code class="code">erase</code> members do not take <code class="code">const_iterator</code> arguments (N2350).</td></tr><tr bgcolor="#B0B0B0"><td align="left">23.3.7</td><td align="left">Class <code class="code">vector<bool></code></td><td align="left">Partial</td><td align="left"><code class="code">insert</code> and <code class="code">erase</code> members do not take <code class="code">const_iterator</code> arguments (N2350).</td></tr><tr><td align="left">23.4</td><td align="left">Associative containers</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">23.4.4</td><td align="left">Class template <code class="code">map</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">23.4.5</td><td align="left">Class template <code class="code">multimap</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">23.4.6</td><td align="left">Class template <code class="code">set</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">23.4.7</td><td align="left">Class template <code class="code">multiset</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">23.5</td><td align="left">Unordered associative containers</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">23.5.4</td><td align="left">Class template <code class="code">unordered_map</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">23.5.5</td><td align="left">Class template <code class="code">unordered_multimap</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">23.5.6</td><td align="left">Class template <code class="code">unordered_set</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">23.5.7</td><td align="left">Class template <code class="code">unordered_multiset</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">23.6</td><td align="left">Container adaptors</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">23.6.1</td><td align="left">Class template <code class="code">queue</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">23.6.2</td><td align="left">Class template <code class="code">priority_queue</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">23.6.3</td><td align="left">Class template <code class="code">stack</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left"> <span class="emphasis"><em>24</em></span> @@ -212,11 +217,13 @@ particular release. <span class="emphasis"><em>25</em></span> </td><td colspan="3" align="left"> <span class="emphasis"><em>Algorithms</em></span> - </td></tr><tr><td align="left">25.1</td><td align="left">General</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">25.2</td><td align="left">Non-modifying sequence operations</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">25.3</td><td align="left">Mutating sequence operations</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">25.4</td><td align="left">Sorting and related operations</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">25.5</td><td align="left">C library algorithms</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left"> + </td></tr><tr><td align="left">25.1</td><td align="left">General</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">25.2</td><td align="left">Non-modifying sequence operations</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">25.3</td><td align="left">Mutating sequence operations</td><td align="left">Partial</td><td align="left"><code class="code">rotate</code> returns <code class="code">void</code>.</td></tr><tr><td align="left">25.4</td><td align="left">Sorting and related operations</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">25.5</td><td align="left">C library algorithms</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left"> <span class="emphasis"><em>26</em></span> </td><td colspan="3" align="left"> <span class="emphasis"><em>Numerics</em></span> - </td></tr><tr><td align="left">26.1</td><td align="left">General</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.2</td><td align="left">Numeric type requirements</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.3</td><td align="left">The floating-point environment</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.4</td><td align="left">Complex numbers</td><td align="left">Partial</td><td align="left">Missing constexpr</td></tr><tr><td align="left">26.5</td><td align="left">Random number generation</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.5.1</td><td align="left">Requirements</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.5.2</td><td align="left">Header <code class="code"><random></code> synopsis</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.5.3</td><td align="left">Random number engine class templates</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.5.3.1</td><td align="left">Class template <code class="code">linear_congruential_engine</code></td><td align="left">Y</td><td align="left">Missing constexpr</td></tr><tr><td align="left">26.5.3.2</td><td align="left">Class template <code class="code">mersenne_twister_engine</code></td><td align="left">Y</td><td align="left">Missing constexpr</td></tr><tr><td align="left">26.5.3.3</td><td align="left">Class template <code class="code">subtract_with_carry_engine</code></td><td align="left">Y</td><td align="left">Missing constexpr</td></tr><tr><td align="left">26.5.4</td><td align="left">Random number engine adaptor class templates</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.5.4.2</td><td align="left">Class template <code class="code">discard_block_engine</code></td><td align="left">Y</td><td align="left">Missing constexpr</td></tr><tr><td align="left">26.5.4.3</td><td align="left">Class template <code class="code">independent_bits_engine</code></td><td align="left">Y</td><td align="left">Missing constexpr</td></tr><tr><td align="left">26.5.4.4</td><td align="left">Class template <code class="code">shuffle_order_engine</code></td><td align="left">Y</td><td align="left">Missing constexpr</td></tr><tr><td align="left">26.5.5</td><td align="left">Engines and engine adaptors with predefined parameters</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.6</td><td align="left">Class <code class="code">random_device</code></td><td align="left">Y</td><td align="left">Missing constexpr</td></tr><tr><td align="left">26.5.7</td><td align="left">Utilities</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.5.7.1</td><td align="left">Class <code class="code">seed_seq</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.7.2</td><td align="left">Function template <code class="code">generate_canonical</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8</td><td align="left">Random number distribution class templates</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.5.8.2</td><td align="left">Uniform distributions</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.5.8.2.1</td><td align="left">Class template <code class="code">uniform_int_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.2.2</td><td align="left">Class template <code class="code">uniform_real_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.3</td><td align="left">Bernoulli distributions</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.5.8.3.1</td><td align="left">Class <code class="code">bernoulli_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.3.2</td><td align="left">Class template <code class="code">binomial_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.3.3</td><td align="left">Class template <code class="code">geometric_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.3.4</td><td align="left">Class template <code class="code">negative_binomial_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.4</td><td align="left">Poisson distributions</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.5.8.4.1</td><td align="left">Class template <code class="code">poisson_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.4.2</td><td align="left">Class template <code class="code">exponential_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.4.3</td><td align="left">Class template <code class="code">gamma_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.4.4</td><td align="left">Class template <code class="code">weibull_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.4.5</td><td align="left">Class template <code class="code">extreme_value_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.5</td><td align="left">Normal distributions</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.5.8.5.1</td><td align="left">Class template <code class="code">normal_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.5.2</td><td align="left">Class template <code class="code">lognormal_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.5.3</td><td align="left">Class template <code class="code">chi_squared_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.5.4</td><td align="left">Class template <code class="code">cauchy_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.5.5</td><td align="left">Class template <code class="code">fisher_f_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.5.6</td><td align="left">Class template <code class="code">student_t_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.6</td><td align="left">Sampling distributions</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.5.8.6.1</td><td align="left">Class template <code class="code">discrete_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.6.2</td><td align="left">Class template <code class="code">piecewise_constant_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.6.3</td><td align="left">Class template <code class="code">piecewise_linear_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.6</td><td align="left">Numeric arrays</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.6.1</td><td align="left">Header <code class="code"><valarray></code> synopsis</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.6.2</td><td align="left">Class template <code class="code">valarray</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.6.3</td><td align="left"><code class="code">valarray</code> non-member operations</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.6.4</td><td align="left">Class <code class="code">slice</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.6.5</td><td align="left">Class template <code class="code">slice_array</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.6.6</td><td align="left">The <code class="code">gslice</code> class</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.6.7</td><td align="left">Class template <code class="code">gslice_array</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.6.8</td><td align="left">Class template <code class="code">mask_array</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.6.9</td><td align="left">Class template <code class="code">indirect_array</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.6.10</td><td align="left"><code class="code">valarray</code> range access</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.7</td><td align="left">Generalized numeric operations</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.7.1</td><td align="left">Header <code class="code"><numeric></code> synopsis</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.7.2</td><td align="left"><code class="code">accumulate</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.7.3</td><td align="left"><code class="code">inner_product</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.7.4</td><td align="left"><code class="code">partial_sum</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.7.5</td><td align="left"><code class="code">adjacent_difference</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.7.6</td><td align="left">iota</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.8</td><td align="left">C Library</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left"> + </td></tr><tr><td align="left">26.1</td><td align="left">General</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.2</td><td align="left">Numeric type requirements</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.3</td><td align="left">The floating-point environment</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.4</td><td align="left">Complex numbers</td><td align="left">Partial</td><td align="left">Missing constexpr</td></tr><tr><td align="left">26.5</td><td align="left">Random number generation</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.5.1</td><td align="left">Requirements</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.5.2</td><td align="left">Header <code class="code"><random></code> synopsis</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.5.3</td><td align="left">Random number engine class templates</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.5.3.1</td><td align="left">Class template <code class="code">linear_congruential_engine</code></td><td align="left">Y</td><td align="left">Missing constexpr</td></tr><tr><td align="left">26.5.3.2</td><td align="left">Class template <code class="code">mersenne_twister_engine</code></td><td align="left">Y</td><td align="left">Missing constexpr</td></tr><tr><td align="left">26.5.3.3</td><td align="left">Class template <code class="code">subtract_with_carry_engine</code></td><td align="left">Y</td><td align="left">Missing constexpr</td></tr><tr><td align="left">26.5.4</td><td align="left">Random number engine adaptor class templates</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.5.4.2</td><td align="left">Class template <code class="code">discard_block_engine</code></td><td align="left">Y</td><td align="left">Missing constexpr</td></tr><tr><td align="left">26.5.4.3</td><td align="left">Class template <code class="code">independent_bits_engine</code></td><td align="left">Y</td><td align="left">Missing constexpr</td></tr><tr><td align="left">26.5.4.4</td><td align="left">Class template <code class="code">shuffle_order_engine</code></td><td align="left">Y</td><td align="left">Missing constexpr</td></tr><tr><td align="left">26.5.5</td><td align="left">Engines and engine adaptors with predefined parameters</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.6</td><td align="left">Class <code class="code">random_device</code></td><td align="left">Y</td><td align="left">Missing constexpr</td></tr><tr><td align="left">26.5.7</td><td align="left">Utilities</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.5.7.1</td><td align="left">Class <code class="code">seed_seq</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.7.2</td><td align="left">Function template <code class="code">generate_canonical</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8</td><td align="left">Random number distribution class templates</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.5.8.2</td><td align="left">Uniform distributions</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.5.8.2.1</td><td align="left">Class template <code class="code">uniform_int_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.2.2</td><td align="left">Class template <code class="code">uniform_real_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.3</td><td align="left">Bernoulli distributions</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.5.8.3.1</td><td align="left">Class <code class="code">bernoulli_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.3.2</td><td align="left">Class template <code class="code">binomial_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.3.3</td><td align="left">Class template <code class="code">geometric_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.3.4</td><td align="left">Class template <code class="code">negative_binomial_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.4</td><td align="left">Poisson distributions</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.5.8.4.1</td><td align="left">Class template <code class="code">poisson_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.4.2</td><td align="left">Class template <code class="code">exponential_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.4.3</td><td align="left">Class template <code class="code">gamma_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.4.4</td><td align="left">Class template <code class="code">weibull_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.4.5</td><td align="left">Class template <code class="code">extreme_value_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.5</td><td align="left">Normal distributions</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.5.8.5.1</td><td align="left">Class template <code class="code">normal_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.5.2</td><td align="left">Class template <code class="code">lognormal_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.5.3</td><td align="left">Class template <code class="code">chi_squared_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.5.4</td><td align="left">Class template <code class="code">cauchy_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.5.5</td><td align="left">Class template <code class="code">fisher_f_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.5.6</td><td align="left">Class template <code class="code">student_t_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.6</td><td align="left">Sampling distributions</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.5.8.6.1</td><td align="left">Class template <code class="code">discrete_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.6.2</td><td align="left">Class template <code class="code">piecewise_constant_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.5.8.6.3</td><td align="left">Class template <code class="code">piecewise_linear_distribution</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.6</td><td align="left">Numeric arrays</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.6.1</td><td align="left">Header <code class="code"><valarray></code> synopsis</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.6.2</td><td align="left">Class template <code class="code">valarray</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.6.3</td><td align="left"><code class="code">valarray</code> non-member operations</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.6.4</td><td align="left">Class <code class="code">slice</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.6.5</td><td align="left">Class template <code class="code">slice_array</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.6.6</td><td align="left">The <code class="code">gslice</code> class</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.6.7</td><td align="left">Class template <code class="code">gslice_array</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.6.8</td><td align="left">Class template <code class="code">mask_array</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.6.9</td><td align="left">Class template <code class="code">indirect_array</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.6.10</td><td align="left"><code class="code">valarray</code> range access</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.7</td><td align="left">Generalized numeric operations</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">26.7.1</td><td align="left">Header <code class="code"><numeric></code> synopsis</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.7.2</td><td align="left"><code class="code">accumulate</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.7.3</td><td align="left"><code class="code">inner_product</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.7.4</td><td align="left"><code class="code">partial_sum</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.7.5</td><td align="left"><code class="code">adjacent_difference</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">26.7.6</td><td align="left">iota</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">26.8</td><td align="left">C Library</td><td align="left">Partial</td><td align="left"><code class="code"><ctgmath></code> doesn't include + <code class="code"><ccomplex></code> + </td></tr><tr><td align="left"> <span class="emphasis"><em>27</em></span> </td><td colspan="3" align="left"> <span class="emphasis"><em>Input/output library</em></span> @@ -224,6 +231,7 @@ particular release. Missing move and swap operations on <code class="code">basic_ios</code>. Missing <code class="code">io_errc</code> and <code class="code">iostream_category</code>. <code class="code">ios_base::failure</code> is not derived from <code class="code">system_error</code>. + Missing <code class="code">ios_base::hexfloat</code>. </td></tr><tr><td align="left">27.6</td><td align="left">Stream buffers</td><td align="left">Y</td><td align="left"> </td></tr><tr bgcolor="#B0B0B0"><td align="left">27.7</td><td align="left">Formatting and manipulators</td><td align="left">Partial</td><td align="left"> Missing move and swap operations Missing <code class="code">get_time</code> and <code class="code">put_time</code> manipulators. diff --git a/libstdc++-v3/doc/html/manual/std_contents.html b/libstdc++-v3/doc/html/manual/std_contents.html index c09b29e57df..c3919242e71 100644 --- a/libstdc++-v3/doc/html/manual/std_contents.html +++ b/libstdc++-v3/doc/html/manual/std_contents.html @@ -21,7 +21,7 @@ </a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales">Locales</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales.locale">locale</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locales.locale.req">Requirements</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.design">Design</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locale.impl.c">Interacting with "C" locales</a></span></dt></dl></dd><dt><span class="section"><a href="localization.html#locales.locale.future">Future</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="facets.html">Facets</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#std.localization.facet.ctype">ctype</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.ctype.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#idm269999753024">Specializations</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.ctype.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#std.localization.facet.codecvt">codecvt</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.codecvt.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#codecvt.design.wchar_t_size"><span class="type">wchar_t</span> Size</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.unicode">Support for Unicode</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.issues">Other Issues</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.codecvt.impl">Implementation</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#manual.localization.facet.messages">messages</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.messages.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.design">Design</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#messages.impl.models">Models</a></span></dt><dt><span class="section"><a href="facets.html#messages.impl.gnu">The GNU Model</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.messages.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.future">Future</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="chapter"><a href="containers.html">9. Containers -</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd><dt><span class="section"><a href="containers.html#containers.sequences.vector">vector</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.vector.management">Space Overhead Management</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="iterators.html">10. +</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="iterators.html">10. Iterators </a></span></dt><dd><dl><dt><span class="section"><a href="iterators.html#std.iterators.predefined">Predefined</a></span></dt><dd><dl><dt><span class="section"><a href="iterators.html#iterators.predefined.vs_pointers">Iterators vs. Pointers</a></span></dt><dt><span class="section"><a href="iterators.html#iterators.predefined.end">One Past the End</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="algorithms.html">11. @@ -42,4 +42,4 @@ </a></span></dt><dd><dl><dt><span class="section"><a href="concurrency.html#std.concurrency.api">API Reference</a></span></dt></dl></dd></dl></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="debug.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="index.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="support.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Debugging Support </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Chapter 4. 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\ No newline at end of file +</td></tr></table></div></body></html> diff --git a/libstdc++-v3/doc/xml/manual/containers.xml b/libstdc++-v3/doc/xml/manual/containers.xml index 920b491db36..7424a7eb174 100644 --- a/libstdc++-v3/doc/xml/manual/containers.xml +++ b/libstdc++-v3/doc/xml/manual/containers.xml @@ -25,8 +25,9 @@ <section xml:id="sequences.list.size" xreflabel="list::size() is O(n)"><info><title>list::size() is O(n)</title></info> <para> - Yes it is, and that's okay. This is a decision that we preserved - when we imported SGI's STL implementation. The following is + Yes it is, and that was okay until the 2011 edition of the C++ standard. + In future GCC will change it to O(1) but O(N) was a decision that we + preserved when we imported SGI's STL implementation. The following is quoted from <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="http://www.sgi.com/tech/stl/FAQ.html">their FAQ</link>: </para> <blockquote> @@ -72,26 +73,6 @@ </section> </section> -<section xml:id="containers.sequences.vector" xreflabel="vector"><info><title>vector</title></info> -<?dbhtml filename="vector.html"?> - - <para> - </para> - <section xml:id="sequences.vector.management" xreflabel="Space Overhead Management"><info><title>Space Overhead Management</title></info> - - <para> - In <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="http://gcc.gnu.org/ml/libstdc++/2002-04/msg00105.html">this - message to the list</link>, Daniel Kostecky announced work on an - alternate form of <code>std::vector</code> that would support - hints on the number of elements to be over-allocated. The design - was also described, along with possible implementation choices. - </para> - <para> - The first two alpha releases were announced <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="http://gcc.gnu.org/ml/libstdc++/2002-07/msg00048.html">here</link> - and <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="http://gcc.gnu.org/ml/libstdc++/2002-07/msg00111.html">here</link>. - </para> - - </section></section> </section> <!-- Sect1 02 : Associative --> diff --git a/libstdc++-v3/doc/xml/manual/status_cxx2011.xml b/libstdc++-v3/doc/xml/manual/status_cxx2011.xml index 8b781c0695f..2ef420eb414 100644 --- a/libstdc++-v3/doc/xml/manual/status_cxx2011.xml +++ b/libstdc++-v3/doc/xml/manual/status_cxx2011.xml @@ -226,10 +226,12 @@ particular release. <entry/> </row> <row> + <?dbhtml bgcolor="#B0B0B0" ?> <entry>18.8.6</entry> <entry><code>nested_exception</code></entry> - <entry>Y</entry> - <entry/> + <entry>Partial</entry> + <entry>Follows an earlier C++0x draft, not the final specification. + </entry> </row> <row> <entry>18.9</entry> @@ -612,10 +614,11 @@ particular release. <entry/> </row> <row> + <?dbhtml bgcolor="#B0B0B0" ?> <entry>20.6.12.4</entry> <entry><code>uninitialized_fill_n</code></entry> - <entry>Y</entry> - <entry/> + <entry>Partial</entry> + <entry>Returns <code>void</code>.</entry> </row> <row> <entry>20.6.13</entry> @@ -1119,10 +1122,13 @@ particular release. <entry/> </row> <row> + <?dbhtml bgcolor="#B0B0B0" ?> <entry>21.4</entry> <entry>Class template <code>basic_string</code></entry> - <entry>Y</entry> - <entry/> + <entry>Partial</entry> + <entry>Non-conforming Copy-On-Write implementation. + Missing <code>getline</code> overloads for rvalue streams. + </entry> </row> <row> <entry>21.5</entry> @@ -1190,10 +1196,11 @@ particular release. <entry/> </row> <row> + <?dbhtml bgcolor="#B0B0B0" ?> <entry>22.3.3.1</entry> <entry>Character classification</entry> - <entry>Y</entry> - <entry/> + <entry>Partial</entry> + <entry>Missing <code>isblank</code>.</entry> </row> <row> <entry>22.3.3.2</entry> @@ -1272,16 +1279,18 @@ particular release. <entry/> </row> <row> + <?dbhtml bgcolor="#B0B0B0" ?> <entry>22.4.5.1</entry> <entry>Class template <code>time_get</code></entry> - <entry>Y</entry> - <entry/> + <entry>Partial</entry> + <entry>Missing <code>get</code> and <code>do_get</code></entry> </row> <row> + <?dbhtml bgcolor="#B0B0B0" ?> <entry>22.4.5.2</entry> <entry>Class template <code>time_get_byname</code></entry> - <entry>Y</entry> - <entry/> + <entry>Partial</entry> + <entry>Likewise</entry> </row> <row> <entry>22.4.5.3</entry> @@ -1434,8 +1443,10 @@ particular release. <entry>23.3.5</entry> <entry>Class template <code>list</code></entry> <entry>Partial</entry> - <entry><code>insert</code> and <code>erase</code> members do not - take <code>const_iterator</code> arguments (N2350).</entry> + <entry>O(N) size. + <code>insert</code> and <code>erase</code> members do not + take <code>const_iterator</code> arguments (N2350). + </entry> </row> <row> <?dbhtml bgcolor="#B0B0B0" ?> @@ -1650,10 +1661,11 @@ particular release. <entry/> </row> <row> + <?dbhtml bgcolor="#B0B0B0" ?> <entry>25.3</entry> <entry>Mutating sequence operations</entry> - <entry>Y</entry> - <entry/> + <entry>Partial</entry> + <entry><code>rotate</code> returns <code>void</code>.</entry> </row> <row> <entry>25.4</entry> @@ -2060,10 +2072,13 @@ particular release. <entry/> </row> <row> + <?dbhtml bgcolor="#B0B0B0" ?> <entry>26.8</entry> <entry>C Library</entry> - <entry>Y</entry> - <entry/> + <entry>Partial</entry> + <entry><code><ctgmath></code> doesn't include + <code><ccomplex></code> + </entry> </row> <row> <entry> @@ -2143,6 +2158,7 @@ particular release. Missing move and swap operations on <code>basic_ios</code>. Missing <code>io_errc</code> and <code>iostream_category</code>. <code>ios_base::failure</code> is not derived from <code>system_error</code>. + Missing <code>ios_base::hexfloat</code>. </entry> </row> <row> diff --git a/libstdc++-v3/libsupc++/dyncast.cc b/libstdc++-v3/libsupc++/dyncast.cc index 2e5dbf0a33d..b9db8ee5fc4 100644 --- a/libstdc++-v3/libsupc++/dyncast.cc +++ b/libstdc++-v3/libsupc++/dyncast.cc @@ -55,6 +55,18 @@ __dynamic_cast (const void *src_ptr, // object started from adjust_pointer <void> (src_ptr, prefix->whole_object); const __class_type_info *whole_type = prefix->whole_type; __class_type_info::__dyncast_result result; + + // If the whole object vptr doesn't refer to the whole object type, we're + // in the middle of constructing a primary base, and src is a separate + // base. This has undefined behavior and we can't find anything outside + // of the base we're actually constructing, so fail now rather than + // segfault later trying to use a vbase offset that doesn't exist. + const void *whole_vtable = *static_cast <const void *const *> (whole_ptr); + const vtable_prefix *whole_prefix = + adjust_pointer <vtable_prefix> (whole_vtable, + -offsetof (vtable_prefix, origin)); + if (whole_prefix->whole_type != whole_type) + return NULL; whole_type->__do_dyncast (src2dst, __class_type_info::__contained_public, dst_type, whole_ptr, src_type, src_ptr, result); diff --git a/libstdc++-v3/python/libstdcxx/v6/printers.py b/libstdc++-v3/python/libstdcxx/v6/printers.py index e6f20074979..1a1f02dbc7e 100644 --- a/libstdc++-v3/python/libstdcxx/v6/printers.py +++ b/libstdc++-v3/python/libstdcxx/v6/printers.py @@ -1,4 +1,4 @@ -# Pretty-printers for libstc++. +# Pretty-printers for libstdc++. # Copyright (C) 2008-2013 Free Software Foundation, Inc. @@ -18,6 +18,50 @@ import gdb import itertools import re +import sys + +### Python 2 + Python 3 compatibility code + +# Resources about compatibility: +# +# * <http://pythonhosted.org/six/>: Documentation of the "six" module + +# FIXME: The handling of e.g. std::basic_string (at least on char) +# probably needs updating to work with Python 3's new string rules. +# +# In particular, Python 3 has a separate type (called byte) for +# bytestrings, and a special b"" syntax for the byte literals; the old +# str() type has been redefined to always store Unicode text. +# +# We probably can't do much about this until this GDB PR is addressed: +# <https://sourceware.org/bugzilla/show_bug.cgi?id=17138> + +if sys.version_info[0] > 2: + ### Python 3 stuff + Iterator = object + # Python 3 folds these into the normal functions. + imap = map + izip = zip + # Also, int subsumes long + long = int +else: + ### Python 2 stuff + class Iterator: + """Compatibility mixin for iterators + + Instead of writing next() methods for iterators, write + __next__() methods and use this mixin to make them work in + Python 2 as well as Python 3. + + Idea stolen from the "six" documentation: + <http://pythonhosted.org/six/#six.Iterator> + """ + + def next(self): + return self.__next__() + + # In Python 2, we still need these from itertools + from itertools import imap, izip # Try to use the new-style pretty-printing if available. _use_gdb_pp = True @@ -51,7 +95,7 @@ def find_type(orig, name): # anything fancier here. field = typ.fields()[0] if not field.is_base_class: - raise ValueError, "Cannot find type %s::%s" % (str(orig), name) + raise ValueError("Cannot find type %s::%s" % (str(orig), name)) typ = field.type class SharedPointerPrinter: @@ -87,7 +131,7 @@ class UniquePointerPrinter: class StdListPrinter: "Print a std::list" - class _iterator: + class _iterator(Iterator): def __init__(self, nodetype, head): self.nodetype = nodetype self.base = head['_M_next'] @@ -97,7 +141,7 @@ class StdListPrinter: def __iter__(self): return self - def next(self): + def __next__(self): if self.base == self.head: raise StopIteration elt = self.base.cast(self.nodetype).dereference() @@ -135,7 +179,7 @@ class StdListIteratorPrinter: class StdSlistPrinter: "Print a __gnu_cxx::slist" - class _iterator: + class _iterator(Iterator): def __init__(self, nodetype, head): self.nodetype = nodetype self.base = head['_M_head']['_M_next'] @@ -144,7 +188,7 @@ class StdSlistPrinter: def __iter__(self): return self - def next(self): + def __next__(self): if self.base == 0: raise StopIteration elt = self.base.cast(self.nodetype).dereference() @@ -180,7 +224,7 @@ class StdSlistIteratorPrinter: class StdVectorPrinter: "Print a std::vector" - class _iterator: + class _iterator(Iterator): def __init__ (self, start, finish, bitvec): self.bitvec = bitvec if bitvec: @@ -198,7 +242,7 @@ class StdVectorPrinter: def __iter__(self): return self - def next(self): + def __next__(self): count = self.count self.count = self.count + 1 if self.bitvec: @@ -265,7 +309,7 @@ class StdVectorIteratorPrinter: class StdTuplePrinter: "Print a std::tuple" - class _iterator: + class _iterator(Iterator): def __init__ (self, head): self.head = head @@ -276,20 +320,20 @@ class StdTuplePrinter: # Set the actual head to the first pair. self.head = self.head.cast (nodes[0].type) elif len (nodes) != 0: - raise ValueError, "Top of tuple tree does not consist of a single node." + raise ValueError("Top of tuple tree does not consist of a single node.") self.count = 0 def __iter__ (self): return self - def next (self): + def __next__ (self): nodes = self.head.type.fields () # Check for further recursions in the inheritance tree. if len (nodes) == 0: raise StopIteration # Check that this iteration has an expected structure. if len (nodes) != 2: - raise ValueError, "Cannot parse more than 2 nodes in a tuple tree." + raise ValueError("Cannot parse more than 2 nodes in a tuple tree.") # - Left node is the next recursion parent. # - Right node is the actual class contained in the tuple. @@ -341,7 +385,7 @@ class StdStackOrQueuePrinter: return self.visualizer.display_hint () return None -class RbtreeIterator: +class RbtreeIterator(Iterator): def __init__(self, rbtree): self.size = rbtree['_M_t']['_M_impl']['_M_node_count'] self.node = rbtree['_M_t']['_M_impl']['_M_header']['_M_left'] @@ -353,7 +397,7 @@ class RbtreeIterator: def __len__(self): return int (self.size) - def next(self): + def __next__(self): if self.count == self.size: raise StopIteration result = self.node @@ -405,7 +449,7 @@ class StdMapPrinter: "Print a std::map or std::multimap" # Turn an RbtreeIterator into a pretty-print iterator. - class _iter: + class _iter(Iterator): def __init__(self, rbiter, type): self.rbiter = rbiter self.count = 0 @@ -414,9 +458,9 @@ class StdMapPrinter: def __iter__(self): return self - def next(self): + def __next__(self): if self.count % 2 == 0: - n = self.rbiter.next() + n = next(self.rbiter) n = n.cast(self.type).dereference()['_M_value_field'] self.pair = n item = n['first'] @@ -447,7 +491,7 @@ class StdSetPrinter: "Print a std::set or std::multiset" # Turn an RbtreeIterator into a pretty-print iterator. - class _iter: + class _iter(Iterator): def __init__(self, rbiter, type): self.rbiter = rbiter self.count = 0 @@ -456,8 +500,8 @@ class StdSetPrinter: def __iter__(self): return self - def next(self): - item = self.rbiter.next() + def __next__(self): + item = next(self.rbiter) item = item.cast(self.type).dereference()['_M_value_field'] # FIXME: this is weird ... what to do? # Maybe a 'set' display hint? @@ -522,7 +566,7 @@ class StdBitsetPrinter: class StdDequePrinter: "Print a std::deque" - class _iter: + class _iter(Iterator): def __init__(self, node, start, end, last, buffer_size): self.node = node self.p = start @@ -534,7 +578,7 @@ class StdDequePrinter: def __iter__(self): return self - def next(self): + def __next__(self): if self.p == self.last: raise StopIteration @@ -619,7 +663,7 @@ class StdStringPrinter: def display_hint (self): return 'string' -class Tr1HashtableIterator: +class Tr1HashtableIterator(Iterator): def __init__ (self, hash): self.node = hash['_M_bbegin']['_M_node']['_M_nxt'] self.node_type = find_type(hash.type, '__node_type').pointer() @@ -627,7 +671,7 @@ class Tr1HashtableIterator: def __iter__ (self): return self - def next (self): + def __next__ (self): if self.node == 0: raise StopIteration node = self.node.cast(self.node_type) @@ -655,8 +699,8 @@ class Tr1UnorderedSetPrinter: return '[%d]' % i def children (self): - counter = itertools.imap (self.format_count, itertools.count()) - return itertools.izip (counter, Tr1HashtableIterator (self.hashtable())) + counter = imap (self.format_count, itertools.count()) + return izip (counter, Tr1HashtableIterator (self.hashtable())) class Tr1UnorderedMapPrinter: "Print a tr1::unordered_map" @@ -688,11 +732,11 @@ class Tr1UnorderedMapPrinter: return '[%d]' % i def children (self): - counter = itertools.imap (self.format_count, itertools.count()) + counter = imap (self.format_count, itertools.count()) # Map over the hash table and flatten the result. - data = self.flatten (itertools.imap (self.format_one, Tr1HashtableIterator (self.hashtable()))) + data = self.flatten (imap (self.format_one, Tr1HashtableIterator (self.hashtable()))) # Zip the two iterators together. - return itertools.izip (counter, data) + return izip (counter, data) def display_hint (self): return 'map' @@ -700,7 +744,7 @@ class Tr1UnorderedMapPrinter: class StdForwardListPrinter: "Print a std::forward_list" - class _iterator: + class _iterator(Iterator): def __init__(self, nodetype, head): self.nodetype = nodetype self.base = head['_M_next'] @@ -709,7 +753,7 @@ class StdForwardListPrinter: def __iter__(self): return self - def next(self): + def __next__(self): if self.base == 0: raise StopIteration elt = self.base.cast(self.nodetype).dereference() @@ -764,7 +808,7 @@ class Printer(object): # A small sanity check. # FIXME if not self.compiled_rx.match(name + '<>'): - raise ValueError, 'libstdc++ programming error: "%s" does not match' % name + raise ValueError('libstdc++ programming error: "%s" does not match' % name) printer = RxPrinter(name, function) self.subprinters.append(printer) self.lookup[name] = printer diff --git a/libstdc++-v3/testsuite/lib/gdb-test.exp b/libstdc++-v3/testsuite/lib/gdb-test.exp index 66dcc666faa..506282823a4 100644 --- a/libstdc++-v3/testsuite/lib/gdb-test.exp +++ b/libstdc++-v3/testsuite/lib/gdb-test.exp @@ -91,7 +91,7 @@ proc gdb-test { marker {selector {}} } { } } - set do_whatis_tests [gdb_batch_check "python print gdb.type_printers" \ + set do_whatis_tests [gdb_batch_check "python print(gdb.type_printers)" \ "\\\[\\\]"] if {!$do_whatis_tests} { send_log "skipping 'whatis' tests - gdb too old" @@ -252,6 +252,6 @@ proc gdb_batch_check {command pattern} { # but not earlier versions. # Return 1 if the version is ok, 0 otherwise. proc gdb_version_check {} { - return [gdb_batch_check "python print gdb.lookup_global_symbol" \ + return [gdb_batch_check "python print(gdb.lookup_global_symbol)" \ "<built-in function lookup_global_symbol>"] } |