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authorhjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4>2013-11-12 14:38:49 +0000
committerhjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4>2013-11-12 14:38:49 +0000
commitd080ea7f8a40e5e17e519c6f71b685b4d536151b (patch)
treeb0098adaa21a7e1f68aed2b7b58cb835a26b4c46
parenta706a8b87f35e0e996f65f8fce6cc981067f5f29 (diff)
downloadgcc-d080ea7f8a40e5e17e519c6f71b685b4d536151b.tar.gz
Turn on SEE unaligned load and store for Haswell
Backported from mainline PR target/59088 * config/i386/i386.c (initial_ix86_tune_features): Set X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL and X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL for m_HASWELL. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@204703 138bc75d-0d04-0410-961f-82ee72b054a4
-rw-r--r--gcc/ChangeLog10
-rw-r--r--gcc/config/i386/i386.c4
2 files changed, 12 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1174501fcf7..37f7ae01feb 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2013-11-12 H.J. Lu <hongjiu.lu@intel.com>
+
+ Backported from mainline
+ 2013-11-12 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR target/59088
+ * config/i386/i386.c (initial_ix86_tune_features): Set
+ X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL and
+ X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL for m_HASWELL.
+
2013-11-11 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Backported from mainline
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 65b2767ba52..5fef9729cfe 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -1894,10 +1894,10 @@ static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_AMDFAM10 | m_BDVER | m_GENERIC,
/* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */
- m_COREI7 | m_AMDFAM10 | m_BDVER | m_BTVER,
+ m_COREI7 | m_HASWELL | m_AMDFAM10 | m_BDVER | m_BTVER,
/* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */
- m_COREI7 | m_BDVER,
+ m_COREI7 | m_HASWELL| m_BDVER,
/* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL */
m_BDVER ,