2013-11-12 Michael Meissner <meissner@linux.vnet.ibm.com>

	PR target/59054
	* config/rs6000/rs6000.md (movdi_internal32): Eliminate
	constraints that would allow DImode into the traditional Altivec
	registers, but cause undesirable code generation when loading 0 as
	a constant.
	(movdi_internal64): Likewise.
	(cmp<mode>_fpr): Do not use %x for CR register output.
	(extendsfdf2_fpr): Fix constraints when -mallow-upper-df and
	-mallow-upper-sf debug switches are used.

[gcc/testsuite]
2013-11-12  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/59054
	* gcc.target/powerpc/pr59054.c: New test.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@204718 138bc75d-0d04-0410-961f-82ee72b054a4

4 files changed, 46 insertions, 27 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a6b57240832..97ad345b2c3 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+2013-11-12  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	PR target/59054
+	* config/rs6000/rs6000.md (movdi_internal32): Eliminate
+	constraints that would allow DImode into the traditional Altivec
+	registers, but cause undesirable code generation when loading 0 as
+	a constant.
+	(movdi_internal64): Likewise.
+	(cmp<mode>_fpr): Do not use %x for CR register output.
+	(extendsfdf2_fpr): Fix constraints when -mallow-upper-df and
+	-mallow-upper-sf debug switches are used.
+
 2013-11-12  Andrew MacLeod  <amacleod@redhat.com>
 
 	* gimple-expr.h (create_tmp_var_name, create_tmp_var_raw,
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 3f13c4603f7..d299a466a2d 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5226,7 +5226,7 @@
   "TARGET_<MODE>_FPR"
   "@
    fcmpu %0,%1,%2
-   xscmpudp %x0,%x1,%x2"
+   xscmpudp %0,%x1,%x2"
   [(set_attr "type" "fpcompare")])
 
 ;; Floating point conversions
@@ -5237,8 +5237,8 @@
   "")
 
 (define_insn_and_split "*extendsfdf2_fpr"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,wy,?wy,wv")
-	(float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wz,Z")))]
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wv")
+	(float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z")))]
   "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
   "@
    #
@@ -5360,7 +5360,7 @@
   "TARGET_<MODE>_FPR && TARGET_CMPB"
   "@
    fcpsgn %0,%2,%1
-   xscpsgn<VSs> %x0,%x2,%x1"
+   xscpsgn<Fvsx> %x0,%x2,%x1"
   [(set_attr "type" "fp")])
 
 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
@@ -10081,8 +10081,8 @@
 ;; Use of fprs is disparaged slightly otherwise reload prefers to reload
 ;; a gpr into a fpr instead of reloading an invalid 'Y' address
 (define_insn "*movdi_internal32"
-  [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r,?wa")
-	(match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF,O"))]
+  [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r")
+	(match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF"))]
   "! TARGET_POWERPC64
    && (gpc_reg_operand (operands[0], DImode)
        || gpc_reg_operand (operands[1], DImode))"
@@ -10093,8 +10093,7 @@
    stfd%U0%X0 %1,%0
    lfd%U1%X1 %0,%1
    fmr %0,%1
-   #
-   xxlxor %x0,%x0,%x0"
+   #"
   [(set_attr_alternative "type"
       [(const_string "store")
        (const_string "load")
@@ -10114,8 +10113,7 @@
 	   (const_string "fpload_u")
 	   (const_string "fpload")))
        (const_string "fp")
-       (const_string "*")
-       (const_string "vecsimple")])])
+       (const_string "*")])])
 
 (define_split
   [(set (match_operand:DI 0 "gpc_reg_operand" "")
@@ -10146,8 +10144,8 @@
 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
 
 (define_insn "*movdi_internal64"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,?Z,?wv,?wa,r,*h,*h,?wa,r,?*wg,r,?*wm")
-	(match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,wv,Z,wa,*h,r,0,O,*wg,r,*wm,r"))]
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wm")
+	(match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wm,r"))]
   "TARGET_POWERPC64
    && (gpc_reg_operand (operands[0], DImode)
        || gpc_reg_operand (operands[1], DImode))"
@@ -10161,13 +10159,9 @@
    stfd%U0%X0 %1,%0
    lfd%U1%X1 %0,%1
    fmr %0,%1
-   stxsd%U0x %x1,%y0
-   lxsd%U1x %x0,%y1
-   xxlor %x0,%x1,%x1
    mf%1 %0
    mt%0 %1
    nop
-   xxlxor %x0,%x0,%x0
    mftgpr %0,%1
    mffgpr %0,%1
    mfvsrd %0,%x1
@@ -10206,24 +10200,14 @@
 	   (const_string "fpload_u")
 	   (const_string "fpload")))
        (const_string "fp")
-       (if_then_else
-	 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
-	 (const_string "fpstore_ux")
-	 (const_string "fpstore"))
-       (if_then_else
-	 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
-	 (const_string "fpload_ux")
-	 (const_string "fpload"))
-       (const_string "vecsimple")
        (const_string "mfjmpr")
        (const_string "mtjmpr")
        (const_string "*")
-       (const_string "vecsimple")
        (const_string "mftgpr")
        (const_string "mffgpr")
        (const_string "mftgpr")
        (const_string "mffgpr")])
-   (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4,4,4,4,4")])
+   (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4")])
 
 ;; Generate all one-bits and clear left or right.
 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index c15733a8e8a..a8ac6f8acc4 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2013-11-12  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	PR target/59054
+	* gcc.target/powerpc/pr59054.c: New test.
+
 2013-11-12  Adam Butcher  <adam@jessamine.co.uk>
 
 	* g++.dg/cpp1y/lambda-generic.C: New test case.
diff --git a/gcc/testsuite/gcc.target/powerpc/pr59054.c b/gcc/testsuite/gcc.target/powerpc/pr59054.c
new file mode 100644
index 00000000000..0379aeee635
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr59054.c
@@ -0,0 +1,18 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mcpu=power7 -O0 -m64" } */
+
+long foo (void) { return 0; }
+
+/* { dg-final { scan-assembler-not "xxlor" } } */
+/* { dg-final { scan-assembler-not "stfd" } } */
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mcpu=power7 -O0 -m64" } */
+
+long foo (void) { return 0; }
+
+/* { dg-final { scan-assembler-not "xxlor" } } */
+/* { dg-final { scan-assembler-not "stfd" } } */