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authoramylaar <amylaar@138bc75d-0d04-0410-961f-82ee72b054a4>2000-07-25 22:10:38 +0000
committeramylaar <amylaar@138bc75d-0d04-0410-961f-82ee72b054a4>2000-07-25 22:10:38 +0000
commit43b590e34e265e6ba4275e9372fa99363b1a736b (patch)
treea410a85c383837a53e5115dd4a1d8e13fe9161e7
parenta28d16c04c2a18ba995d6d34610d23b2423e688b (diff)
downloadgcc-43b590e34e265e6ba4275e9372fa99363b1a736b.tar.gz
* sh.md (cmpgtdi_t): Must be split.
(cmpgtdi_t+1): New splitter. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@35257 138bc75d-0d04-0410-961f-82ee72b054a4
-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/config/sh/sh.md34
2 files changed, 32 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 90527ac01fd..346c8f80d99 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+Tue Jul 25 23:08:33 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ * sh.md (cmpgtdi_t): Must be split.
+ (cmpgtdi_t+1): New splitter.
+
2000-07-25 Zack Weinberg <zack@wolery.cumb.org>
* cpplib.c (_cpp_check_directive): Issue -Wtraditional
diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index 49631d30af2..5e73c1f90c4 100644
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -627,16 +627,36 @@
[(set (reg:SI 18) (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
(match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
""
- "*
- return output_branchy_insn
- (EQ,
- (which_alternative
- ? \"cmp/eq\\t%S1,%S0\;bf\\t%l9\;cmp/eq\\t%R1,%R0\"
- : \"tst\\t%S0,%S0\;bf\\t%l9\;tst\\t%R0,%R0\"),
- insn, operands);"
+ "#"
[(set_attr "length" "6")
(set_attr "type" "arith3b")])
+(define_split
+ [(set (reg:SI 18) (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
+ (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
+ "reload_completed"
+ [(set (reg:SI 18) (eq:SI (match_dup 2) (match_dup 3)))
+ (set (pc) (if_then_else (ne (reg:SI 18) (const_int 0))
+ (label_ref (match_dup 6))
+ (pc)))
+ (set (reg:SI 18) (eq:SI (match_dup 4) (match_dup 5)))
+ (match_dup 6)]
+ "
+{
+ operands[2]
+ = gen_rtx_REG (SImode,
+ true_regnum (operands[0]) + (TARGET_LITTLE_ENDIAN ? 1 : 0));
+ operands[3]
+ = (operands[1] == const0_rtx
+ ? const0_rtx
+ : gen_rtx_REG (SImode,
+ true_regnum (operands[1])
+ + (TARGET_LITTLE_ENDIAN ? 1 : 0)));
+ operands[4] = gen_lowpart (SImode, operands[0]);
+ operands[5] = gen_lowpart (SImode, operands[1]);
+ operands[6] = gen_label_rtx ();
+}")
+
(define_insn "cmpgtdi_t"
[(set (reg:SI 18) (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
(match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]