Backports from trunk:

	2016-08-15  Segher Boessenkool  <segher@kernel.crashing.org>
	PR rtl-optimization/73650
	* lra-constraints.c (simple_move_p): If the insn is multiple_sets
	it is not a simple move.

	2017-01-20  Segher Boessenkool  <segher@kernel.crashing.org>
	PR target/61729
	PR target/77850
	* config/rs6000/rs6000.c (rs6000_gimplify_va_arg): Adjust address to
	read from, for big endian.

	2017-04-04  Segher Boessenkool  <segher@kernel.crashing.org>
	PR rtl-optimization/60818
	* simplify-rtx.c (simplify_binary_operation_1): Do not replace
	a compare of comparisons with the thing compared if this results
	in a different machine mode.

	2017-04-12  Segher Boessenkool  <segher@kernel.crashing.org>
	PR target/80382
	* config/rs6000/sync.md (atomic_load<mode>, atomic_store<mode): Test
	for quad_address_p for TImode, instead of just not indexed_address.

	2017-04-19  Segher Boessenkool  <segher@kernel.crashing.org>
	PR rtl-optimization/80429
	* ira.c (split_live_ranges_for_shrink_wrap): Don't split regs that
	are only used in debug insns.

	2017-05-17  Segher Boessenkool  <segher@kernel.crashing.org>
	PR middle-end/80692
	* real.c (do_compare): Give decimal_do_compare preference over
	comparing just the signs.

	2017-05-31  Segher Boessenkool  <segher@kernel.crashing.org>
	PR target/80618
	* config/rs6000/vector.md (*vector_uneq<mode>): Write the nor in the
	splitter result in the canonical way.

	2017-06-09  Segher Boessenkool  <segher@kernel.crashing.org>
	PR target/80966
	* config/rs6000/rs6000.c (rs6000_emit_allocate_stack): Assert that
	gen_add3_insn did not fail.
	* config/rs6000/rs6000.md (add<mode>3): If asked to add a constant to
	r0, construct that number in a temporary reg and add that reg to r0.
	If asked to put the result in r0 as well, fail.

	2017-06-23  Segher Boessenkool  <segher@kernel.crashing.org>
	PR middle-end/80902
	* builtins.c (expand_builtin_atomic_fetch_op): If emitting code after
	a call, force the call to not be a tail call.

gcc/testsuite/
	Backports from trunk:

	2017-04-04  Segher Boessenkool  <segher@kernel.crashing.org>
	PR rtl-optimization/60818
	* gcc.c-torture/compile/pr60818.c: New testcase.

	2017-05-17  Segher Boessenkool  <segher@kernel.crashing.org>
	PR middle-end/80692
	* gcc.c-torture/execute/pr80692.c: New testcase.

	2017-06-09  Segher Boessenkool  <segher@kernel.crashing.org>
	PR target/80966
	* gcc.target/powerpc/stack-limit.c: New testcase.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-6-branch@249700 138bc75d-0d04-0410-961f-82ee72b054a4

14 files changed, 168 insertions, 22 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 37b3dc26118..101e86e30bf 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,57 @@
+2017-06-27  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	Backports from trunk:
+
+	2016-08-15  Segher Boessenkool  <segher@kernel.crashing.org>
+	PR rtl-optimization/73650
+	* lra-constraints.c (simple_move_p): If the insn is multiple_sets
+	it is not a simple move.
+
+	2017-01-20  Segher Boessenkool  <segher@kernel.crashing.org>
+	PR target/61729
+	PR target/77850
+	* config/rs6000/rs6000.c (rs6000_gimplify_va_arg): Adjust address to
+	read from, for big endian.
+
+	2017-04-04  Segher Boessenkool  <segher@kernel.crashing.org>
+	PR rtl-optimization/60818
+	* simplify-rtx.c (simplify_binary_operation_1): Do not replace
+	a compare of comparisons with the thing compared if this results
+	in a different machine mode.
+
+	2017-04-12  Segher Boessenkool  <segher@kernel.crashing.org>
+	PR target/80382
+	* config/rs6000/sync.md (atomic_load<mode>, atomic_store<mode): Test
+	for quad_address_p for TImode, instead of just not indexed_address.
+
+	2017-04-19  Segher Boessenkool  <segher@kernel.crashing.org>
+	PR rtl-optimization/80429
+	* ira.c (split_live_ranges_for_shrink_wrap): Don't split regs that
+	are only used in debug insns.
+
+	2017-05-17  Segher Boessenkool  <segher@kernel.crashing.org>
+	PR middle-end/80692
+	* real.c (do_compare): Give decimal_do_compare preference over
+	comparing just the signs.
+
+	2017-05-31  Segher Boessenkool  <segher@kernel.crashing.org>
+	PR target/80618
+	* config/rs6000/vector.md (*vector_uneq<mode>): Write the nor in the
+	splitter result in the canonical way.
+
+	2017-06-09  Segher Boessenkool  <segher@kernel.crashing.org>
+	PR target/80966
+	* config/rs6000/rs6000.c (rs6000_emit_allocate_stack): Assert that
+	gen_add3_insn did not fail.
+	* config/rs6000/rs6000.md (add<mode>3): If asked to add a constant to
+	r0, construct that number in a temporary reg and add that reg to r0.
+	If asked to put the result in r0 as well, fail.
+
+	2017-06-23  Segher Boessenkool  <segher@kernel.crashing.org>
+	PR middle-end/80902
+	* builtins.c (expand_builtin_atomic_fetch_op): If emitting code after
+	a call, force the call to not be a tail call.
+
 2017-06-23  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 
 	Backport from mainline
diff --git a/gcc/builtins.c b/gcc/builtins.c
index bb9ee35cd8c..c70c0f5004c 100644
--- a/gcc/builtins.c
+++ b/gcc/builtins.c
@@ -5288,6 +5288,12 @@ expand_builtin_atomic_fetch_op (machine_mode mode, tree exp, rtx target,
   gcc_assert (TREE_OPERAND (addr, 0) == fndecl);
   TREE_OPERAND (addr, 0) = builtin_decl_explicit (ext_call);
 
+  /* If we will emit code after the call, the call can not be a tail call.
+     If it is emitted as a tail call, a barrier is emitted after it, and
+     then all trailing code is removed.  */
+  if (!ignore)
+    CALL_EXPR_TAILCALL (exp) = 0;
+
   /* Expand the call here so we can emit trailing code.  */
   ret = expand_call (exp, target, ignore);
 
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index f07305f8cec..67011707bfa 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -12614,6 +12614,7 @@ rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
 
   size = int_size_in_bytes (type);
   rsize = (size + 3) / 4;
+  int pad = 4 * rsize - size;
   align = 1;
 
   machine_mode mode = TYPE_MODE (type);
@@ -12695,6 +12696,10 @@ rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
 	  && mode == SDmode)
 	t = fold_build_pointer_plus_hwi (t, size);
 
+      /* Args are right-aligned.  */
+      if (BYTES_BIG_ENDIAN)
+	t = fold_build_pointer_plus_hwi (t, pad);
+
       gimplify_assign (addr, t, pre_p);
 
       gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
@@ -12720,6 +12725,11 @@ rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
       t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
 		  build_int_cst (TREE_TYPE (t), -align));
     }
+
+  /* Args are right-aligned.  */
+  if (BYTES_BIG_ENDIAN)
+    t = fold_build_pointer_plus_hwi (t, pad);
+
   gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
 
   gimplify_assign (unshare_expr (addr), t, pre_p);
@@ -25435,9 +25445,11 @@ rs6000_emit_allocate_stack (HOST_WIDE_INT size, rtx copy_reg, int copy_off)
 	  && REGNO (stack_limit_rtx) > 1
 	  && REGNO (stack_limit_rtx) <= 31)
 	{
-	  emit_insn (gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size)));
-	  emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
-				    const0_rtx));
+	  rtx_insn *insn
+	    = gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size));
+	  gcc_assert (insn);
+	  emit_insn (insn);
+	  emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, const0_rtx));
 	}
       else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
 	       && TARGET_32BIT
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 36d695db6d4..a16d8a29d26 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -1559,6 +1559,17 @@
 		  || rtx_equal_p (operands[0], operands[1]))
 		 ? operands[0] : gen_reg_rtx (<MODE>mode));
 
+      /* Adding a constant to r0 is not a valid insn, so use a different
+	 strategy in that case.  */
+      if (REGNO (operands[1]) == 0 || REGNO (tmp) == 0)
+	{
+	  if (operands[0] == operands[1])
+	    FAIL;
+	  rs6000_emit_move (operands[0], operands[2], <MODE>mode);
+	  emit_insn (gen_add<mode>3 (operands[0], operands[1], operands[0]));
+	  DONE;
+	}
+
       HOST_WIDE_INT val = INTVAL (operands[2]);
       HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
       HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
diff --git a/gcc/config/rs6000/sync.md b/gcc/config/rs6000/sync.md
index ee6e68d6e97..cf9e0ef17a5 100644
--- a/gcc/config/rs6000/sync.md
+++ b/gcc/config/rs6000/sync.md
@@ -157,8 +157,7 @@
       rtx op1 = operands[1];
       rtx pti_reg = gen_reg_rtx (PTImode);
 
-      // Can't have indexed address for 'lq'
-      if (indexed_address (XEXP (op1, 0), TImode))
+      if (!quad_address_p (XEXP (op1, 0), TImode, false))
 	{
 	  rtx old_addr = XEXP (op1, 0);
 	  rtx new_addr = force_reg (Pmode, old_addr);
@@ -231,8 +230,7 @@
       rtx op1 = operands[1];
       rtx pti_reg = gen_reg_rtx (PTImode);
 
-      // Can't have indexed address for 'stq'
-      if (indexed_address (XEXP (op0, 0), TImode))
+      if (!quad_address_p (XEXP (op0, 0), TImode, false))
 	{
 	  rtx old_addr = XEXP (op0, 0);
 	  rtx new_addr = force_reg (Pmode, old_addr);
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index 3983c3b8f08..f3d28228ee8 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -556,13 +556,12 @@
 	(gt:VEC_F (match_dup 2)
 		  (match_dup 1)))
    (set (match_dup 0)
-	(not:VEC_F (ior:VEC_F (match_dup 3)
-			      (match_dup 4))))]
-  "
+	(and:VEC_F (not:VEC_F (match_dup 3))
+		   (not:VEC_F (match_dup 4))))]
 {
   operands[3] = gen_reg_rtx (<MODE>mode);
   operands[4] = gen_reg_rtx (<MODE>mode);
-}")
+})
 
 (define_insn_and_split "*vector_ltgt<mode>"
   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
diff --git a/gcc/ira.c b/gcc/ira.c
index 8ac153badb3..087ba6ab1f4 100644
--- a/gcc/ira.c
+++ b/gcc/ira.c
@@ -4991,25 +4991,40 @@ split_live_ranges_for_shrink_wrap (void)
       if (!dest || dest == pic_offset_table_rtx)
 	continue;
 
-      rtx newreg = NULL_RTX;
+      bool need_newreg = false;
       df_ref use, next;
       for (use = DF_REG_USE_CHAIN (REGNO (dest)); use; use = next)
 	{
 	  rtx_insn *uin = DF_REF_INSN (use);
 	  next = DF_REF_NEXT_REG (use);
 
+	  if (DEBUG_INSN_P (uin))
+	    continue;
+
 	  basic_block ubb = BLOCK_FOR_INSN (uin);
 	  if (ubb == call_dom
 	      || dominated_by_p (CDI_DOMINATORS, ubb, call_dom))
 	    {
-	      if (!newreg)
-		newreg = ira_create_new_reg (dest);
-	      validate_change (uin, DF_REF_REAL_LOC (use), newreg, true);
+	      need_newreg = true;
+	      break;
 	    }
 	}
 
-      if (newreg)
+      if (need_newreg)
 	{
+	  rtx newreg = ira_create_new_reg (dest);
+
+	  for (use = DF_REG_USE_CHAIN (REGNO (dest)); use; use = next)
+	    {
+	      rtx_insn *uin = DF_REF_INSN (use);
+	      next = DF_REF_NEXT_REG (use);
+
+	      basic_block ubb = BLOCK_FOR_INSN (uin);
+	      if (ubb == call_dom
+		  || dominated_by_p (CDI_DOMINATORS, ubb, call_dom))
+		validate_change (uin, DF_REF_REAL_LOC (use), newreg, true);
+	    }
+
 	  rtx_insn *new_move = gen_move_insn (newreg, dest);
 	  emit_insn_after (new_move, bb_note (call_dom));
 	  if (dump_file)
diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c
index f96fd458e23..54f67cb1772 100644
--- a/gcc/lra-constraints.c
+++ b/gcc/lra-constraints.c
@@ -3380,6 +3380,13 @@ simple_move_p (void)
   lra_assert (curr_insn_set != NULL_RTX);
   dest = SET_DEST (curr_insn_set);
   src = SET_SRC (curr_insn_set);
+
+  /* If the instruction has multiple sets we need to process it even if it
+     is single_set.  This can happen if one or more of the SETs are dead.
+     See PR73650.  */
+  if (multiple_sets (curr_insn))
+    return false;
+
   return ((dclass = get_op_class (dest)) != NO_REGS
 	  && (sclass = get_op_class (src)) != NO_REGS
 	  /* The backend guarantees that register moves of cost 2
diff --git a/gcc/real.c b/gcc/real.c
index fbebbf0ac62..fa5b9585a04 100644
--- a/gcc/real.c
+++ b/gcc/real.c
@@ -960,12 +960,12 @@ do_compare (const REAL_VALUE_TYPE *a, const REAL_VALUE_TYPE *b,
       gcc_unreachable ();
     }
 
-  if (a->sign != b->sign)
-    return -a->sign - -b->sign;
-
   if (a->decimal || b->decimal)
     return decimal_do_compare (a, b, nan_result);
 
+  if (a->sign != b->sign)
+    return -a->sign - -b->sign;
+
   if (REAL_EXP (a) > REAL_EXP (b))
     ret = 1;
   else if (REAL_EXP (a) < REAL_EXP (b))
diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index 2920298956b..ef6b06d6980 100644
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -2273,10 +2273,10 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
 	      return xop00;
 
 	    if (REG_P (xop00) && REG_P (xop10)
-		&& GET_MODE (xop00) == GET_MODE (xop10)
 		&& REGNO (xop00) == REGNO (xop10)
-		&& GET_MODE_CLASS (GET_MODE (xop00)) == MODE_CC
-		&& GET_MODE_CLASS (GET_MODE (xop10)) == MODE_CC)
+		&& GET_MODE (xop00) == mode
+		&& GET_MODE (xop10) == mode
+		&& GET_MODE_CLASS (mode) == MODE_CC)
 	      return xop00;
 	}
       break;
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index af99d62d778..3a2cc0a018a 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,19 @@
+2017-06-27  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	Backports from trunk:
+
+	2017-04-04  Segher Boessenkool  <segher@kernel.crashing.org>
+	PR rtl-optimization/60818
+	* gcc.c-torture/compile/pr60818.c: New testcase.
+
+	2017-05-17  Segher Boessenkool  <segher@kernel.crashing.org>
+	PR middle-end/80692
+	* gcc.c-torture/execute/pr80692.c: New testcase.
+
+	2017-06-09  Segher Boessenkool  <segher@kernel.crashing.org>
+	PR target/80966
+	* gcc.target/powerpc/stack-limit.c: New testcase.
+
 2017-06-24  Marek Polacek  <polacek@redhat.com>
 
 	Backported from mainline
diff --git a/gcc/testsuite/gcc.c-torture/compile/pr60818.c b/gcc/testsuite/gcc.c-torture/compile/pr60818.c
new file mode 100644
index 00000000000..b6171bbcdf0
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/pr60818.c
@@ -0,0 +1,5 @@
+int
+lx (int oi, int mb)
+{
+  return (oi < mb) < (mb < oi);
+}
diff --git a/gcc/testsuite/gcc.c-torture/execute/pr80692.c b/gcc/testsuite/gcc.c-torture/execute/pr80692.c
new file mode 100644
index 00000000000..e653c71c913
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/pr80692.c
@@ -0,0 +1,13 @@
+/* { dg-require-effective-target dfp } */
+
+int main () {
+	_Decimal64 d64 = -0.DD;
+
+	if (d64 != 0.DD)
+		__builtin_abort ();
+
+	if (d64 != -0.DD)
+		__builtin_abort ();
+
+	return 0;
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/stack-limit.c b/gcc/testsuite/gcc.target/powerpc/stack-limit.c
new file mode 100644
index 00000000000..e676c96eb8e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/stack-limit.c
@@ -0,0 +1,10 @@
+/* { dg-options "-O0 -fstack-limit-register=r14" } */
+
+// PR80966
+
+int foo (int i)
+{
+  char arr[135000];
+
+  arr[i] = 0;
+}