diff options
| author | uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-10-14 21:18:19 +0000 |
|---|---|---|
| committer | uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-10-14 21:18:19 +0000 |
| commit | 0a71c5e8e2248ff7314297052cc105b4274efeb3 (patch) | |
| tree | ff8ab093e181895ad9bc63d0365ea27f4e00b855 | |
| parent | 3bdac2395598b9fe27ccd52d6f94f931a380f9a6 (diff) | |
| download | gcc-0a71c5e8e2248ff7314297052cc105b4274efeb3.tar.gz | |
PR target/67967
* config/i386/i386.c (ix86_emit_save_reg_using_mov): Do not add
REG_CFA_EXPRESSION to aligned SSE stores.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228826 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/i386/i386.c | 11 |
2 files changed, 10 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7c64fa8e92e..8b6ed9a040e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2015-10-14 Uros Bizjak <ubizjak@gmail.com> + + PR target/67967 + * config/i386/i386.c (ix86_emit_save_reg_using_mov): Do not add + REG_CFA_EXPRESSION to aligned SSE stores. + 2015-10-14 Jeff Law <law@redhat.com> * tree-ssa-threadupdate.c (thread_through_all_blocks): Bump diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index a2314e75ee6..ebe2b0aa8ab 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -11612,6 +11612,7 @@ ix86_emit_save_reg_using_mov (machine_mode mode, unsigned int regno, { struct machine_function *m = cfun->machine; rtx reg = gen_rtx_REG (mode, regno); + rtx unspec = NULL_RTX; rtx mem, addr, base, insn; unsigned int align; @@ -11626,13 +11627,9 @@ ix86_emit_save_reg_using_mov (machine_mode mode, unsigned int regno, In case INCOMING_STACK_BOUNDARY is misaligned, we have to emit unaligned store. */ if (mode == V4SFmode && align < 128) - { - rtx unspec = gen_rtx_UNSPEC (mode, gen_rtvec (1, reg), UNSPEC_STOREU); - insn = emit_insn (gen_rtx_SET (mem, unspec)); - } - else - insn = emit_insn (gen_rtx_SET (mem, reg)); + unspec = gen_rtx_UNSPEC (mode, gen_rtvec (1, reg), UNSPEC_STOREU); + insn = emit_insn (gen_rtx_SET (mem, unspec ? unspec : reg)); RTX_FRAME_RELATED_P (insn) = 1; base = addr; @@ -11679,7 +11676,7 @@ ix86_emit_save_reg_using_mov (machine_mode mode, unsigned int regno, mem = gen_rtx_MEM (mode, addr); add_reg_note (insn, REG_CFA_OFFSET, gen_rtx_SET (mem, reg)); } - else + else if (unspec) add_reg_note (insn, REG_CFA_EXPRESSION, gen_rtx_SET (mem, reg)); } |