diff options
| author | yroux <yroux@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-08-17 11:22:49 +0000 |
|---|---|---|
| committer | yroux <yroux@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-08-17 11:22:49 +0000 |
| commit | 79032e78dc96828b5fc0d42c780503e8bb9b4758 (patch) | |
| tree | 7b6695cc4ef9788811db73c8b6558faaaabebe9d | |
| parent | 14bafad6027067fd562da0397e05c88b7e8cf337 (diff) | |
| download | gcc-79032e78dc96828b5fc0d42c780503e8bb9b4758.tar.gz | |
2015-08-17 Yvan Roux <yvan.roux@linaro.org>
Backport from mainline:
2015-08-12 Yvan Roux <yvan.roux@linaro.org>
PR target/67127
* config/arm/arm.md (movdi): Restrict illegitimate ldrd/strd checking
to ARM core registers.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-5-branch@226937 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 4 |
2 files changed, 11 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f74a48d8efd..b0736ed85cf 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2015-08-17 Yvan Roux <yvan.roux@linaro.org> + + Backport from mainline: + 2015-08-12 Yvan Roux <yvan.roux@linaro.org> + + PR target/67127 + * config/arm/arm.md (movdi): Restrict illegitimate ldrd/strd checking + to ARM core registers. + 2015-08-16 Uros Bizjak <ubizjak@gmail.com> Backport from mainline: diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index f63fc39e63a..f9c23736341 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -5415,7 +5415,7 @@ if (!REG_P (operands[0])) operands[1] = force_reg (DImode, operands[1]); } - if (REG_P (operands[0]) && REGNO (operands[0]) < FIRST_VIRTUAL_REGISTER + if (REG_P (operands[0]) && REGNO (operands[0]) <= LAST_ARM_REGNUM && !HARD_REGNO_MODE_OK (REGNO (operands[0]), DImode)) { /* Avoid LDRD's into an odd-numbered register pair in ARM state @@ -5434,7 +5434,7 @@ gen_highpart (SImode, operands[1])); DONE; } - else if (REG_P (operands[1]) && REGNO (operands[1]) < FIRST_VIRTUAL_REGISTER + else if (REG_P (operands[1]) && REGNO (operands[1]) <= LAST_ARM_REGNUM && !HARD_REGNO_MODE_OK (REGNO (operands[1]), DImode)) { /* Avoid STRD's from an odd-numbered register pair in ARM state |