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authorwalt <walt@138bc75d-0d04-0410-961f-82ee72b054a4>2014-01-25 20:14:59 +0000
committerwalt <walt@138bc75d-0d04-0410-961f-82ee72b054a4>2014-01-25 20:14:59 +0000
commit9433582b3fc1b28e764855e8455c31cf84e562eb (patch)
treeca38791f7dfe04f6427df32a011aafcd401fc9f7
parentce51867bd7b1b20c89a8f5efa856d13f0d2ac732 (diff)
downloadgcc-9433582b3fc1b28e764855e8455c31cf84e562eb.tar.gz
2014-01-25 Walter Lee <walt@tilera.com>
* config/tilepro/tilepro.md (ctzdi2): Use register_operand predicate. (clzdi2): Ditto. (ffsdi2): Ditto. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@207078 138bc75d-0d04-0410-961f-82ee72b054a4
-rw-r--r--gcc/ChangeLog7
-rw-r--r--gcc/config/tilepro/tilepro.md6
2 files changed, 10 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5b9991d2c7d..cb0176dbb4a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,12 @@
2014-01-25 Walter Lee <walt@tilera.com>
+ * config/tilepro/tilepro.md (ctzdi2): Use register_operand
+ predicate.
+ (clzdi2): Ditto.
+ (ffsdi2): Ditto.
+
+2014-01-25 Walter Lee <walt@tilera.com>
+
* config/tilegx/tilegx.c (tilegx_expand_to_rtl_hook): New.
(TARGET_EXPAND_TO_RTL_HOOK): Define.
diff --git a/gcc/config/tilepro/tilepro.md b/gcc/config/tilepro/tilepro.md
index adf49baee7a..314dd90bfe0 100644
--- a/gcc/config/tilepro/tilepro.md
+++ b/gcc/config/tilepro/tilepro.md
@@ -795,7 +795,7 @@
(define_expand "ctzdi2"
[(set (match_operand:DI 0 "register_operand" "")
- (ctz:DI (match_operand:DI 1 "reg_or_0_operand" "")))]
+ (ctz:DI (match_operand:DI 1 "register_operand" "")))]
""
{
rtx lo, hi, ctz_lo, ctz_hi, ctz_hi_plus_32, result;
@@ -823,7 +823,7 @@
(define_expand "clzdi2"
[(set (match_operand:DI 0 "register_operand" "")
- (clz:DI (match_operand:DI 1 "reg_or_0_operand" "")))]
+ (clz:DI (match_operand:DI 1 "register_operand" "")))]
""
{
rtx lo, hi, clz_lo, clz_hi, clz_lo_plus_32, result;
@@ -851,7 +851,7 @@
(define_expand "ffsdi2"
[(set (match_operand:DI 0 "register_operand" "")
- (ffs:DI (match_operand:DI 1 "reg_or_0_operand" "")))]
+ (ffs:DI (match_operand:DI 1 "register_operand" "")))]
""
{
rtx lo, hi, ctz_lo, ctz_hi, ctz_hi_plus_32, ctz, ctz_plus_1,ctz_cond;