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| author | H.J. Lu <hjl.tools@gmail.com> | 2016-04-01 13:26:57 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2016-08-08 08:48:50 -0700 |
| commit | 4169bdfeeb2c8331e41775f0ca6d9ca6bf21bd83 (patch) | |
| tree | e7c05cf7e1fac8a92679831eea3e4aa25a4ba516 | |
| parent | 04c0403f4098dd206e11171c5618e88f2e28dea3 (diff) | |
| download | gcc-4169bdfeeb2c8331e41775f0ca6d9ca6bf21bd83.tar.gz | |
Support 128-bit constant store in 64-bit STV
We can load a 128-bit constant from memory and store it.
* config/i386/i386.c (scalar_to_vector_candidate_p_64): Allow
store from 128-bit constant.
(scalar_chain_64::convert_insn): Handle store from 128-bit
constant.
| -rw-r--r-- | gcc/config/i386/i386.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index a07f9d56b82..35811f8a57a 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -2877,6 +2877,12 @@ timode_scalar_to_vector_candidate_p (rtx_insn *insn) case REG: return true; + case CONST_WIDE_INT: + /* For store from 128-bit constant, memory must be aligned + or unaligned store is optimal. */ + return (!misaligned_operand (dst, TImode) + || TARGET_SSE_UNALIGNED_STORE_OPTIMAL); + case CONST_INT: return standard_sse_constant_p (src, TImode); } @@ -3868,6 +3874,19 @@ timode_scalar_chain::convert_insn (rtx_insn *insn) PUT_MODE (src, V1TImode); break; + case CONST_WIDE_INT: + if (NONDEBUG_INSN_P (insn)) + { + /* Since there are no instructions to store 128-bit constant, + temporary register usage is required. */ + rtx tmp = gen_reg_rtx (V1TImode); + src = gen_rtx_CONST_VECTOR (V1TImode, gen_rtvec (1, src)); + src = validize_mem (force_const_mem (V1TImode, src)); + emit_conversion_insns (gen_rtx_SET (dst, tmp), insn); + dst = tmp; + } + break; + case CONST_INT: switch (standard_sse_constant_p (src, TImode)) { |