diff options
| author | bernds <bernds@138bc75d-0d04-0410-961f-82ee72b054a4> | 2007-05-03 13:17:51 +0000 |
|---|---|---|
| committer | bernds <bernds@138bc75d-0d04-0410-961f-82ee72b054a4> | 2007-05-03 13:17:51 +0000 |
| commit | b9904d32ef6f542e175420d42d51dd23d21db110 (patch) | |
| tree | b82df934a8d2b54015019c10765a1d67515d6667 | |
| parent | 30f263a419dd1cf9804dea818dab0c2c40fda265 (diff) | |
| download | gcc-b9904d32ef6f542e175420d42d51dd23d21db110.tar.gz | |
* config/bfin/bfin.md (addpdi3, us_truncpdisi2): New patterns.
(umulsi3_highpart): Use them.
* config/bfin/lib1funcs.asm (__umulsi3_highpart): Use unsigned move
for final accumulator to D regisster tranfser.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@124376 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/bfin/bfin.md | 18 | ||||
| -rw-r--r-- | gcc/config/bfin/lib1funcs.asm | 3 |
3 files changed, 26 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e39d94e7423..0d7c9ddd0d7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2007-05-03 Bernd Schmidt <bernd.schmidt@analog.com> + + * config/bfin/bfin.md (addpdi3, us_truncpdisi2): New patterns. + (umulsi3_highpart): Use them. + * config/bfin/lib1funcs.asm (__umulsi3_highpart): Use unsigned move + for final accumulator to D regisster tranfser. + 2007-05-03 Dorit Nuzman <dorit@il.ibm.com> PR tree-optimization/31699 diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md index c7eb7d97393..217c26d7d15 100644 --- a/gcc/config/bfin/bfin.md +++ b/gcc/config/bfin/bfin.md @@ -1227,6 +1227,14 @@ ;; Accumulator addition +(define_insn "addpdi3" + [(set (match_operand:PDI 0 "register_operand" "=A") + (ss_plus:PDI (match_operand:PDI 1 "register_operand" "%0") + (match_operand:PDI 2 "nonmemory_operand" "B")))] + "" + "A0 += A1%!" + [(set_attr "type" "dsp32")]) + (define_insn "sum_of_accumulators" [(set (match_operand:SI 0 "register_operand" "=d") (ss_truncate:SI @@ -1238,6 +1246,13 @@ "%0 = (A0 += A1)%!" [(set_attr "type" "dsp32")]) +(define_insn "us_truncpdisi2" + [(set (match_operand:SI 0 "register_operand" "=D,W") + (us_truncate:SI (match_operand:PDI 1 "register_operand" "A,B")))] + "" + "%0 = %1 (FU)%!" + [(set_attr "type" "dsp32")]) + ;; Bit test instructions (define_insn "*not_bittst" @@ -1501,7 +1516,8 @@ const1_rtx, const0_rtx, a1reg, const0_rtx, GEN_INT (MACFLAG_FU))); emit_insn (gen_lshrpdi3 (a1reg, a1reg, GEN_INT (16))); - emit_insn (gen_sum_of_accumulators (operands[0], a0reg, a0reg, a1reg)); + emit_insn (gen_addpdi3 (a0reg, a0reg, a1reg)); + emit_insn (gen_us_truncpdisi2 (operands[0], a0reg)); } else { diff --git a/gcc/config/bfin/lib1funcs.asm b/gcc/config/bfin/lib1funcs.asm index fe4c3d53eb5..c8d7fe855cf 100644 --- a/gcc/config/bfin/lib1funcs.asm +++ b/gcc/config/bfin/lib1funcs.asm @@ -128,7 +128,8 @@ ___umulsi3_highpart: A0 = R1.H * R0.H, A1 += R1.L * R0.H (FU); A1 += R0.L * R1.H (FU); A1 = A1 >> 16; - R0 = (A0 += A1); + A0 += A1; + R0 = A0 (FU); RTS; #endif |