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authorJakub Jelinek <jakub@redhat.com>2020-04-03 19:44:42 +0200
committerJakub Jelinek <jakub@redhat.com>2020-04-07 21:01:13 +0200
commitdbff1829843180dc2a6c8ce5ce7883146b5cf083 (patch)
treee81a050c7efb61167fa5e593a06584fe5940d443
parent4486a537f14bc3b05ac552c3cbe18e540e397ed7 (diff)
downloadgcc-dbff1829843180dc2a6c8ce5ce7883146b5cf083.tar.gz
i386: Fix vph{add,subs?}[wd] 256-bit AVX2 RTL patterns [PR94460]
The following testcase is miscompiled, because the AVX2 patterns don't describe correctly what the insn does. E.g. vphaddd with %ymm* operands (the second pattern) instruction as per: https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_hadd_epi32&expand=2941 does { a0+a1, a2+a3, b0+b1, b2+b3, a4+a5, a6+a7, b4+b5, b6+b7 } but our RTL pattern did { a0+a1, a2+a3, a4+a5, a6+a7, b0+b1, b2+b3, b4+b5, b6+b7 } where the first and last 64 bits are the same and two middle 64 bits swapped. https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_hadd_epi16&expand=2939 similarly, insn does: { a0+a1, a2+a3, a4+a5, a6+a7, b0+b1, b2+b3, b4+b5, b6+b7, a8+a9, a10+a11, a12+a13, a14+a15, b8+b9, b10+b11, b12+b13, b14+b15 } but RTL pattern did { a0+a1, a2+a3, a4+a5, a6+a7, a8+a9, a10+a11, a12+a13, a14+a15, b0+b1, b2+b3, b4+b5, b6+b7, b8+b9, b10+b11, b12+b13, b14+b15 } again, first and last 64 bits are the same and the two middle 64 bits swapped. 2020-04-03 Jakub Jelinek <jakub@redhat.com> PR target/94460 * config/i386/sse.md (avx2_ph<plusminus_mnemonic>wv16hi3, avx2_ph<plusminus_mnemonic>dv8si3): Fix up RTL pattern to do second half of first lane from first lane of second operand and first half of second lane from second lane of first operand. * gcc.target/i386/avx2-pr94460.c: New test.
-rw-r--r--gcc/ChangeLog10
-rw-r--r--gcc/config/i386/sse.md52
-rw-r--r--gcc/testsuite/ChangeLog5
-rw-r--r--gcc/testsuite/gcc.target/i386/avx2-pr94460.c31
4 files changed, 72 insertions, 26 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4cb05e922e9..022d71e9e73 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,6 +1,16 @@
2020-04-07 Jakub Jelinek <jakub@redhat.com>
Backported from mainline
+ 2020-04-03 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/94460
+ * config/i386/sse.md (avx2_ph<plusminus_mnemonic>wv16hi3,
+ avx2_ph<plusminus_mnemonic>dv8si3): Fix up RTL pattern to do
+ second half of first lane from first lane of second operand and
+ first half of second lane from second lane of first operand.
+
+2020-04-07 Jakub Jelinek <jakub@redhat.com>
+
2020-04-01 Jakub Jelinek <jakub@redhat.com>
PR middle-end/94423
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index a8b879bcdc4..618fc231c40 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -15543,22 +15543,6 @@
(vec_concat:V4HI
(vec_concat:V2HI
(ssse3_plusminus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 8)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 9)])))
- (ssse3_plusminus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 10)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 11)]))))
- (vec_concat:V2HI
- (ssse3_plusminus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 12)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 13)])))
- (ssse3_plusminus:HI
- (vec_select:HI (match_dup 1) (parallel [(const_int 14)]))
- (vec_select:HI (match_dup 1) (parallel [(const_int 15)]))))))
- (vec_concat:V8HI
- (vec_concat:V4HI
- (vec_concat:V2HI
- (ssse3_plusminus:HI
(vec_select:HI
(match_operand:V16HI 2 "nonimmediate_operand" "xm")
(parallel [(const_int 0)]))
@@ -15572,7 +15556,23 @@
(vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
(ssse3_plusminus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))
+ (vec_select:HI (match_dup 2) (parallel [(const_int 7)]))))))
+ (vec_concat:V8HI
+ (vec_concat:V4HI
+ (vec_concat:V2HI
+ (ssse3_plusminus:HI
+ (vec_select:HI (match_dup 1) (parallel [(const_int 8)]))
+ (vec_select:HI (match_dup 1) (parallel [(const_int 9)])))
+ (ssse3_plusminus:HI
+ (vec_select:HI (match_dup 1) (parallel [(const_int 10)]))
+ (vec_select:HI (match_dup 1) (parallel [(const_int 11)]))))
+ (vec_concat:V2HI
+ (ssse3_plusminus:HI
+ (vec_select:HI (match_dup 1) (parallel [(const_int 12)]))
+ (vec_select:HI (match_dup 1) (parallel [(const_int 13)])))
+ (ssse3_plusminus:HI
+ (vec_select:HI (match_dup 1) (parallel [(const_int 14)]))
+ (vec_select:HI (match_dup 1) (parallel [(const_int 15)])))))
(vec_concat:V4HI
(vec_concat:V2HI
(ssse3_plusminus:HI
@@ -15688,21 +15688,21 @@
(vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
(vec_concat:V2SI
(plusminus:SI
- (vec_select:SI (match_dup 1) (parallel [(const_int 4)]))
- (vec_select:SI (match_dup 1) (parallel [(const_int 5)])))
- (plusminus:SI
- (vec_select:SI (match_dup 1) (parallel [(const_int 6)]))
- (vec_select:SI (match_dup 1) (parallel [(const_int 7)])))))
- (vec_concat:V4SI
- (vec_concat:V2SI
- (plusminus:SI
(vec_select:SI
(match_operand:V8SI 2 "nonimmediate_operand" "xm")
(parallel [(const_int 0)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
(plusminus:SI
(vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
- (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))
+ (vec_select:SI (match_dup 2) (parallel [(const_int 3)])))))
+ (vec_concat:V4SI
+ (vec_concat:V2SI
+ (plusminus:SI
+ (vec_select:SI (match_dup 1) (parallel [(const_int 4)]))
+ (vec_select:SI (match_dup 1) (parallel [(const_int 5)])))
+ (plusminus:SI
+ (vec_select:SI (match_dup 1) (parallel [(const_int 6)]))
+ (vec_select:SI (match_dup 1) (parallel [(const_int 7)]))))
(vec_concat:V2SI
(plusminus:SI
(vec_select:SI (match_dup 2) (parallel [(const_int 4)]))
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 78f4b5119d8..963a1af39be 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,6 +1,11 @@
2020-04-07 Jakub Jelinek <jakub@redhat.com>
Backported from mainline
+ 2020-04-03 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/94460
+ * gcc.target/i386/avx2-pr94460.c: New test.
+
2020-04-01 Jakub Jelinek <jakub@redhat.com>
PR middle-end/94423
diff --git a/gcc/testsuite/gcc.target/i386/avx2-pr94460.c b/gcc/testsuite/gcc.target/i386/avx2-pr94460.c
new file mode 100644
index 00000000000..75b7a7bf313
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx2-pr94460.c
@@ -0,0 +1,31 @@
+/* PR target/94460 */
+/* { dg-do run { target { avx2 && int128 } } } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <x86intrin.h>
+#include "avx2-check.h"
+
+typedef __int128 v2ti __attribute__ ((__vector_size__ (32)));
+
+static inline v2ti
+foo (__v16hi b)
+{
+ return (v2ti) _mm256_hsub_epi16 ((__m256i) b, (__m256i) b);
+}
+
+static inline v2ti
+bar (__v8si b)
+{
+ return (v2ti) _mm256_hsub_epi32 ((__m256i) b, (__m256i) b);
+}
+
+static void
+avx2_test (void)
+{
+ v2ti x = foo ((__v16hi) { 1 });
+ if (x[0] != ((__int128)1 << 64 | 1) || x[1] != 0)
+ abort ();
+ x = bar ((__v8si) { 1 });
+ if (x[0] != ((__int128)1 << 64 | 1) || x[1] != 0)
+ abort ();
+}