Add new nds32 port, including machine description, libgcc, and documentation.

[gcc/ChangeLog]
	* config.gcc (nds32*-*-*): Add nds32 target.
	* config/nds32/nds32.c: New file.
	* config/nds32/nds32.h: New file.
	* config/nds32/nds32.md: New file.
	* config/nds32/constants.md: New file.
	* config/nds32/constraints.md: New file.
	* config/nds32/iterators.md: New file.
	* config/nds32/nds32-doubleword.md: New file.
	* config/nds32/nds32-intrinsic.md: New file.
	* config/nds32/nds32_intrinsic.h: New file.
	* config/nds32/nds32-modes.def: New file.
	* config/nds32/nds32-multiple.md: New file.
	* config/nds32/nds32.opt: New file.
	* config/nds32/nds32-opts.h: New file.
	* config/nds32/nds32-protos.h: New file.
	* config/nds32/nds32-peephole2.md: New file.
	* config/nds32/pipelines.md: New file.
	* config/nds32/predicates.md: New file.
	* config/nds32/t-mlibs: New file.
	* common/config/nds32: New directory and files.

	* doc/invoke.texi (NDS32 options): Document nds32 specific options.
	* doc/md.texi (NDS32 family): Document nds32 specific constraints.
	* doc/install.texi (Cross-Compiler-Specific Options): Document
	--with-nds32-lib for nds32 target.
	* doc/extend.texi (Function Attributes, Target Builtins): Document
	nds32 specific attributes.
	
[libgcc/ChangeLog]
	* config.host (nds32*-elf*): Add nds32 target.
	* config/nds32 : New directory and files.
	
[contrib/ChangeLog]
	* config-list.mk (nds32le-elf, nds32be-elf): Add nds32 target.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@204269 138bc75d-0d04-0410-961f-82ee72b054a4

284 files changed, 26215 insertions, 3 deletions

diff --git a/contrib/ChangeLog b/contrib/ChangeLog
index 029548bf29d..3b0d76349e2 100644
--- a/contrib/ChangeLog
+++ b/contrib/ChangeLog
@@ -1,3 +1,7 @@
+2013-10-31  Chung-Ju Wu  <jasonwucj@gmail.com>
+
+	* config-list.mk (nds32le-elf, nds32be-elf): Add nds32 target.
+
 2013-10-29  Tobias Burnus  <burnus@net-b.de>
 
 	* gcc_update (files_and_dependencies): Add rules for
diff --git a/contrib/config-list.mk b/contrib/config-list.mk
index 6ab0ca68397..23d6e4aadda 100644
--- a/contrib/config-list.mk
+++ b/contrib/config-list.mk
@@ -47,6 +47,7 @@ LIST = aarch64-elf aarch64-linux-gnu \
   mips-wrs-vxworks mipstx39-elf mmix-knuth-mmixware mn10300-elf moxie-elf \
   moxie-uclinux moxie-rtems pdp11-aout picochip-elfOPT-enable-obsolete \
   msp430-elf \
+  nds32le-elf nds32be-elf \
   powerpc-darwin8 \
   powerpc-darwin7 powerpc64-darwin powerpc-freebsd6 powerpc-netbsd \
   powerpc-eabispe powerpc-eabisimaltivec powerpc-eabisim ppc-elf \
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3da5361978f..c2e139faaff 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,34 @@
+2013-10-31  Chung-Ju Wu  <jasonwucj@gmail.com>
+	    Shiva Chen  <shiva0217@gmail.com>
+
+	* config.gcc (nds32*-*-*): Add nds32 target.
+	* config/nds32/nds32.c: New file.
+	* config/nds32/nds32.h: New file.
+	* config/nds32/nds32.md: New file.
+	* config/nds32/constants.md: New file.
+	* config/nds32/constraints.md: New file.
+	* config/nds32/iterators.md: New file.
+	* config/nds32/nds32-doubleword.md: New file.
+	* config/nds32/nds32-intrinsic.md: New file.
+	* config/nds32/nds32_intrinsic.h: New file.
+	* config/nds32/nds32-modes.def: New file.
+	* config/nds32/nds32-multiple.md: New file.
+	* config/nds32/nds32.opt: New file.
+	* config/nds32/nds32-opts.h: New file.
+	* config/nds32/nds32-protos.h: New file.
+	* config/nds32/nds32-peephole2.md: New file.
+	* config/nds32/pipelines.md: New file.
+	* config/nds32/predicates.md: New file.
+	* config/nds32/t-mlibs: New file.
+	* common/config/nds32: New directory and files.
+
+	* doc/invoke.texi (NDS32 options): Document nds32 specific options.
+	* doc/md.texi (NDS32 family): Document nds32 specific constraints.
+	* doc/install.texi (Cross-Compiler-Specific Options): Document
+	--with-nds32-lib for nds32 target.
+	* doc/extend.texi (Function Attributes, Target Builtins): Document
+	nds32 specific attributes.
+
 2013-10-31  Vladimir Makarov  <vmakarov@redhat.com>
 
 	* lra-constraints (process_alt_operands): Use the result
diff --git a/gcc/common/config/nds32/nds32-common.c b/gcc/common/config/nds32/nds32-common.c
new file mode 100644
index 00000000000..f82f725af14
--- /dev/null
+++ b/gcc/common/config/nds32/nds32-common.c
@@ -0,0 +1,117 @@
+/* Common hooks of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "diagnostic-core.h"
+#include "tm.h"
+#include "common/common-target.h"
+#include "common/common-target-def.h"
+#include "opts.h"
+#include "flags.h"
+
+/* ------------------------------------------------------------------------ */
+
+/* Implement TARGET_HANDLE_OPTION.  */
+static bool
+nds32_handle_option (struct gcc_options *opts ATTRIBUTE_UNUSED,
+		     struct gcc_options *opts_set ATTRIBUTE_UNUSED,
+		     const struct cl_decoded_option *decoded,
+		     location_t loc)
+{
+  size_t     code  = decoded->opt_index;
+  int        value = decoded->value;
+
+  switch (code)
+    {
+    case OPT_misr_vector_size_:
+      /* Check the valid vector size: 4 or 16.  */
+      if (value != 4 && value != 16)
+	{
+	  error_at (loc, "for the option -misr-vector-size=X, the valid X "
+			 "must be: 4 or 16");
+	  return false;
+	}
+
+      return true;
+
+    case OPT_mcache_block_size_:
+      /* Check valid value: 4 8 16 32 64 128 256 512.  */
+      if (exact_log2 (value) < 2 || exact_log2 (value) > 9)
+	{
+	  error_at (loc, "for the option -mcache-block-size=X, the valid X "
+			 "must be: 4, 8, 16, 32, 64, 128, 256, or 512");
+	  return false;
+	}
+
+      return true;
+
+    default:
+      return true;
+    }
+}
+
+/* ------------------------------------------------------------------------ */
+
+/* Implement TARGET_OPTION_OPTIMIZATION_TABLE.  */
+static const struct default_options nds32_option_optimization_table[] =
+{
+  /* Enable -fomit-frame-pointer by default at -O1 or higher.  */
+  { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
+  /* Enable -mv3push by default at -Os, but it is useless under V2 ISA.  */
+  { OPT_LEVELS_SIZE,   OPT_mv3push,             NULL, 1 },
+
+  { OPT_LEVELS_NONE,   0,                       NULL, 0 }
+};
+
+/* ------------------------------------------------------------------------ */
+
+/* Run-time Target Specification.  */
+
+/* Default enable
+     TARGET_GP_DIRECT: Generate gp-imply instruction.
+     TARGET_16_BIT   : Generate 16/32 bit mixed length instruction.
+     TARGET_PERF_EXT : Generate performance extention instrcution.
+     TARGET_CMOV     : Generate conditional move instruction.  */
+#undef TARGET_DEFAULT_TARGET_FLAGS
+#define TARGET_DEFAULT_TARGET_FLAGS		\
+  (MASK_GP_DIRECT				\
+   | MASK_16_BIT				\
+   | MASK_PERF_EXT				\
+   | MASK_CMOV)
+
+#undef TARGET_HANDLE_OPTION
+#define TARGET_HANDLE_OPTION nds32_handle_option
+
+#undef TARGET_OPTION_OPTIMIZATION_TABLE
+#define TARGET_OPTION_OPTIMIZATION_TABLE nds32_option_optimization_table
+
+
+/* Defining the Output Assembler Language.  */
+
+#undef TARGET_EXCEPT_UNWIND_INFO
+#define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info
+
+/* ------------------------------------------------------------------------ */
+
+struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
+
+/* ------------------------------------------------------------------------ */
diff --git a/gcc/config.gcc b/gcc/config.gcc
index a90ab25f37a..e1878bd8b45 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -421,6 +421,10 @@ mips*-*-*)
 	extra_headers="loongson.h"
 	extra_options="${extra_options} g.opt mips/mips-tables.opt"
 	;;
+nds32*)
+	cpu_type=nds32
+	extra_headers="nds32_intrinsic.h"
+	;;
 picochip-*-*)
         cpu_type=picochip
         ;;
@@ -2091,6 +2095,18 @@ msp430*-*-*)
 	target_has_targetm_common=no
 	tmake_file="${tmake_file} msp430/t-msp430"
 	;;
+nds32le-*-*)
+	target_cpu_default="0"
+	tm_defines="${tm_defines}"
+	tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file}"
+	tmake_file="nds32/t-mlibs"
+	;;
+nds32be-*-*)
+	target_cpu_default="0|MASK_BIG_ENDIAN"
+	tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1"
+	tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file}"
+	tmake_file="nds32/t-mlibs"
+	;;
 pdp11-*-*)
 	tm_file="${tm_file} newlib-stdint.h"
 	use_gcc_stdint=wrap
@@ -3754,6 +3770,39 @@ case "${target}" in
 		esac
 		;;
 
+	nds32*-*-*)
+		supported_defaults="arch nds32_lib"
+
+		# process --with-arch
+		case "${with_arch}" in
+		"" | v2 | v3 | v3m)
+			# OK
+			;;
+		*)
+			echo "Cannot accept --with-arch=$with_arch, available values are: v2 v3 v3m" 1>&2
+			exit 1
+			;;
+		esac
+
+		# process --with-nds32-lib
+		case "${with_nds32_lib}" in
+		"")
+			# the default library is newlib
+			with_nds32_lib=newlib
+			;;
+		newlib)
+			# OK
+			;;
+		mculib)
+			# OK
+			;;
+		*)
+			echo "Cannot accept --with-nds32-lib=$with_nds32_lib, available values are: newlib mculib" 1>&2
+			exit 1
+			;;
+		esac
+		;;
+
 	powerpc*-*-* | rs6000-*-*)
 		supported_defaults="cpu cpu_32 cpu_64 float tune tune_32 tune_64"
 
diff --git a/gcc/config/nds32/constants.md b/gcc/config/nds32/constants.md
new file mode 100644
index 00000000000..03a21dba1b2
--- /dev/null
+++ b/gcc/config/nds32/constants.md
@@ -0,0 +1,46 @@
+;; Constant defintions of Andes NDS32 cpu for GNU compiler
+;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
+;; Contributed by Andes Technology Corporation.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+
+;; Register numbers.
+(define_constants
+  [(R8_REGNUM  8)
+   (TA_REGNUM 15)
+   (FP_REGNUM 28)
+   (GP_REGNUM 29)
+   (LP_REGNUM 30)
+   (SP_REGNUM 31)
+  ])
+
+
+;; The unspec_volatile operation index.
+(define_c_enum "unspec_volatile_element" [
+  UNSPEC_VOLATILE_FUNC_RETURN
+  UNSPEC_VOLATILE_ISYNC
+  UNSPEC_VOLATILE_ISB
+  UNSPEC_VOLATILE_MFSR
+  UNSPEC_VOLATILE_MFUSR
+  UNSPEC_VOLATILE_MTSR
+  UNSPEC_VOLATILE_MTUSR
+  UNSPEC_VOLATILE_SETGIE_EN
+  UNSPEC_VOLATILE_SETGIE_DIS
+])
+
+;; ------------------------------------------------------------------------
diff --git a/gcc/config/nds32/constraints.md b/gcc/config/nds32/constraints.md
new file mode 100644
index 00000000000..b4ae6c7258c
--- /dev/null
+++ b/gcc/config/nds32/constraints.md
@@ -0,0 +1,254 @@
+;; Constraint definitions of Andes NDS32 cpu for GNU compiler
+;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
+;; Contributed by Andes Technology Corporation.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; Check 16.8.7 Defining Machine-Specific Constraints for detail.
+
+;; NO contrains can be prefixed with: E F V X g i m n o p r s
+;; Machine-dependent integer: I J K L M N O P
+;; Machine-dependent floating: G H
+
+
+(define_register_constraint "w" "(TARGET_ISA_V3 || TARGET_ISA_V3M) ? LOW_REGS : NO_REGS"
+  "LOW register class $r0 ~ $r7 constraint for V3/V3M ISA")
+
+(define_register_constraint "l" "LOW_REGS"
+  "LOW register class $r0 ~ $r7")
+
+(define_register_constraint "d" "MIDDLE_REGS"
+  "MIDDLE register class $r0 ~ $r11, $r16 ~ $r19")
+
+(define_register_constraint "h" "HIGH_REGS"
+  "HIGH register class $r12 ~ $r14, $r20 ~ $r31")
+
+
+(define_register_constraint "t" "R15_TA_REG"
+  "Temporary Assist register $ta (i.e. $r15)")
+
+(define_register_constraint "k" "STACK_REG"
+  "Stack register $sp")
+
+
+(define_constraint "Iu03"
+  "Unsigned immediate 3-bit value"
+  (and (match_code "const_int")
+       (match_test "ival < (1 << 3) && ival >= 0")))
+
+(define_constraint "In03"
+  "Negative immediate 3-bit value in the range of -7 to 0"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (ival, -7, 0)")))
+
+(define_constraint "Iu04"
+  "Unsigned immediate 4-bit value"
+  (and (match_code "const_int")
+       (match_test "ival < (1 << 4) && ival >= 0")))
+
+(define_constraint "Is05"
+  "Signed immediate 5-bit value"
+  (and (match_code "const_int")
+       (match_test "ival < (1 << 4) && ival >= -(1 << 4)")))
+
+(define_constraint "Iu05"
+  "Unsigned immediate 5-bit value"
+  (and (match_code "const_int")
+       (match_test "ival < (1 << 5) && ival >= 0")))
+
+(define_constraint "In05"
+  "Negative immediate 5-bit value in the range of -31 to 0"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (ival, -31, 0)")))
+
+;; Ip05 is special and dedicated for v3 movpi45 instruction.
+;; movpi45 has imm5u field but the range is 16 ~ 47.
+(define_constraint "Ip05"
+  "Unsigned immediate 5-bit value for movpi45 instruction with range 16-47"
+  (and (match_code "const_int")
+       (match_test "ival < ((1 << 5) + 16)
+		    && ival >= (0 + 16)
+		    && (TARGET_ISA_V3 || TARGET_ISA_V3M)")))
+
+(define_constraint "Iu06"
+  "Unsigned immediate 6-bit value constraint for addri36.sp instruction"
+  (and (match_code "const_int")
+       (match_test "ival < (1 << 6)
+		    && ival >= 0
+		    && (ival % 4 == 0)
+		    && (TARGET_ISA_V3 || TARGET_ISA_V3M)")))
+
+(define_constraint "Iu08"
+  "Unsigned immediate 8-bit value"
+  (and (match_code "const_int")
+       (match_test "ival < (1 << 8) && ival >= 0")))
+
+(define_constraint "Iu09"
+  "Unsigned immediate 9-bit value"
+  (and (match_code "const_int")
+       (match_test "ival < (1 << 9) && ival >= 0")))
+
+
+(define_constraint "Is10"
+  "Signed immediate 10-bit value"
+  (and (match_code "const_int")
+       (match_test "ival < (1 << 9) && ival >= -(1 << 9)")))
+
+(define_constraint "Is11"
+  "Signed immediate 11-bit value"
+  (and (match_code "const_int")
+       (match_test "ival < (1 << 10) && ival >= -(1 << 10)")))
+
+
+(define_constraint "Is15"
+  "Signed immediate 15-bit value"
+  (and (match_code "const_int")
+       (match_test "ival < (1 << 14) && ival >= -(1 << 14)")))
+
+(define_constraint "Iu15"
+  "Unsigned immediate 15-bit value"
+  (and (match_code "const_int")
+       (match_test "ival < (1 << 15) && ival >= 0")))
+
+
+;; Ic15 is special and dedicated for performance extension
+;; 'bclr' (single-bit-clear) instruction.
+;; It is used in andsi3 pattern and recognized for the immediate
+;; which is NOT in the range of imm15u but OK for 'bclr' instruction.
+;; (If the immediate value IS in the range of imm15u,
+;;  we can directly use 'andi' instruction.)
+(define_constraint "Ic15"
+  "A constant which is not in the range of imm15u but ok for bclr instruction"
+  (and (match_code "const_int")
+       (match_test "(ival & 0xffff8000) && nds32_can_use_bclr_p (ival)")))
+
+;; Ie15 is special and dedicated for performance extension
+;; 'bset' (single-bit-set) instruction.
+;; It is used in iorsi3 pattern and recognized for the immediate
+;; which is NOT in the range of imm15u but OK for 'bset' instruction.
+;; (If the immediate value IS in the range of imm15u,
+;;  we can directly use 'ori' instruction.)
+(define_constraint "Ie15"
+  "A constant which is not in the range of imm15u but ok for bset instruction"
+  (and (match_code "const_int")
+       (match_test "(ival & 0xffff8000) && nds32_can_use_bset_p (ival)")))
+
+;; It15 is special and dedicated for performance extension
+;; 'btgl' (single-bit-toggle) instruction.
+;; It is used in xorsi3 pattern and recognized for the immediate
+;; which is NOT in the range of imm15u but OK for 'btgl' instruction.
+;; (If the immediate value IS in the range of imm15u,
+;;  we can directly use 'xori' instruction.)
+(define_constraint "It15"
+  "A constant which is not in the range of imm15u but ok for btgl instruction"
+  (and (match_code "const_int")
+       (match_test "(ival & 0xffff8000) && nds32_can_use_btgl_p (ival)")))
+
+
+;; Ii15 is special and dedicated for v3 isa
+;; 'bitci' (bit-clear-immediate) instruction.
+;; It is used in andsi3 pattern and recognized for the immediate whose
+;; (~ival) value is in the range of imm15u and OK for 'bitci' instruction.
+;; For example, 'andi $r0,$r0,0xfffffffc' can be presented
+;  with 'bitci $r0,$r0,3'.
+(define_constraint "Ii15"
+  "A constant whose compliment value is in the range of imm15u
+   and ok for bitci instruction"
+  (and (match_code "const_int")
+       (match_test "nds32_can_use_bitci_p (ival)")))
+
+
+(define_constraint "Is16"
+  "Signed immediate 16-bit value"
+  (and (match_code "const_int")
+       (match_test "ival < (1 << 15) && ival >= -(1 << 15)")))
+
+(define_constraint "Is17"
+  "Signed immediate 17-bit value"
+  (and (match_code "const_int")
+       (match_test "ival < (1 << 16) && ival >= -(1 << 16)")))
+
+
+(define_constraint "Is19"
+  "Signed immediate 19-bit value"
+  (and (match_code "const_int")
+       (match_test "ival < (1 << 18) && ival >= -(1 << 18)")))
+
+
+(define_constraint "Is20"
+  "Signed immediate 20-bit value"
+  (and (match_code "const_int")
+       (match_test "ival < (1 << 19) && ival >= -(1 << 19)")))
+
+
+(define_constraint "Ihig"
+  "The immediate value that can be simply set high 20-bit"
+  (and (match_code "const_int")
+       (match_test "(ival != 0) && ((ival & 0xfff) == 0)")))
+
+(define_constraint "Izeb"
+  "The immediate value 0xff"
+  (and (match_code "const_int")
+       (match_test "(ival == 0xff)")))
+
+(define_constraint "Izeh"
+  "The immediate value 0xffff"
+  (and (match_code "const_int")
+       (match_test "(ival == 0xffff)")))
+
+(define_constraint "Ixls"
+  "The immediate value 0x01"
+  (and (match_code "const_int")
+       (match_test "TARGET_PERF_EXT && (ival == 0x1)")))
+
+(define_constraint "Ix11"
+  "The immediate value 0x7ff"
+  (and (match_code "const_int")
+       (match_test "TARGET_PERF_EXT && (ival == 0x7ff)")))
+
+(define_constraint "Ibms"
+  "The immediate value with power of 2"
+  (and (match_code "const_int")
+       (match_test "(TARGET_ISA_V3 || TARGET_ISA_V3M)
+		    && (IN_RANGE (exact_log2 (ival), 0, 7))")))
+
+(define_constraint "Ifex"
+  "The immediate value with power of 2 minus 1"
+  (and (match_code "const_int")
+       (match_test "(TARGET_ISA_V3 || TARGET_ISA_V3M)
+		    && (IN_RANGE (exact_log2 (ival + 1), 1, 8))")))
+
+
+(define_memory_constraint "U33"
+  "Memory constraint for 333 format"
+  (and (match_code "mem")
+       (match_test "nds32_mem_format (op) == ADDRESS_LO_REG_IMM3U")))
+
+(define_memory_constraint "U45"
+  "Memory constraint for 45 format"
+  (and (match_code "mem")
+       (match_test "(nds32_mem_format (op) == ADDRESS_REG)
+		    && (GET_MODE (op) == SImode)")))
+
+(define_memory_constraint "U37"
+  "Memory constraint for 37 format"
+  (and (match_code "mem")
+       (match_test "(nds32_mem_format (op) == ADDRESS_SP_IMM7U
+		    || nds32_mem_format (op) == ADDRESS_FP_IMM7U)
+		    && (GET_MODE (op) == SImode)")))
+
+;; ------------------------------------------------------------------------
diff --git a/gcc/config/nds32/iterators.md b/gcc/config/nds32/iterators.md
new file mode 100644
index 00000000000..6ec519618a9
--- /dev/null
+++ b/gcc/config/nds32/iterators.md
@@ -0,0 +1,55 @@
+;; Code and mode itertator and attribute definitions
+;; of Andes NDS32 cpu for GNU compiler
+;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
+;; Contributed by Andes Technology Corporation.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;;----------------------------------------------------------------------------
+;; Mode iterators.
+;;----------------------------------------------------------------------------
+
+;; A list of integer modes that are up to one word long.
+(define_mode_iterator QIHISI [QI HI SI])
+
+;; A list of integer modes that are up to one half-word long.
+(define_mode_iterator QIHI [QI HI])
+
+;; A list of the modes that are up to double-word long.
+(define_mode_iterator DIDF [DI DF])
+
+
+;;----------------------------------------------------------------------------
+;; Mode attributes.
+;;----------------------------------------------------------------------------
+
+(define_mode_attr size [(QI "b") (HI "h") (SI "w")])
+
+(define_mode_attr byte [(QI "1") (HI "2") (SI "4")])
+
+
+;;----------------------------------------------------------------------------
+;; Code iterators.
+;;----------------------------------------------------------------------------
+
+
+;;----------------------------------------------------------------------------
+;; Code attributes.
+;;----------------------------------------------------------------------------
+
+
+;;----------------------------------------------------------------------------
diff --git a/gcc/config/nds32/nds32-doubleword.md b/gcc/config/nds32/nds32-doubleword.md
new file mode 100644
index 00000000000..4bfede4236a
--- /dev/null
+++ b/gcc/config/nds32/nds32-doubleword.md
@@ -0,0 +1,251 @@
+;; DImode/DFmode patterns description of Andes NDS32 cpu for GNU compiler
+;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
+;; Contributed by Andes Technology Corporation.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+
+;; -------------------------------------------------------------
+;; Move DImode/DFmode instructions.
+;; -------------------------------------------------------------
+
+
+(define_expand "movdi"
+  [(set (match_operand:DI 0 "general_operand" "")
+	(match_operand:DI 1 "general_operand" ""))]
+  ""
+{
+  /* Need to force register if mem <- !reg.  */
+  if (MEM_P (operands[0]) && !REG_P (operands[1]))
+    operands[1] = force_reg (DImode, operands[1]);
+})
+
+(define_expand "movdf"
+  [(set (match_operand:DF 0 "general_operand" "")
+	(match_operand:DF 1 "general_operand" ""))]
+  ""
+{
+  /* Need to force register if mem <- !reg.  */
+  if (MEM_P (operands[0]) && !REG_P (operands[1]))
+    operands[1] = force_reg (DFmode, operands[1]);
+})
+
+
+(define_insn "move_<mode>"
+  [(set (match_operand:DIDF 0 "nonimmediate_operand" "=r, r, r, m")
+	(match_operand:DIDF 1 "general_operand"      " r, i, m, r"))]
+  ""
+{
+  rtx addr;
+  rtx otherops[5];
+
+  switch (which_alternative)
+    {
+    case 0:
+      return "movd44\t%0, %1";
+
+    case 1:
+      /* reg <- const_int, we ask gcc to split instruction.  */
+      return "#";
+
+    case 2:
+      /* Refer to nds32_legitimate_address_p() in nds32.c,
+         we only allow "reg", "symbol_ref", "const", and "reg + const_int"
+         as address rtx for DImode/DFmode memory access.  */
+      addr = XEXP (operands[1], 0);
+
+      otherops[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
+      otherops[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
+      otherops[2] = addr;
+
+      if (REG_P (addr))
+	{
+	  /* (reg) <- (mem (reg)) */
+	  output_asm_insn ("lmw.bi\t%0, [%2], %1, 0", otherops);
+	}
+      else if (GET_CODE (addr) == PLUS)
+	{
+	  /* (reg) <- (mem (plus (reg) (const_int))) */
+	  rtx op0 = XEXP (addr, 0);
+	  rtx op1 = XEXP (addr, 1);
+
+	  if (REG_P (op0))
+	    {
+	      otherops[2] = op0;
+	      otherops[3] = op1;
+	      otherops[4] = gen_int_mode (INTVAL (op1) + 4, SImode);
+	    }
+	  else
+	    {
+	      otherops[2] = op1;
+	      otherops[3] = op0;
+	      otherops[4] = gen_int_mode (INTVAL (op0) + 4, SImode);
+	    }
+
+	  /* To avoid base overwrite when REGNO(%0) == REGNO(%2).  */
+	  if (REGNO (otherops[0]) != REGNO (otherops[2]))
+	    {
+	      output_asm_insn ("lwi\t%0, [%2 + (%3)]", otherops);
+	      output_asm_insn ("lwi\t%1, [%2 + (%4)]", otherops);
+	    }
+	  else
+	    {
+	      output_asm_insn ("lwi\t%1, [%2 + (%4)]", otherops);
+	      output_asm_insn ("lwi\t%0,[ %2 + (%3)]", otherops);
+	    }
+	}
+      else
+	{
+	  /* (reg) <- (mem (symbol_ref ...))
+	     (reg) <- (mem (const ...)) */
+	  output_asm_insn ("lwi.gp\t%0, [ + %2]", otherops);
+	  output_asm_insn ("lwi.gp\t%1, [ + %2 + 4]", otherops);
+	}
+
+      /* We have already used output_asm_insn() by ourself,
+         so return an empty string.  */
+      return "";
+
+    case 3:
+      /* Refer to nds32_legitimate_address_p() in nds32.c,
+         we only allow "reg", "symbol_ref", "const", and "reg + const_int"
+         as address rtx for DImode/DFmode memory access.  */
+      addr = XEXP (operands[0], 0);
+
+      otherops[0] = gen_rtx_REG (SImode, REGNO (operands[1]));
+      otherops[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
+      otherops[2] = addr;
+
+      if (REG_P (addr))
+	{
+	  /* (mem (reg)) <- (reg) */
+	  output_asm_insn ("smw.bi\t%0, [%2], %1, 0", otherops);
+	}
+      else if (GET_CODE (addr) == PLUS)
+	{
+	  /* (mem (plus (reg) (const_int))) <- (reg) */
+	  rtx op0 = XEXP (addr, 0);
+	  rtx op1 = XEXP (addr, 1);
+
+	  if (REG_P (op0))
+	    {
+	      otherops[2] = op0;
+	      otherops[3] = op1;
+	      otherops[4] = gen_int_mode (INTVAL (op1) + 4, SImode);
+	    }
+	  else
+	    {
+	      otherops[2] = op1;
+	      otherops[3] = op0;
+	      otherops[4] = gen_int_mode (INTVAL (op0) + 4, SImode);
+	    }
+
+	  /* To avoid base overwrite when REGNO(%0) == REGNO(%2).  */
+	  if (REGNO (otherops[0]) != REGNO (otherops[2]))
+	    {
+	      output_asm_insn ("swi\t%0, [%2 + (%3)]", otherops);
+	      output_asm_insn ("swi\t%1, [%2 + (%4)]", otherops);
+	    }
+	  else
+	    {
+	      output_asm_insn ("swi\t%1, [%2 + (%4)]", otherops);
+	      output_asm_insn ("swi\t%0, [%2 + (%3)]", otherops);
+	    }
+	}
+      else
+	{
+	  /* (mem (symbol_ref ...)) <- (reg)
+	     (mem (const ...))      <- (reg) */
+	  output_asm_insn ("swi.gp\t%0, [ + %2]", otherops);
+	  output_asm_insn ("swi.gp\t%1, [ + %2 + 4]", otherops);
+	}
+
+      /* We have already used output_asm_insn() by ourself,
+         so return an empty string.  */
+      return "";
+
+    default:
+      gcc_unreachable ();
+    }
+}
+  [(set_attr "type"   "move,move,move,move")
+   (set_attr "length" "   4,  16,   8,   8")])
+
+(define_split
+  [(set (match_operand:DIDF 0 "register_operand"     "")
+	(match_operand:DIDF 1 "const_double_operand" ""))]
+  "reload_completed"
+  [(set (match_dup 2) (match_dup 3))
+   (set (match_dup 4) (match_dup 5))]
+{
+  /* Construct lowpart rtx.  */
+  operands[2] = gen_lowpart (SImode, operands[0]);
+  operands[3] = gen_lowpart (SImode, operands[1]);
+
+  /* Construct highpart rtx.  */
+  /* Note that operands[1] can be VOIDmode constant,
+     so we need to use gen_highpart_mode().
+     Refer to gcc/emit-rtl.c for more information.  */
+  operands[4] = gen_highpart (SImode, operands[0]);
+  operands[5] = gen_highpart_mode (SImode,
+				   GET_MODE (operands[0]), operands[1]);
+
+  /* Actually we would like to create move behavior by ourself.
+     So that movsi expander could have chance to split large constant.  */
+  emit_move_insn (operands[2], operands[3]);
+  emit_move_insn (operands[4], operands[5]);
+  DONE;
+})
+
+;; There is 'movd44' instruction for DImode/DFmode movement under V3/V3M ISA.
+;; We only need to split it under V2 ISA or none-16-bit code generation.
+(define_split
+  [(set (match_operand:DIDF 0 "register_operand" "")
+	(match_operand:DIDF 1 "register_operand" ""))]
+  "reload_completed
+   && (TARGET_ISA_V2 || !TARGET_16_BIT)"
+  [(set (match_dup 0) (match_dup 1))
+   (set (match_dup 2) (match_dup 3))]
+{
+  operands[2] = gen_highpart (SImode, operands[0]);
+  operands[3] = gen_highpart (SImode, operands[1]);
+  operands[0] = gen_lowpart (SImode, operands[0]);
+  operands[1] = gen_lowpart (SImode, operands[1]);
+
+  /* Handle a partial overlap.  */
+  if (rtx_equal_p (operands[0], operands[3]))
+    {
+      rtx tmp0 = operands[0];
+      rtx tmp1 = operands[1];
+
+      operands[0] = operands[2];
+      operands[1] = operands[3];
+      operands[2] = tmp0;
+      operands[3] = tmp1;
+    }
+})
+
+;; -------------------------------------------------------------
+;; Boolean DImode instructions.
+;; -------------------------------------------------------------
+
+;; Nowadays, the generic code is supposed to split the DImode
+;; boolean operations and have good code generation.
+;; Unless we find out some bad cases, there is no need to
+;; define DImode boolean operations by ourself.
+
+;; -------------------------------------------------------------
diff --git a/gcc/config/nds32/nds32-intrinsic.md b/gcc/config/nds32/nds32-intrinsic.md
new file mode 100644
index 00000000000..4ee2d851023
--- /dev/null
+++ b/gcc/config/nds32/nds32-intrinsic.md
@@ -0,0 +1,97 @@
+;; Intrinsic patterns description of Andes NDS32 cpu for GNU compiler
+;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
+;; Contributed by Andes Technology Corporation.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; ------------------------------------------------------------------------
+
+;; Register Transfer.
+
+(define_insn "unspec_volatile_mfsr"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_MFSR))]
+  ""
+  "mfsr\t%0, %V1"
+  [(set_attr "type"   "misc")
+   (set_attr "length"    "4")]
+)
+
+(define_insn "unspec_volatile_mfusr"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_MFUSR))]
+  ""
+  "mfusr\t%0, %V1"
+  [(set_attr "type"   "misc")
+   (set_attr "length"    "4")]
+)
+
+(define_insn "unspec_volatile_mtsr"
+  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
+			(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_MTSR)]
+  ""
+  "mtsr\t%0, %V1"
+  [(set_attr "type"   "misc")
+   (set_attr "length"    "4")]
+)
+
+(define_insn "unspec_volatile_mtusr"
+  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
+			(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_MTUSR)]
+  ""
+  "mtusr\t%0, %V1"
+  [(set_attr "type"   "misc")
+   (set_attr "length"    "4")]
+)
+
+;; ------------------------------------------------------------------------
+
+;; Interrupt Instructions.
+
+(define_insn "unspec_volatile_setgie_en"
+  [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_SETGIE_EN)]
+  ""
+  "setgie.e"
+  [(set_attr "type" "misc")]
+)
+
+(define_insn "unspec_volatile_setgie_dis"
+  [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_SETGIE_DIS)]
+  ""
+  "setgie.d"
+  [(set_attr "type" "misc")]
+)
+
+;; ------------------------------------------------------------------------
+
+;; Cache Synchronization Instructions
+
+(define_insn "unspec_volatile_isync"
+  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_ISYNC)]
+  ""
+  "isync\t%0"
+  [(set_attr "type" "misc")]
+)
+
+(define_insn "unspec_volatile_isb"
+  [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_ISB)]
+  ""
+  "isb"
+  [(set_attr "type" "misc")]
+)
+
+;; ------------------------------------------------------------------------
diff --git a/gcc/config/nds32/nds32-modes.def b/gcc/config/nds32/nds32-modes.def
new file mode 100644
index 00000000000..9d32ada0ce8
--- /dev/null
+++ b/gcc/config/nds32/nds32-modes.def
@@ -0,0 +1,21 @@
+/* Extra machine modes of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+/* So far, there is no need to define any modes for nds32 target.  */
diff --git a/gcc/config/nds32/nds32-multiple.md b/gcc/config/nds32/nds32-multiple.md
new file mode 100644
index 00000000000..da89a490d3a
--- /dev/null
+++ b/gcc/config/nds32/nds32-multiple.md
@@ -0,0 +1,410 @@
+;; Load/Store Multiple patterns description of Andes NDS32 cpu for GNU compiler
+;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
+;; Contributed by Andes Technology Corporation.for NDS32.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+
+;; Load Multiple Insns.
+;;
+;; operands[0] is the first of the consecutive registers.
+;; operands[1] is the first memory location.
+;; operands[2] is the number of consecutive registers.
+
+(define_expand "load_multiple"
+  [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
+			  (match_operand:SI 1 "" ""))
+		     (use (match_operand:SI 2 "" ""))])]
+  ""
+{
+  int maximum;
+
+  /* Because reduced-set regsiters has few registers
+     (r0~r5, r6~10, r15, r28~r31, where 'r15' and 'r28~r31' cannot
+     be used for register allocation),
+     using 8 registers for load_multiple may easily consume all of them.
+     It makes register allocation/spilling hard to work.
+     So we only allow maximum=4 registers for load_multiple
+     under reduced-set registers.  */
+  if (TARGET_REDUCED_REGS)
+    maximum = 4;
+  else
+    maximum = 8;
+
+  /* Here are the conditions that must be all passed,
+     otherwise we have to FAIL this rtx generation:
+       1. The number of consecutive registers must be integer.
+       2. Maximum 4 or 8 registers for lmw.bi instruction
+          (based on this nds32-multiple.md design).
+       3. Minimum 2 registers for lmw.bi instruction
+          (based on this nds32-multiple.md design).
+       4. operands[0] must be register for sure.
+       5. operands[1] must be memory for sure.
+       6. Do not cross $r15 register because it is not allocatable.  */
+  if (GET_CODE (operands[2]) != CONST_INT
+      || INTVAL (operands[2]) > maximum
+      || INTVAL (operands[2]) < 2
+      || GET_CODE (operands[0]) != REG
+      || GET_CODE (operands[1]) != MEM
+      || REGNO (operands[0]) + INTVAL (operands[2]) > TA_REGNUM)
+    FAIL;
+
+  /* For (mem addr), we force_reg on addr here,
+     so that nds32_expand_load_multiple can easily use it.  */
+  operands[3] = nds32_expand_load_multiple (REGNO (operands[0]),
+					    INTVAL (operands[2]),
+					    force_reg (SImode,
+						       XEXP (operands[1], 0)),
+					    operands[1]);
+})
+
+;; Ordinary Load Multiple.
+
+(define_insn "*lmwsi8"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 20))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 24))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
+  "(XVECLEN (operands[0], 0) == 8)"
+  "lmw.bi\t%2, [%1], %9, 0x0"
+  [(set_attr "type"   "load")
+   (set_attr "length"    "4")]
+)
+
+(define_insn "*lmwsi7"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 20))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
+  "(XVECLEN (operands[0], 0) == 7)"
+  "lmw.bi\t%2, [%1], %8, 0x0"
+  [(set_attr "type"   "load")
+   (set_attr "length"    "4")]
+)
+
+(define_insn "*lmwsi6"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
+  "(XVECLEN (operands[0], 0) == 6)"
+  "lmw.bi\t%2, [%1], %7, 0x0"
+  [(set_attr "type"   "load")
+   (set_attr "length"    "4")]
+)
+
+(define_insn "*lmwsi5"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
+  "(XVECLEN (operands[0], 0) == 5)"
+  "lmw.bi\t%2, [%1], %6, 0x0"
+  [(set_attr "type"   "load")
+   (set_attr "length"    "4")]
+)
+
+(define_insn "*lmwsi4"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
+  "(XVECLEN (operands[0], 0) == 4)"
+  "lmw.bi\t%2, [%1], %5, 0x0"
+  [(set_attr "type"   "load")
+   (set_attr "length"    "4")]
+)
+
+(define_insn "*lmwsi3"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
+  "(XVECLEN (operands[0], 0) == 3)"
+  "lmw.bi\t%2, [%1], %4, 0x0"
+  [(set_attr "type"   "load")
+   (set_attr "length"    "4")]
+)
+
+(define_insn "*lmwsi2"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))])]
+  "(XVECLEN (operands[0], 0) == 2)"
+  "lmw.bi\t%2, [%1], %3, 0x0"
+  [(set_attr "type"   "load")
+   (set_attr "length"    "4")]
+)
+
+
+;; Store Multiple Insns.
+;;
+;; operands[0] is the first memory location.
+;; opernads[1] is the first of the consecutive registers.
+;; operands[2] is the number of consecutive registers.
+
+(define_expand "store_multiple"
+  [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
+			  (match_operand:SI 1 "" ""))
+		     (use (match_operand:SI 2 "" ""))])]
+  ""
+{
+  int maximum;
+
+  /* Because reduced-set regsiters has few registers
+     (r0~r5, r6~10, r15, r28~r31, where 'r15' and 'r28~r31' cannot
+     be used for register allocation),
+     using 8 registers for store_multiple may easily consume all of them.
+     It makes register allocation/spilling hard to work.
+     So we only allow maximum=4 registers for store_multiple
+     under reduced-set registers.  */
+  if (TARGET_REDUCED_REGS)
+    maximum = 4;
+  else
+    maximum = 8;
+
+  /* Here are the conditions that must be all passed,
+     otherwise we have to FAIL this rtx generation:
+       1. The number of consecutive registers must be integer.
+       2. Maximum 4 or 8 registers for smw.bi instruction
+          (based on this nds32-multiple.md design).
+       3. Minimum 2 registers for smw.bi instruction
+          (based on this nds32-multiple.md design).
+       4. operands[0] must be memory for sure.
+       5. operands[1] must be register for sure.
+       6. Do not cross $r15 register because it is not allocatable.  */
+  if (GET_CODE (operands[2]) != CONST_INT
+      || INTVAL (operands[2]) > maximum
+      || INTVAL (operands[2]) < 2
+      || GET_CODE (operands[0]) != MEM
+      || GET_CODE (operands[1]) != REG
+      || REGNO (operands[1]) + INTVAL (operands[2]) > TA_REGNUM)
+    FAIL;
+
+  /* For (mem addr), we force_reg on addr here,
+     so that nds32_expand_store_multiple can easily use it.  */
+  operands[3] = nds32_expand_store_multiple (REGNO (operands[1]),
+					     INTVAL (operands[2]),
+					     force_reg (SImode,
+							XEXP (operands[0], 0)),
+					     operands[0]);
+})
+
+;; Ordinary Store Multiple.
+
+(define_insn "*stmsi8"
+  [(match_parallel 0 "nds32_store_multiple_operation"
+    [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	  (match_operand:SI 2 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
+	  (match_operand:SI 9 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 8)"
+  "smw.bi\t%2, [%1], %9, 0x0"
+  [(set_attr "type"   "store")
+   (set_attr "length"     "4")]
+)
+
+(define_insn "*stmsi7"
+  [(match_parallel 0 "nds32_store_multiple_operation"
+    [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	  (match_operand:SI 2 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
+	  (match_operand:SI 8 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 7)"
+  "smw.bi\t%2, [%1], %8, 0x0"
+  [(set_attr "type"   "store")
+   (set_attr "length"     "4")]
+)
+
+(define_insn "*stmsi6"
+  [(match_parallel 0 "nds32_store_multiple_operation"
+    [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	  (match_operand:SI 2 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
+	  (match_operand:SI 7 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 6)"
+  "smw.bi\t%2, [%1], %7, 0x0"
+  [(set_attr "type"   "store")
+   (set_attr "length"     "4")]
+)
+
+(define_insn "*stmsi5"
+  [(match_parallel 0 "nds32_store_multiple_operation"
+    [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	  (match_operand:SI 2 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
+	  (match_operand:SI 6 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 5)"
+  "smw.bi\t%2, [%1], %6, 0x0"
+  [(set_attr "type"   "store")
+   (set_attr "length"     "4")]
+)
+
+(define_insn "*stmsi4"
+  [(match_parallel 0 "nds32_store_multiple_operation"
+    [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	  (match_operand:SI 2 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
+	  (match_operand:SI 5 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 4)"
+  "smw.bi\t%2, [%1], %5, 0x0"
+  [(set_attr "type"   "store")
+   (set_attr "length"     "4")]
+)
+
+(define_insn "*stmsi3"
+  [(match_parallel 0 "nds32_store_multiple_operation"
+    [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	  (match_operand:SI 2 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
+	  (match_operand:SI 4 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 3)"
+  "smw.bi\t%2, [%1], %4, 0x0"
+  [(set_attr "type"   "store")
+   (set_attr "length"     "4")]
+)
+
+(define_insn "*stmsi2"
+  [(match_parallel 0 "nds32_store_multiple_operation"
+    [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	  (match_operand:SI 2 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+	  (match_operand:SI 3 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 2)"
+  "smw.bi\t%2, [%1], %3, 0x0"
+  [(set_attr "type"   "store")
+   (set_attr "length"     "4")]
+)
+
+;; Move a block of memory if it is word aligned and MORE than 2 words long.
+;; We could let this apply for blocks of less than this, but it clobbers so
+;; many registers that there is then probably a better way.
+;;
+;; operands[0] is the destination block of memory.
+;; operands[1] is the source block of memory.
+;; operands[2] is the number of bytes to move.
+;; operands[3] is the known shared alignment.
+
+(define_expand "movmemqi"
+  [(match_operand:BLK 0 "general_operand" "")
+   (match_operand:BLK 1 "general_operand" "")
+   (match_operand:SI 2 "const_int_operand" "")
+   (match_operand:SI 3 "const_int_operand" "")]
+  ""
+{
+  if (nds32_expand_movmemqi (operands[0],
+			     operands[1],
+			     operands[2],
+			     operands[3]))
+    DONE;
+
+  FAIL;
+})
+
+;; ------------------------------------------------------------------------
diff --git a/gcc/config/nds32/nds32-opts.h b/gcc/config/nds32/nds32-opts.h
new file mode 100644
index 00000000000..b38672f0e2f
--- /dev/null
+++ b/gcc/config/nds32/nds32-opts.h
@@ -0,0 +1,35 @@
+/* Definitions for option handling of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef NDS32_OPTS_H
+#define NDS32_OPTS_H
+
+#define NDS32_DEFAULT_CACHE_BLOCK_SIZE 16
+#define NDS32_DEFAULT_ISR_VECTOR_SIZE (TARGET_ISA_V3 ? 4 : 16)
+
+/* The various ANDES ISA.  */
+enum nds32_arch_type
+{
+  ARCH_V2,
+  ARCH_V3,
+  ARCH_V3M
+};
+
+#endif
diff --git a/gcc/config/nds32/nds32-peephole2.md b/gcc/config/nds32/nds32-peephole2.md
new file mode 100644
index 00000000000..dbe2d6c8a62
--- /dev/null
+++ b/gcc/config/nds32/nds32-peephole2.md
@@ -0,0 +1,25 @@
+;; define_peephole2 optimization patterns of Andes NDS32 cpu for GNU compiler
+;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
+;; Contributed by Andes Technology Corporation.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+
+;; Use define_peephole and define_peephole2 to handle possible
+;; target-specific optimization in this file.
+
+;; ------------------------------------------------------------------------
diff --git a/gcc/config/nds32/nds32-protos.h b/gcc/config/nds32/nds32-protos.h
new file mode 100644
index 00000000000..2bc405db0f4
--- /dev/null
+++ b/gcc/config/nds32/nds32-protos.h
@@ -0,0 +1,128 @@
+/* Prototypes for exported functions of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+
+/* ------------------------------------------------------------------------ */
+
+/* Defining Data Structures for Per-function Information.  */
+
+extern void nds32_init_expanders (void);
+
+
+/* Register Usage.  */
+
+/* -- How Values Fit in Registers.  */
+
+extern int nds32_hard_regno_nregs (int, enum machine_mode);
+extern int nds32_hard_regno_mode_ok (int, enum machine_mode);
+
+
+/* Register Classes.  */
+
+extern enum reg_class nds32_regno_reg_class (int);
+
+
+/* Stack Layout and Calling Conventions.  */
+
+/* -- Basic Stack Layout.  */
+
+extern rtx nds32_return_addr_rtx (int, rtx);
+
+/* -- Eliminating Frame Pointer and Arg Pointer.  */
+
+extern HOST_WIDE_INT nds32_initial_elimination_offset (unsigned int,
+						       unsigned int);
+
+/* -- Passing Arguments in Registers.  */
+
+extern void nds32_init_cumulative_args (CUMULATIVE_ARGS *,
+					tree, rtx, tree, int);
+
+/* -- Function Entry and Exit.  */
+
+extern void nds32_expand_prologue (void);
+extern void nds32_expand_epilogue (void);
+extern void nds32_expand_prologue_v3push (void);
+extern void nds32_expand_epilogue_v3pop (void);
+
+/* ------------------------------------------------------------------------ */
+
+/* Auxiliary functions for auxiliary macros in nds32.h.  */
+
+extern bool nds32_ls_333_p (rtx, rtx, rtx, enum machine_mode);
+
+/* Auxiliary functions for expanding rtl used in nds32-multiple.md.  */
+
+extern rtx nds32_expand_load_multiple (int, int, rtx, rtx);
+extern rtx nds32_expand_store_multiple (int, int, rtx, rtx);
+extern int nds32_expand_movmemqi (rtx, rtx, rtx, rtx);
+
+/* Auxiliary functions for multiple load/store predicate checking.  */
+
+extern bool nds32_valid_multiple_load_store (rtx, bool);
+
+/* Auxiliary functions for stack operation predicate checking.  */
+
+extern bool nds32_valid_stack_push_pop (rtx, bool);
+
+/* Auxiliary functions for bit operation detection.  */
+
+extern int nds32_can_use_bclr_p (int);
+extern int nds32_can_use_bset_p (int);
+extern int nds32_can_use_btgl_p (int);
+
+extern int nds32_can_use_bitci_p (int);
+
+/* Auxiliary function for 'Computing the Length of an Insn'.  */
+
+extern int nds32_adjust_insn_length (rtx, int);
+
+/* Auxiliary functions for FP_AS_GP detection.  */
+
+extern bool nds32_symbol_load_store_p (rtx);
+extern int nds32_fp_as_gp_check_available (void);
+
+/* Auxiliary functions for jump table generation.  */
+
+extern const char *nds32_output_casesi_pc_relative (rtx *);
+extern const char *nds32_output_casesi (rtx *);
+
+/* Auxiliary functions to identify 16 bit addresing mode.  */
+
+extern enum nds32_16bit_address_type nds32_mem_format (rtx);
+
+/* Auxiliary functions to output assembly code.  */
+
+extern const char *nds32_output_16bit_store (rtx *, int);
+extern const char *nds32_output_16bit_load (rtx *, int);
+extern const char *nds32_output_32bit_store (rtx *, int);
+extern const char *nds32_output_32bit_load (rtx *, int);
+extern const char *nds32_output_32bit_load_s (rtx *, int);
+
+/* Auxiliary functions to output stack push/pop instruction.  */
+
+extern const char *nds32_output_stack_push (void);
+extern const char *nds32_output_stack_pop (void);
+
+/* Auxiliary functions to decide output alignment or not.  */
+
+extern int nds32_target_alignment (rtx);
+
+/* ------------------------------------------------------------------------ */
diff --git a/gcc/config/nds32/nds32.c b/gcc/config/nds32/nds32.c
new file mode 100644
index 00000000000..2700a872360
--- /dev/null
+++ b/gcc/config/nds32/nds32.c
@@ -0,0 +1,5721 @@
+/* Subroutines used for code generation of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "tree.h"
+#include "rtl.h"
+#include "regs.h"
+#include "hard-reg-set.h"
+#include "insn-config.h"	/* Required by recog.h.  */
+#include "conditions.h"
+#include "output.h"
+#include "insn-attr.h"		/* For DFA state_t.  */
+#include "insn-codes.h"		/* For CODE_FOR_xxx.  */
+#include "reload.h"		/* For push_reload().  */
+#include "flags.h"
+#include "function.h"
+#include "expr.h"
+#include "recog.h"
+#include "diagnostic-core.h"
+#include "df.h"
+#include "tm_p.h"
+#include "tm-constrs.h"
+#include "optabs.h"		/* For GEN_FCN.  */
+#include "target.h"
+#include "target-def.h"
+#include "langhooks.h"		/* For add_builtin_function().  */
+#include "ggc.h"
+
+/* ------------------------------------------------------------------------ */
+
+/* This file is divided into five parts:
+
+     PART 1: Auxiliary static variable definitions and
+             target hook static variable definitions.
+
+     PART 2: Auxiliary static function definitions.
+
+     PART 3: Implement target hook stuff definitions.
+
+     PART 4: Implemet extern function definitions,
+             the prototype is in nds32-protos.h.
+
+     PART 5: Initialize target hook structure and definitions.  */
+
+/* ------------------------------------------------------------------------ */
+
+/* PART 1: Auxiliary static variable definitions and
+           target hook static variable definitions.  */
+
+/* Refer to nds32.h, there are maximum 73 isr vectors in nds32 architecture.
+   0 for reset handler with __attribute__((reset())),
+   1-8 for exception handler with __attribute__((exception(1,...,8))),
+   and 9-72 for interrupt handler with __attribute__((interrupt(0,...,63))).
+   We use an array to record essential information for each vector.  */
+static struct nds32_isr_info nds32_isr_vectors[NDS32_N_ISR_VECTORS];
+
+/* Define intrinsic register names.
+   Please refer to nds32_intrinsic.h file, the index is corresponding to
+   'enum nds32_intrinsic_registers' data type values.
+   NOTE that the base value starting from 1024.  */
+static const char * const nds32_intrinsic_register_names[] =
+{
+  "$PSW", "$IPSW", "$ITYPE", "$IPC"
+};
+
+/* Defining target-specific uses of __attribute__.  */
+static const struct attribute_spec nds32_attribute_table[] =
+{
+  /* Syntax: { name, min_len, max_len, decl_required, type_required,
+               function_type_required, handler, affects_type_identity } */
+
+  /* The interrupt vid: [0-63]+ (actual vector number starts from 9 to 72).  */
+  { "interrupt",    1, 64, false, false, false, NULL, false },
+  /* The exception vid: [1-8]+  (actual vector number starts from 1 to 8).  */
+  { "exception",    1,  8, false, false, false, NULL, false },
+  /* Argument is user's interrupt numbers.  The vector number is always 0.  */
+  { "reset",        1,  1, false, false, false, NULL, false },
+
+  /* The attributes describing isr nested type.  */
+  { "nested",       0,  0, false, false, false, NULL, false },
+  { "not_nested",   0,  0, false, false, false, NULL, false },
+  { "nested_ready", 0,  0, false, false, false, NULL, false },
+
+  /* The attributes describing isr register save scheme.  */
+  { "save_all",     0,  0, false, false, false, NULL, false },
+  { "partial_save", 0,  0, false, false, false, NULL, false },
+
+  /* The attributes used by reset attribute.  */
+  { "nmi",          1,  1, false, false, false, NULL, false },
+  { "warm",         1,  1, false, false, false, NULL, false },
+
+  /* The attribute telling no prologue/epilogue.  */
+  { "naked",        0,  0, false, false, false, NULL, false },
+
+  /* The last attribute spec is set to be NULL.  */
+  { NULL,           0,  0, false, false, false, NULL, false }
+};
+
+
+/* ------------------------------------------------------------------------ */
+
+/* PART 2: Auxiliary static function definitions.  */
+
+/* Function to save and restore machine-specific function data.  */
+static struct machine_function *
+nds32_init_machine_status (void)
+{
+  struct machine_function *machine;
+  machine = ggc_alloc_cleared_machine_function ();
+
+  /* Initially assume this function needs prologue/epilogue.  */
+  machine->naked_p = 0;
+
+  /* Initially assume this function does NOT use fp_as_gp optimization.  */
+  machine->fp_as_gp_p = 0;
+
+  return machine;
+}
+
+/* Function to compute stack frame size and
+   store into cfun->machine structure.  */
+static void
+nds32_compute_stack_frame (void)
+{
+  int r;
+  int block_size;
+
+  /* Because nds32_compute_stack_frame() will be called from different place,
+     everytime we enter this function, we have to assume this function
+     needs prologue/epilogue.  */
+  cfun->machine->naked_p = 0;
+
+  /* Get variadic arguments size to prepare pretend arguments and
+     push them into stack at prologue.
+     Currently, we do not push variadic arguments by ourself.
+     We have GCC handle all the works.
+     The caller will push all corresponding nameless arguments into stack,
+     and the callee is able to retrieve them without problems.
+     These variables are still preserved in case one day
+     we would like caller passing arguments with registers.  */
+  cfun->machine->va_args_size = 0;
+  cfun->machine->va_args_first_regno = SP_REGNUM;
+  cfun->machine->va_args_last_regno  = SP_REGNUM;
+
+  /* Get local variables, incoming variables, and temporary variables size.
+     Note that we need to make sure it is 8-byte alignment because
+     there may be no padding bytes if we are using LRA.  */
+  cfun->machine->local_size = NDS32_ROUND_UP_DOUBLE_WORD (get_frame_size ());
+
+  /* Get outgoing arguments size.  */
+  cfun->machine->out_args_size = crtl->outgoing_args_size;
+
+  /* If $fp value is required to be saved on stack, it needs 4 bytes space.
+     Check whether $fp is ever live.  */
+  cfun->machine->fp_size = (df_regs_ever_live_p (FP_REGNUM)) ? 4 : 0;
+
+  /* If $gp value is required to be saved on stack, it needs 4 bytes space.
+     Check whether we are using PIC code genration.  */
+  cfun->machine->gp_size = (flag_pic) ? 4 : 0;
+
+  /* If $lp value is required to be saved on stack, it needs 4 bytes space.
+     Check whether $lp is ever live.  */
+  cfun->machine->lp_size = (df_regs_ever_live_p (LP_REGNUM)) ? 4 : 0;
+
+  /* Initially there is no padding bytes.  */
+  cfun->machine->callee_saved_area_padding_bytes = 0;
+
+  /* Calculate the bytes of saving callee-saved registers on stack.  */
+  cfun->machine->callee_saved_regs_size = 0;
+  cfun->machine->callee_saved_regs_first_regno = SP_REGNUM;
+  cfun->machine->callee_saved_regs_last_regno  = SP_REGNUM;
+  /* Currently, there is no need to check $r28~$r31
+     because we will save them in another way.  */
+  for (r = 0; r < 28; r++)
+    {
+      if (NDS32_REQUIRED_CALLEE_SAVED_P (r))
+	{
+	  /* Mark the first required callee-saved register
+	     (only need to set it once).
+	     If first regno == SP_REGNUM, we can tell that
+	     it is the first time to be here.  */
+	  if (cfun->machine->callee_saved_regs_first_regno == SP_REGNUM)
+	    cfun->machine->callee_saved_regs_first_regno = r;
+	  /* Mark the last required callee-saved register.  */
+	  cfun->machine->callee_saved_regs_last_regno = r;
+	}
+    }
+
+  /* Check if this function can omit prologue/epilogue code fragment.
+     If there is 'naked' attribute in this function,
+     we can set 'naked_p' flag to indicate that
+     we do not have to generate prologue/epilogue.
+     Or, if all the following conditions succeed,
+     we can set this function 'naked_p' as well:
+       condition 1: first_regno == last_regno == SP_REGNUM,
+                    which means we do not have to save
+                    any callee-saved registers.
+       condition 2: Both $lp and $fp are NOT live in this function,
+                    which means we do not need to save them.
+       condition 3: There is no local_size, which means
+                    we do not need to adjust $sp.  */
+  if (lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl))
+      || (cfun->machine->callee_saved_regs_first_regno == SP_REGNUM
+	  && cfun->machine->callee_saved_regs_last_regno == SP_REGNUM
+	  && !df_regs_ever_live_p (FP_REGNUM)
+	  && !df_regs_ever_live_p (LP_REGNUM)
+	  && cfun->machine->local_size == 0))
+    {
+      /* Set this function 'naked_p' and
+         other functions can check this flag.  */
+      cfun->machine->naked_p = 1;
+
+      /* No need to save $fp, $gp, and $lp.
+         We should set these value to be zero
+         so that nds32_initial_elimination_offset() can work properly.  */
+      cfun->machine->fp_size = 0;
+      cfun->machine->gp_size = 0;
+      cfun->machine->lp_size = 0;
+
+      /* If stack usage computation is required,
+         we need to provide the static stack size.  */
+      if (flag_stack_usage_info)
+	current_function_static_stack_size = 0;
+
+      /* No need to do following adjustment, return immediately.  */
+      return;
+    }
+
+  /* Adjustment for v3push instructions:
+     If we are using v3push (push25/pop25) instructions,
+     we need to make sure Rb is $r6 and Re is
+     located on $r6, $r8, $r10, or $r14.
+     Some results above will be discarded and recomputed.
+     Note that it is only available under V3/V3M ISA.  */
+  if (TARGET_V3PUSH)
+    {
+      /* Recompute:
+           cfun->machine->fp_size
+           cfun->machine->gp_size
+           cfun->machine->lp_size
+           cfun->machine->callee_saved_regs_first_regno
+           cfun->machine->callee_saved_regs_last_regno */
+
+      /* For v3push instructions, $fp, $gp, and $lp are always saved.  */
+      cfun->machine->fp_size = 4;
+      cfun->machine->gp_size = 4;
+      cfun->machine->lp_size = 4;
+
+      /* Remember to set Rb = $r6.  */
+      cfun->machine->callee_saved_regs_first_regno = 6;
+
+      if (cfun->machine->callee_saved_regs_last_regno <= 6)
+	{
+	  /* Re = $r6 */
+	  cfun->machine->callee_saved_regs_last_regno = 6;
+	}
+      else if (cfun->machine->callee_saved_regs_last_regno <= 8)
+	{
+	  /* Re = $r8 */
+	  cfun->machine->callee_saved_regs_last_regno = 8;
+	}
+      else if (cfun->machine->callee_saved_regs_last_regno <= 10)
+	{
+	  /* Re = $r10 */
+	  cfun->machine->callee_saved_regs_last_regno = 10;
+	}
+      else if (cfun->machine->callee_saved_regs_last_regno <= 14)
+	{
+	  /* Re = $r14 */
+	  cfun->machine->callee_saved_regs_last_regno = 14;
+	}
+      else if (cfun->machine->callee_saved_regs_last_regno == SP_REGNUM)
+	{
+	  /* If last_regno is SP_REGNUM, which means
+	     it is never changed, so set it to Re = $r6.  */
+	  cfun->machine->callee_saved_regs_last_regno = 6;
+	}
+      else
+	{
+	  /* The program flow should not go here.  */
+	  gcc_unreachable ();
+	}
+    }
+
+  /* We have correctly set callee_saved_regs_first_regno
+     and callee_saved_regs_last_regno.
+     Initially, the callee_saved_regs_size is supposed to be 0.
+     As long as callee_saved_regs_last_regno is not SP_REGNUM,
+     we can update callee_saved_regs_size with new size.  */
+  if (cfun->machine->callee_saved_regs_last_regno != SP_REGNUM)
+    {
+      /* Compute pushed size of callee-saved registers.  */
+      cfun->machine->callee_saved_regs_size
+	= 4 * (cfun->machine->callee_saved_regs_last_regno
+	       - cfun->machine->callee_saved_regs_first_regno
+	       + 1);
+    }
+
+  /* Important: We need to make sure that
+                (va_args_size + fp_size + gp_size
+                 + lp_size + callee_saved_regs_size)
+                is 8-byte alignment.
+                If it is not, calculate the padding bytes.  */
+  block_size = cfun->machine->va_args_size
+	       + cfun->machine->fp_size
+	       + cfun->machine->gp_size
+	       + cfun->machine->lp_size
+	       + cfun->machine->callee_saved_regs_size;
+  if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size))
+    {
+      cfun->machine->callee_saved_area_padding_bytes
+	= NDS32_ROUND_UP_DOUBLE_WORD (block_size) - block_size;
+    }
+
+  /* If stack usage computation is required,
+     we need to provide the static stack size.  */
+  if (flag_stack_usage_info)
+    {
+      current_function_static_stack_size
+	= NDS32_ROUND_UP_DOUBLE_WORD (block_size)
+	  + cfun->machine->local_size
+	  + cfun->machine->out_args_size;
+    }
+}
+
+/* Function to create a parallel rtx pattern
+   which presents stack push multiple behavior.
+   The overall concept are:
+     "push registers to memory",
+     "adjust stack pointer".  */
+static rtx
+nds32_gen_stack_push_multiple (rtx Rb, rtx Re,
+			       rtx En4 ATTRIBUTE_UNUSED)
+{
+  int regno;
+  int extra_count;
+  int num_use_regs;
+  int par_index;
+  int offset;
+
+  rtx reg;
+  rtx mem;
+  rtx push_rtx;
+  rtx adjust_sp_rtx;
+  rtx parallel_insn;
+
+  /* We need to provide a customized rtx which contains
+     necessary information for data analysis,
+     so we create a parallel rtx like this:
+     (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32)))
+                     (reg:SI Rb))
+                (set (mem (plus (reg:SI SP_REGNUM) (const_int -28)))
+                     (reg:SI Rb+1))
+                ...
+                (set (mem (plus (reg:SI SP_REGNUM) (const_int -16)))
+                     (reg:SI Re))
+                (set (mem (plus (reg:SI SP_REGNUM) (const_int -12)))
+                     (reg:SI FP_REGNUM))
+                (set (mem (plus (reg:SI SP_REGNUM) (const_int -8)))
+                     (reg:SI GP_REGNUM))
+                (set (mem (plus (reg:SI SP_REGNUM) (const_int -4)))
+                     (reg:SI LP_REGNUM))
+                (set (reg:SI SP_REGNUM)
+                     (plus (reg:SI SP_REGNUM) (const_int -32)))]) */
+
+  /* Calculate the number of registers that will be pushed.  */
+  extra_count = 0;
+  if (cfun->machine->fp_size)
+    extra_count++;
+  if (cfun->machine->gp_size)
+    extra_count++;
+  if (cfun->machine->lp_size)
+    extra_count++;
+  /* Note that Rb and Re may be SP_REGNUM.  DO NOT count it in.  */
+  if (REGNO (Rb) == SP_REGNUM && REGNO (Re) == SP_REGNUM)
+    num_use_regs = extra_count;
+  else
+    num_use_regs = REGNO (Re) - REGNO (Rb) + 1 + extra_count;
+
+  /* In addition to used registers,
+     we need one more space for (set sp sp-x) rtx.  */
+  parallel_insn = gen_rtx_PARALLEL (VOIDmode,
+				    rtvec_alloc (num_use_regs + 1));
+  par_index = 0;
+
+  /* Initialize offset and start to create push behavior.  */
+  offset = -(num_use_regs * 4);
+
+  /* Create (set mem regX) from Rb, Rb+1 up to Re.  */
+  for (regno = REGNO (Rb); regno <= (int) REGNO (Re); regno++)
+    {
+      /* Rb and Re may be SP_REGNUM.
+         We need to break this loop immediately.  */
+      if (regno == SP_REGNUM)
+        break;
+
+      reg = gen_rtx_REG (SImode, regno);
+      mem = gen_frame_mem (SImode, plus_constant (Pmode,
+						  stack_pointer_rtx,
+						  offset));
+      push_rtx = gen_rtx_SET (VOIDmode, mem, reg);
+      XVECEXP (parallel_insn, 0, par_index) = push_rtx;
+      RTX_FRAME_RELATED_P (push_rtx) = 1;
+      offset = offset + 4;
+      par_index++;
+    }
+
+  /* Create (set mem fp), (set mem gp), and (set mem lp) if necessary.  */
+  if (cfun->machine->fp_size)
+    {
+      reg = gen_rtx_REG (SImode, FP_REGNUM);
+      mem = gen_frame_mem (SImode, plus_constant (Pmode,
+						  stack_pointer_rtx,
+						  offset));
+      push_rtx = gen_rtx_SET (VOIDmode, mem, reg);
+      XVECEXP (parallel_insn, 0, par_index) = push_rtx;
+      RTX_FRAME_RELATED_P (push_rtx) = 1;
+      offset = offset + 4;
+      par_index++;
+    }
+  if (cfun->machine->gp_size)
+    {
+      reg = gen_rtx_REG (SImode, GP_REGNUM);
+      mem = gen_frame_mem (SImode, plus_constant (Pmode,
+						  stack_pointer_rtx,
+						  offset));
+      push_rtx = gen_rtx_SET (VOIDmode, mem, reg);
+      XVECEXP (parallel_insn, 0, par_index) = push_rtx;
+      RTX_FRAME_RELATED_P (push_rtx) = 1;
+      offset = offset + 4;
+      par_index++;
+    }
+  if (cfun->machine->lp_size)
+    {
+      reg = gen_rtx_REG (SImode, LP_REGNUM);
+      mem = gen_frame_mem (SImode, plus_constant (Pmode,
+						  stack_pointer_rtx,
+						  offset));
+      push_rtx = gen_rtx_SET (VOIDmode, mem, reg);
+      XVECEXP (parallel_insn, 0, par_index) = push_rtx;
+      RTX_FRAME_RELATED_P (push_rtx) = 1;
+      offset = offset + 4;
+      par_index++;
+    }
+
+  /* Create (set sp sp-x).  */
+
+  /* We need to re-calculate the offset value again for adjustment.  */
+  offset = -(num_use_regs * 4);
+  adjust_sp_rtx
+    = gen_rtx_SET (VOIDmode,
+		   stack_pointer_rtx,
+		   plus_constant (Pmode, stack_pointer_rtx, offset));
+  XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx;
+  RTX_FRAME_RELATED_P (adjust_sp_rtx) = 1;
+
+  return parallel_insn;
+}
+
+/* Function to create a parallel rtx pattern
+   which presents stack pop multiple behavior.
+   The overall concept are:
+     "pop registers from memory",
+     "adjust stack pointer".  */
+static rtx
+nds32_gen_stack_pop_multiple (rtx Rb, rtx Re,
+			      rtx En4 ATTRIBUTE_UNUSED)
+{
+  int regno;
+  int extra_count;
+  int num_use_regs;
+  int par_index;
+  int offset;
+
+  rtx reg;
+  rtx mem;
+  rtx pop_rtx;
+  rtx adjust_sp_rtx;
+  rtx parallel_insn;
+
+  /* We need to provide a customized rtx which contains
+     necessary information for data analysis,
+     so we create a parallel rtx like this:
+     (parallel [(set (reg:SI Rb)
+                     (mem (reg:SI SP_REGNUM)))
+                (set (reg:SI Rb+1)
+                     (mem (plus (reg:SI SP_REGNUM) (const_int 4))))
+                ...
+                (set (reg:SI Re)
+                     (mem (plus (reg:SI SP_REGNUM) (const_int 16))))
+                (set (reg:SI FP_REGNUM)
+                     (mem (plus (reg:SI SP_REGNUM) (const_int 20))))
+                (set (reg:SI GP_REGNUM)
+                     (mem (plus (reg:SI SP_REGNUM) (const_int 24))))
+                (set (reg:SI LP_REGNUM)
+                     (mem (plus (reg:SI SP_REGNUM) (const_int 28))))
+                (set (reg:SI SP_REGNUM)
+                     (plus (reg:SI SP_REGNUM) (const_int 32)))]) */
+
+  /* Calculate the number of registers that will be poped.  */
+  extra_count = 0;
+  if (cfun->machine->fp_size)
+    extra_count++;
+  if (cfun->machine->gp_size)
+    extra_count++;
+  if (cfun->machine->lp_size)
+    extra_count++;
+  /* Note that Rb and Re may be SP_REGNUM.  DO NOT count it in.  */
+  if (REGNO (Rb) == SP_REGNUM && REGNO (Re) == SP_REGNUM)
+    num_use_regs = extra_count;
+  else
+    num_use_regs = REGNO (Re) - REGNO (Rb) + 1 + extra_count;
+
+  /* In addition to used registers,
+     we need one more space for (set sp sp+x) rtx.  */
+  parallel_insn = gen_rtx_PARALLEL (VOIDmode,
+				    rtvec_alloc (num_use_regs + 1));
+  par_index = 0;
+
+  /* Initialize offset and start to create pop behavior.  */
+  offset = 0;
+
+  /* Create (set regX mem) from Rb, Rb+1 up to Re.  */
+  for (regno = REGNO (Rb); regno <= (int) REGNO (Re); regno++)
+    {
+      /* Rb and Re may be SP_REGNUM.
+         We need to break this loop immediately.  */
+      if (regno == SP_REGNUM)
+        break;
+
+      reg = gen_rtx_REG (SImode, regno);
+      mem = gen_frame_mem (SImode, plus_constant (Pmode,
+						  stack_pointer_rtx,
+						  offset));
+      pop_rtx = gen_rtx_SET (VOIDmode, reg, mem);
+      XVECEXP (parallel_insn, 0, par_index) = pop_rtx;
+      RTX_FRAME_RELATED_P (pop_rtx) = 1;
+      offset = offset + 4;
+      par_index++;
+    }
+
+  /* Create (set fp mem), (set gp mem), and (set lp mem) if necessary.  */
+  if (cfun->machine->fp_size)
+    {
+      reg = gen_rtx_REG (SImode, FP_REGNUM);
+      mem = gen_frame_mem (SImode, plus_constant (Pmode,
+						  stack_pointer_rtx,
+						  offset));
+      pop_rtx = gen_rtx_SET (VOIDmode, reg, mem);
+      XVECEXP (parallel_insn, 0, par_index) = pop_rtx;
+      RTX_FRAME_RELATED_P (pop_rtx) = 1;
+      offset = offset + 4;
+      par_index++;
+    }
+  if (cfun->machine->gp_size)
+    {
+      reg = gen_rtx_REG (SImode, GP_REGNUM);
+      mem = gen_frame_mem (SImode, plus_constant (Pmode,
+						  stack_pointer_rtx,
+						  offset));
+      pop_rtx = gen_rtx_SET (VOIDmode, reg, mem);
+      XVECEXP (parallel_insn, 0, par_index) = pop_rtx;
+      RTX_FRAME_RELATED_P (pop_rtx) = 1;
+      offset = offset + 4;
+      par_index++;
+    }
+  if (cfun->machine->lp_size)
+    {
+      reg = gen_rtx_REG (SImode, LP_REGNUM);
+      mem = gen_frame_mem (SImode, plus_constant (Pmode,
+						  stack_pointer_rtx,
+						  offset));
+      pop_rtx = gen_rtx_SET (VOIDmode, reg, mem);
+      XVECEXP (parallel_insn, 0, par_index) = pop_rtx;
+      RTX_FRAME_RELATED_P (pop_rtx) = 1;
+      offset = offset + 4;
+      par_index++;
+    }
+
+  /* Create (set sp sp+x).  */
+
+  /* The offset value is already in place.  No need to re-calculate it.  */
+  adjust_sp_rtx
+    = gen_rtx_SET (VOIDmode,
+		   stack_pointer_rtx,
+		   plus_constant (Pmode, stack_pointer_rtx, offset));
+  XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx;
+  RTX_FRAME_RELATED_P (adjust_sp_rtx) = 1;
+
+  return parallel_insn;
+}
+
+/* Function to create a parallel rtx pattern
+   which presents stack v3push behavior.
+   The overall concept are:
+     "push registers to memory",
+     "adjust stack pointer".  */
+static rtx
+nds32_gen_stack_v3push (rtx Rb,
+			rtx Re,
+			rtx En4 ATTRIBUTE_UNUSED,
+			rtx imm8u)
+{
+  int regno;
+  int num_use_regs;
+  int par_index;
+  int offset;
+
+  rtx reg;
+  rtx mem;
+  rtx push_rtx;
+  rtx adjust_sp_rtx;
+  rtx parallel_insn;
+
+  /* We need to provide a customized rtx which contains
+     necessary information for data analysis,
+     so we create a parallel rtx like this:
+     (parallel [
+                (set (mem (plus (reg:SI SP_REGNUM) (const_int -32)))
+                     (reg:SI Rb))
+                (set (mem (plus (reg:SI SP_REGNUM) (const_int -28)))
+                     (reg:SI Rb+1))
+                ...
+                (set (mem (plus (reg:SI SP_REGNUM) (const_int -16)))
+                     (reg:SI Re))
+                (set (mem (plus (reg:SI SP_REGNUM) (const_int -12)))
+                     (reg:SI FP_REGNUM))
+                (set (mem (plus (reg:SI SP_REGNUM) (const_int -8)))
+                     (reg:SI GP_REGNUM))
+                (set (mem (plus (reg:SI SP_REGNUM) (const_int -4)))
+                     (reg:SI LP_REGNUM))
+                (set (reg:SI SP_REGNUM)
+                     (plus (reg:SI SP_REGNUM) (const_int -32-imm8u)))]) */
+
+  /* Calculate the number of registers that will be pushed.
+     Since $fp, $gp, and $lp is always pushed with v3push instruction,
+     we need to count these three registers.
+     Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
+     So there is no need to worry about Rb=Re=SP_REGNUM case.  */
+  num_use_regs = REGNO (Re) - REGNO (Rb) + 1 + 3;
+
+  /* In addition to used registers,
+     we need one more space for (set sp sp-x-imm8u) rtx.  */
+  parallel_insn = gen_rtx_PARALLEL (VOIDmode,
+				    rtvec_alloc (num_use_regs + 1));
+  par_index = 0;
+
+  /* Initialize offset and start to create push behavior.  */
+  offset = -(num_use_regs * 4);
+
+  /* Create (set mem regX) from Rb, Rb+1 up to Re.
+     Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
+     So there is no need to worry about Rb=Re=SP_REGNUM case.  */
+  for (regno = REGNO (Rb); regno <= (int) REGNO (Re); regno++)
+    {
+      reg = gen_rtx_REG (SImode, regno);
+      mem = gen_frame_mem (SImode, plus_constant (Pmode,
+						  stack_pointer_rtx,
+						  offset));
+      push_rtx = gen_rtx_SET (VOIDmode, mem, reg);
+      XVECEXP (parallel_insn, 0, par_index) = push_rtx;
+      RTX_FRAME_RELATED_P (push_rtx) = 1;
+      offset = offset + 4;
+      par_index++;
+    }
+
+  /* Create (set mem fp).  */
+  reg = gen_rtx_REG (SImode, FP_REGNUM);
+  mem = gen_frame_mem (SImode, plus_constant (Pmode,
+					      stack_pointer_rtx,
+					      offset));
+  push_rtx = gen_rtx_SET (VOIDmode, mem, reg);
+  XVECEXP (parallel_insn, 0, par_index) = push_rtx;
+  RTX_FRAME_RELATED_P (push_rtx) = 1;
+  offset = offset + 4;
+  par_index++;
+  /* Create (set mem gp).  */
+  reg = gen_rtx_REG (SImode, GP_REGNUM);
+  mem = gen_frame_mem (SImode, plus_constant (Pmode,
+					      stack_pointer_rtx,
+					      offset));
+  push_rtx = gen_rtx_SET (VOIDmode, mem, reg);
+  XVECEXP (parallel_insn, 0, par_index) = push_rtx;
+  RTX_FRAME_RELATED_P (push_rtx) = 1;
+  offset = offset + 4;
+  par_index++;
+  /* Create (set mem lp).  */
+  reg = gen_rtx_REG (SImode, LP_REGNUM);
+  mem = gen_frame_mem (SImode, plus_constant (Pmode,
+					      stack_pointer_rtx,
+					      offset));
+  push_rtx = gen_rtx_SET (VOIDmode, mem, reg);
+  XVECEXP (parallel_insn, 0, par_index) = push_rtx;
+  RTX_FRAME_RELATED_P (push_rtx) = 1;
+  offset = offset + 4;
+  par_index++;
+
+  /* Create (set sp sp-x-imm8u).  */
+
+  /* We need to re-calculate the offset value again for adjustment.  */
+  offset = -(num_use_regs * 4);
+  adjust_sp_rtx
+    = gen_rtx_SET (VOIDmode,
+		   stack_pointer_rtx,
+		   plus_constant (Pmode,
+				  stack_pointer_rtx,
+				  offset - INTVAL (imm8u)));
+  XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx;
+  RTX_FRAME_RELATED_P (adjust_sp_rtx) = 1;
+
+  return parallel_insn;
+}
+
+/* Function to create a parallel rtx pattern
+   which presents stack v3pop behavior.
+   The overall concept are:
+     "pop registers from memory",
+     "adjust stack pointer".  */
+static rtx
+nds32_gen_stack_v3pop (rtx Rb,
+		       rtx Re,
+		       rtx En4 ATTRIBUTE_UNUSED,
+		       rtx imm8u)
+{
+  int regno;
+  int num_use_regs;
+  int par_index;
+  int offset;
+
+  rtx reg;
+  rtx mem;
+  rtx pop_rtx;
+  rtx adjust_sp_rtx;
+  rtx parallel_insn;
+
+  /* We need to provide a customized rtx which contains
+     necessary information for data analysis,
+     so we create a parallel rtx like this:
+     (parallel [(set (reg:SI Rb)
+                     (mem (reg:SI SP_REGNUM)))
+                (set (reg:SI Rb+1)
+                     (mem (plus (reg:SI SP_REGNUM) (const_int 4))))
+                ...
+                (set (reg:SI Re)
+                     (mem (plus (reg:SI SP_REGNUM) (const_int 16))))
+                (set (reg:SI FP_REGNUM)
+                     (mem (plus (reg:SI SP_REGNUM) (const_int 20))))
+                (set (reg:SI GP_REGNUM)
+                     (mem (plus (reg:SI SP_REGNUM) (const_int 24))))
+                (set (reg:SI LP_REGNUM)
+                     (mem (plus (reg:SI SP_REGNUM) (const_int 28))))
+                (set (reg:SI SP_REGNUM)
+                     (plus (reg:SI SP_REGNUM) (const_int 32+imm8u)))]) */
+
+  /* Calculate the number of registers that will be poped.
+     Since $fp, $gp, and $lp is always poped with v3pop instruction,
+     we need to count these three registers.
+     Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
+     So there is no need to worry about Rb=Re=SP_REGNUM case.  */
+  num_use_regs = REGNO (Re) - REGNO (Rb) + 1 + 3;
+
+  /* In addition to used registers,
+     we need one more space for (set sp sp+x+imm8u) rtx.  */
+  parallel_insn = gen_rtx_PARALLEL (VOIDmode,
+				    rtvec_alloc (num_use_regs + 1));
+  par_index = 0;
+
+  /* Initialize offset and start to create pop behavior.  */
+  offset = 0;
+
+  /* Create (set regX mem) from Rb, Rb+1 up to Re.
+     Under v3pop, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
+     So there is no need to worry about Rb=Re=SP_REGNUM case.  */
+  for (regno = REGNO (Rb); regno <= (int) REGNO (Re); regno++)
+    {
+      reg = gen_rtx_REG (SImode, regno);
+      mem = gen_frame_mem (SImode, plus_constant (Pmode,
+						  stack_pointer_rtx,
+						  offset));
+      pop_rtx = gen_rtx_SET (VOIDmode, reg, mem);
+      XVECEXP (parallel_insn, 0, par_index) = pop_rtx;
+      RTX_FRAME_RELATED_P (pop_rtx) = 1;
+      offset = offset + 4;
+      par_index++;
+    }
+
+  /* Create (set fp mem).  */
+  reg = gen_rtx_REG (SImode, FP_REGNUM);
+  mem = gen_frame_mem (SImode, plus_constant (Pmode,
+					      stack_pointer_rtx,
+					      offset));
+  pop_rtx = gen_rtx_SET (VOIDmode, reg, mem);
+  XVECEXP (parallel_insn, 0, par_index) = pop_rtx;
+  RTX_FRAME_RELATED_P (pop_rtx) = 1;
+  offset = offset + 4;
+  par_index++;
+  /* Create (set gp mem).  */
+  reg = gen_rtx_REG (SImode, GP_REGNUM);
+  mem = gen_frame_mem (SImode, plus_constant (Pmode,
+					      stack_pointer_rtx,
+					      offset));
+  pop_rtx = gen_rtx_SET (VOIDmode, reg, mem);
+  XVECEXP (parallel_insn, 0, par_index) = pop_rtx;
+  RTX_FRAME_RELATED_P (pop_rtx) = 1;
+  offset = offset + 4;
+  par_index++;
+  /* Create (set lp mem ).  */
+  reg = gen_rtx_REG (SImode, LP_REGNUM);
+  mem = gen_frame_mem (SImode, plus_constant (Pmode,
+					      stack_pointer_rtx,
+					      offset));
+  pop_rtx = gen_rtx_SET (VOIDmode, reg, mem);
+  XVECEXP (parallel_insn, 0, par_index) = pop_rtx;
+  RTX_FRAME_RELATED_P (pop_rtx) = 1;
+  offset = offset + 4;
+  par_index++;
+
+  /* Create (set sp sp+x+imm8u).  */
+
+  /* The offset value is already in place.  No need to re-calculate it.  */
+  adjust_sp_rtx
+    = gen_rtx_SET (VOIDmode,
+		   stack_pointer_rtx,
+		   plus_constant (Pmode,
+				  stack_pointer_rtx,
+				  offset + INTVAL (imm8u)));
+  XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx;
+  RTX_FRAME_RELATED_P (adjust_sp_rtx) = 1;
+
+  return parallel_insn;
+}
+
+/* A subroutine that checks multiple load and store
+   using consecutive registers.
+     OP is a parallel rtx we would like to check.
+     LOAD_P indicates whether we are checking load operation.
+     PAR_INDEX is starting element of parallel rtx.
+     FIRST_ELT_REGNO is used to tell starting register number.
+     COUNT helps us to check consecutive register numbers.  */
+static bool
+nds32_consecutive_registers_load_store_p (rtx op,
+					  bool load_p,
+					  int par_index,
+					  int first_elt_regno,
+					  int count)
+{
+  int i;
+  int check_regno;
+  rtx elt;
+  rtx elt_reg;
+  rtx elt_mem;
+
+  for (i = 0; i < count; i++)
+    {
+      /* Pick up each element from parallel rtx.  */
+      elt = XVECEXP (op, 0, i + par_index);
+
+      /* If this element is not a 'set' rtx, return false immediately.  */
+      if (GET_CODE (elt) != SET)
+	return false;
+
+      /* Pick up reg and mem of this element.  */
+      elt_reg = load_p ? SET_DEST (elt) : SET_SRC (elt);
+      elt_mem = load_p ? SET_SRC (elt) : SET_DEST (elt);
+
+      /* If elt_reg is not a expected reg rtx, return false.  */
+      if (GET_CODE (elt_reg) != REG || GET_MODE (elt_reg) != SImode)
+	return false;
+      /* If elt_mem is not a expected mem rtx, return false.  */
+      if (GET_CODE (elt_mem) != MEM || GET_MODE (elt_mem) != SImode)
+	return false;
+
+      /* The consecutive registers should be in (Rb,Rb+1...Re) order.  */
+      check_regno = first_elt_regno + i;
+
+      /* If the register number is not continuous, return false.  */
+      if (REGNO (elt_reg) != (unsigned int) check_regno)
+	return false;
+    }
+
+  return true;
+}
+
+/* A helper function to emit section head template.  */
+static void
+nds32_emit_section_head_template (char section_name[],
+				  char symbol_name[],
+				  int align_value,
+				  bool object_p)
+{
+  const char *flags_str;
+  const char *type_str;
+
+  flags_str = (object_p) ? "\"a\"" : "\"ax\"";
+  type_str = (object_p) ? "@object" : "@function";
+
+  fprintf (asm_out_file, "\t.section\t%s, %s\n", section_name, flags_str);
+  fprintf (asm_out_file, "\t.align\t%d\n", align_value);
+  fprintf (asm_out_file, "\t.global\t%s\n", symbol_name);
+  fprintf (asm_out_file, "\t.type\t%s, %s\n", symbol_name, type_str);
+  fprintf (asm_out_file, "%s:\n", symbol_name);
+}
+
+/* A helper function to emit section tail template.  */
+static void
+nds32_emit_section_tail_template (char symbol_name[])
+{
+  fprintf (asm_out_file, "\t.size\t%s, .-%s\n", symbol_name, symbol_name);
+}
+
+/* Function to emit isr jump table section.  */
+static void
+nds32_emit_isr_jmptbl_section (int vector_id)
+{
+  char section_name[100];
+  char symbol_name[100];
+
+  /* Prepare jmptbl section and symbol name.  */
+  snprintf (section_name, sizeof (section_name),
+	    ".nds32_jmptbl.%02d", vector_id);
+  snprintf (symbol_name, sizeof (symbol_name),
+	    "_nds32_jmptbl_%02d", vector_id);
+
+  nds32_emit_section_head_template (section_name, symbol_name, 2, true);
+  fprintf (asm_out_file, "\t.word\t%s\n",
+			 nds32_isr_vectors[vector_id].func_name);
+  nds32_emit_section_tail_template (symbol_name);
+}
+
+/* Function to emit isr vector section.  */
+static void
+nds32_emit_isr_vector_section (int vector_id)
+{
+  unsigned int vector_number_offset = 0;
+  const char *c_str = "CATEGORY";
+  const char *sr_str = "SR";
+  const char *nt_str = "NT";
+  const char *vs_str = "VS";
+  char first_level_handler_name[100];
+  char section_name[100];
+  char symbol_name[100];
+
+  /* Set the vector number offset so that we can calculate
+     the value that user specifies in the attribute.
+     We also prepare the category string for first level handler name.  */
+  switch (nds32_isr_vectors[vector_id].category)
+    {
+    case NDS32_ISR_INTERRUPT:
+      vector_number_offset = 9;
+      c_str = "i";
+      break;
+    case NDS32_ISR_EXCEPTION:
+      vector_number_offset = 0;
+      c_str = "e";
+      break;
+    case NDS32_ISR_NONE:
+    case NDS32_ISR_RESET:
+      /* Normally it should not be here.  */
+      gcc_unreachable ();
+      break;
+    }
+
+  /* Prepare save reg string for first level handler name.  */
+  switch (nds32_isr_vectors[vector_id].save_reg)
+    {
+    case NDS32_SAVE_ALL:
+      sr_str = "sa";
+      break;
+    case NDS32_PARTIAL_SAVE:
+      sr_str = "ps";
+      break;
+    }
+
+  /* Prepare nested type string for first level handler name.  */
+  switch (nds32_isr_vectors[vector_id].nested_type)
+    {
+    case NDS32_NESTED:
+      nt_str = "ns";
+      break;
+    case NDS32_NOT_NESTED:
+      nt_str = "nn";
+      break;
+    case NDS32_NESTED_READY:
+      nt_str = "nr";
+      break;
+    }
+
+  /* Currently we have 4-byte or 16-byte size for each vector.
+     If it is 4-byte, the first level handler name has suffix string "_4b".  */
+  vs_str = (nds32_isr_vector_size == 4) ? "_4b" : "";
+
+  /* Now we can create first level handler name.  */
+  snprintf (first_level_handler_name, sizeof (first_level_handler_name),
+	    "_nds32_%s_%s_%s%s", c_str, sr_str, nt_str, vs_str);
+
+  /* Prepare vector section and symbol name.  */
+  snprintf (section_name, sizeof (section_name),
+	    ".nds32_vector.%02d", vector_id);
+  snprintf (symbol_name, sizeof (symbol_name),
+	    "_nds32_vector_%02d%s", vector_id, vs_str);
+
+
+  /* Everything is ready.  We can start emit vector section content.  */
+  nds32_emit_section_head_template (section_name, symbol_name,
+				    floor_log2 (nds32_isr_vector_size), false);
+
+  /* According to the vector size, the instructions in the
+     vector section may be different.  */
+  if (nds32_isr_vector_size == 4)
+    {
+      /* This block is for 4-byte vector size.
+         Hardware $VID support is necessary and only one instruction
+         is needed in vector section.  */
+      fprintf (asm_out_file, "\tj\t%s ! jump to first level handler\n",
+			     first_level_handler_name);
+    }
+  else
+    {
+      /* This block is for 16-byte vector size.
+         There is NO hardware $VID so that we need several instructions
+         such as pushing GPRs and preparing software vid at vector section.
+         For pushing GPRs, there are four variations for
+         16-byte vector content and we have to handle each combination.
+         For preparing software vid, note that the vid need to
+         be substracted vector_number_offset.  */
+      if (TARGET_REDUCED_REGS)
+	{
+	  if (nds32_isr_vectors[vector_id].save_reg == NDS32_SAVE_ALL)
+	    {
+	      /* Case of reduced set registers and save_all attribute.  */
+	      fprintf (asm_out_file, "\t! reduced set regs + save_all\n");
+	      fprintf (asm_out_file, "\tsmw.adm\t$r15, [$sp], $r15, 0xf\n");
+	      fprintf (asm_out_file, "\tsmw.adm\t$r0, [$sp], $r10, 0x0\n");
+
+	    }
+	  else
+	    {
+	      /* Case of reduced set registers and partial_save attribute.  */
+	      fprintf (asm_out_file, "\t! reduced set regs + partial_save\n");
+	      fprintf (asm_out_file, "\tsmw.adm\t$r15, [$sp], $r15, 0x2\n");
+	      fprintf (asm_out_file, "\tsmw.adm\t$r0, [$sp], $r5, 0x0\n");
+	    }
+	}
+      else
+	{
+	  if (nds32_isr_vectors[vector_id].save_reg == NDS32_SAVE_ALL)
+	    {
+	      /* Case of full set registers and save_all attribute.  */
+	      fprintf (asm_out_file, "\t! full set regs + save_all\n");
+	      fprintf (asm_out_file, "\tsmw.adm\t$r0, [$sp], $r27, 0xf\n");
+	    }
+	  else
+	    {
+	      /* Case of full set registers and partial_save attribute.  */
+	      fprintf (asm_out_file, "\t! full set regs + partial_save\n");
+	      fprintf (asm_out_file, "\tsmw.adm\t$r15, [$sp], $r27, 0x2\n");
+	      fprintf (asm_out_file, "\tsmw.adm\t$r0, [$sp], $r5, 0x0\n");
+	    }
+	}
+
+      fprintf (asm_out_file, "\tmovi\t$r0, %d ! preparing software vid\n",
+			     vector_id - vector_number_offset);
+      fprintf (asm_out_file, "\tj\t%s ! jump to first level handler\n",
+			     first_level_handler_name);
+    }
+
+  nds32_emit_section_tail_template (symbol_name);
+}
+
+/* Function to emit isr reset handler content.
+   Including all jmptbl/vector references, jmptbl section,
+   vector section, nmi handler section, and warm handler section.  */
+static void
+nds32_emit_isr_reset_content (void)
+{
+  unsigned int i;
+  unsigned int total_n_vectors;
+  const char *vs_str;
+  char reset_handler_name[100];
+  char section_name[100];
+  char symbol_name[100];
+
+  total_n_vectors = nds32_isr_vectors[0].total_n_vectors;
+  vs_str = (nds32_isr_vector_size == 4) ? "_4b" : "";
+
+  fprintf (asm_out_file, "\t! RESET HANDLER CONTENT - BEGIN !\n");
+
+  /* Create references in .rodata according to total number of vectors.  */
+  fprintf (asm_out_file, "\t.section\t.rodata\n");
+  fprintf (asm_out_file, "\t.align\t2\n");
+
+  /* Emit jmptbl references.  */
+  fprintf (asm_out_file, "\t ! references to jmptbl section entries\n");
+  for (i = 0; i < total_n_vectors; i++)
+    fprintf (asm_out_file, "\t.word\t_nds32_jmptbl_%02d\n", i);
+
+  /* Emit vector references.  */
+  fprintf (asm_out_file, "\t ! references to vector section entries\n");
+  for (i = 0; i < total_n_vectors; i++)
+    fprintf (asm_out_file, "\t.word\t_nds32_vector_%02d%s\n", i, vs_str);
+
+  /* Emit jmptbl_00 section.  */
+  snprintf (section_name, sizeof (section_name), ".nds32_jmptbl.00");
+  snprintf (symbol_name, sizeof (symbol_name), "_nds32_jmptbl_00");
+
+  fprintf (asm_out_file, "\t! ....................................\n");
+  nds32_emit_section_head_template (section_name, symbol_name, 2, true);
+  fprintf (asm_out_file, "\t.word\t%s\n",
+			 nds32_isr_vectors[0].func_name);
+  nds32_emit_section_tail_template (symbol_name);
+
+  /* Emit vector_00 section.  */
+  snprintf (section_name, sizeof (section_name), ".nds32_vector.00");
+  snprintf (symbol_name, sizeof (symbol_name), "_nds32_vector_00%s", vs_str);
+  snprintf (reset_handler_name, sizeof (reset_handler_name),
+	    "_nds32_reset%s", vs_str);
+
+  fprintf (asm_out_file, "\t! ....................................\n");
+  nds32_emit_section_head_template (section_name, symbol_name,
+				    floor_log2 (nds32_isr_vector_size), false);
+  fprintf (asm_out_file, "\tj\t%s ! jump to reset handler\n",
+			 reset_handler_name);
+  nds32_emit_section_tail_template (symbol_name);
+
+  /* Emit nmi handler section.  */
+  snprintf (section_name, sizeof (section_name), ".nds32_nmih");
+  snprintf (symbol_name, sizeof (symbol_name), "_nds32_nmih");
+
+  fprintf (asm_out_file, "\t! ....................................\n");
+  nds32_emit_section_head_template (section_name, symbol_name, 2, true);
+  fprintf (asm_out_file, "\t.word\t%s\n",
+			 (strlen (nds32_isr_vectors[0].nmi_name) == 0)
+			 ? "0"
+			 : nds32_isr_vectors[0].nmi_name);
+  nds32_emit_section_tail_template (symbol_name);
+
+  /* Emit warm handler section.  */
+  snprintf (section_name, sizeof (section_name), ".nds32_wrh");
+  snprintf (symbol_name, sizeof (symbol_name), "_nds32_wrh");
+
+  fprintf (asm_out_file, "\t! ....................................\n");
+  nds32_emit_section_head_template (section_name, symbol_name, 2, true);
+  fprintf (asm_out_file, "\t.word\t%s\n",
+			 (strlen (nds32_isr_vectors[0].warm_name) == 0)
+			 ? "0"
+			 : nds32_isr_vectors[0].warm_name);
+  nds32_emit_section_tail_template (symbol_name);
+
+  fprintf (asm_out_file, "\t! RESET HANDLER CONTENT - END !\n");
+}
+
+/* Function for nds32_merge_decl_attributes() and nds32_insert_attributes()
+   to check if there are any conflict isr-specific attributes being set.
+   We need to check:
+     1. Only 'save_all' or 'partial_save' in the attributes.
+     2. Only 'nested', 'not_nested', or 'nested_ready' in the attributes.
+     3. Only 'interrupt', 'exception', or 'reset' in the attributes.  */
+static void
+nds32_check_isr_attrs_conflict (tree func_decl, tree func_attrs)
+{
+  int save_all_p, partial_save_p;
+  int nested_p, not_nested_p, nested_ready_p;
+  int intr_p, excp_p, reset_p;
+
+  /* Initialize variables.  */
+  save_all_p = partial_save_p = 0;
+  nested_p = not_nested_p = nested_ready_p = 0;
+  intr_p = excp_p = reset_p = 0;
+
+  /* We must check at MOST one attribute to set save-reg.  */
+  if (lookup_attribute ("save_all", func_attrs))
+    save_all_p = 1;
+  if (lookup_attribute ("partial_save", func_attrs))
+    partial_save_p = 1;
+
+  if ((save_all_p + partial_save_p) > 1)
+    error ("multiple save reg attributes to function %qD", func_decl);
+
+  /* We must check at MOST one attribute to set nested-type.  */
+  if (lookup_attribute ("nested", func_attrs))
+    nested_p = 1;
+  if (lookup_attribute ("not_nested", func_attrs))
+    not_nested_p = 1;
+  if (lookup_attribute ("nested_ready", func_attrs))
+    nested_ready_p = 1;
+
+  if ((nested_p + not_nested_p + nested_ready_p) > 1)
+    error ("multiple nested types attributes to function %qD", func_decl);
+
+  /* We must check at MOST one attribute to
+     set interrupt/exception/reset.  */
+  if (lookup_attribute ("interrupt", func_attrs))
+    intr_p = 1;
+  if (lookup_attribute ("exception", func_attrs))
+    excp_p = 1;
+  if (lookup_attribute ("reset", func_attrs))
+    reset_p = 1;
+
+  if ((intr_p + excp_p + reset_p) > 1)
+    error ("multiple interrupt attributes to function %qD", func_decl);
+}
+
+/* Function to construct isr vectors information array.
+   We DO NOT HAVE TO check if the attributes are valid
+   because those works are supposed to be done on
+   nds32_merge_decl_attributes() and nds32_insert_attributes().  */
+static void
+nds32_construct_isr_vectors_information (tree func_attrs,
+					 const char *func_name)
+{
+  tree save_all, partial_save;
+  tree nested, not_nested, nested_ready;
+  tree intr, excp, reset;
+
+  save_all     = lookup_attribute ("save_all", func_attrs);
+  partial_save = lookup_attribute ("partial_save", func_attrs);
+
+  nested       = lookup_attribute ("nested", func_attrs);
+  not_nested   = lookup_attribute ("not_nested", func_attrs);
+  nested_ready = lookup_attribute ("nested_ready", func_attrs);
+
+  intr  = lookup_attribute ("interrupt", func_attrs);
+  excp  = lookup_attribute ("exception", func_attrs);
+  reset = lookup_attribute ("reset", func_attrs);
+
+  /* If there is no interrupt/exception/reset, we can return immediately.  */
+  if (!intr && !excp && !reset)
+    return;
+
+  /* If we are here, either we have interrupt/exception,
+     or reset attribute.  */
+  if (intr || excp)
+    {
+      tree id_list;
+
+      /* Prepare id list so that we can traverse and set vector id.  */
+      id_list = (intr) ? (TREE_VALUE (intr)) : (TREE_VALUE (excp));
+
+      while (id_list)
+	{
+	  tree id;
+	  int vector_id;
+	  unsigned int vector_number_offset;
+
+	  /* The way to handle interrupt or exception is the same,
+	     we just need to take care of actual vector number.
+	     For interrupt(0..63), the actual vector number is (9..72).
+	     For exception(1..8), the actual vector number is (1..8).  */
+	  vector_number_offset = (intr) ? (9) : (0);
+
+	  /* Pick up each vector id value.  */
+	  id = TREE_VALUE (id_list);
+	  /* Add vector_number_offset to get actual vector number.  */
+	  vector_id = TREE_INT_CST_LOW (id) + vector_number_offset;
+
+	  /* Enable corresponding vector and set function name.  */
+	  nds32_isr_vectors[vector_id].category = (intr)
+						  ? (NDS32_ISR_INTERRUPT)
+						  : (NDS32_ISR_EXCEPTION);
+	  strcpy (nds32_isr_vectors[vector_id].func_name, func_name);
+
+	  /* Set register saving scheme.  */
+	  if (save_all)
+	    nds32_isr_vectors[vector_id].save_reg = NDS32_SAVE_ALL;
+	  else if (partial_save)
+	    nds32_isr_vectors[vector_id].save_reg = NDS32_PARTIAL_SAVE;
+
+	  /* Set nested type.  */
+	  if (nested)
+	    nds32_isr_vectors[vector_id].nested_type = NDS32_NESTED;
+	  else if (not_nested)
+	    nds32_isr_vectors[vector_id].nested_type = NDS32_NOT_NESTED;
+	  else if (nested_ready)
+	    nds32_isr_vectors[vector_id].nested_type = NDS32_NESTED_READY;
+
+	  /* Advance to next id.  */
+	  id_list = TREE_CHAIN (id_list);
+	}
+    }
+  else
+    {
+      tree id_list;
+      tree id;
+      tree nmi, warm;
+
+      /* Deal with reset attribute.  Its vector number is always 0.  */
+      nds32_isr_vectors[0].category = NDS32_ISR_RESET;
+
+      /* Prepare id_list and identify id value so that
+         we can set total number of vectors.  */
+      id_list = TREE_VALUE (reset);
+      id = TREE_VALUE (id_list);
+
+      /* The total vectors = interrupt + exception numbers + reset.
+         There are 8 exception and 1 reset in nds32 architecture.  */
+      nds32_isr_vectors[0].total_n_vectors = TREE_INT_CST_LOW (id) + 8 + 1;
+      strcpy (nds32_isr_vectors[0].func_name, func_name);
+
+      /* Retrieve nmi and warm function.  */
+      nmi  = lookup_attribute ("nmi", func_attrs);
+      warm = lookup_attribute ("warm", func_attrs);
+
+      if (nmi != NULL_TREE)
+	{
+	  tree nmi_func_list;
+	  tree nmi_func;
+
+	  nmi_func_list = TREE_VALUE (nmi);
+	  nmi_func = TREE_VALUE (nmi_func_list);
+
+	  /* Record nmi function name.  */
+	  strcpy (nds32_isr_vectors[0].nmi_name,
+		  IDENTIFIER_POINTER (nmi_func));
+	}
+
+      if (warm != NULL_TREE)
+	{
+	  tree warm_func_list;
+	  tree warm_func;
+
+	  warm_func_list = TREE_VALUE (warm);
+	  warm_func = TREE_VALUE (warm_func_list);
+
+	  /* Record warm function name.  */
+	  strcpy (nds32_isr_vectors[0].warm_name,
+		  IDENTIFIER_POINTER (warm_func));
+	}
+    }
+}
+
+/* Function that may creates more instructions
+   for large value on adjusting stack pointer.
+
+   In nds32 target, 'addi' can be used for stack pointer
+   adjustment in prologue/epilogue stage.
+   However, sometimes there are too many local variables so that
+   the adjustment value is not able to be fit in the 'addi' instruction.
+   One solution is to move value into a register
+   and then use 'add' instruction.
+   In practice, we use TA_REGNUM ($r15) to accomplish this purpose.
+   Also, we need to return zero for sp adjustment so that
+   proglogue/epilogue knows there is no need to create 'addi' instruction.  */
+static int
+nds32_force_addi_stack_int (int full_value)
+{
+  int adjust_value;
+
+  rtx tmp_reg;
+  rtx sp_adjust_insn;
+
+  if (!satisfies_constraint_Is15 (GEN_INT (full_value)))
+    {
+      /* The value is not able to fit in single addi instruction.
+         Create more instructions of moving value into a register
+         and then add stack pointer with it.  */
+
+      /* $r15 is going to be temporary register to hold the value.  */
+      tmp_reg = gen_rtx_REG (SImode, TA_REGNUM);
+
+      /* Create one more instruction to move value
+         into the temporary register.  */
+      emit_move_insn (tmp_reg, GEN_INT (full_value));
+
+      /* Create new 'add' rtx.  */
+      sp_adjust_insn = gen_addsi3 (stack_pointer_rtx,
+				   stack_pointer_rtx,
+				   tmp_reg);
+      /* Emit rtx into insn list and receive its transformed insn rtx.  */
+      sp_adjust_insn = emit_insn (sp_adjust_insn);
+
+      /* At prologue, we need to tell GCC that this is frame related insn,
+         so that we can consider this instruction to output debug information.
+         If full_value is NEGATIVE, it means this function
+         is invoked by expand_prologue.  */
+      if (full_value < 0)
+	{
+	  /* Because (tmp_reg <- full_value) may be split into two
+	     rtl patterns, we can not set its RTX_FRAME_RELATED_P.
+	     We need to construct another (sp <- sp + full_value)
+	     and then insert it into sp_adjust_insn's reg note to
+	     represent a frame related expression.
+	     GCC knows how to refer it and output debug information.  */
+
+	  rtx plus_rtx;
+	  rtx set_rtx;
+
+	  plus_rtx = plus_constant (Pmode, stack_pointer_rtx, full_value);
+	  set_rtx = gen_rtx_SET (VOIDmode, stack_pointer_rtx, plus_rtx);
+	  add_reg_note (sp_adjust_insn, REG_FRAME_RELATED_EXPR, set_rtx);
+
+	  RTX_FRAME_RELATED_P (sp_adjust_insn) = 1;
+	}
+
+      /* We have used alternative way to adjust stack pointer value.
+         Return zero so that prologue/epilogue
+         will not generate other instructions.  */
+      return 0;
+    }
+  else
+    {
+      /* The value is able to fit in addi instruction.
+         However, remember to make it to be positive value
+         because we want to return 'adjustment' result.  */
+      adjust_value = (full_value < 0) ? (-full_value) : (full_value);
+
+      return adjust_value;
+    }
+}
+
+/* Return true if MODE/TYPE need double word alignment.  */
+static bool
+nds32_needs_double_word_align (enum machine_mode mode, const_tree type)
+{
+  unsigned int align;
+
+  /* When 'type' is nonnull, there is no need to look at 'mode'.  */
+  align = (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode));
+
+  return (align > PARM_BOUNDARY);
+}
+
+/* Return true if FUNC is a naked function.  */
+static bool nds32_naked_function_p (tree func)
+{
+  tree t;
+
+  if (TREE_CODE (func) != FUNCTION_DECL)
+    abort ();
+
+  t = lookup_attribute ("naked", DECL_ATTRIBUTES (func));
+
+  return (t != NULL_TREE);
+}
+
+/* Function that check if 'X' is a valid address register.
+   The variable 'STRICT' is very important to
+   make decision for register number.
+
+   STRICT : true
+     => We are in reload pass or after reload pass.
+        The register number should be strictly limited in general registers.
+
+   STRICT : false
+     => Before reload pass, we are free to use any register number.  */
+static bool
+nds32_address_register_rtx_p (rtx x, bool strict)
+{
+  int regno;
+
+  if (GET_CODE (x) != REG)
+    return false;
+
+  regno = REGNO (x);
+
+  if (strict)
+    return REGNO_OK_FOR_BASE_P (regno);
+  else
+    return true;
+}
+
+/* Function that check if 'INDEX' is valid to be a index rtx for address.
+
+   OUTER_MODE : Machine mode of outer address rtx.
+        INDEX : Check if this rtx is valid to be a index for address.
+       STRICT : If it is true, we are in reload pass or after reload pass.  */
+static bool
+nds32_legitimate_index_p (enum machine_mode outer_mode,
+			  rtx index,
+			  bool strict)
+{
+  int regno;
+  rtx op0;
+  rtx op1;
+
+  switch (GET_CODE (index))
+    {
+    case REG:
+      regno = REGNO (index);
+      /* If we are in reload pass or after reload pass,
+         we need to limit it to general register.  */
+      if (strict)
+	return REGNO_OK_FOR_INDEX_P (regno);
+      else
+	return true;
+
+    case CONST_INT:
+      /* The alignment of the integer value is determined by 'outer_mode'.  */
+      if (GET_MODE_SIZE (outer_mode) == 1)
+	{
+	  /* Further check if the value is legal for the 'outer_mode'.  */
+	  if (!satisfies_constraint_Is15 (index))
+	    return false;
+
+	  /* Pass all test, the value is valid, return true.  */
+	  return true;
+	}
+      if (GET_MODE_SIZE (outer_mode) == 2
+	  && NDS32_HALF_WORD_ALIGN_P (INTVAL (index)))
+	{
+	  /* Further check if the value is legal for the 'outer_mode'.  */
+	  if (!satisfies_constraint_Is16 (index))
+	    return false;
+
+	  /* Pass all test, the value is valid, return true.  */
+	  return true;
+	}
+      if (GET_MODE_SIZE (outer_mode) == 4
+	  && NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index)))
+	{
+	  /* Further check if the value is legal for the 'outer_mode'.  */
+	  if (!satisfies_constraint_Is17 (index))
+	    return false;
+
+	  /* Pass all test, the value is valid, return true.  */
+	  return true;
+	}
+      if (GET_MODE_SIZE (outer_mode) == 8
+	  && NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index)))
+	{
+	  /* Further check if the value is legal for the 'outer_mode'.  */
+	  if (!satisfies_constraint_Is17 (gen_int_mode (INTVAL (index) + 4,
+							SImode)))
+	    return false;
+
+	  /* Pass all test, the value is valid, return true.  */
+	  return true;
+	}
+
+      return false;
+
+    case MULT:
+      op0 = XEXP (index, 0);
+      op1 = XEXP (index, 1);
+
+      if (REG_P (op0) && CONST_INT_P (op1))
+	{
+	  int multiplier;
+	  multiplier = INTVAL (op1);
+
+	  /* We only allow (mult reg const_int_1)
+	     or (mult reg const_int_2) or (mult reg const_int_4).  */
+	  if (multiplier != 1 && multiplier != 2 && multiplier != 4)
+	    return false;
+
+	  regno = REGNO (op0);
+	  /* Limit it in general registers if we are
+	     in reload pass or after reload pass.  */
+	  if(strict)
+	    return REGNO_OK_FOR_INDEX_P (regno);
+	  else
+	    return true;
+	}
+
+      return false;
+
+    case ASHIFT:
+      op0 = XEXP (index, 0);
+      op1 = XEXP (index, 1);
+
+      if (REG_P (op0) && CONST_INT_P (op1))
+	{
+	  int sv;
+	  /* op1 is already the sv value for use to do left shift.  */
+	  sv = INTVAL (op1);
+
+	  /* We only allow (ashift reg const_int_0)
+	     or (ashift reg const_int_1) or (ashift reg const_int_2).  */
+	  if (sv != 0 && sv != 1 && sv !=2)
+	    return false;
+
+	  regno = REGNO (op0);
+	  /* Limit it in general registers if we are
+	     in reload pass or after reload pass.  */
+	  if(strict)
+	    return REGNO_OK_FOR_INDEX_P (regno);
+	  else
+	    return true;
+	}
+
+      return false;
+
+    default:
+      return false;
+    }
+}
+
+/* Function to expand builtin function for
+   '[(unspec_volatile [(reg)])]'.  */
+static rtx
+nds32_expand_builtin_null_ftype_reg (enum insn_code icode,
+				     tree exp, rtx target)
+{
+  /* Mapping:
+       ops[0] <--> value0 <--> arg0 */
+  struct expand_operand ops[1];
+  tree arg0;
+  rtx value0;
+
+  /* Grab the incoming arguments and extract its rtx.  */
+  arg0 = CALL_EXPR_ARG (exp, 0);
+  value0 = expand_normal (arg0);
+
+  /* Create operands.  */
+  create_input_operand (&ops[0], value0, TYPE_MODE (TREE_TYPE (arg0)));
+
+  /* Emit new instruction.  */
+  if (!maybe_expand_insn (icode, 1, ops))
+    error ("invalid argument to built-in function");
+
+  return target;
+}
+
+/* Function to expand builtin function for
+   '[(set (reg) (unspec_volatile [(imm)]))]'.  */
+static rtx
+nds32_expand_builtin_reg_ftype_imm (enum insn_code icode,
+				    tree exp, rtx target)
+{
+  /* Mapping:
+       ops[0] <--> target <--> exp
+       ops[1] <--> value0 <--> arg0 */
+  struct expand_operand ops[2];
+  tree arg0;
+  rtx value0;
+
+  /* Grab the incoming arguments and extract its rtx.  */
+  arg0 = CALL_EXPR_ARG (exp, 0);
+  value0 = expand_normal (arg0);
+
+  /* Create operands.  */
+  create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp)));
+  create_input_operand (&ops[1], value0, TYPE_MODE (TREE_TYPE (arg0)));
+
+  /* Emit new instruction.  */
+  if (!maybe_expand_insn (icode, 2, ops))
+    error ("invalid argument to built-in function");
+
+  return target;
+}
+
+/* Function to expand builtin function for
+   '[(unspec_volatile [(reg) (imm)])]' pattern.  */
+static rtx
+nds32_expand_builtin_null_ftype_reg_imm (enum insn_code icode,
+					 tree exp, rtx target)
+{
+  /* Mapping:
+       ops[0] <--> value0 <--> arg0
+       ops[1] <--> value1 <--> arg1 */
+  struct expand_operand ops[2];
+  tree arg0, arg1;
+  rtx value0, value1;
+
+  /* Grab the incoming arguments and extract its rtx.  */
+  arg0 = CALL_EXPR_ARG (exp, 0);
+  arg1 = CALL_EXPR_ARG (exp, 1);
+  value0 = expand_normal (arg0);
+  value1 = expand_normal (arg1);
+
+  /* Create operands.  */
+  create_input_operand (&ops[0], value0, TYPE_MODE (TREE_TYPE (arg0)));
+  create_input_operand (&ops[1], value1, TYPE_MODE (TREE_TYPE (arg1)));
+
+  /* Emit new instruction.  */
+  if (!maybe_expand_insn (icode, 2, ops))
+    error ("invalid argument to built-in function");
+
+  return target;
+}
+
+/* A helper function to return character based on byte size.  */
+static char
+nds32_byte_to_size (int byte)
+{
+  switch (byte)
+    {
+    case 4:
+      return 'w';
+    case 2:
+      return 'h';
+    case 1:
+      return 'b';
+    default:
+      /* Normally it should not be here.  */
+      gcc_unreachable ();
+    }
+}
+
+/* A helper function to check if this function should contain prologue.  */
+static int
+nds32_have_prologue_p (void)
+{
+  int i;
+
+  for (i = 0; i < 28; i++)
+    if (NDS32_REQUIRED_CALLEE_SAVED_P (i))
+      return 1;
+
+  return (flag_pic
+	  || NDS32_REQUIRED_CALLEE_SAVED_P (FP_REGNUM)
+	  || NDS32_REQUIRED_CALLEE_SAVED_P (LP_REGNUM));
+}
+
+/* ------------------------------------------------------------------------ */
+
+/* PART 3: Implement target hook stuff definitions.  */
+
+/* Register Classes.  */
+
+static unsigned char
+nds32_class_max_nregs (reg_class_t rclass ATTRIBUTE_UNUSED,
+		       enum machine_mode mode)
+{
+  /* Return the maximum number of consecutive registers
+     needed to represent "mode" in a register of "rclass".  */
+  return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
+}
+
+static int
+nds32_register_priority (int hard_regno)
+{
+  /* Encourage to use r0-r7 for LRA when optimize for size.  */
+  if (optimize_size && hard_regno < 8)
+    return 4;
+  return 3;
+}
+
+
+/* Stack Layout and Calling Conventions.  */
+
+/* There are three kinds of pointer concepts using in GCC compiler:
+
+     frame pointer: A pointer to the first location of local variables.
+     stack pointer: A pointer to the top of a stack frame.
+     argument pointer: A pointer to the incoming arguments.
+
+   In nds32 target calling convention, we are using 8-byte alignment.
+   Besides, we would like to have each stack frame of a function includes:
+
+     [Block A]
+       1. previous hard frame pointer
+       2. return address
+       3. callee-saved registers
+       4. <padding bytes> (we will calculte in nds32_compute_stack_frame()
+                           and save it at
+                           cfun->machine->callee_saved_area_padding_bytes)
+
+     [Block B]
+       1. local variables
+       2. spilling location
+       3. <padding bytes> (it will be calculated by GCC itself)
+       4. incoming arguments
+       5. <padding bytes> (it will be calculated by GCC itself)
+
+     [Block C]
+       1. <padding bytes> (it will be calculated by GCC itself)
+       2. outgoing arguments
+
+   We 'wrap' these blocks together with
+   hard frame pointer ($r28) and stack pointer ($r31).
+   By applying the basic frame/stack/argument pointers concept,
+   the layout of a stack frame shoule be like this:
+
+                            |    |
+       old stack pointer ->  ----
+                            |    | \
+                            |    |   saved arguments for
+                            |    |   vararg functions
+                            |    | /
+      hard frame pointer ->   --
+      & argument pointer    |    | \
+                            |    |   previous hardware frame pointer
+                            |    |   return address
+                            |    |   callee-saved registers
+                            |    | /
+           frame pointer ->   --
+                            |    | \
+                            |    |   local variables
+                            |    |   and incoming arguments
+                            |    | /
+                              --
+                            |    | \
+                            |    |   outgoing
+                            |    |   arguments
+                            |    | /
+           stack pointer ->  ----
+
+  $SFP and $AP are used to represent frame pointer and arguments pointer,
+  which will be both eliminated as hard frame pointer.  */
+
+/* -- Eliminating Frame Pointer and Arg Pointer.  */
+
+static bool nds32_can_eliminate (const int from_reg, const int to_reg)
+{
+  if (from_reg == ARG_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM)
+    return true;
+
+  if (from_reg == ARG_POINTER_REGNUM && to_reg == HARD_FRAME_POINTER_REGNUM)
+    return true;
+
+  if (from_reg == FRAME_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM)
+    return true;
+
+  if (from_reg == FRAME_POINTER_REGNUM && to_reg == HARD_FRAME_POINTER_REGNUM)
+    return true;
+
+  return false;
+}
+
+/* -- Passing Arguments in Registers.  */
+
+static rtx
+nds32_function_arg (cumulative_args_t ca, enum machine_mode mode,
+		    const_tree type, bool named)
+{
+  CUMULATIVE_ARGS *cum = get_cumulative_args (ca);
+
+  /* The last time this hook is called,
+     it is called with MODE == VOIDmode.  */
+  if (mode == VOIDmode)
+    return NULL_RTX;
+
+  /* For nameless arguments, they are passed on the stack.  */
+  if (!named)
+    return NULL_RTX;
+
+  /* If there are still registers available, return it.  */
+  if (NDS32_ARG_PASS_IN_REG_P (cum->reg_offset, mode, type))
+    {
+      /* Pick up the next available register number.  */
+      return gen_rtx_REG (mode,
+			  NDS32_AVAILABLE_REGNUM_FOR_ARG (cum->reg_offset,
+							  mode,
+							  type));
+    }
+  else
+    {
+      /* No register available, return NULL_RTX.
+         The compiler will use stack to pass argument instead.  */
+      return NULL_RTX;
+    }
+}
+
+static void
+nds32_function_arg_advance (cumulative_args_t ca, enum machine_mode mode,
+			    const_tree type, bool named)
+{
+  CUMULATIVE_ARGS *cum = get_cumulative_args (ca);
+
+  /* Advance next register for use.
+     Only named argument could be advanced.  */
+  if (named)
+    {
+      cum->reg_offset
+	= NDS32_AVAILABLE_REGNUM_FOR_ARG (cum->reg_offset, mode, type)
+	  - NDS32_GPR_ARG_FIRST_REGNUM
+	  + NDS32_NEED_N_REGS_FOR_ARG (mode, type);
+    }
+}
+
+static unsigned int
+nds32_function_arg_boundary (enum machine_mode mode, const_tree type)
+{
+  return (nds32_needs_double_word_align (mode, type)
+	  ? NDS32_DOUBLE_WORD_ALIGNMENT
+	  : PARM_BOUNDARY);
+}
+
+/* -- How Scalar Function Values Are Returned.  */
+
+static rtx
+nds32_function_value (const_tree ret_type,
+		      const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
+		      bool outgoing ATTRIBUTE_UNUSED)
+{
+  enum machine_mode mode;
+  int unsignedp;
+
+  mode = TYPE_MODE (ret_type);
+  unsignedp = TYPE_UNSIGNED (ret_type);
+
+  mode = promote_mode (ret_type, mode, &unsignedp);
+
+  return gen_rtx_REG (mode, NDS32_GPR_RET_FIRST_REGNUM);
+}
+
+static rtx
+nds32_libcall_value (enum machine_mode mode,
+		     const_rtx fun ATTRIBUTE_UNUSED)
+{
+  return gen_rtx_REG (mode, NDS32_GPR_RET_FIRST_REGNUM);
+}
+
+static bool
+nds32_function_value_regno_p (const unsigned int regno)
+{
+  return (regno == NDS32_GPR_RET_FIRST_REGNUM);
+}
+
+/* -- Function Entry and Exit.  */
+
+/* The content produced from this function
+   will be placed before prologue body.  */
+static void
+nds32_asm_function_prologue (FILE *file,
+			     HOST_WIDE_INT size ATTRIBUTE_UNUSED)
+{
+  int r;
+  const char *func_name;
+  tree attrs;
+  tree name;
+
+  /* All stack frame information is supposed to be
+     already computed when expanding prologue.
+     The result is in cfun->machine.
+     DO NOT call nds32_compute_stack_frame() here
+     because it may corrupt the essential information.  */
+
+  fprintf (file, "\t! BEGIN PROLOGUE\n");
+  fprintf (file, "\t!     fp needed: %d\n", frame_pointer_needed);
+  fprintf (file, "\t!  pretend_args: %d\n", cfun->machine->va_args_size);
+  fprintf (file, "\t!    local_size: %d\n", cfun->machine->local_size);
+  fprintf (file, "\t! out_args_size: %d\n", cfun->machine->out_args_size);
+
+  /* Use df_regs_ever_live_p() to detect if the register
+     is ever used in the current function.  */
+  fprintf (file, "\t! registers ever_live: ");
+  for (r = 0; r < 32; r++)
+    {
+      if (df_regs_ever_live_p (r))
+	fprintf (file, "%s, ", reg_names[r]);
+    }
+  fputc ('\n', file);
+
+  /* Display the attributes of this function.  */
+  fprintf (file, "\t! function attributes: ");
+  /* GCC build attributes list with reverse order,
+     so we use nreverse() to make it looks like
+     the order that user specifies.  */
+  attrs = nreverse (DECL_ATTRIBUTES (current_function_decl));
+
+  /* If there is no any attribute, print out "None".  */
+  if (!attrs)
+    fprintf (file, "None");
+
+  /* If there are some attributes, try if we need to
+     construct isr vector information.  */
+  func_name = IDENTIFIER_POINTER (DECL_NAME (current_function_decl));
+  nds32_construct_isr_vectors_information (attrs, func_name);
+
+  /* Display all attributes of this function.  */
+  while (attrs)
+    {
+      name = TREE_PURPOSE (attrs);
+      fprintf (file, "%s ", IDENTIFIER_POINTER (name));
+
+      /* Pick up the next attribute.  */
+      attrs = TREE_CHAIN (attrs);
+    }
+  fputc ('\n', file);
+}
+
+/* After rtl prologue has been expanded, this function is used.  */
+static void
+nds32_asm_function_end_prologue (FILE *file)
+{
+  fprintf (file, "\t! END PROLOGUE\n");
+
+  /* If frame pointer is NOT needed and -mfp-as-gp is issued,
+     we can generate special directive: ".omit_fp_begin"
+     to guide linker doing fp-as-gp optimization.
+     However, for a naked function, which means
+     it should not have prologue/epilogue,
+     using fp-as-gp still requires saving $fp by push/pop behavior and
+     there is no benefit to use fp-as-gp on such small function.
+     So we need to make sure this function is NOT naked as well.  */
+  if (!frame_pointer_needed
+      && !cfun->machine->naked_p
+      && cfun->machine->fp_as_gp_p)
+    {
+      fprintf (file, "\t! ----------------------------------------\n");
+      fprintf (file, "\t! Guide linker to do "
+		     "link time optimization: fp-as-gp\n");
+      fprintf (file, "\t! We add one more instruction to "
+		     "initialize $fp near to $gp location.\n");
+      fprintf (file, "\t! If linker fails to use fp-as-gp transformation,\n");
+      fprintf (file, "\t! this extra instruction should be "
+		     "eliminated at link stage.\n");
+      fprintf (file, "\t.omit_fp_begin\n");
+      fprintf (file, "\tla\t$fp,_FP_BASE_\n");
+      fprintf (file, "\t! ----------------------------------------\n");
+    }
+}
+
+/* Before rtl epilogue has been expanded, this function is used.  */
+static void
+nds32_asm_function_begin_epilogue (FILE *file)
+{
+  /* If frame pointer is NOT needed and -mfp-as-gp is issued,
+     we can generate special directive: ".omit_fp_end"
+     to claim fp-as-gp optimization range.
+     However, for a naked function,
+     which means it should not have prologue/epilogue,
+     using fp-as-gp still requires saving $fp by push/pop behavior and
+     there is no benefit to use fp-as-gp on such small function.
+     So we need to make sure this function is NOT naked as well.  */
+  if (!frame_pointer_needed
+      && !cfun->machine->naked_p
+      && cfun->machine->fp_as_gp_p)
+    {
+      fprintf (file, "\t! ----------------------------------------\n");
+      fprintf (file, "\t! Claim the range of fp-as-gp "
+		     "link time optimization\n");
+      fprintf (file, "\t.omit_fp_end\n");
+      fprintf (file, "\t! ----------------------------------------\n");
+    }
+
+  fprintf (file, "\t! BEGIN EPILOGUE\n");
+}
+
+/* The content produced from this function
+   will be placed after epilogue body.  */
+static void
+nds32_asm_function_epilogue (FILE *file,
+			     HOST_WIDE_INT size ATTRIBUTE_UNUSED)
+{
+  fprintf (file, "\t! END EPILOGUE\n");
+}
+
+static void
+nds32_asm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
+			   HOST_WIDE_INT delta,
+			   HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
+			   tree function)
+{
+  int this_regno;
+
+  /* Make sure unwind info is emitted for the thunk if needed.  */
+  final_start_function (emit_barrier (), file, 1);
+
+  this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
+		? 1
+		: 0);
+
+  if (delta != 0)
+    {
+      if (satisfies_constraint_Is15 (GEN_INT (delta)))
+	{
+	  fprintf (file, "\taddi\t$r%d, $r%d, %ld\n",
+		   this_regno, this_regno, delta);
+	}
+      else if (satisfies_constraint_Is20 (GEN_INT (delta)))
+	{
+	  fprintf (file, "\tmovi\t$ta, %ld\n", delta);
+	  fprintf (file, "\tadd\t$r%d, $r%d, $ta\n", this_regno, this_regno);
+	}
+      else
+	{
+	  fprintf (file, "\tsethi\t$ta, hi20(%ld)\n", delta);
+	  fprintf (file, "\tori\t$ta, $ta, lo12(%ld)\n", delta);
+	  fprintf (file, "\tadd\t$r%d, $r%d, $ta\n", this_regno, this_regno);
+	}
+    }
+
+  fprintf (file, "\tb\t");
+  assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
+  fprintf (file, "\n");
+
+  final_end_function ();
+}
+
+/* -- Permitting tail calls.  */
+
+/* Determine whether we need to enable warning for function return check.  */
+static bool
+nds32_warn_func_return (tree decl)
+{
+/* Naked functions are implemented entirely in assembly, including the
+   return sequence, so suppress warnings about this.  */
+  return !nds32_naked_function_p (decl);
+}
+
+
+/* Implementing the Varargs Macros.  */
+
+static bool
+nds32_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
+{
+  /* Return true so that all the named arguments for FUNCTION_ARG have named=1.
+     If return false, for the variadic function, all named arguments EXCEPT
+     the last are treated as named.  */
+  return true;
+}
+
+
+/* Trampolines for Nested Functions.  */
+
+static void
+nds32_asm_trampoline_template (FILE *f)
+{
+  if (TARGET_REDUCED_REGS)
+    {
+      /* Trampoline is not supported on reduced-set registers yet.  */
+      sorry ("a nested function is not supported for reduced registers");
+    }
+  else
+    {
+      asm_fprintf (f, "\t! Trampoline code template\n");
+      asm_fprintf (f, "\t! This code fragment will be copied "
+		      "into stack on demand\n");
+
+      asm_fprintf (f, "\tmfusr\t$r16,$pc\n");
+      asm_fprintf (f, "\tlwi\t$r15,[$r16 + 20] "
+		      "! load nested function address\n");
+      asm_fprintf (f, "\tlwi\t$r16,[$r16 + 16] "
+		      "! load chain_value\n");
+      asm_fprintf (f, "\tjr\t$r15\n");
+    }
+
+  /* Preserve space ($pc + 16) for saving chain_value,
+     nds32_trampoline_init will fill the value in this slot.  */
+  asm_fprintf (f, "\t! space for saving chain_value\n");
+  assemble_aligned_integer (UNITS_PER_WORD, const0_rtx);
+
+  /* Preserve space ($pc + 20) for saving nested function address,
+     nds32_trampoline_init will fill the value in this slot.  */
+  asm_fprintf (f, "\t! space for saving nested function address\n");
+  assemble_aligned_integer (UNITS_PER_WORD, const0_rtx);
+}
+
+/* Emit RTL insns to initialize the variable parts of a trampoline.  */
+static void
+nds32_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
+{
+  int i;
+
+  /* Nested function address.  */
+  rtx fnaddr;
+  /* The memory rtx that is going to
+     be filled with chain_value.  */
+  rtx chain_value_mem;
+  /* The memory rtx that is going to
+     be filled with nested function address.  */
+  rtx nested_func_mem;
+
+  /* Start address of trampoline code in stack, for doing cache sync.  */
+  rtx sync_cache_addr;
+  /* Temporary register for sync instruction.  */
+  rtx tmp_reg;
+  /* Instruction-cache sync instruction,
+     requesting an argument as starting address.  */
+  rtx isync_insn;
+  /* For convenience reason of doing comparison.  */
+  int tramp_align_in_bytes;
+
+  /* Trampoline is not supported on reduced-set registers yet.  */
+  if (TARGET_REDUCED_REGS)
+    sorry ("a nested function is not supported for reduced registers");
+
+  /* STEP 1: Copy trampoline code template into stack,
+             fill up essential data into stack.  */
+
+  /* Extract nested function address rtx.  */
+  fnaddr = XEXP (DECL_RTL (fndecl), 0);
+
+  /* m_tramp is memory rtx that is going to be filled with trampoline code.
+     We have nds32_asm_trampoline_template() to emit template pattern.  */
+  emit_block_move (m_tramp, assemble_trampoline_template (),
+		   GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
+
+  /* After copying trampoline code into stack,
+     fill chain_value into stack.  */
+  chain_value_mem = adjust_address (m_tramp, SImode, 16);
+  emit_move_insn (chain_value_mem, chain_value);
+  /* After copying trampoline code int stack,
+     fill nested function address into stack.  */
+  nested_func_mem = adjust_address (m_tramp, SImode, 20);
+  emit_move_insn (nested_func_mem, fnaddr);
+
+  /* STEP 2: Sync instruction-cache.  */
+
+  /* We have successfully filled trampoline code into stack.
+     However, in order to execute code in stack correctly,
+     we must sync instruction cache.  */
+  sync_cache_addr = XEXP (m_tramp, 0);
+  tmp_reg         = gen_reg_rtx (SImode);
+  isync_insn      = gen_unspec_volatile_isync (tmp_reg);
+
+  /* Because nds32_cache_block_size is in bytes,
+     we get trampoline alignment in bytes for convenient comparison.  */
+  tramp_align_in_bytes = TRAMPOLINE_ALIGNMENT / BITS_PER_UNIT;
+
+  if (tramp_align_in_bytes >= nds32_cache_block_size
+      && (tramp_align_in_bytes % nds32_cache_block_size) == 0)
+    {
+      /* Under this condition, the starting address of trampoline
+         must be aligned to the starting address of each cache block
+         and we do not have to worry about cross-boundary issue.  */
+      for (i = 0;
+	   i < (TRAMPOLINE_SIZE + nds32_cache_block_size - 1)
+	       / nds32_cache_block_size;
+	   i++)
+	{
+	  emit_move_insn (tmp_reg,
+			  plus_constant (Pmode, sync_cache_addr,
+					 nds32_cache_block_size * i));
+	  emit_insn (isync_insn);
+	}
+    }
+  else if (TRAMPOLINE_SIZE > nds32_cache_block_size)
+    {
+      /* The starting address of trampoline code
+         may not be aligned to the cache block,
+         so the trampoline code may be across two cache block.
+         We need to sync the last element, which is 4-byte size,
+         of trampoline template.  */
+      for (i = 0;
+	   i < (TRAMPOLINE_SIZE + nds32_cache_block_size - 1)
+	       / nds32_cache_block_size;
+	   i++)
+	{
+	  emit_move_insn (tmp_reg,
+			  plus_constant (Pmode, sync_cache_addr,
+					 nds32_cache_block_size * i));
+	  emit_insn (isync_insn);
+	}
+
+      /* The last element of trampoline template is 4-byte size.  */
+      emit_move_insn (tmp_reg,
+		      plus_constant (Pmode, sync_cache_addr,
+				     TRAMPOLINE_SIZE - 4));
+      emit_insn (isync_insn);
+    }
+  else
+    {
+      /* This is the simplest case.
+         Because TRAMPOLINE_SIZE is less than or
+         equal to nds32_cache_block_size,
+         we can just sync start address and
+         the last element of trampoline code.  */
+
+      /* Sync starting address of tampoline code.  */
+      emit_move_insn (tmp_reg, sync_cache_addr);
+      emit_insn (isync_insn);
+      /* Sync the last element, which is 4-byte size,
+         of trampoline template.  */
+      emit_move_insn (tmp_reg,
+		      plus_constant (Pmode, sync_cache_addr,
+				     TRAMPOLINE_SIZE - 4));
+      emit_insn (isync_insn);
+    }
+
+  /* Set instruction serialization barrier
+     to guarantee the correct operations.  */
+  emit_insn (gen_unspec_volatile_isb ());
+}
+
+
+/* Addressing Modes.  */
+
+static bool
+nds32_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
+{
+  /* For (mem:DI addr) or (mem:DF addr) case,
+     we only allow 'addr' to be [reg], [symbol_ref],
+                                [const], or [reg + const_int] pattern.  */
+  if (mode == DImode || mode == DFmode)
+    {
+      /* Allow [Reg + const_int] addressing mode.  */
+      if (GET_CODE (x) == PLUS)
+	{
+	  if (nds32_address_register_rtx_p (XEXP (x, 0), strict)
+	      && nds32_legitimate_index_p (mode, XEXP (x, 1), strict)
+	      && CONST_INT_P (XEXP (x, 1)))
+	    return true;
+
+	  else if (nds32_address_register_rtx_p (XEXP (x, 1), strict)
+		   && nds32_legitimate_index_p (mode, XEXP (x, 0), strict)
+		   && CONST_INT_P (XEXP (x, 0)))
+	    return true;
+	}
+
+      /* Now check [reg], [symbol_ref], and [const].  */
+      if (GET_CODE (x) != REG
+	  && GET_CODE (x) != SYMBOL_REF
+	  && GET_CODE (x) != CONST)
+	return false;
+    }
+
+  /* Check if 'x' is a valid address.  */
+  switch (GET_CODE (x))
+    {
+    case REG:
+      /* (mem (reg A)) => [Ra] */
+      return nds32_address_register_rtx_p (x, strict);
+
+    case SYMBOL_REF:
+
+      if (!TARGET_GP_DIRECT
+	  && (reload_completed
+	      || reload_in_progress
+	      || lra_in_progress))
+	return false;
+
+      /* (mem (symbol_ref A)) => [symbol_ref] */
+      return !currently_expanding_to_rtl;
+
+    case CONST:
+
+      if (!TARGET_GP_DIRECT
+	  && (reload_completed
+	      || reload_in_progress
+	      || lra_in_progress))
+	return false;
+
+      /* (mem (const (...)))
+         => [ + const_addr ], where const_addr = symbol_ref + const_int */
+      if (GET_CODE (XEXP (x, 0)) == PLUS)
+	{
+	  rtx plus_op = XEXP (x, 0);
+
+	  rtx op0 = XEXP (plus_op, 0);
+	  rtx op1 = XEXP (plus_op, 1);
+
+	  if (GET_CODE (op0) == SYMBOL_REF && CONST_INT_P (op1))
+	    return true;
+	  else
+	    return false;
+	}
+
+	return false;
+
+    case POST_MODIFY:
+      /* (mem (post_modify (reg) (plus (reg) (reg))))
+         => [Ra], Rb */
+      /* (mem (post_modify (reg) (plus (reg) (const_int))))
+         => [Ra], const_int */
+      if (GET_CODE (XEXP (x, 0)) == REG
+	  && GET_CODE (XEXP (x, 1)) == PLUS)
+	{
+	  rtx plus_op = XEXP (x, 1);
+
+	  rtx op0 = XEXP (plus_op, 0);
+	  rtx op1 = XEXP (plus_op, 1);
+
+	  if (nds32_address_register_rtx_p (op0, strict)
+	      && nds32_legitimate_index_p (mode, op1, strict))
+	    return true;
+	  else
+	    return false;
+	}
+
+	return false;
+
+    case POST_INC:
+    case POST_DEC:
+      /* (mem (post_inc reg)) => [Ra], 1/2/4 */
+      /* (mem (post_dec reg)) => [Ra], -1/-2/-4 */
+      /* The 1/2/4 or -1/-2/-4 have been displayed in nds32.md.
+         We only need to deal with register Ra.  */
+      if (nds32_address_register_rtx_p (XEXP (x, 0), strict))
+	return true;
+      else
+	return false;
+
+    case PLUS:
+      /* (mem (plus reg const_int))
+         => [Ra + imm] */
+      /* (mem (plus reg reg))
+         => [Ra + Rb] */
+      /* (mem (plus (mult reg const_int) reg))
+         => [Ra + Rb << sv] */
+      if (nds32_address_register_rtx_p (XEXP (x, 0), strict)
+	  && nds32_legitimate_index_p (mode, XEXP (x, 1), strict))
+	return true;
+      else if (nds32_address_register_rtx_p (XEXP (x, 1), strict)
+	       && nds32_legitimate_index_p (mode, XEXP (x, 0), strict))
+	return true;
+      else
+	return false;
+
+    case LO_SUM:
+      if (!TARGET_GP_DIRECT)
+	return true;
+
+    default:
+      return false;
+    }
+}
+
+
+/* Describing Relative Costs of Operations.  */
+
+static int nds32_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
+				     reg_class_t from,
+				     reg_class_t to)
+{
+  if (from == HIGH_REGS || to == HIGH_REGS)
+    return 6;
+
+  return 2;
+}
+
+static int nds32_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
+				   reg_class_t rclass ATTRIBUTE_UNUSED,
+				   bool in ATTRIBUTE_UNUSED)
+{
+  return 8;
+}
+
+/* This target hook describes the relative costs of RTL expressions.
+   Return 'true' when all subexpressions of x have been processed.
+   Return 'false' to sum the costs of sub-rtx, plus cost of this operation.
+   Refer to gcc/rtlanal.c for more information.  */
+static bool
+nds32_rtx_costs (rtx x,
+		 int code,
+		 int outer_code,
+		 int opno ATTRIBUTE_UNUSED,
+		 int *total,
+		 bool speed)
+{
+  /* According to 'speed', goto suitable cost model section.  */
+  if (speed)
+    goto performance_cost;
+  else
+    goto size_cost;
+
+
+performance_cost:
+  /* This is section for performance cost model.  */
+
+  /* In gcc/rtl.h, the default value of COSTS_N_INSNS(N) is N*4.
+     We treat it as 4-cycle cost for each instruction
+     under performance consideration.  */
+  switch (code)
+    {
+    case SET:
+      /* For 'SET' rtx, we need to return false
+         so that it can recursively calculate costs.  */
+      return false;
+
+    case USE:
+      /* Used in combine.c as a marker.  */
+      *total = 0;
+      break;
+
+    case MULT:
+      *total = COSTS_N_INSNS (5);
+      break;
+
+    case DIV:
+    case UDIV:
+    case MOD:
+    case UMOD:
+      *total = COSTS_N_INSNS (7);
+      break;
+
+    default:
+      *total = COSTS_N_INSNS (1);
+      break;
+    }
+
+  return true;
+
+
+size_cost:
+  /* This is section for size cost model.  */
+
+  /* In gcc/rtl.h, the default value of COSTS_N_INSNS(N) is N*4.
+     We treat it as 4-byte cost for each instruction
+     under code size consideration.  */
+  switch (code)
+    {
+    case SET:
+      /* For 'SET' rtx, we need to return false
+         so that it can recursively calculate costs.  */
+      return false;
+
+    case USE:
+      /* Used in combine.c as a marker.  */
+      *total = 0;
+      break;
+
+    case CONST_INT:
+      /* All instructions involving constant operation
+         need to be considered for cost evaluation.  */
+      if (outer_code == SET)
+	{
+	  /* (set X imm5s), use movi55, 2-byte cost.
+	     (set X imm20s), use movi, 4-byte cost.
+	     (set X BIG_INT), use sethi/ori, 8-byte cost.  */
+	  if (satisfies_constraint_Is05 (x))
+	    *total = COSTS_N_INSNS (1) - 2;
+	  else if (satisfies_constraint_Is20 (x))
+	    *total = COSTS_N_INSNS (1);
+	  else
+	    *total = COSTS_N_INSNS (2);
+	}
+      else if (outer_code == PLUS || outer_code == MINUS)
+	{
+	  /* Possible addi333/subi333 or subi45/addi45, 2-byte cost.
+	     General case, cost 1 instruction with 4-byte.  */
+	  if (satisfies_constraint_Iu05 (x))
+	    *total = COSTS_N_INSNS (1) - 2;
+	  else
+	    *total = COSTS_N_INSNS (1);
+	}
+      else if (outer_code == ASHIFT)
+	{
+	  /* Possible slli333, 2-byte cost.
+	     General case, cost 1 instruction with 4-byte.  */
+	  if (satisfies_constraint_Iu03 (x))
+	    *total = COSTS_N_INSNS (1) - 2;
+	  else
+	    *total = COSTS_N_INSNS (1);
+	}
+      else if (outer_code == ASHIFTRT || outer_code == LSHIFTRT)
+	{
+	  /* Possible srai45 or srli45, 2-byte cost.
+	     General case, cost 1 instruction with 4-byte.  */
+	  if (satisfies_constraint_Iu05 (x))
+	    *total = COSTS_N_INSNS (1) - 2;
+	  else
+	    *total = COSTS_N_INSNS (1);
+	}
+      else
+	{
+	  /* For other cases, simply set it 4-byte cost.  */
+	  *total = COSTS_N_INSNS (1);
+	}
+      break;
+
+    case CONST_DOUBLE:
+      /* It requires high part and low part processing, set it 8-byte cost.  */
+      *total = COSTS_N_INSNS (2);
+      break;
+
+    default:
+      /* For other cases, generally we set it 4-byte cost
+         and stop resurively traversing.  */
+      *total = COSTS_N_INSNS (1);
+      break;
+    }
+
+  return true;
+}
+
+static int nds32_address_cost (rtx address,
+			       enum machine_mode mode ATTRIBUTE_UNUSED,
+			       addr_space_t as ATTRIBUTE_UNUSED,
+			       bool speed)
+{
+  rtx plus0, plus1;
+  enum rtx_code code;
+
+  code = GET_CODE (address);
+
+  /* According to 'speed', goto suitable cost model section.  */
+  if (speed)
+    goto performance_cost;
+  else
+    goto size_cost;
+
+performance_cost:
+  /* This is section for performance cost model.  */
+
+  /* FALLTHRU, currently we use same cost model as size_cost.  */
+
+size_cost:
+  /* This is section for size cost model.  */
+
+  switch (code)
+    {
+    case POST_MODIFY:
+    case POST_INC:
+    case POST_DEC:
+      /* We encourage that rtx contains
+         POST_MODIFY/POST_INC/POST_DEC behavior.  */
+      return 0;
+
+    case SYMBOL_REF:
+      /* We can have gp-relative load/store for symbol_ref.
+         Have it 4-byte cost.  */
+      return COSTS_N_INSNS (1);
+
+    case CONST:
+      /* It is supposed to be the pattern (const (plus symbol_ref const_int)).
+         Have it 4-byte cost.  */
+      return COSTS_N_INSNS (1);
+
+    case REG:
+      /* Simply return 4-byte costs.  */
+      return COSTS_N_INSNS (1);
+
+    case PLUS:
+      /* We do not need to check if the address is a legitimate address,
+         because this hook is never called with an invalid address.
+         But we better check the range of
+         const_int value for cost, if it exists.  */
+      plus0 = XEXP (address, 0);
+      plus1 = XEXP (address, 1);
+
+      if (REG_P (plus0) && CONST_INT_P (plus1))
+        {
+	  /* If it is possible to be lwi333/swi333 form,
+	     make it 2-byte cost.  */
+	  if (satisfies_constraint_Iu05 (plus1))
+	    return (COSTS_N_INSNS (1) - 2);
+	  else
+	    return COSTS_N_INSNS (1);
+	}
+
+      /* For other 'plus' situation, make it cost 4-byte.  */
+      return COSTS_N_INSNS (1);
+
+    default:
+      break;
+    }
+
+  return COSTS_N_INSNS (4);
+}
+
+
+/* Defining the Output Assembler Language.  */
+
+/* -- The Overall Framework of an Assembler File.  */
+
+static void
+nds32_asm_file_start (void)
+{
+  int i;
+
+  default_file_start ();
+
+  /* Tell assembler which ABI we are using.  */
+  fprintf (asm_out_file, "\t! ABI version\n");
+  fprintf (asm_out_file, "\t.abi_2\n");
+
+  /* Tell assembler that this asm code is generated by compiler.  */
+  fprintf (asm_out_file, "\t! This asm file is generated by compiler\n");
+  fprintf (asm_out_file, "\t.flag\tverbatim\n");
+  /* Give assembler the size of each vector for interrupt handler.  */
+  fprintf (asm_out_file, "\t! This vector size directive is required "
+			 "for checking inconsistency on interrupt handler\n");
+  fprintf (asm_out_file, "\t.vec_size\t%d\n", nds32_isr_vector_size);
+
+  /* If user enables '-mforce-fp-as-gp' or compiles programs with -Os,
+     the compiler may produce 'la $fp,_FP_BASE_' instruction
+     at prologue for fp-as-gp optimization.
+     We should emit weak reference of _FP_BASE_ to avoid undefined reference
+     in case user does not pass '--relax' option to linker.  */
+  if (TARGET_FORCE_FP_AS_GP || optimize_size)
+    {
+      fprintf (asm_out_file, "\t! This weak reference is required to do "
+			     "fp-as-gp link time optimization\n");
+      fprintf (asm_out_file, "\t.weak\t_FP_BASE_\n");
+    }
+  /* If user enables '-mex9', we should emit relaxation directive
+     to tell linker that this file is allowed to do ex9 optimization.  */
+  if (TARGET_EX9)
+    {
+      fprintf (asm_out_file, "\t! This relaxation directive is required "
+			     "to do ex9 link time optimization\n");
+      fprintf (asm_out_file, "\t.relax\tex9\n");
+    }
+
+  fprintf (asm_out_file, "\t! ------------------------------------\n");
+
+  if (TARGET_ISA_V2)
+    fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V2");
+  if (TARGET_ISA_V3)
+    fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V3");
+  if (TARGET_ISA_V3M)
+    fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V3M");
+
+  fprintf (asm_out_file, "\t! Endian setting\t: %s\n",
+			 ((TARGET_BIG_ENDIAN) ? "big-endian"
+					      : "little-endian"));
+
+  fprintf (asm_out_file, "\t! ------------------------------------\n");
+
+  fprintf (asm_out_file, "\t! Use conditional move\t\t: %s\n",
+			 ((TARGET_CMOV) ? "Yes"
+					: "No"));
+  fprintf (asm_out_file, "\t! Use performance extension\t: %s\n",
+			 ((TARGET_PERF_EXT) ? "Yes"
+					    : "No"));
+
+  fprintf (asm_out_file, "\t! ------------------------------------\n");
+
+  fprintf (asm_out_file, "\t! V3PUSH instructions\t: %s\n",
+			 ((TARGET_V3PUSH) ? "Yes"
+					  : "No"));
+  fprintf (asm_out_file, "\t! 16-bit instructions\t: %s\n",
+			 ((TARGET_16_BIT) ? "Yes"
+					  : "No"));
+  fprintf (asm_out_file, "\t! GP base access\t: %s\n",
+			 ((TARGET_GP_DIRECT) ? "Yes"
+					     : "No"));
+  fprintf (asm_out_file, "\t! Reduced registers set\t: %s\n",
+			 ((TARGET_REDUCED_REGS) ? "Yes"
+						: "No"));
+
+  fprintf (asm_out_file, "\t! ------------------------------------\n");
+
+  if (optimize_size)
+    fprintf (asm_out_file, "\t! Optimization level\t: -Os\n");
+  else
+    fprintf (asm_out_file, "\t! Optimization level\t: -O%d\n", optimize);
+
+  fprintf (asm_out_file, "\t! ------------------------------------\n");
+
+  fprintf (asm_out_file, "\t! Cache block size\t: %d\n",
+			 nds32_cache_block_size);
+
+  fprintf (asm_out_file, "\t! ------------------------------------\n");
+
+  /* Initialize isr vector information array before compiling functions.  */
+  for (i = 0; i < NDS32_N_ISR_VECTORS; i++)
+    {
+      nds32_isr_vectors[i].category = NDS32_ISR_NONE;
+      strcpy (nds32_isr_vectors[i].func_name, "");
+      nds32_isr_vectors[i].save_reg = NDS32_PARTIAL_SAVE;
+      nds32_isr_vectors[i].nested_type = NDS32_NOT_NESTED;
+      nds32_isr_vectors[i].total_n_vectors = 0;
+      strcpy (nds32_isr_vectors[i].nmi_name, "");
+      strcpy (nds32_isr_vectors[i].warm_name, "");
+    }
+}
+
+static void
+nds32_asm_file_end (void)
+{
+  int i;
+
+  /* If all the vectors are NDS32_ISR_NONE, we can return immediately.  */
+  for (i = 0; i < NDS32_N_ISR_VECTORS; i++)
+    if (nds32_isr_vectors[i].category != NDS32_ISR_NONE)
+      break;
+
+  if (i == NDS32_N_ISR_VECTORS)
+    return;
+
+  /* At least one vector is NOT NDS32_ISR_NONE,
+     we should output isr vector information.  */
+  fprintf (asm_out_file, "\t! ------------------------------------\n");
+  fprintf (asm_out_file, "\t! The isr vector information:\n");
+  fprintf (asm_out_file, "\t! ------------------------------------\n");
+
+  /* Check reset handler first.  Its vector number is always 0.  */
+  if (nds32_isr_vectors[0].category == NDS32_ISR_RESET)
+    {
+      nds32_emit_isr_reset_content ();
+      fprintf (asm_out_file, "\t! ------------------------------------\n");
+    }
+
+  /* Check other vectors, starting from vector number 1.  */
+  for (i = 1; i < NDS32_N_ISR_VECTORS; i++)
+    {
+      if (nds32_isr_vectors[i].category == NDS32_ISR_INTERRUPT
+	  || nds32_isr_vectors[i].category == NDS32_ISR_EXCEPTION)
+	{
+	  /* Found one vector which is interupt or exception.
+	     Output its jmptbl and vector section content.  */
+	  fprintf (asm_out_file, "\t! interrupt/exception vector %02d\n", i);
+	  fprintf (asm_out_file, "\t! ------------------------------------\n");
+	  nds32_emit_isr_jmptbl_section (i);
+	  fprintf (asm_out_file, "\t! ....................................\n");
+	  nds32_emit_isr_vector_section (i);
+	  fprintf (asm_out_file, "\t! ------------------------------------\n");
+	}
+    }
+
+  fprintf (asm_out_file, "\t! ------------------------------------\n");
+}
+
+/* -- Output and Generation of Labels.  */
+
+static void
+nds32_asm_globalize_label (FILE *stream, const char *name)
+{
+  fputs ("\t.global\t", stream);
+  assemble_name (stream, name);
+  fputs ("\n", stream);
+}
+
+/* -- Output of Assembler Instructions.  */
+
+static void
+nds32_print_operand (FILE *stream, rtx x, int code)
+{
+  int op_value;
+
+  switch (code)
+    {
+    case 0 :
+      /* Do nothing special.  */
+      break;
+
+    case 'V':
+      /* 'x' is supposed to be CONST_INT, get the value.  */
+      gcc_assert (CONST_INT_P (x));
+      op_value = INTVAL (x);
+
+      /* According to the Andes architecture,
+         the system/user register index range is 0 ~ 1023.
+         In order to avoid conflict between user-specified-integer value
+         and enum-specified-register value,
+         the 'enum nds32_intrinsic_registers' value
+         in nds32_intrinsic.h starts from 1024.  */
+      if (op_value < 1024 && op_value >= 0)
+	{
+	  /* If user gives integer value directly (0~1023),
+	     we just print out the value.  */
+	  fprintf (stream, "%d", op_value);
+	}
+      else if (op_value < 0
+	       || op_value >= ((int) ARRAY_SIZE (nds32_intrinsic_register_names)
+			       + 1024))
+	{
+	  /* The enum index value for array size is out of range.  */
+	  error ("intrinsic register index is out of range");
+	}
+      else
+	{
+	  /* If user applies normal way with __NDS32_REG_XXX__ enum data,
+	     we can print out register name.  Remember to substract 1024.  */
+	  fprintf (stream, "%s",
+			   nds32_intrinsic_register_names[op_value - 1024]);
+	}
+
+      /* No need to handle following process, so return immediately.  */
+      return;
+
+    default :
+      /* Unknown flag.  */
+      output_operand_lossage ("invalid operand output code");
+      break;
+    }
+
+  switch (GET_CODE (x))
+    {
+    case LABEL_REF:
+    case SYMBOL_REF:
+      output_addr_const (stream, x);
+      break;
+
+    case REG:
+      /* Forbid using static chain register ($r16)
+         on reduced-set registers configuration.  */
+      if (TARGET_REDUCED_REGS
+	  && REGNO (x) == STATIC_CHAIN_REGNUM)
+	sorry ("a nested function is not supported for reduced registers");
+
+      /* Normal cases, print out register name.  */
+      fputs (reg_names[REGNO (x)], stream);
+      break;
+
+    case MEM:
+      output_address (XEXP (x, 0));
+      break;
+
+    case CODE_LABEL:
+    case CONST_INT:
+    case CONST:
+      output_addr_const (stream, x);
+      break;
+
+    default:
+      /* Generally, output_addr_const () is able to handle most cases.
+         We want to see what CODE could appear,
+         so we use gcc_unreachable() to stop it.  */
+      debug_rtx (x);
+      gcc_unreachable ();
+      break;
+    }
+}
+
+static void
+nds32_print_operand_address (FILE *stream, rtx x)
+{
+  rtx op0, op1;
+
+  switch (GET_CODE (x))
+    {
+    case SYMBOL_REF:
+    case CONST:
+      /* [ + symbol_ref] */
+      /* [ + const_addr], where const_addr = symbol_ref + const_int */
+      fputs ("[ + ", stream);
+      output_addr_const (stream, x);
+      fputs ("]", stream);
+      break;
+
+    case REG:
+      /* Forbid using static chain register ($r16)
+         on reduced-set registers configuration.  */
+      if (TARGET_REDUCED_REGS
+	  && REGNO (x) == STATIC_CHAIN_REGNUM)
+	sorry ("a nested function is not supported for reduced registers");
+
+      /* [Ra] */
+      fprintf (stream, "[%s]", reg_names[REGNO (x)]);
+      break;
+
+    case PLUS:
+      op0 = XEXP (x, 0);
+      op1 = XEXP (x, 1);
+
+      /* Checking op0, forbid using static chain register ($r16)
+         on reduced-set registers configuration.  */
+      if (TARGET_REDUCED_REGS
+	  && REG_P (op0)
+	  && REGNO (op0) == STATIC_CHAIN_REGNUM)
+	sorry ("a nested function is not supported for reduced registers");
+      /* Checking op1, forbid using static chain register ($r16)
+         on reduced-set registers configuration.  */
+      if (TARGET_REDUCED_REGS
+	  && REG_P (op1)
+	  && REGNO (op1) == STATIC_CHAIN_REGNUM)
+	sorry ("a nested function is not supported for reduced registers");
+
+      if (REG_P (op0) && CONST_INT_P (op1))
+	{
+	  /* [Ra + imm] */
+	  fprintf (stream, "[%s + (%d)]",
+			   reg_names[REGNO (op0)], (int)INTVAL (op1));
+	}
+      else if (REG_P (op0) && REG_P (op1))
+	{
+	  /* [Ra + Rb] */
+	  fprintf (stream, "[%s + %s]",
+			   reg_names[REGNO (op0)], reg_names[REGNO (op1)]);
+	}
+      else if (GET_CODE (op0) == MULT && REG_P (op1))
+	{
+	  /* [Ra + Rb << sv]
+	     From observation, the pattern looks like:
+	     (plus:SI (mult:SI (reg:SI 58)
+	                       (const_int 4 [0x4]))
+	              (reg/f:SI 57)) */
+	  int sv;
+
+	  /* We need to set sv to output shift value.  */
+	  if (INTVAL (XEXP (op0, 1)) == 1)
+	    sv = 0;
+	  else if (INTVAL (XEXP (op0, 1)) == 2)
+	    sv = 1;
+	  else if (INTVAL (XEXP (op0, 1)) == 4)
+	    sv = 2;
+	  else
+	    gcc_unreachable ();
+
+	  fprintf (stream, "[%s + %s << %d]",
+			   reg_names[REGNO (op1)],
+			   reg_names[REGNO (XEXP (op0, 0))],
+			   sv);
+	}
+      else
+	{
+	  /* The control flow is not supposed to be here.  */
+	  debug_rtx (x);
+	  gcc_unreachable ();
+	}
+
+      break;
+
+    case POST_MODIFY:
+      /* (post_modify (regA) (plus (regA) (regB)))
+         (post_modify (regA) (plus (regA) (const_int)))
+         We would like to extract
+         regA and regB (or const_int) from plus rtx.  */
+      op0 = XEXP (XEXP (x, 1), 0);
+      op1 = XEXP (XEXP (x, 1), 1);
+
+      /* Checking op0, forbid using static chain register ($r16)
+         on reduced-set registers configuration.  */
+      if (TARGET_REDUCED_REGS
+	  && REG_P (op0)
+	  && REGNO (op0) == STATIC_CHAIN_REGNUM)
+	sorry ("a nested function is not supported for reduced registers");
+      /* Checking op1, forbid using static chain register ($r16)
+         on reduced-set registers configuration.  */
+      if (TARGET_REDUCED_REGS
+	  && REG_P (op1)
+	  && REGNO (op1) == STATIC_CHAIN_REGNUM)
+	sorry ("a nested function is not supported for reduced registers");
+
+      if (REG_P (op0) && REG_P (op1))
+	{
+	  /* [Ra], Rb */
+	  fprintf (stream, "[%s], %s",
+			   reg_names[REGNO (op0)], reg_names[REGNO (op1)]);
+	}
+      else if (REG_P (op0) && CONST_INT_P (op1))
+	{
+	  /* [Ra], imm */
+	  fprintf (stream, "[%s], %d",
+			   reg_names[REGNO (op0)], (int)INTVAL (op1));
+	}
+      else
+	{
+	  /* The control flow is not supposed to be here.  */
+	  debug_rtx (x);
+	  gcc_unreachable ();
+	}
+
+      break;
+
+    case POST_INC:
+    case POST_DEC:
+      op0 = XEXP (x, 0);
+
+      /* Checking op0, forbid using static chain register ($r16)
+         on reduced-set registers configuration.  */
+      if (TARGET_REDUCED_REGS
+	  && REG_P (op0)
+	  && REGNO (op0) == STATIC_CHAIN_REGNUM)
+	sorry ("a nested function is not supported for reduced registers");
+
+      if (REG_P (op0))
+	{
+	  /* "[Ra], 1/2/4" or "[Ra], -1/-2/-4"
+	     The 1/2/4 or -1/-2/-4 have been displayed in nds32.md.
+	     We only need to deal with register Ra.  */
+	  fprintf (stream, "[%s]", reg_names[REGNO (op0)]);
+	}
+      else
+	{
+	  /* The control flow is not supposed to be here.  */
+	  debug_rtx (x);
+	  gcc_unreachable ();
+	}
+
+      break;
+
+    default :
+      /* Generally, output_addr_const () is able to handle most cases.
+         We want to see what CODE could appear,
+         so we use gcc_unreachable() to stop it.  */
+      debug_rtx (x);
+      gcc_unreachable ();
+      break;
+    }
+}
+
+
+/* Defining target-specific uses of __attribute__.  */
+
+/* Add some checking after merging attributes.  */
+static tree
+nds32_merge_decl_attributes (tree olddecl, tree newdecl)
+{
+  tree combined_attrs;
+
+  /* Create combined attributes.  */
+  combined_attrs = merge_attributes (DECL_ATTRIBUTES (olddecl),
+				     DECL_ATTRIBUTES (newdecl));
+
+  /* Sinc newdecl is acutally a duplicate of olddecl,
+     we can take olddecl for some operations.  */
+  if (TREE_CODE (olddecl) == FUNCTION_DECL)
+    {
+      /* Check isr-specific attributes conflict.  */
+      nds32_check_isr_attrs_conflict (olddecl, combined_attrs);
+    }
+
+  return combined_attrs;
+}
+
+/* Add some checking when inserting attributes.  */
+static void
+nds32_insert_attributes (tree decl, tree *attributes)
+{
+  /* For function declaration, we need to check isr-specific attributes:
+       1. Call nds32_check_isr_attrs_conflict() to check any conflict.
+       2. Check valid integer value for interrupt/exception.
+       3. Check valid integer value for reset.
+       4. Check valid function for nmi/warm.  */
+  if (TREE_CODE (decl) == FUNCTION_DECL)
+    {
+      tree func_attrs;
+      tree intr, excp, reset;
+
+      /* Pick up function attributes.  */
+      func_attrs = *attributes;
+
+      /* 1. Call nds32_check_isr_attrs_conflict() to check any conflict.  */
+      nds32_check_isr_attrs_conflict (decl, func_attrs);
+
+      /* Now we are starting to check valid id value
+         for interrupt/exception/reset.
+         Note that we ONLY check its validity here.
+         To construct isr vector information, it is still performed
+         by nds32_construct_isr_vectors_information().  */
+      intr  = lookup_attribute ("interrupt", func_attrs);
+      excp  = lookup_attribute ("exception", func_attrs);
+      reset = lookup_attribute ("reset", func_attrs);
+
+      if (intr || excp)
+	{
+	  /* Deal with interrupt/exception.  */
+	  tree id_list;
+	  unsigned int lower_bound, upper_bound;
+
+	  /* The way to handle interrupt or exception is the same,
+	     we just need to take care of actual vector number.
+	     For interrupt(0..63), the actual vector number is (9..72).
+	     For exception(1..8), the actual vector number is (1..8).  */
+	  lower_bound = (intr) ? (0) : (1);
+	  upper_bound = (intr) ? (63) : (8);
+
+	  /* Prepare id list so that we can traverse id value.  */
+	  id_list = (intr) ? (TREE_VALUE (intr)) : (TREE_VALUE (excp));
+
+	  /* 2. Check valid integer value for interrupt/exception.  */
+	  while (id_list)
+	    {
+	      tree id;
+
+	      /* Pick up each vector id value.  */
+	      id = TREE_VALUE (id_list);
+	      /* Issue error if it is not a valid integer value.  */
+	      if (TREE_CODE (id) != INTEGER_CST
+		  || TREE_INT_CST_LOW (id) < lower_bound
+		  || TREE_INT_CST_LOW (id) > upper_bound)
+		error ("invalid id value for interrupt/exception attribute");
+
+	      /* Advance to next id.  */
+	      id_list = TREE_CHAIN (id_list);
+	    }
+	}
+      else if (reset)
+	{
+	  /* Deal with reset.  */
+	  tree id_list;
+	  tree id;
+	  tree nmi, warm;
+	  unsigned int lower_bound;
+	  unsigned int upper_bound;
+
+	  /* Prepare id_list and identify id value so that
+	     we can check if total number of vectors is valid.  */
+	  id_list = TREE_VALUE (reset);
+	  id = TREE_VALUE (id_list);
+
+	  /* The maximum numbers for user's interrupt is 64.  */
+	  lower_bound = 0;
+	  upper_bound = 64;
+
+	  /* 3. Check valid integer value for reset.  */
+	  if (TREE_CODE (id) != INTEGER_CST
+	      || TREE_INT_CST_LOW (id) < lower_bound
+	      || TREE_INT_CST_LOW (id) > upper_bound)
+	    error ("invalid id value for reset attribute");
+
+	  /* 4. Check valid function for nmi/warm.  */
+	  nmi  = lookup_attribute ("nmi", func_attrs);
+	  warm = lookup_attribute ("warm", func_attrs);
+
+	  if (nmi != NULL_TREE)
+	    {
+	      tree nmi_func_list;
+	      tree nmi_func;
+
+	      nmi_func_list = TREE_VALUE (nmi);
+	      nmi_func = TREE_VALUE (nmi_func_list);
+
+	      /* Issue error if it is not a valid nmi function.  */
+	      if (TREE_CODE (nmi_func) != IDENTIFIER_NODE)
+		error ("invalid nmi function for reset attribute");
+	    }
+
+	  if (warm != NULL_TREE)
+	    {
+	      tree warm_func_list;
+	      tree warm_func;
+
+	      warm_func_list = TREE_VALUE (warm);
+	      warm_func = TREE_VALUE (warm_func_list);
+
+	      /* Issue error if it is not a valid warm function.  */
+	      if (TREE_CODE (warm_func) != IDENTIFIER_NODE)
+		error ("invalid warm function for reset attribute");
+	    }
+	}
+      else
+	{
+	  /* No interrupt, exception, or reset attribute is set.  */
+	  return;
+	}
+    }
+}
+
+static bool
+nds32_option_pragma_parse (tree args ATTRIBUTE_UNUSED,
+			   tree pop_target ATTRIBUTE_UNUSED)
+{
+  /* Currently, we do not parse any pragma target by ourself,
+     so just simply return false.  */
+  return false;
+}
+
+static void
+nds32_option_override (void)
+{
+  /* After all the command options have been parsed,
+     we shall deal with some flags for changing compiler settings.  */
+
+  /* At first, we check if we have to strictly
+     set some flags based on ISA family.  */
+  if (TARGET_ISA_V2)
+    {
+      /* Under V2 ISA, we need to strictly disable TARGET_V3PUSH.  */
+      target_flags &= ~MASK_V3PUSH;
+    }
+  if (TARGET_ISA_V3)
+    {
+      /* Under V3 ISA, currently nothing should be strictly set.  */
+    }
+  if (TARGET_ISA_V3M)
+    {
+      /* Under V3M ISA, we need to strictly enable TARGET_REDUCED_REGS.  */
+      target_flags |= MASK_REDUCED_REGS;
+      /* Under V3M ISA, we need to strictly disable TARGET_PERF_EXT.  */
+      target_flags &= ~MASK_PERF_EXT;
+    }
+
+  /* See if we are using reduced-set registers:
+       $r0~$r5, $r6~$r10, $r15, $r28, $r29, $r30, $r31
+     If so, we must forbid using $r11~$r14, $r16~$r27.  */
+  if (TARGET_REDUCED_REGS)
+    {
+      int r;
+
+      /* Prevent register allocator from
+         choosing it as doing register allocation.  */
+      for (r = 11; r <= 14; r++)
+	fixed_regs[r] = call_used_regs[r] = 1;
+      for (r = 16; r <= 27; r++)
+	fixed_regs[r] = call_used_regs[r] = 1;
+    }
+
+  /* See if user explicitly would like to use fp-as-gp optimization.
+     If so, we must prevent $fp from being allocated
+     during register allocation.  */
+  if (TARGET_FORCE_FP_AS_GP)
+    fixed_regs[FP_REGNUM] = call_used_regs[FP_REGNUM] = 1;
+
+  if (!TARGET_16_BIT)
+    {
+      /* Under no 16 bit ISA, we need to strictly disable TARGET_V3PUSH.  */
+      target_flags &= ~MASK_V3PUSH;
+    }
+
+  /* Currently, we don't support PIC code generation yet.  */
+  if (flag_pic)
+    sorry ("not support -fpic");
+}
+
+
+/* Miscellaneous Parameters.  */
+
+static void
+nds32_init_builtins (void)
+{
+  tree pointer_type_node  = build_pointer_type (integer_type_node);
+
+  tree void_ftype_void    = build_function_type (void_type_node,
+						 void_list_node);
+
+  tree void_ftype_pint    = build_function_type_list (void_type_node,
+						      pointer_type_node,
+						      NULL_TREE);
+
+  tree int_ftype_int      = build_function_type_list (integer_type_node,
+						      integer_type_node,
+						      NULL_TREE);
+
+  tree void_ftype_int_int = build_function_type_list (void_type_node,
+						      integer_type_node,
+						      integer_type_node,
+						      NULL_TREE);
+
+  /* Cache.  */
+  add_builtin_function ("__builtin_nds32_isync",  void_ftype_pint,
+			NDS32_BUILTIN_ISYNC,
+			BUILT_IN_MD, NULL, NULL_TREE);
+  add_builtin_function ("__builtin_nds32_isb",  void_ftype_void,
+			NDS32_BUILTIN_ISB,
+			BUILT_IN_MD, NULL, NULL_TREE);
+
+  /* Register Transfer.  */
+  add_builtin_function ("__builtin_nds32_mfsr",  int_ftype_int,
+			NDS32_BUILTIN_MFSR,
+			BUILT_IN_MD, NULL, NULL_TREE);
+  add_builtin_function ("__builtin_nds32_mfusr", int_ftype_int,
+			NDS32_BUILTIN_MFUSR,
+			BUILT_IN_MD, NULL, NULL_TREE);
+  add_builtin_function ("__builtin_nds32_mtsr",  void_ftype_int_int,
+			NDS32_BUILTIN_MTSR,
+			BUILT_IN_MD, NULL, NULL_TREE);
+  add_builtin_function ("__builtin_nds32_mtusr", void_ftype_int_int,
+			NDS32_BUILTIN_MTUSR,
+			BUILT_IN_MD, NULL, NULL_TREE);
+
+  /* Interrupt.  */
+  add_builtin_function ("__builtin_nds32_setgie_en",  void_ftype_void,
+			NDS32_BUILTIN_SETGIE_EN,
+			BUILT_IN_MD, NULL, NULL_TREE);
+  add_builtin_function ("__builtin_nds32_setgie_dis", void_ftype_void,
+			NDS32_BUILTIN_SETGIE_DIS,
+			BUILT_IN_MD, NULL, NULL_TREE);
+}
+
+static rtx
+nds32_expand_builtin (tree exp,
+		      rtx target,
+		      rtx subtarget ATTRIBUTE_UNUSED,
+		      enum machine_mode mode ATTRIBUTE_UNUSED,
+		      int ignore ATTRIBUTE_UNUSED)
+{
+  tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
+
+  int fcode = DECL_FUNCTION_CODE (fndecl);
+
+  switch (fcode)
+    {
+    /* Cache.  */
+    case NDS32_BUILTIN_ISYNC:
+      return nds32_expand_builtin_null_ftype_reg
+	     (CODE_FOR_unspec_volatile_isync, exp, target);
+    case NDS32_BUILTIN_ISB:
+      /* Since there are no result and operands for isb instruciton,
+         we can simply emit this rtx.  */
+      emit_insn (gen_unspec_volatile_isb ());
+      return target;
+
+    /* Register Transfer.  */
+    case NDS32_BUILTIN_MFSR:
+      return nds32_expand_builtin_reg_ftype_imm
+	     (CODE_FOR_unspec_volatile_mfsr, exp, target);
+    case NDS32_BUILTIN_MFUSR:
+      return nds32_expand_builtin_reg_ftype_imm
+	     (CODE_FOR_unspec_volatile_mfusr, exp, target);
+    case NDS32_BUILTIN_MTSR:
+      return nds32_expand_builtin_null_ftype_reg_imm
+	     (CODE_FOR_unspec_volatile_mtsr, exp, target);
+    case NDS32_BUILTIN_MTUSR:
+      return nds32_expand_builtin_null_ftype_reg_imm
+	     (CODE_FOR_unspec_volatile_mtusr, exp, target);
+
+    /* Interrupt.  */
+    case NDS32_BUILTIN_SETGIE_EN:
+      /* Since there are no result and operands for setgie.e instruciton,
+         we can simply emit this rtx.  */
+      emit_insn (gen_unspec_volatile_setgie_en ());
+      return target;
+    case NDS32_BUILTIN_SETGIE_DIS:
+      /* Since there are no result and operands for setgie.d instruciton,
+         we can simply emit this rtx.  */
+      emit_insn (gen_unspec_volatile_setgie_dis ());
+      return target;
+
+    default:
+      gcc_unreachable ();
+    }
+
+  return NULL_RTX;
+}
+
+
+/* ------------------------------------------------------------------------ */
+
+/* PART 4: Implemet extern function definitions,
+           the prototype is in nds32-protos.h.  */
+
+/* Defining Data Structures for Per-function Information.  */
+
+void
+nds32_init_expanders (void)
+{
+  /* Arrange to initialize and mark the machine per-function status.  */
+  init_machine_status = nds32_init_machine_status;
+}
+
+
+/* Register Usage.  */
+
+/* -- How Values Fit in Registers.  */
+
+int
+nds32_hard_regno_nregs (int regno ATTRIBUTE_UNUSED,
+			enum machine_mode mode)
+{
+  return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
+}
+
+int
+nds32_hard_regno_mode_ok (int regno, enum machine_mode mode)
+{
+  /* Restrict double-word quantities to even register pairs.  */
+  if (HARD_REGNO_NREGS (regno, mode) == 1
+      || !((regno) & 1))
+    return 1;
+
+  return 0;
+}
+
+
+/* Register Classes.  */
+
+enum reg_class
+nds32_regno_reg_class (int regno)
+{
+  /* Refer to nds32.h for more register class details.  */
+
+  if (regno >= 0 && regno <= 7)
+    return LOW_REGS;
+  else if (regno >= 8 && regno <= 11)
+    return MIDDLE_REGS;
+  else if (regno >= 12 && regno <= 14)
+    return HIGH_REGS;
+  else if (regno == 15)
+    return R15_TA_REG;
+  else if (regno >= 16 && regno <= 19)
+    return MIDDLE_REGS;
+  else if (regno >= 20 && regno <= 31)
+    return HIGH_REGS;
+  else if (regno == 32 || regno == 33)
+    return FRAME_REGS;
+  else
+    return NO_REGS;
+}
+
+
+/* Stack Layout and Calling Conventions.  */
+
+/* -- Basic Stack Layout.  */
+
+rtx
+nds32_return_addr_rtx (int count,
+		       rtx frameaddr ATTRIBUTE_UNUSED)
+{
+  /* There is no way to determine the return address
+     if frameaddr is the frame that has 'count' steps
+     up from current frame.  */
+  if (count != 0)
+    return NULL_RTX;
+
+  /* If count == 0, it means we are at current frame,
+     the return address is $r30 ($lp).  */
+  return get_hard_reg_initial_val (Pmode, LP_REGNUM);
+}
+
+/* -- Eliminating Frame Pointer and Arg Pointer.  */
+
+HOST_WIDE_INT
+nds32_initial_elimination_offset (unsigned int from_reg, unsigned int to_reg)
+{
+  HOST_WIDE_INT offset;
+
+  /* Compute and setup stack frame size.
+     The result will be in cfun->machine.  */
+  nds32_compute_stack_frame ();
+
+  /* Remember to consider
+     cfun->machine->callee_saved_area_padding_bytes
+     when calculating offset.  */
+  if (from_reg == ARG_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM)
+    {
+      offset = (cfun->machine->fp_size
+	        + cfun->machine->gp_size
+		+ cfun->machine->lp_size
+		+ cfun->machine->callee_saved_regs_size
+		+ cfun->machine->callee_saved_area_padding_bytes
+		+ cfun->machine->local_size
+		+ cfun->machine->out_args_size);
+    }
+  else if (from_reg == ARG_POINTER_REGNUM
+	   && to_reg == HARD_FRAME_POINTER_REGNUM)
+    {
+      offset = 0;
+    }
+  else if (from_reg == FRAME_POINTER_REGNUM
+	   && to_reg == STACK_POINTER_REGNUM)
+    {
+      offset = (cfun->machine->local_size + cfun->machine->out_args_size);
+    }
+  else if (from_reg == FRAME_POINTER_REGNUM
+	   && to_reg == HARD_FRAME_POINTER_REGNUM)
+    {
+      offset = (-1) * (cfun->machine->fp_size
+		       + cfun->machine->gp_size
+		       + cfun->machine->lp_size
+		       + cfun->machine->callee_saved_regs_size
+		       + cfun->machine->callee_saved_area_padding_bytes);
+    }
+  else
+    {
+      gcc_unreachable ();
+    }
+
+  return offset;
+}
+
+/* -- Passing Arguments in Registers.  */
+
+void
+nds32_init_cumulative_args (CUMULATIVE_ARGS *cum,
+			    tree fntype ATTRIBUTE_UNUSED,
+			    rtx libname ATTRIBUTE_UNUSED,
+			    tree fndecl ATTRIBUTE_UNUSED,
+			    int n_named_args ATTRIBUTE_UNUSED)
+{
+  /* Initial available registers
+     (in offset, corresponding to NDS32_GPR_ARG_FIRST_REGNUM)
+     for passing arguments.  */
+  cum->reg_offset = 0;
+}
+
+/* -- Function Entry and Exit.  */
+
+/* Function for normal multiple push prologue.  */
+void
+nds32_expand_prologue (void)
+{
+  int fp_adjust;
+  int sp_adjust;
+  int en4_const;
+
+  rtx Rb, Re;
+  rtx push_insn;
+  rtx fp_adjust_insn, sp_adjust_insn;
+
+  /* Before computing everything for stack frame size,
+     we check if it is still worth to use fp_as_gp optimization.
+     If it is, the 'df_regs_ever_live_p (FP_REGNUM)' will be set
+     so that $fp will be saved on stack.  */
+  cfun->machine->fp_as_gp_p = nds32_fp_as_gp_check_available ();
+
+  /* Compute and setup stack frame size.
+     The result will be in cfun->machine.  */
+  nds32_compute_stack_frame ();
+
+  /* If the function is 'naked',
+     we do not have to generate prologue code fragment.  */
+  if (cfun->machine->naked_p)
+    return;
+
+  /* Get callee_first_regno and callee_last_regno.  */
+  Rb = gen_rtx_REG (SImode, cfun->machine->callee_saved_regs_first_regno);
+  Re = gen_rtx_REG (SImode, cfun->machine->callee_saved_regs_last_regno);
+
+  /* push_insn = gen_stack_push_multiple(first_regno, last_regno),
+     the pattern 'stack_push_multiple' is implemented in nds32.md.
+     For En4 field, we have to calculate its constant value.
+     Refer to Andes ISA for more information.  */
+  en4_const = 0;
+  if (cfun->machine->fp_size)
+    en4_const += 8;
+  if (cfun->machine->gp_size)
+    en4_const += 4;
+  if (cfun->machine->lp_size)
+    en4_const += 2;
+
+  /* If $fp, $gp, $lp, and all callee-save registers are NOT required
+     to be saved, we don't have to create multiple push instruction.
+     Otherwise, a multiple push instruction is needed.  */
+  if (!(REGNO (Rb) == SP_REGNUM && REGNO (Re) == SP_REGNUM && en4_const == 0))
+    {
+      /* Create multiple push instruction rtx.  */
+      push_insn = nds32_gen_stack_push_multiple (Rb, Re, GEN_INT (en4_const));
+      /* Emit rtx into instructions list and receive INSN rtx form.  */
+      push_insn = emit_insn (push_insn);
+
+      /* The insn rtx 'push_insn' will change frame layout.
+         We need to use RTX_FRAME_RELATED_P so that GCC is able to
+         generate CFI (Call Frame Information) stuff.  */
+      RTX_FRAME_RELATED_P (push_insn) = 1;
+    }
+
+  /* Check frame_pointer_needed to see
+     if we shall emit fp adjustment instruction.  */
+  if (frame_pointer_needed)
+    {
+      /* adjust $fp = $sp + ($fp size) + ($gp size) + ($lp size)
+                          + (4 * callee-saved-registers)
+         Note: No need to adjust
+               cfun->machine->callee_saved_area_padding_bytes,
+               because, at this point, stack pointer is just
+               at the position after push instruction.  */
+      fp_adjust = cfun->machine->fp_size
+		  + cfun->machine->gp_size
+		  + cfun->machine->lp_size
+		  + cfun->machine->callee_saved_regs_size;
+      fp_adjust_insn = gen_addsi3 (hard_frame_pointer_rtx,
+				   stack_pointer_rtx,
+				   GEN_INT (fp_adjust));
+      /* Emit rtx into instructions list and receive INSN rtx form.  */
+      fp_adjust_insn = emit_insn (fp_adjust_insn);
+    }
+
+  /* Adjust $sp = $sp - local_size - out_args_size
+                      - callee_saved_area_padding_bytes.  */
+  sp_adjust = cfun->machine->local_size
+	      + cfun->machine->out_args_size
+	      + cfun->machine->callee_saved_area_padding_bytes;
+  /* sp_adjust value may be out of range of the addi instruction,
+     create alternative add behavior with TA_REGNUM if necessary,
+     using NEGATIVE value to tell that we are decreasing address.  */
+  sp_adjust = nds32_force_addi_stack_int ( (-1) * sp_adjust);
+  if (sp_adjust)
+    {
+      /* Generate sp adjustment instruction if and only if sp_adjust != 0.  */
+      sp_adjust_insn = gen_addsi3 (stack_pointer_rtx,
+				   stack_pointer_rtx,
+				   GEN_INT (-1 * sp_adjust));
+      /* Emit rtx into instructions list and receive INSN rtx form.  */
+      sp_adjust_insn = emit_insn (sp_adjust_insn);
+
+      /* The insn rtx 'sp_adjust_insn' will change frame layout.
+         We need to use RTX_FRAME_RELATED_P so that GCC is able to
+         generate CFI (Call Frame Information) stuff.  */
+      RTX_FRAME_RELATED_P (sp_adjust_insn) = 1;
+    }
+
+  /* Prevent the instruction scheduler from
+     moving instructions across the boundary.  */
+  emit_insn (gen_blockage ());
+}
+
+/* Function for normal multiple pop epilogue.  */
+void
+nds32_expand_epilogue (void)
+{
+  int sp_adjust;
+  int en4_const;
+
+  rtx Rb, Re;
+  rtx pop_insn;
+  rtx sp_adjust_insn;
+
+  /* Compute and setup stack frame size.
+     The result will be in cfun->machine.  */
+  nds32_compute_stack_frame ();
+
+  /* Prevent the instruction scheduler from
+     moving instructions across the boundary.  */
+  emit_insn (gen_blockage ());
+
+  /* If the function is 'naked', we do not have to generate
+     epilogue code fragment BUT 'ret' instruction.  */
+  if (cfun->machine->naked_p)
+    {
+      /* Generate return instruction by using
+         unspec_volatile_func_return pattern.
+         Make sure this instruction is after gen_blockage().
+         NOTE that $lp will become 'live'
+         after this instruction has been emitted.  */
+      emit_insn (gen_unspec_volatile_func_return ());
+      return;
+    }
+
+  if (frame_pointer_needed)
+    {
+      /* adjust $sp = $fp - ($fp size) - ($gp size) - ($lp size)
+                          - (4 * callee-saved-registers)
+         Note: No need to adjust
+               cfun->machine->callee_saved_area_padding_bytes,
+               because we want to adjust stack pointer
+               to the position for pop instruction.  */
+      sp_adjust = cfun->machine->fp_size
+		  + cfun->machine->gp_size
+		  + cfun->machine->lp_size
+		  + cfun->machine->callee_saved_regs_size;
+      sp_adjust_insn = gen_addsi3 (stack_pointer_rtx,
+				   hard_frame_pointer_rtx,
+				   GEN_INT (-1 * sp_adjust));
+      /* Emit rtx into instructions list and receive INSN rtx form.  */
+      sp_adjust_insn = emit_insn (sp_adjust_insn);
+    }
+  else
+    {
+      /* If frame pointer is NOT needed,
+         we cannot calculate the sp adjustment from frame pointer.
+         Instead, we calculate the adjustment by local_size,
+         out_args_size, and callee_saved_area_padding_bytes.
+         Notice that such sp adjustment value may be out of range,
+         so we have to deal with it as well.  */
+
+      /* Adjust $sp = $sp + local_size + out_args_size
+                          + callee_saved_area_padding_bytes.  */
+      sp_adjust = cfun->machine->local_size
+		  + cfun->machine->out_args_size
+		  + cfun->machine->callee_saved_area_padding_bytes;
+      /* sp_adjust value may be out of range of the addi instruction,
+         create alternative add behavior with TA_REGNUM if necessary,
+         using POSITIVE value to tell that we are increasing address.  */
+      sp_adjust = nds32_force_addi_stack_int (sp_adjust);
+      if (sp_adjust)
+	{
+	  /* Generate sp adjustment instruction
+	     if and only if sp_adjust != 0.  */
+	  sp_adjust_insn = gen_addsi3 (stack_pointer_rtx,
+				       stack_pointer_rtx,
+				       GEN_INT (sp_adjust));
+	  /* Emit rtx into instructions list and receive INSN rtx form.  */
+	  sp_adjust_insn = emit_insn (sp_adjust_insn);
+	}
+    }
+
+  /* Get callee_first_regno and callee_last_regno.  */
+  Rb = gen_rtx_REG (SImode, cfun->machine->callee_saved_regs_first_regno);
+  Re = gen_rtx_REG (SImode, cfun->machine->callee_saved_regs_last_regno);
+
+  /* pop_insn = gen_stack_pop_multiple(first_regno, last_regno),
+     the pattern 'stack_pop_multiple' is implementad in nds32.md.
+     For En4 field, we have to calculate its constant value.
+     Refer to Andes ISA for more information.  */
+  en4_const = 0;
+  if (cfun->machine->fp_size)
+    en4_const += 8;
+  if (cfun->machine->gp_size)
+    en4_const += 4;
+  if (cfun->machine->lp_size)
+    en4_const += 2;
+
+  /* If $fp, $gp, $lp, and all callee-save registers are NOT required
+     to be saved, we don't have to create multiple pop instruction.
+     Otherwise, a multiple pop instruction is needed.  */
+  if (!(REGNO (Rb) == SP_REGNUM && REGNO (Re) == SP_REGNUM && en4_const == 0))
+    {
+      /* Create multiple pop instruction rtx.  */
+      pop_insn = nds32_gen_stack_pop_multiple (Rb, Re, GEN_INT (en4_const));
+      /* Emit pop instruction.  */
+      emit_insn (pop_insn);
+    }
+
+  /* Generate return instruction by using
+     unspec_volatile_func_return pattern.  */
+  emit_insn (gen_unspec_volatile_func_return ());
+}
+
+/* Function for v3push prologue.  */
+void
+nds32_expand_prologue_v3push (void)
+{
+  int fp_adjust;
+  int sp_adjust;
+
+  rtx Rb, Re;
+  rtx push_insn;
+  rtx fp_adjust_insn, sp_adjust_insn;
+
+  /* Before computing everything for stack frame size,
+     we check if it is still worth to use fp_as_gp optimization.
+     If it is, the 'df_regs_ever_live_p (FP_REGNUM)' will be set
+     so that $fp will be saved on stack.  */
+  cfun->machine->fp_as_gp_p = nds32_fp_as_gp_check_available ();
+
+  /* Compute and setup stack frame size.
+     The result will be in cfun->machine.  */
+  nds32_compute_stack_frame ();
+
+  /* If the function is 'naked',
+     we do not have to generate prologue code fragment.  */
+  if (cfun->machine->naked_p)
+    return;
+
+  /* Get callee_first_regno and callee_last_regno.  */
+  Rb = gen_rtx_REG (SImode, cfun->machine->callee_saved_regs_first_regno);
+  Re = gen_rtx_REG (SImode, cfun->machine->callee_saved_regs_last_regno);
+
+  /* Calculate sp_adjust first to test if 'push25 Re,imm8u' is available,
+     where imm8u has to be 8-byte alignment.  */
+  sp_adjust = cfun->machine->local_size
+	      + cfun->machine->out_args_size
+	      + cfun->machine->callee_saved_area_padding_bytes;
+
+  if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust))
+      && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust))
+    {
+      /* We can use 'push25 Re,imm8u'.  */
+
+      /* push_insn = gen_stack_v3push(last_regno, sp_adjust),
+         the pattern 'stack_v3push' is implemented in nds32.md.
+         The (const_int 14) means v3push always push { $fp $gp $lp }.  */
+      push_insn = nds32_gen_stack_v3push (Rb, Re,
+					  GEN_INT (14), GEN_INT (sp_adjust));
+      /* emit rtx into instructions list and receive INSN rtx form */
+      push_insn = emit_insn (push_insn);
+
+      /* The insn rtx 'push_insn' will change frame layout.
+         We need to use RTX_FRAME_RELATED_P so that GCC is able to
+         generate CFI (Call Frame Information) stuff.  */
+      RTX_FRAME_RELATED_P (push_insn) = 1;
+
+      /* Check frame_pointer_needed to see
+         if we shall emit fp adjustment instruction.  */
+      if (frame_pointer_needed)
+	{
+	  /* adjust $fp = $sp   + 4         ($fp size)
+	                        + 4         ($gp size)
+	                        + 4         ($lp size)
+	                        + (4 * n)   (callee-saved registers)
+	                        + sp_adjust ('push25 Re,imm8u')
+	     Note: Since we use 'push25 Re,imm8u',
+	           the position of stack pointer is further
+	           changed after push instruction.
+	           Hence, we need to take sp_adjust value
+	           into consideration.  */
+	  fp_adjust = cfun->machine->fp_size
+		      + cfun->machine->gp_size
+		      + cfun->machine->lp_size
+		      + cfun->machine->callee_saved_regs_size
+		      + sp_adjust;
+	  fp_adjust_insn = gen_addsi3 (hard_frame_pointer_rtx,
+				       stack_pointer_rtx,
+				       GEN_INT (fp_adjust));
+	  /* Emit rtx into instructions list and receive INSN rtx form.  */
+	  fp_adjust_insn = emit_insn (fp_adjust_insn);
+	}
+    }
+  else
+    {
+      /* We have to use 'push25 Re,0' and
+         expand one more instruction to adjust $sp later.  */
+
+      /* push_insn = gen_stack_v3push(last_regno, sp_adjust),
+         the pattern 'stack_v3push' is implemented in nds32.md.
+         The (const_int 14) means v3push always push { $fp $gp $lp }.  */
+      push_insn = nds32_gen_stack_v3push (Rb, Re,
+					  GEN_INT (14), GEN_INT (0));
+      /* Emit rtx into instructions list and receive INSN rtx form.  */
+      push_insn = emit_insn (push_insn);
+
+      /* The insn rtx 'push_insn' will change frame layout.
+         We need to use RTX_FRAME_RELATED_P so that GCC is able to
+         generate CFI (Call Frame Information) stuff.  */
+      RTX_FRAME_RELATED_P (push_insn) = 1;
+
+      /* Check frame_pointer_needed to see
+         if we shall emit fp adjustment instruction.  */
+      if (frame_pointer_needed)
+	{
+	  /* adjust $fp = $sp + 4        ($fp size)
+	                      + 4        ($gp size)
+	                      + 4        ($lp size)
+	                      + (4 * n)  (callee-saved registers)
+	     Note: Since we use 'push25 Re,0',
+	           the stack pointer is just at the position
+	           after push instruction.
+	           No need to take sp_adjust into consideration.  */
+	  fp_adjust = cfun->machine->fp_size
+		      + cfun->machine->gp_size
+		      + cfun->machine->lp_size
+		      + cfun->machine->callee_saved_regs_size;
+	  fp_adjust_insn = gen_addsi3 (hard_frame_pointer_rtx,
+				       stack_pointer_rtx,
+				       GEN_INT (fp_adjust));
+	  /* Emit rtx into instructions list and receive INSN rtx form.  */
+	  fp_adjust_insn = emit_insn (fp_adjust_insn);
+	}
+
+      /* Because we use 'push25 Re,0',
+         we need to expand one more instruction to adjust $sp.
+         However, sp_adjust value may be out of range of the addi instruction,
+         create alternative add behavior with TA_REGNUM if necessary,
+         using NEGATIVE value to tell that we are decreasing address.  */
+      sp_adjust = nds32_force_addi_stack_int ( (-1) * sp_adjust);
+      if (sp_adjust)
+	{
+	  /* Generate sp adjustment instruction
+	     if and only if sp_adjust != 0.  */
+	  sp_adjust_insn = gen_addsi3 (stack_pointer_rtx,
+				       stack_pointer_rtx,
+				       GEN_INT (-1 * sp_adjust));
+	  /* Emit rtx into instructions list and receive INSN rtx form.  */
+	  sp_adjust_insn = emit_insn (sp_adjust_insn);
+
+	  /* The insn rtx 'sp_adjust_insn' will change frame layout.
+	     We need to use RTX_FRAME_RELATED_P so that GCC is able to
+	     generate CFI (Call Frame Information) stuff.  */
+	  RTX_FRAME_RELATED_P (sp_adjust_insn) = 1;
+	}
+    }
+
+  /* Prevent the instruction scheduler from
+     moving instructions across the boundary.  */
+  emit_insn (gen_blockage ());
+}
+
+/* Function for v3pop epilogue.  */
+void
+nds32_expand_epilogue_v3pop (void)
+{
+  int sp_adjust;
+
+  rtx Rb, Re;
+  rtx pop_insn;
+  rtx sp_adjust_insn;
+
+  /* Compute and setup stack frame size.
+     The result will be in cfun->machine.  */
+  nds32_compute_stack_frame ();
+
+  /* Prevent the instruction scheduler from
+     moving instructions across the boundary.  */
+  emit_insn (gen_blockage ());
+
+  /* If the function is 'naked', we do not have to generate
+     epilogue code fragment BUT 'ret' instruction.  */
+  if (cfun->machine->naked_p)
+    {
+      /* Generate return instruction by using
+         unspec_volatile_func_return pattern.
+         Make sure this instruction is after gen_blockage().
+         NOTE that $lp will become 'live'
+         after this instruction has been emitted.  */
+      emit_insn (gen_unspec_volatile_func_return ());
+      return;
+    }
+
+  /* Get callee_first_regno and callee_last_regno.  */
+  Rb = gen_rtx_REG (SImode, cfun->machine->callee_saved_regs_first_regno);
+  Re = gen_rtx_REG (SImode, cfun->machine->callee_saved_regs_last_regno);
+
+  /* Calculate sp_adjust first to test if 'pop25 Re,imm8u' is available,
+     where imm8u has to be 8-byte alignment.  */
+  sp_adjust = cfun->machine->local_size
+	      + cfun->machine->out_args_size
+	      + cfun->machine->callee_saved_area_padding_bytes;
+
+  /* We have to consider alloca issue as well.
+     If the function does call alloca(), the stack pointer is not fixed.
+     In that case, we cannot use 'pop25 Re,imm8u' directly.
+     We have to caculate stack pointer from frame pointer
+     and then use 'pop25 Re,0'.
+     Of course, the frame_pointer_needed should be nonzero
+     if the function calls alloca().  */
+  if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust))
+      && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust)
+      && !cfun->calls_alloca)
+    {
+      /* We can use 'pop25 Re,imm8u'.  */
+
+      /* pop_insn = gen_stack_v3pop(last_regno, sp_adjust),
+         the pattern 'stack_v3pop' is implementad in nds32.md.
+         The (const_int 14) means v3pop always pop { $fp $gp $lp }.  */
+      pop_insn = nds32_gen_stack_v3pop (Rb, Re,
+					GEN_INT (14), GEN_INT (sp_adjust));
+
+      /* Emit pop instruction.  */
+      emit_insn (pop_insn);
+    }
+  else
+    {
+      /* We have to use 'pop25 Re,0', and prior to it,
+         we must expand one more instruction to adjust $sp.  */
+
+      if (frame_pointer_needed)
+	{
+	  /* adjust $sp = $fp - 4        ($fp size)
+	                      - 4        ($gp size)
+	                      - 4        ($lp size)
+	                      - (4 * n)  (callee-saved registers)
+	     Note: No need to adjust
+	           cfun->machine->callee_saved_area_padding_bytes,
+	           because we want to adjust stack pointer
+	           to the position for pop instruction.  */
+	  sp_adjust = cfun->machine->fp_size
+		      + cfun->machine->gp_size
+		      + cfun->machine->lp_size
+		      + cfun->machine->callee_saved_regs_size;
+	  sp_adjust_insn = gen_addsi3 (stack_pointer_rtx,
+				       hard_frame_pointer_rtx,
+				       GEN_INT (-1 * sp_adjust));
+	  /* Emit rtx into instructions list and receive INSN rtx form.  */
+	  sp_adjust_insn = emit_insn (sp_adjust_insn);
+	}
+      else
+	{
+	  /* If frame pointer is NOT needed,
+	     we cannot calculate the sp adjustment from frame pointer.
+	     Instead, we calculate the adjustment by local_size,
+	     out_args_size, and callee_saved_area_padding_bytes.
+	     Notice that such sp adjustment value may be out of range,
+	     so we have to deal with it as well.  */
+
+	  /* Adjust $sp = $sp + local_size + out_args_size
+			      + callee_saved_area_padding_bytes.  */
+	  sp_adjust = cfun->machine->local_size
+		      + cfun->machine->out_args_size
+		      + cfun->machine->callee_saved_area_padding_bytes;
+	  /* sp_adjust value may be out of range of the addi instruction,
+	     create alternative add behavior with TA_REGNUM if necessary,
+	     using POSITIVE value to tell that we are increasing address.  */
+	  sp_adjust = nds32_force_addi_stack_int (sp_adjust);
+	  if (sp_adjust)
+	    {
+	      /* Generate sp adjustment instruction
+	         if and only if sp_adjust != 0.  */
+	      sp_adjust_insn = gen_addsi3 (stack_pointer_rtx,
+					   stack_pointer_rtx,
+					   GEN_INT (sp_adjust));
+	      /* Emit rtx into instructions list and receive INSN rtx form.  */
+	      sp_adjust_insn = emit_insn (sp_adjust_insn);
+	    }
+	}
+
+      /* pop_insn = gen_stack_v3pop(last_regno, sp_adjust),
+         the pattern 'stack_v3pop' is implementad in nds32.md.  */
+      /* The (const_int 14) means v3pop always pop { $fp $gp $lp }.  */
+      pop_insn = nds32_gen_stack_v3pop (Rb, Re,
+					GEN_INT (14), GEN_INT (0));
+
+      /* Emit pop instruction.  */
+      emit_insn (pop_insn);
+    }
+}
+
+/* ------------------------------------------------------------------------ */
+
+/* Function to test 333-form for load/store instructions.
+   This is auxiliary extern function for auxiliary macro in nds32.h.
+   Because it is a little complicated, we use function instead of macro.  */
+bool
+nds32_ls_333_p (rtx rt, rtx ra, rtx imm, enum machine_mode mode)
+{
+  if (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS
+      && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS)
+    {
+      if (GET_MODE_SIZE (mode) == 4)
+	return satisfies_constraint_Iu05 (imm);
+
+      if (GET_MODE_SIZE (mode) == 2)
+	return satisfies_constraint_Iu04 (imm);
+
+      if (GET_MODE_SIZE (mode) == 1)
+	return satisfies_constraint_Iu03 (imm);
+    }
+
+  return false;
+}
+
+
+/* Functions to expand load_multiple and store_multiple.
+   They are auxiliary extern functions to help create rtx template.
+   Check nds32-multiple.md file for the patterns.  */
+rtx
+nds32_expand_load_multiple (int base_regno, int count,
+			    rtx base_addr, rtx basemem)
+{
+  int par_index;
+  int offset;
+  rtx result;
+  rtx new_addr, mem, reg;
+
+  /* Create the pattern that is presented in nds32-multiple.md.  */
+
+  result = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
+
+  for (par_index = 0; par_index < count; par_index++)
+    {
+      offset   = par_index * 4;
+      /* 4-byte for loading data to each register.  */
+      new_addr = plus_constant (Pmode, base_addr, offset);
+      mem      = adjust_automodify_address_nv (basemem, SImode,
+					       new_addr, offset);
+      reg      = gen_rtx_REG (SImode, base_regno + par_index);
+
+      XVECEXP (result, 0, par_index) = gen_rtx_SET (VOIDmode, reg, mem);
+    }
+
+  return result;
+}
+
+rtx
+nds32_expand_store_multiple (int base_regno, int count,
+			     rtx base_addr, rtx basemem)
+{
+  int par_index;
+  int offset;
+  rtx result;
+  rtx new_addr, mem, reg;
+
+  /* Create the pattern that is presented in nds32-multiple.md.  */
+
+  result = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
+
+  for (par_index = 0; par_index < count; par_index++)
+    {
+      offset   = par_index * 4;
+      /* 4-byte for storing data to memory.  */
+      new_addr = plus_constant (Pmode, base_addr, offset);
+      mem      = adjust_automodify_address_nv (basemem, SImode,
+					       new_addr, offset);
+      reg      = gen_rtx_REG (SImode, base_regno + par_index);
+
+      XVECEXP (result, 0, par_index) = gen_rtx_SET (VOIDmode, mem, reg);
+    }
+
+  return result;
+}
+
+/* Function to move block memory content by
+   using load_multiple and store_multiple.
+   This is auxiliary extern function to help create rtx template.
+   Check nds32-multiple.md file for the patterns.  */
+int
+nds32_expand_movmemqi (rtx dstmem, rtx srcmem, rtx total_bytes, rtx alignment)
+{
+  HOST_WIDE_INT in_words, out_words;
+  rtx dst_base_reg, src_base_reg;
+  int maximum_bytes;
+
+  /* Because reduced-set regsiters has few registers
+     (r0~r5, r6~10, r15, r28~r31, where 'r15' and 'r28~r31'
+      cannot be used for register allocation),
+     using 8 registers (32 bytes) for moving memory block
+     may easily consume all of them.
+     It makes register allocation/spilling hard to work.
+     So we only allow maximum=4 registers (16 bytes) for
+     moving memory block under reduced-set registers.  */
+  if (TARGET_REDUCED_REGS)
+    maximum_bytes = 16;
+  else
+    maximum_bytes = 32;
+
+  /* 1. Total_bytes is integer for sure.
+     2. Alignment is integer for sure.
+     3. Maximum 4 or 8 registers, 4 * 4 = 16 bytes, 8 * 4 = 32 bytes.
+     4. Requires (n * 4) block size.
+     5. Requires 4-byte alignment.  */
+  if (GET_CODE (total_bytes) != CONST_INT
+      || GET_CODE (alignment) != CONST_INT
+      || INTVAL (total_bytes) > maximum_bytes
+      || INTVAL (total_bytes) & 3
+      || INTVAL (alignment) & 3)
+    return 0;
+
+  dst_base_reg = copy_to_mode_reg (SImode, XEXP (dstmem, 0));
+  src_base_reg = copy_to_mode_reg (SImode, XEXP (srcmem, 0));
+
+  out_words = in_words = INTVAL (total_bytes) / UNITS_PER_WORD;
+
+  emit_insn (nds32_expand_load_multiple (0, in_words, src_base_reg, srcmem));
+  emit_insn (nds32_expand_store_multiple (0, out_words, dst_base_reg, dstmem));
+
+  /* Successfully create patterns, return 1.  */
+  return 1;
+}
+
+/* Function to check whether the OP is a valid load/store operation.
+   This is a helper function for the predicates:
+   'nds32_load_multiple_operation' and 'nds32_store_multiple_operation'
+   in predicates.md file.
+
+   The OP is supposed to be a parallel rtx.
+   For each element within this parallel rtx:
+     (set (reg) (mem addr)) is the form for load operation.
+     (set (mem addr) (reg)) is the form for store operation.
+   We have to extract reg and mem of every element and
+   check if the information is valid for multiple load/store operation.  */
+bool
+nds32_valid_multiple_load_store (rtx op, bool load_p)
+{
+  int count;
+  int first_elt_regno;
+  rtx elt;
+
+  /* Get the counts of elements in the parallel rtx.  */
+  count = XVECLEN (op, 0);
+  /* Pick up the first element.  */
+  elt = XVECEXP (op, 0, 0);
+
+  /* Perform some quick check for the first element in the parallel rtx.  */
+  if (GET_CODE (elt) != SET
+      || count <= 1
+      || count > 8)
+    return false;
+
+  /* Pick up regno of first element for further detail checking.
+     Note that the form is different between load and store operation.  */
+  if (load_p)
+    {
+      if (GET_CODE (SET_DEST (elt)) != REG
+	  || GET_CODE (SET_SRC (elt)) != MEM)
+	return false;
+
+      first_elt_regno = REGNO (SET_DEST (elt));
+    }
+  else
+    {
+      if (GET_CODE (SET_SRC (elt)) != REG
+	  || GET_CODE (SET_DEST (elt)) != MEM)
+	return false;
+
+      first_elt_regno = REGNO (SET_SRC (elt));
+    }
+
+  /* Perform detail check for each element.
+     Refer to nds32-multiple.md for more information
+     about following checking.
+     The starting element of parallel rtx is index 0.  */
+  if (!nds32_consecutive_registers_load_store_p (op, load_p, 0,
+						 first_elt_regno,
+						 count))
+    return false;
+
+  /* Pass all test, this is a valid rtx.  */
+  return true;
+}
+
+/* Function to check whether the OP is a valid stack push/pop operation.
+   For a valid stack operation, it must satisfy following conditions:
+     1. Consecutive registers push/pop operations.
+     2. Valid $fp/$gp/$lp push/pop operations.
+     3. The last element must be stack adjustment rtx.
+   See the prologue/epilogue implementation for details.  */
+bool
+nds32_valid_stack_push_pop (rtx op, bool push_p)
+{
+  int index;
+  int total_count;
+  int rest_count;
+  int first_regno;
+  rtx elt;
+  rtx elt_reg;
+  rtx elt_mem;
+  rtx elt_plus;
+
+  /* Get the counts of elements in the parallel rtx.  */
+  total_count = XVECLEN (op, 0);
+
+  /* Perform some quick check for that every element should be 'set'.  */
+  for (index = 0; index < total_count; index++)
+    {
+      elt = XVECEXP (op, 0, index);
+      if (GET_CODE (elt) != SET)
+        return false;
+    }
+
+  /* For push operation, the parallel rtx looks like:
+     (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32)))
+                     (reg:SI Rb))
+                (set (mem (plus (reg:SI SP_REGNUM) (const_int -28)))
+                     (reg:SI Rb+1))
+                ...
+                (set (mem (plus (reg:SI SP_REGNUM) (const_int -16)))
+                     (reg:SI Re))
+                (set (mem (plus (reg:SI SP_REGNUM) (const_int -12)))
+                     (reg:SI FP_REGNUM))
+                (set (mem (plus (reg:SI SP_REGNUM) (const_int -8)))
+                     (reg:SI GP_REGNUM))
+                (set (mem (plus (reg:SI SP_REGNUM) (const_int -4)))
+                     (reg:SI LP_REGNUM))
+                (set (reg:SI SP_REGNUM)
+                     (plus (reg:SI SP_REGNUM) (const_int -32)))])
+
+     For pop operation, the parallel rtx looks like:
+     (parallel [(set (reg:SI Rb)
+                     (mem (reg:SI SP_REGNUM)))
+                (set (reg:SI Rb+1)
+                     (mem (plus (reg:SI SP_REGNUM) (const_int 4))))
+                ...
+                (set (reg:SI Re)
+                     (mem (plus (reg:SI SP_REGNUM) (const_int 16))))
+                (set (reg:SI FP_REGNUM)
+                     (mem (plus (reg:SI SP_REGNUM) (const_int 20))))
+                (set (reg:SI GP_REGNUM)
+                     (mem (plus (reg:SI SP_REGNUM) (const_int 24))))
+                (set (reg:SI LP_REGNUM)
+                     (mem (plus (reg:SI SP_REGNUM) (const_int 28))))
+                (set (reg:SI SP_REGNUM)
+                     (plus (reg:SI SP_REGNUM) (const_int 32)))]) */
+
+  /* 1. Consecutive registers push/pop operations.
+        We need to calculate how many registers should be consecutive.
+        The $sp adjustment rtx, $fp push rtx, $gp push rtx,
+        and $lp push rtx are excluded.  */
+
+  /* Exclude last $sp adjustment rtx.  */
+  rest_count = total_count - 1;
+  /* Exclude $fp, $gp, and $lp if they are in the parallel rtx.  */
+  if (cfun->machine->fp_size)
+    rest_count--;
+  if (cfun->machine->gp_size)
+    rest_count--;
+  if (cfun->machine->lp_size)
+    rest_count--;
+
+  if (rest_count > 0)
+    {
+      elt = XVECEXP (op, 0, 0);
+      /* Pick up register element.  */
+      elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
+      first_regno = REGNO (elt_reg);
+
+      /* The 'push' operation is a kind of store operation.
+         The 'pop' operation is a kind of load operation.
+         Pass corresponding false/true as second argument (bool load_p).
+         The par_index is supposed to start with index 0.  */
+      if (!nds32_consecutive_registers_load_store_p (op,
+						     !push_p ? true : false,
+						     0,
+						     first_regno,
+						     rest_count))
+        return false;
+    }
+
+  /* 2. Valid $fp/$gp/$lp push/pop operations.
+        Remember to set start index for checking them.  */
+
+  /* The rest_count is the start index for checking $fp/$gp/$lp.  */
+  index = rest_count;
+  /* If index < 0, this parallel rtx is definitely
+     not a valid stack push/pop operation.  */
+  if (index < 0)
+    return false;
+
+  /* Check $fp/$gp/$lp one by one.
+     We use 'push_p' to pick up reg rtx and mem rtx.  */
+  if (cfun->machine->fp_size)
+    {
+      elt = XVECEXP (op, 0, index);
+      elt_mem = push_p ? SET_DEST (elt) : SET_SRC (elt);
+      elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
+      index++;
+
+      if (GET_CODE (elt_mem) != MEM
+          || GET_CODE (elt_reg) != REG
+          || REGNO (elt_reg) != FP_REGNUM)
+        return false;
+    }
+  if (cfun->machine->gp_size)
+    {
+      elt = XVECEXP (op, 0, index);
+      elt_mem = push_p ? SET_DEST (elt) : SET_SRC (elt);
+      elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
+      index++;
+
+      if (GET_CODE (elt_mem) != MEM
+          || GET_CODE (elt_reg) != REG
+          || REGNO (elt_reg) != GP_REGNUM)
+        return false;
+    }
+  if (cfun->machine->lp_size)
+    {
+      elt = XVECEXP (op, 0, index);
+      elt_mem = push_p ? SET_DEST (elt) : SET_SRC (elt);
+      elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
+      index++;
+
+      if (GET_CODE (elt_mem) != MEM
+          || GET_CODE (elt_reg) != REG
+          || REGNO (elt_reg) != LP_REGNUM)
+        return false;
+    }
+
+  /* 3. The last element must be stack adjustment rtx.
+        Its form of rtx should be:
+          (set (reg:SI SP_REGNUM)
+               (plus (reg:SI SP_REGNUM) (const_int X)))
+        The X could be positive or negative value.  */
+
+  /* Pick up the last element.  */
+  elt = XVECEXP (op, 0, total_count - 1);
+
+  /* Extract its destination and source rtx.  */
+  elt_reg  = SET_DEST (elt);
+  elt_plus = SET_SRC (elt);
+
+  /* Check this is (set (stack_reg) (plus stack_reg const)) pattern.  */
+  if (GET_CODE (elt_reg) != REG
+      || GET_CODE (elt_plus) != PLUS
+      || REGNO (elt_reg) != SP_REGNUM)
+    return false;
+
+  /* Pass all test, this is a valid rtx.  */
+  return true;
+}
+
+/* Computing the Length of an Insn.
+   Modifies the length assigned to instruction INSN.
+   LEN is the initially computed length of the insn.  */
+int
+nds32_adjust_insn_length (rtx insn, int length)
+{
+  rtx src, dst;
+
+  switch (recog_memoized (insn))
+    {
+    case CODE_FOR_move_df:
+    case CODE_FOR_move_di:
+      /* Adjust length of movd44 to 2.  */
+      src = XEXP (PATTERN (insn), 1);
+      dst = XEXP (PATTERN (insn), 0);
+
+      if (REG_P (src)
+	  && REG_P (dst)
+	  && (REGNO (src) % 2) == 0
+	  && (REGNO (dst) % 2) == 0)
+	length = 2;
+      break;
+
+    default:
+      break;
+    }
+
+  return length;
+}
+
+
+/* Function to check if 'bclr' instruction can be used with IVAL.  */
+int
+nds32_can_use_bclr_p (int ival)
+{
+  int one_bit_count;
+
+  /* Calculate the number of 1-bit of (~ival), if there is only one 1-bit,
+     it means the original ival has only one 0-bit,
+     So it is ok to perform 'bclr' operation.  */
+
+  one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (~ival));
+
+  /* 'bclr' is a performance extension instruction.  */
+  return (TARGET_PERF_EXT && (one_bit_count == 1));
+}
+
+/* Function to check if 'bset' instruction can be used with IVAL.  */
+int
+nds32_can_use_bset_p (int ival)
+{
+  int one_bit_count;
+
+  /* Caculate the number of 1-bit of ival, if there is only one 1-bit,
+     it is ok to perform 'bset' operation.  */
+
+  one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (ival));
+
+  /* 'bset' is a performance extension instruction.  */
+  return (TARGET_PERF_EXT && (one_bit_count == 1));
+}
+
+/* Function to check if 'btgl' instruction can be used with IVAL.  */
+int
+nds32_can_use_btgl_p (int ival)
+{
+  int one_bit_count;
+
+  /* Caculate the number of 1-bit of ival, if there is only one 1-bit,
+     it is ok to perform 'btgl' operation.  */
+
+  one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (ival));
+
+  /* 'btgl' is a performance extension instruction.  */
+  return (TARGET_PERF_EXT && (one_bit_count == 1));
+}
+
+/* Function to check if 'bitci' instruction can be used with IVAL.  */
+int
+nds32_can_use_bitci_p (int ival)
+{
+  /* If we are using V3 ISA, we have 'bitci' instruction.
+     Try to see if we can present 'andi' semantic with
+     such 'bit-clear-immediate' operation.
+     For example, 'andi $r0,$r0,0xfffffffc' can be
+     presented with 'bitci $r0,$r0,3'.  */
+  return (TARGET_ISA_V3
+	  && (ival < 0)
+	  && satisfies_constraint_Iu15 (gen_int_mode (~ival, SImode)));
+}
+
+
+/* Return true if is load/store with SYMBOL_REF addressing mode
+   and memory mode is SImode.  */
+bool
+nds32_symbol_load_store_p (rtx insn)
+{
+  rtx mem_src = NULL_RTX;
+
+  switch (get_attr_type (insn))
+    {
+    case TYPE_LOAD:
+      mem_src = SET_SRC (PATTERN (insn));
+      break;
+    case TYPE_STORE:
+      mem_src = SET_DEST (PATTERN (insn));
+      break;
+    default:
+      break;
+    }
+
+  /* Find load/store insn with addressing mode is SYMBOL_REF.  */
+  if (mem_src != NULL_RTX)
+    {
+      if ((GET_CODE (mem_src) == ZERO_EXTEND)
+	  || (GET_CODE (mem_src) == SIGN_EXTEND))
+	mem_src = XEXP (mem_src, 0);
+
+      if ((GET_CODE (XEXP (mem_src, 0)) == SYMBOL_REF)
+	   || (GET_CODE (XEXP (mem_src, 0)) == LO_SUM))
+	return true;
+    }
+
+  return false;
+}
+
+/* Function to determine whether it is worth to do fp_as_gp optimization.
+   Return 0: It is NOT worth to do fp_as_gp optimization.
+   Return 1: It is APPROXIMATELY worth to do fp_as_gp optimization.
+   Note that if it is worth to do fp_as_gp optimization,
+   we MUST set FP_REGNUM ever live in this function.  */
+int
+nds32_fp_as_gp_check_available (void)
+{
+  /* If there exists ANY of following conditions,
+     we DO NOT perform fp_as_gp optimization:
+       1. TARGET_FORBID_FP_AS_GP is set
+          regardless of the TARGET_FORCE_FP_AS_GP.
+       2. User explicitly uses 'naked' attribute.
+       3. Not optimize for size.
+       4. Need frame pointer.
+       5. If $fp is already required to be saved,
+          it means $fp is already choosen by register allocator.
+          Thus we better not to use it for fp_as_gp optimization.
+       6. This function is a vararg function.
+          DO NOT apply fp_as_gp optimization on this function
+          because it may change and break stack frame.
+       7. The epilogue is empty.
+          This happens when the function uses exit()
+          or its attribute is no_return.
+          In that case, compiler will not expand epilogue
+          so that we have no chance to output .omit_fp_end directive.  */
+  if (TARGET_FORBID_FP_AS_GP
+      || lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl))
+      || !optimize_size
+      || frame_pointer_needed
+      || NDS32_REQUIRED_CALLEE_SAVED_P (FP_REGNUM)
+      || (cfun->stdarg == 1)
+      || (find_fallthru_edge (EXIT_BLOCK_PTR->preds) == NULL))
+    return 0;
+
+  /* Now we can check the possibility of using fp_as_gp optimization.  */
+  if (TARGET_FORCE_FP_AS_GP)
+    {
+      /* User explicitly issues -mforce-fp-as-gp option.  */
+      df_set_regs_ever_live (FP_REGNUM, 1);
+      return 1;
+    }
+  else
+    {
+      /* In the following we are going to evaluate whether
+         it is worth to do fp_as_gp optimization.  */
+      int good_gain     = 0;
+      int symbol_count  = 0;
+
+      int threshold;
+      rtx insn;
+
+      /* We check if there already requires prologue.
+         Note that $gp will be saved in prologue for PIC code generation.
+         After that, we can set threshold by the existence of prologue.
+         Each fp-implied instruction will gain 2-byte code size
+         from gp-aware instruction, so we have following heuristics.  */
+      if (flag_pic
+	  || nds32_have_prologue_p ())
+	{
+	  /* Have-prologue:
+	       Compiler already intends to generate prologue content,
+	       so the fp_as_gp optimization will only insert
+	       'la $fp,_FP_BASE_' instruction, which will be
+	       converted into 4-byte instruction at link time.
+	       The threshold is "3" symbol accesses, 2 + 2 + 2 > 4.  */
+	  threshold = 3;
+	}
+      else
+	{
+	  /* None-prologue:
+	       Compiler originally does not generate prologue content,
+	       so the fp_as_gp optimization will NOT ONLY insert
+	       'la $fp,_FP_BASE' instruction, but also causes
+	       push/pop instructions.
+	       If we are using v3push (push25/pop25),
+	       the threshold is "5" symbol accesses, 5*2 > 4 + 2 + 2;
+	       If we are using normal push (smw/lmw),
+	       the threshold is "5+2" symbol accesses 7*2 > 4 + 4 + 4.  */
+	  threshold = 5 + (TARGET_V3PUSH ? 0 : 2);
+	}
+
+      /* We would like to traverse every instruction in this function.
+         So we need to have push_topmost_sequence()/pop_topmost_sequence()
+         surrounding our for-loop evaluation.  */
+      push_topmost_sequence ();
+      /* Counting the insn number which the addressing mode is symbol.  */
+      for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
+	{
+	  if (single_set (insn) && nds32_symbol_load_store_p (insn))
+	    symbol_count++;
+
+	  if (symbol_count == threshold)
+	    {
+	      good_gain = 1;
+	      break;
+	    }
+	}
+      pop_topmost_sequence ();
+
+      /* Enable fp_as_gp optimization when potential gain is good enough.  */
+      if (good_gain)
+	{
+	  df_set_regs_ever_live (FP_REGNUM, 1);
+	  return 1;
+	}
+    }
+
+  /* By default we return 0.  */
+  return 0;
+}
+
+
+/* Function to generate PC relative jump table.
+   Refer to nds32.md for more details.
+
+   The following is the sample for the case that diff value
+   can be presented in '.short' size.
+
+     addi    $r1, $r1, -(case_lower_bound)
+     slti    $ta, $r1, (case_number)
+     beqz    $ta, .L_skip_label
+
+     la      $ta, .L35             ! get jump table address
+     lh      $r1, [$ta + $r1 << 1] ! load symbol diff from jump table entry
+     addi    $ta, $r1, $ta
+     jr5     $ta
+
+     ! jump table entry
+   L35:
+     .short  .L25-.L35
+     .short  .L26-.L35
+     .short  .L27-.L35
+     .short  .L28-.L35
+     .short  .L29-.L35
+     .short  .L30-.L35
+     .short  .L31-.L35
+     .short  .L32-.L35
+     .short  .L33-.L35
+     .short  .L34-.L35 */
+const char *
+nds32_output_casesi_pc_relative (rtx *operands)
+{
+  enum machine_mode mode;
+  rtx diff_vec;
+
+  diff_vec = PATTERN (next_active_insn (operands[1]));
+
+  gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
+
+  /* Step C: "t <-- operands[1]".  */
+  output_asm_insn ("la\t$ta, %l1", operands);
+
+  /* Get the mode of each element in the difference vector.  */
+  mode = GET_MODE (diff_vec);
+
+  /* Step D: "z <-- (mem (plus (operands[0] << m) t))",
+     where m is 0, 1, or 2 to load address-diff value from table.  */
+  switch (mode)
+    {
+    case QImode:
+      output_asm_insn ("lb\t%2, [$ta + %0 << 0]", operands);
+      break;
+    case HImode:
+      output_asm_insn ("lh\t%2, [$ta + %0 << 1]", operands);
+      break;
+    case SImode:
+      output_asm_insn ("lw\t%2, [$ta + %0 << 2]", operands);
+      break;
+    default:
+      gcc_unreachable ();
+    }
+
+  /* Step E: "t <-- z + t".
+     Add table label_ref with address-diff value to
+     obtain target case address.  */
+  output_asm_insn ("add\t$ta, %2, $ta", operands);
+
+  /* Step F: jump to target with register t.  */
+  if (TARGET_16_BIT)
+    return "jr5\t$ta";
+  else
+    return "jr\t$ta";
+}
+
+/* Function to generate normal jump table.  */
+const char *
+nds32_output_casesi (rtx *operands)
+{
+  /* Step C: "t <-- operands[1]".  */
+  output_asm_insn ("la\t$ta, %l1", operands);
+
+  /* Step D: "z <-- (mem (plus (operands[0] << 2) t))".  */
+  output_asm_insn ("lw\t%2, [$ta + %0 << 2]", operands);
+
+  /* No need to perform Step E, which is only used for
+     pc relative jump table.  */
+
+  /* Step F: jump to target with register z.  */
+  if (TARGET_16_BIT)
+    return "jr5\t%2";
+  else
+    return "jr\t%2";
+}
+
+
+/* Function to return memory format.  */
+enum nds32_16bit_address_type
+nds32_mem_format (rtx op)
+{
+  enum machine_mode mode_test;
+  int val;
+  int regno;
+
+  if (!TARGET_16_BIT)
+    return ADDRESS_NOT_16BIT_FORMAT;
+
+  mode_test = GET_MODE (op);
+
+  op = XEXP (op, 0);
+
+  /* 45 format.  */
+  if (GET_CODE (op) == REG && (mode_test == SImode))
+    return ADDRESS_REG;
+
+  /* 333 format for QI/HImode.  */
+  if (GET_CODE (op) == REG && (REGNO (op) < R8_REGNUM))
+    return ADDRESS_LO_REG_IMM3U;
+
+  /* post_inc 333 format.  */
+  if ((GET_CODE (op) == POST_INC) && (mode_test == SImode))
+    {
+      regno = REGNO(XEXP (op, 0));
+
+      if (regno < 8)
+	return ADDRESS_POST_INC_LO_REG_IMM3U;
+    }
+
+  /* post_inc 333 format.  */
+  if ((GET_CODE (op) == POST_MODIFY)
+      && (mode_test == SImode)
+      && (REG_P (XEXP (XEXP (op, 1), 0)))
+      && (CONST_INT_P (XEXP (XEXP (op, 1), 1))))
+    {
+      regno = REGNO (XEXP (XEXP (op, 1), 0));
+      val = INTVAL (XEXP (XEXP (op, 1), 1));
+      if (regno < 8 && val < 32)
+	return ADDRESS_POST_INC_LO_REG_IMM3U;
+    }
+
+  if ((GET_CODE (op) == PLUS)
+      && (GET_CODE (XEXP (op, 0)) == REG)
+      && (GET_CODE (XEXP (op, 1)) == CONST_INT))
+    {
+      val = INTVAL (XEXP (op, 1));
+
+      regno = REGNO(XEXP (op, 0));
+
+      if (regno > 7
+	  && regno != SP_REGNUM
+	  && regno != FP_REGNUM)
+	return ADDRESS_NOT_16BIT_FORMAT;
+
+      switch (mode_test)
+	{
+	case QImode:
+	  /* 333 format.  */
+	  if (val >= 0 && val < 8 && regno < 8)
+	    return ADDRESS_LO_REG_IMM3U;
+	  break;
+
+	case HImode:
+	  /* 333 format.  */
+	  if (val >= 0 && val < 16 && (val % 2 == 0) && regno < 8)
+	    return ADDRESS_LO_REG_IMM3U;
+	  break;
+
+	case SImode:
+	case SFmode:
+	case DFmode:
+	  /* fp imply 37 format.  */
+	  if ((regno == FP_REGNUM) &&
+	      (val >= 0 && val < 512 && (val % 4 == 0)))
+	    return ADDRESS_FP_IMM7U;
+	  /* sp imply 37 format.  */
+	  else if ((regno == SP_REGNUM) &&
+		   (val >= 0 && val < 512 && (val % 4 == 0)))
+	    return ADDRESS_SP_IMM7U;
+	  /* 333 format.  */
+	  else if (val >= 0 && val < 32 && (val % 4 == 0) && regno < 8)
+	    return ADDRESS_LO_REG_IMM3U;
+	  break;
+
+	default:
+	  break;
+	}
+    }
+
+  return ADDRESS_NOT_16BIT_FORMAT;
+}
+
+/* Output 16-bit store.  */
+const char *
+nds32_output_16bit_store (rtx *operands, int byte)
+{
+  char pattern[100];
+  char size;
+  rtx code = XEXP (operands[0], 0);
+
+  size = nds32_byte_to_size (byte);
+
+  switch (nds32_mem_format (operands[0]))
+    {
+    case ADDRESS_REG:
+      operands[0] = code;
+      output_asm_insn ("swi450\t%1, [%0]", operands);
+      break;
+    case ADDRESS_LO_REG_IMM3U:
+      snprintf (pattern, sizeof (pattern), "s%ci333\t%%1, %%0", size);
+      output_asm_insn (pattern, operands);
+      break;
+    case ADDRESS_POST_INC_LO_REG_IMM3U:
+      snprintf (pattern, sizeof (pattern), "s%ci333.bi\t%%1, %%0", size);
+      output_asm_insn (pattern, operands);
+      break;
+    case ADDRESS_FP_IMM7U:
+      output_asm_insn ("swi37\t%1, %0", operands);
+      break;
+    case ADDRESS_SP_IMM7U:
+      /* Get immediate value and set back to operands[1].  */
+      operands[0] = XEXP (code, 1);
+      output_asm_insn ("swi37.sp\t%1, [ + (%0)]", operands);
+      break;
+    default:
+      break;
+    }
+
+  return "";
+}
+
+/* Output 16-bit load.  */
+const char *
+nds32_output_16bit_load (rtx *operands, int byte)
+{
+  char pattern[100];
+  unsigned char size;
+  rtx code = XEXP (operands[1], 0);
+
+  size = nds32_byte_to_size (byte);
+
+  switch (nds32_mem_format (operands[1]))
+    {
+    case ADDRESS_REG:
+      operands[1] = code;
+      output_asm_insn ("lwi450\t%0, [%1]", operands);
+      break;
+    case ADDRESS_LO_REG_IMM3U:
+      snprintf (pattern, sizeof (pattern), "l%ci333\t%%0, %%1", size);
+      output_asm_insn (pattern, operands);
+      break;
+    case ADDRESS_POST_INC_LO_REG_IMM3U:
+      snprintf (pattern, sizeof (pattern), "l%ci333.bi\t%%0, %%1", size);
+      output_asm_insn (pattern, operands);
+      break;
+    case ADDRESS_FP_IMM7U:
+      output_asm_insn ("lwi37\t%0, %1", operands);
+      break;
+    case ADDRESS_SP_IMM7U:
+      /* Get immediate value and set back to operands[0].  */
+      operands[1] = XEXP (code, 1);
+      output_asm_insn ("lwi37.sp\t%0, [ + (%1)]", operands);
+      break;
+    default:
+      break;
+    }
+
+  return "";
+}
+
+/* Output 32-bit store.  */
+const char *
+nds32_output_32bit_store (rtx *operands, int byte)
+{
+  char pattern[100];
+  unsigned char size;
+  rtx code = XEXP (operands[0], 0);
+
+  size = nds32_byte_to_size (byte);
+
+  switch (GET_CODE (code))
+    {
+    case REG:
+      /* (mem (reg X))
+	 => access location by using register,
+	 use "sbi / shi / swi" */
+      snprintf (pattern, sizeof (pattern), "s%ci\t%%1, %%0", size);
+      break;
+
+    case SYMBOL_REF:
+    case CONST:
+      /* (mem (symbol_ref X))
+	 (mem (const (...)))
+	 => access global variables,
+	 use "sbi.gp / shi.gp / swi.gp" */
+      operands[0] = XEXP (operands[0], 0);
+      snprintf (pattern, sizeof (pattern), "s%ci.gp\t%%1, [ + %%0]", size);
+      break;
+
+    case POST_INC:
+      /* (mem (post_inc reg))
+	 => access location by using register which will be post increment,
+	 use "sbi.bi / shi.bi / swi.bi" */
+      snprintf (pattern, sizeof (pattern),
+		"s%ci.bi\t%%1, %%0, %d", size, byte);
+      break;
+
+    case POST_DEC:
+      /* (mem (post_dec reg))
+	 => access location by using register which will be post decrement,
+	 use "sbi.bi / shi.bi / swi.bi" */
+      snprintf (pattern, sizeof (pattern),
+		"s%ci.bi\t%%1, %%0, -%d", size, byte);
+      break;
+
+    case POST_MODIFY:
+      switch (GET_CODE (XEXP (XEXP (code, 1), 1)))
+	{
+	case REG:
+	case SUBREG:
+	  /* (mem (post_modify (reg) (plus (reg) (reg))))
+	     => access location by using register which will be
+	     post modified with reg,
+	     use "sb.bi/ sh.bi / sw.bi" */
+	  snprintf (pattern, sizeof (pattern), "s%c.bi\t%%1, %%0", size);
+	  break;
+	case CONST_INT:
+	  /* (mem (post_modify (reg) (plus (reg) (const_int))))
+	     => access location by using register which will be
+	     post modified with const_int,
+	     use "sbi.bi/ shi.bi / swi.bi" */
+	  snprintf (pattern, sizeof (pattern), "s%ci.bi\t%%1, %%0", size);
+	  break;
+	default:
+	  abort ();
+	}
+      break;
+
+    case PLUS:
+      switch (GET_CODE (XEXP (code, 1)))
+	{
+	case REG:
+	case SUBREG:
+	  /* (mem (plus reg reg)) or (mem (plus (mult reg const_int) reg))
+	     => access location by adding two registers,
+	     use "sb / sh / sw" */
+	  snprintf (pattern, sizeof (pattern), "s%c\t%%1, %%0", size);
+	  break;
+	case CONST_INT:
+	  /* (mem (plus reg const_int))
+	     => access location by adding one register with const_int,
+	     use "sbi / shi / swi" */
+	  snprintf (pattern, sizeof (pattern), "s%ci\t%%1, %%0", size);
+	  break;
+	default:
+	  abort ();
+	}
+      break;
+
+    case LO_SUM:
+      operands[2] = XEXP (code, 1);
+      operands[0] = XEXP (code, 0);
+      snprintf (pattern, sizeof (pattern),
+		"s%ci\t%%1, [%%0 + lo12(%%2)]", size);
+      break;
+
+    default:
+      abort ();
+    }
+
+  output_asm_insn (pattern, operands);
+  return "";
+}
+
+/* Output 32-bit load.  */
+const char *
+nds32_output_32bit_load (rtx *operands, int byte)
+{
+  char pattern[100];
+  unsigned char size;
+  rtx code;
+
+  code = XEXP (operands[1], 0);
+
+  size = nds32_byte_to_size (byte);
+
+  switch (GET_CODE (code))
+    {
+    case REG:
+      /* (mem (reg X))
+	 => access location by using register,
+	 use "lbi / lhi / lwi" */
+      snprintf (pattern, sizeof (pattern), "l%ci\t%%0, %%1", size);
+      break;
+
+    case SYMBOL_REF:
+    case CONST:
+      /* (mem (symbol_ref X))
+	 (mem (const (...)))
+	 => access global variables,
+	 use "lbi.gp / lhi.gp / lwi.gp" */
+      operands[1] = XEXP (operands[1], 0);
+      snprintf (pattern, sizeof (pattern), "l%ci.gp\t%%0, [ + %%1]", size);
+      break;
+
+    case POST_INC:
+      /* (mem (post_inc reg))
+	 => access location by using register which will be post increment,
+	 use "lbi.bi / lhi.bi / lwi.bi" */
+      snprintf (pattern, sizeof (pattern),
+		"l%ci.bi\t%%0, %%1, %d", size, byte);
+      break;
+
+    case POST_DEC:
+      /* (mem (post_dec reg))
+	 => access location by using register which will be post decrement,
+	 use "lbi.bi / lhi.bi / lwi.bi" */
+      snprintf (pattern, sizeof (pattern),
+		"l%ci.bi\t%%0, %%1, -%d", size, byte);
+      break;
+
+    case POST_MODIFY:
+      switch (GET_CODE (XEXP (XEXP (code, 1), 1)))
+	{
+	case REG:
+	case SUBREG:
+	  /* (mem (post_modify (reg) (plus (reg) (reg))))
+	     => access location by using register which will be
+	     post modified with reg,
+	     use "lb.bi/ lh.bi / lw.bi" */
+	  snprintf (pattern, sizeof (pattern), "l%c.bi\t%%0, %%1", size);
+	  break;
+	case CONST_INT:
+	  /* (mem (post_modify (reg) (plus (reg) (const_int))))
+	     => access location by using register which will be
+	     post modified with const_int,
+	     use "lbi.bi/ lhi.bi / lwi.bi" */
+	  snprintf (pattern, sizeof (pattern), "l%ci.bi\t%%0, %%1", size);
+	  break;
+	default:
+	  abort ();
+	}
+      break;
+
+    case PLUS:
+      switch (GET_CODE (XEXP (code, 1)))
+	{
+	case REG:
+	case SUBREG:
+	  /* (mem (plus reg reg)) or (mem (plus (mult reg const_int) reg))
+	     use "lb / lh / lw" */
+	  snprintf (pattern, sizeof (pattern), "l%c\t%%0, %%1", size);
+	  break;
+	case CONST_INT:
+	  /* (mem (plus reg const_int))
+	     => access location by adding one register with const_int,
+	     use "lbi / lhi / lwi" */
+	  snprintf (pattern, sizeof (pattern), "l%ci\t%%0, %%1", size);
+	  break;
+	default:
+	  abort ();
+	}
+      break;
+
+    case LO_SUM:
+      operands[2] = XEXP (code, 1);
+      operands[1] = XEXP (code, 0);
+      snprintf (pattern, sizeof (pattern),
+		"l%ci\t%%0, [%%1 + lo12(%%2)]", size);
+      break;
+
+    default:
+      abort ();
+    }
+
+  output_asm_insn (pattern, operands);
+  return "";
+}
+
+/* Output 32-bit load with signed extension.  */
+const char *
+nds32_output_32bit_load_s (rtx *operands, int byte)
+{
+  char pattern[100];
+  unsigned char size;
+  rtx code;
+
+  code = XEXP (operands[1], 0);
+
+  size = nds32_byte_to_size (byte);
+
+  switch (GET_CODE (code))
+    {
+    case REG:
+      /* (mem (reg X))
+         => access location by using register,
+         use "lbsi / lhsi" */
+      snprintf (pattern, sizeof (pattern), "l%csi\t%%0, %%1", size);
+      break;
+
+    case SYMBOL_REF:
+    case CONST:
+      /* (mem (symbol_ref X))
+         (mem (const (...)))
+         => access global variables,
+         use "lbsi.gp / lhsi.gp" */
+      operands[1] = XEXP (operands[1], 0);
+      snprintf (pattern, sizeof (pattern), "l%csi.gp\t%%0, [ + %%1]", size);
+      break;
+
+    case POST_INC:
+      /* (mem (post_inc reg))
+         => access location by using register which will be post increment,
+         use "lbsi.bi / lhsi.bi" */
+      snprintf (pattern, sizeof (pattern),
+		"l%csi.bi\t%%0, %%1, %d", size, byte);
+      break;
+
+    case POST_DEC:
+      /* (mem (post_dec reg))
+         => access location by using register which will be post decrement,
+         use "lbsi.bi / lhsi.bi" */
+      snprintf (pattern, sizeof (pattern),
+		"l%csi.bi\t%%0, %%1, -%d", size, byte);
+      break;
+
+    case POST_MODIFY:
+      switch (GET_CODE (XEXP (XEXP (code, 1), 1)))
+	{
+	case REG:
+	case SUBREG:
+	  /* (mem (post_modify (reg) (plus (reg) (reg))))
+	     => access location by using register which will be
+	     post modified with reg,
+	     use "lbs.bi/ lhs.bi" */
+	  snprintf (pattern, sizeof (pattern), "l%cs.bi\t%%0, %%1", size);
+	  break;
+	case CONST_INT:
+	  /* (mem (post_modify (reg) (plus (reg) (const_int))))
+	     => access location by using register which will be
+	     post modified with const_int,
+	     use "lbsi.bi/ lhsi.bi" */
+	  snprintf (pattern, sizeof (pattern), "l%csi.bi\t%%0, %%1", size);
+	  break;
+	default:
+	  abort ();
+	}
+      break;
+
+    case PLUS:
+      switch (GET_CODE (XEXP (code, 1)))
+	{
+	case REG:
+	case SUBREG:
+	  /* (mem (plus reg reg)) or (mem (plus (mult reg const_int) reg))
+	     use "lbs / lhs" */
+	  snprintf (pattern, sizeof (pattern), "l%cs\t%%0, %%1", size);
+	  break;
+	case CONST_INT:
+	  /* (mem (plus reg const_int))
+	     => access location by adding one register with const_int,
+	     use "lbsi / lhsi" */
+	  snprintf (pattern, sizeof (pattern), "l%csi\t%%0, %%1", size);
+	  break;
+	default:
+	  abort ();
+	}
+      break;
+
+    case LO_SUM:
+      operands[2] = XEXP (code, 1);
+      operands[1] = XEXP (code, 0);
+      snprintf (pattern, sizeof (pattern),
+		"l%csi\t%%0, [%%1 + lo12(%%2)]", size);
+      break;
+
+    default:
+      abort ();
+    }
+
+  output_asm_insn (pattern, operands);
+  return "";
+}
+
+/* Function to output stack push operation.
+   We need to deal with normal stack push multiple or stack v3push.  */
+const char *
+nds32_output_stack_push (void)
+{
+  /* A string pattern for output_asm_insn().  */
+  char pattern[100];
+  /* The operands array which will be used in output_asm_insn().  */
+  rtx operands[3];
+  /* Pick up callee-saved first regno and last regno for further use.  */
+  int rb_regno = cfun->machine->callee_saved_regs_first_regno;
+  int re_regno = cfun->machine->callee_saved_regs_last_regno;
+
+  if (TARGET_V3PUSH)
+    {
+      /* For stack v3push:
+           operands[0]: Re
+           operands[1]: imm8u */
+
+      /* This variable is to check if 'push25 Re,imm8u' is available.  */
+      int sp_adjust;
+
+      /* Set operands[0].  */
+      operands[0] = gen_rtx_REG (SImode, re_regno);
+
+      /* Check if we can generate 'push25 Re,imm8u',
+         otherwise, generate 'push25 Re,0'.  */
+      sp_adjust = cfun->machine->local_size
+		  + cfun->machine->out_args_size
+		  + cfun->machine->callee_saved_area_padding_bytes;
+      if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust))
+	  && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust))
+	operands[1] = GEN_INT (sp_adjust);
+      else
+	operands[1] = GEN_INT (0);
+
+      /* Create assembly code pattern.  */
+      snprintf (pattern, sizeof (pattern), "push25\t%%0, %%1");
+    }
+  else
+    {
+      /* For normal stack push multiple:
+         operands[0]: Rb
+         operands[1]: Re
+         operands[2]: En4 */
+
+      /* This variable is used to check if we only need to generate En4 field.
+         As long as Rb==Re=SP_REGNUM, we set this variable to 1.  */
+      int push_en4_only_p = 0;
+
+      /* Set operands[0] and operands[1].  */
+      operands[0] = gen_rtx_REG (SImode, rb_regno);
+      operands[1] = gen_rtx_REG (SImode, re_regno);
+
+      /* 'smw.adm $sp,[$sp],$sp,0' means push nothing.  */
+      if (!cfun->machine->fp_size
+	  && !cfun->machine->gp_size
+	  && !cfun->machine->lp_size
+	  && REGNO (operands[0]) == SP_REGNUM
+	  && REGNO (operands[1]) == SP_REGNUM)
+	{
+	  /* No need to generate instruction.  */
+	  return "";
+	}
+      else
+	{
+	  /* If Rb==Re=SP_REGNUM, we only need to generate En4 field.  */
+	  if (REGNO (operands[0]) == SP_REGNUM
+	      && REGNO (operands[1]) == SP_REGNUM)
+	    push_en4_only_p = 1;
+
+	  /* Create assembly code pattern.
+	     We need to handle the form: "Rb, Re, { $fp $gp $lp }".  */
+	  snprintf (pattern, sizeof (pattern),
+		    "push.s\t%s{%s%s%s }",
+		    push_en4_only_p ? "" : "%0, %1, ",
+		    cfun->machine->fp_size ? " $fp" : "",
+		    cfun->machine->gp_size ? " $gp" : "",
+		    cfun->machine->lp_size ? " $lp" : "");
+	}
+    }
+
+  /* We use output_asm_insn() to output assembly code by ourself.  */
+  output_asm_insn (pattern, operands);
+  return "";
+}
+
+/* Function to output stack pop operation.
+   We need to deal with normal stack pop multiple or stack v3pop.  */
+const char *
+nds32_output_stack_pop (void)
+{
+  /* A string pattern for output_asm_insn().  */
+  char pattern[100];
+  /* The operands array which will be used in output_asm_insn().  */
+  rtx operands[3];
+  /* Pick up callee-saved first regno and last regno for further use.  */
+  int rb_regno = cfun->machine->callee_saved_regs_first_regno;
+  int re_regno = cfun->machine->callee_saved_regs_last_regno;
+
+  if (TARGET_V3PUSH)
+    {
+      /* For stack v3pop:
+           operands[0]: Re
+           operands[1]: imm8u */
+
+      /* This variable is to check if 'pop25 Re,imm8u' is available.  */
+      int sp_adjust;
+
+      /* Set operands[0].  */
+      operands[0] = gen_rtx_REG (SImode, re_regno);
+
+      /* Check if we can generate 'pop25 Re,imm8u',
+         otherwise, generate 'pop25 Re,0'.
+         We have to consider alloca issue as well.
+         If the function does call alloca(), the stack pointer is not fixed.
+         In that case, we cannot use 'pop25 Re,imm8u' directly.
+         We have to caculate stack pointer from frame pointer
+         and then use 'pop25 Re,0'.  */
+      sp_adjust = cfun->machine->local_size
+		  + cfun->machine->out_args_size
+		  + cfun->machine->callee_saved_area_padding_bytes;
+      if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust))
+	  && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust)
+	  && !cfun->calls_alloca)
+	operands[1] = GEN_INT (sp_adjust);
+      else
+	operands[1] = GEN_INT (0);
+
+      /* Create assembly code pattern.  */
+      snprintf (pattern, sizeof (pattern), "pop25\t%%0, %%1");
+    }
+  else
+    {
+      /* For normal stack pop multiple:
+         operands[0]: Rb
+         operands[1]: Re
+         operands[2]: En4 */
+
+      /* This variable is used to check if we only need to generate En4 field.
+         As long as Rb==Re=SP_REGNUM, we set this variable to 1.  */
+      int pop_en4_only_p = 0;
+
+      /* Set operands[0] and operands[1].  */
+      operands[0] = gen_rtx_REG (SImode, rb_regno);
+      operands[1] = gen_rtx_REG (SImode, re_regno);
+
+      /* 'lmw.bim $sp,[$sp],$sp,0' means pop nothing.  */
+      if (!cfun->machine->fp_size
+	  && !cfun->machine->gp_size
+	  && !cfun->machine->lp_size
+	  && REGNO (operands[0]) == SP_REGNUM
+	  && REGNO (operands[1]) == SP_REGNUM)
+	{
+	  /* No need to generate instruction.  */
+	  return "";
+	}
+      else
+	{
+	  /* If Rb==Re=SP_REGNUM, we only need to generate En4 field.  */
+	  if (REGNO (operands[0]) == SP_REGNUM
+	      && REGNO (operands[1]) == SP_REGNUM)
+	    pop_en4_only_p = 1;
+
+	  /* Create assembly code pattern.
+	     We need to handle the form: "Rb, Re, { $fp $gp $lp }".  */
+	  snprintf (pattern, sizeof (pattern),
+		    "pop.s\t%s{%s%s%s }",
+		    pop_en4_only_p ? "" : "%0, %1, ",
+		    cfun->machine->fp_size ? " $fp" : "",
+		    cfun->machine->gp_size ? " $gp" : "",
+		    cfun->machine->lp_size ? " $lp" : "");
+	}
+    }
+
+  /* We use output_asm_insn() to output assembly code by ourself.  */
+  output_asm_insn (pattern, operands);
+  return "";
+}
+
+/* Return align 2 (log base 2) if the next instruction of LABEL is 4 byte.  */
+int
+nds32_target_alignment (rtx label)
+{
+  rtx insn;
+
+  if (optimize_size)
+    return 0;
+
+  insn = next_active_insn (label);
+
+  if (insn == 0)
+    return 0;
+  else if ((get_attr_length (insn) % 4) == 0)
+    return 2;
+  else
+    return 0;
+}
+
+/* ------------------------------------------------------------------------ */
+
+/* PART 5: Initialize target hook structure and definitions.  */
+
+/* Controlling the Compilation Driver.  */
+
+
+/* Run-time Target Specification.  */
+
+
+/* Defining Data Structures for Per-function Information.  */
+
+
+/* Storage Layout.  */
+
+#undef TARGET_PROMOTE_FUNCTION_MODE
+#define TARGET_PROMOTE_FUNCTION_MODE \
+  default_promote_function_mode_always_promote
+
+
+/* Layout of Source Language Data Types.  */
+
+
+/* Register Usage.  */
+
+/* -- Basic Characteristics of Registers.  */
+
+/* -- Order of Allocation of Registers.  */
+
+/* -- How Values Fit in Registers.  */
+
+/* -- Handling Leaf Functions.  */
+
+/* -- Registers That Form a Stack.  */
+
+
+/* Register Classes.  */
+
+#undef TARGET_CLASS_MAX_NREGS
+#define TARGET_CLASS_MAX_NREGS nds32_class_max_nregs
+
+#undef TARGET_LRA_P
+#define TARGET_LRA_P hook_bool_void_true
+
+#undef TARGET_REGISTER_PRIORITY
+#define TARGET_REGISTER_PRIORITY nds32_register_priority
+
+
+/* Obsolete Macros for Defining Constraints.  */
+
+
+/* Stack Layout and Calling Conventions.  */
+
+/* -- Basic Stack Layout.  */
+
+/* -- Exception Handling Support.  */
+
+/* -- Specifying How Stack Checking is Done.  */
+
+/* -- Registers That Address the Stack Frame.  */
+
+/* -- Eliminating Frame Pointer and Arg Pointer.  */
+
+#undef TARGET_CAN_ELIMINATE
+#define TARGET_CAN_ELIMINATE nds32_can_eliminate
+
+/* -- Passing Function Arguments on the Stack.  */
+
+/* -- Passing Arguments in Registers.  */
+
+#undef TARGET_FUNCTION_ARG
+#define TARGET_FUNCTION_ARG nds32_function_arg
+
+#undef TARGET_FUNCTION_ARG_ADVANCE
+#define TARGET_FUNCTION_ARG_ADVANCE nds32_function_arg_advance
+
+#undef TARGET_FUNCTION_ARG_BOUNDARY
+#define TARGET_FUNCTION_ARG_BOUNDARY nds32_function_arg_boundary
+
+/* -- How Scalar Function Values Are Returned.  */
+
+#undef TARGET_FUNCTION_VALUE
+#define TARGET_FUNCTION_VALUE nds32_function_value
+
+#undef TARGET_LIBCALL_VALUE
+#define TARGET_LIBCALL_VALUE nds32_libcall_value
+
+#undef TARGET_FUNCTION_VALUE_REGNO_P
+#define TARGET_FUNCTION_VALUE_REGNO_P nds32_function_value_regno_p
+
+/* -- How Large Values Are Returned.  */
+
+/* -- Caller-Saves Register Allocation.  */
+
+/* -- Function Entry and Exit.  */
+
+#undef TARGET_ASM_FUNCTION_PROLOGUE
+#define TARGET_ASM_FUNCTION_PROLOGUE nds32_asm_function_prologue
+
+#undef TARGET_ASM_FUNCTION_END_PROLOGUE
+#define TARGET_ASM_FUNCTION_END_PROLOGUE nds32_asm_function_end_prologue
+
+#undef  TARGET_ASM_FUNCTION_BEGIN_EPILOGUE
+#define TARGET_ASM_FUNCTION_BEGIN_EPILOGUE nds32_asm_function_begin_epilogue
+
+#undef TARGET_ASM_FUNCTION_EPILOGUE
+#define TARGET_ASM_FUNCTION_EPILOGUE nds32_asm_function_epilogue
+
+#undef TARGET_ASM_OUTPUT_MI_THUNK
+#define TARGET_ASM_OUTPUT_MI_THUNK nds32_asm_output_mi_thunk
+
+#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
+#define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
+
+/* -- Generating Code for Profiling.  */
+
+/* -- Permitting tail calls.  */
+
+#undef TARGET_WARN_FUNC_RETURN
+#define TARGET_WARN_FUNC_RETURN nds32_warn_func_return
+
+/* Stack smashing protection.  */
+
+
+/* Implementing the Varargs Macros.  */
+
+#undef TARGET_STRICT_ARGUMENT_NAMING
+#define TARGET_STRICT_ARGUMENT_NAMING nds32_strict_argument_naming
+
+
+/* Trampolines for Nested Functions.  */
+
+#undef TARGET_ASM_TRAMPOLINE_TEMPLATE
+#define TARGET_ASM_TRAMPOLINE_TEMPLATE nds32_asm_trampoline_template
+
+#undef TARGET_TRAMPOLINE_INIT
+#define TARGET_TRAMPOLINE_INIT nds32_trampoline_init
+
+
+/* Implicit Calls to Library Routines.  */
+
+
+/* Addressing Modes.  */
+
+#undef TARGET_LEGITIMATE_ADDRESS_P
+#define TARGET_LEGITIMATE_ADDRESS_P nds32_legitimate_address_p
+
+
+/* Anchored Addresses.  */
+
+
+/* Condition Code Status.  */
+
+/* -- Representation of condition codes using (cc0).  */
+
+/* -- Representation of condition codes using registers.  */
+
+/* -- Macros to control conditional execution.  */
+
+
+/* Describing Relative Costs of Operations.  */
+
+#undef TARGET_REGISTER_MOVE_COST
+#define TARGET_REGISTER_MOVE_COST nds32_register_move_cost
+
+#undef TARGET_MEMORY_MOVE_COST
+#define TARGET_MEMORY_MOVE_COST nds32_memory_move_cost
+
+#undef TARGET_RTX_COSTS
+#define TARGET_RTX_COSTS nds32_rtx_costs
+
+#undef TARGET_ADDRESS_COST
+#define TARGET_ADDRESS_COST nds32_address_cost
+
+
+/* Adjusting the Instruction Scheduler.  */
+
+
+/* Dividing the Output into Sections (Texts, Data, . . . ).  */
+
+
+/* Position Independent Code.  */
+
+
+/* Defining the Output Assembler Language.  */
+
+/* -- The Overall Framework of an Assembler File.  */
+
+#undef TARGET_ASM_FILE_START
+#define TARGET_ASM_FILE_START nds32_asm_file_start
+#undef TARGET_ASM_FILE_END
+#define TARGET_ASM_FILE_END nds32_asm_file_end
+
+/* -- Output of Data.  */
+
+#undef TARGET_ASM_ALIGNED_HI_OP
+#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
+
+#undef TARGET_ASM_ALIGNED_SI_OP
+#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
+
+/* -- Output of Uninitialized Variables.  */
+
+/* -- Output and Generation of Labels.  */
+
+#undef TARGET_ASM_GLOBALIZE_LABEL
+#define TARGET_ASM_GLOBALIZE_LABEL nds32_asm_globalize_label
+
+/* -- How Initialization Functions Are Handled.  */
+
+/* -- Macros Controlling Initialization Routines.  */
+
+/* -- Output of Assembler Instructions.  */
+
+#undef TARGET_PRINT_OPERAND
+#define TARGET_PRINT_OPERAND nds32_print_operand
+#undef TARGET_PRINT_OPERAND_ADDRESS
+#define TARGET_PRINT_OPERAND_ADDRESS nds32_print_operand_address
+
+/* -- Output of Dispatch Tables.  */
+
+/* -- Assembler Commands for Exception Regions.  */
+
+/* -- Assembler Commands for Alignment.  */
+
+
+/* Controlling Debugging Information Format.  */
+
+/* -- Macros Affecting All Debugging Formats.  */
+
+/* -- Specific Options for DBX Output.  */
+
+/* -- Open-Ended Hooks for DBX Format.  */
+
+/* -- File Names in DBX Format.  */
+
+/* -- Macros for SDB and DWARF Output.  */
+
+/* -- Macros for VMS Debug Format.  */
+
+
+/* Cross Compilation and Floating Point.  */
+
+
+/* Mode Switching Instructions.  */
+
+
+/* Defining target-specific uses of __attribute__.  */
+
+#undef TARGET_ATTRIBUTE_TABLE
+#define TARGET_ATTRIBUTE_TABLE nds32_attribute_table
+
+#undef TARGET_MERGE_DECL_ATTRIBUTES
+#define TARGET_MERGE_DECL_ATTRIBUTES nds32_merge_decl_attributes
+
+#undef TARGET_INSERT_ATTRIBUTES
+#define TARGET_INSERT_ATTRIBUTES nds32_insert_attributes
+
+#undef TARGET_OPTION_PRAGMA_PARSE
+#define TARGET_OPTION_PRAGMA_PARSE nds32_option_pragma_parse
+
+#undef TARGET_OPTION_OVERRIDE
+#define TARGET_OPTION_OVERRIDE nds32_option_override
+
+
+/* Emulating TLS.  */
+
+
+/* Defining coprocessor specifics for MIPS targets.  */
+
+
+/* Parameters for Precompiled Header Validity Checking.  */
+
+
+/* C++ ABI parameters.  */
+
+
+/* Adding support for named address spaces.  */
+
+
+/* Miscellaneous Parameters.  */
+
+#undef TARGET_INIT_BUILTINS
+#define TARGET_INIT_BUILTINS nds32_init_builtins
+
+#undef TARGET_EXPAND_BUILTIN
+#define TARGET_EXPAND_BUILTIN nds32_expand_builtin
+
+
+/* ------------------------------------------------------------------------ */
+
+/* Initialize the GCC target structure.  */
+
+struct gcc_target targetm = TARGET_INITIALIZER;
+
+/* ------------------------------------------------------------------------ */
diff --git a/gcc/config/nds32/nds32.h b/gcc/config/nds32/nds32.h
new file mode 100644
index 00000000000..74f126cecc4
--- /dev/null
+++ b/gcc/config/nds32/nds32.h
@@ -0,0 +1,982 @@
+/* Definitions of target machine of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+
+/* ------------------------------------------------------------------------ */
+
+/* The following are auxiliary macros or structure declarations
+   that are used all over the nds32.c and nds32.h.  */
+
+
+/* Computing the Length of an Insn.  */
+#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
+  (LENGTH = nds32_adjust_insn_length (INSN, LENGTH))
+
+/* Check instruction LS-37-FP-implied form.
+   Note: actually its immediate range is imm9u
+         since it is used for lwi37/swi37 instructions.  */
+#define NDS32_LS_37_FP_P(rt, ra, imm)       \
+  (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
+   && REGNO (ra) == FP_REGNUM               \
+   && satisfies_constraint_Iu09 (imm))
+
+/* Check instruction LS-37-SP-implied form.
+   Note: actually its immediate range is imm9u
+         since it is used for lwi37/swi37 instructions.  */
+#define NDS32_LS_37_SP_P(rt, ra, imm)       \
+  (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
+   && REGNO (ra) == SP_REGNUM               \
+   && satisfies_constraint_Iu09 (imm))
+
+
+/* Check load/store instruction form : Rt3, Ra3, imm3u.  */
+#define NDS32_LS_333_P(rt, ra, imm, mode) nds32_ls_333_p (rt, ra, imm, mode)
+
+/* Check load/store instruction form : Rt4, Ra5, const_int_0.
+   Note: no need to check ra because Ra5 means it covers all registers.  */
+#define NDS32_LS_450_P(rt, ra, imm)                     \
+  ((imm == const0_rtx)                                  \
+   && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS         \
+       || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
+
+/* Check instruction RRI-333-form.  */
+#define NDS32_RRI_333_P(rt, ra, imm)           \
+  (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS    \
+   && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS \
+   && satisfies_constraint_Iu03 (imm))
+
+/* Check instruction RI-45-form.  */
+#define NDS32_RI_45_P(rt, ra, imm)                     \
+  (REGNO (rt) == REGNO (ra)                            \
+   && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS        \
+       || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS) \
+   && satisfies_constraint_Iu05 (imm))
+
+
+/* Check instruction RR-33-form.  */
+#define NDS32_RR_33_P(rt, ra)                   \
+  (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS     \
+   && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS)
+
+/* Check instruction RRR-333-form.  */
+#define NDS32_RRR_333_P(rt, ra, rb)             \
+  (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS     \
+   && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS  \
+   && REGNO_REG_CLASS (REGNO (rb)) == LOW_REGS)
+
+/* Check instruction RR-45-form.
+   Note: no need to check rb because Rb5 means it covers all registers.  */
+#define NDS32_RR_45_P(rt, ra, rb)               \
+  (REGNO (rt) == REGNO (ra)                     \
+   && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
+       || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
+
+/* Classifies address type to distinguish 16-bit/32-bit format.  */
+enum nds32_16bit_address_type
+{
+  /* [reg]: 45 format address.  */
+  ADDRESS_REG,
+  /* [lo_reg + imm3u]: 333 format address.  */
+  ADDRESS_LO_REG_IMM3U,
+  /* post_inc [lo_reg + imm3u]: 333 format address.  */
+  ADDRESS_POST_INC_LO_REG_IMM3U,
+  /* [$fp + imm7u]: fp imply address.  */
+  ADDRESS_FP_IMM7U,
+  /* [$sp + imm7u]: sp imply address.  */
+  ADDRESS_SP_IMM7U,
+  /* Other address format.  */
+  ADDRESS_NOT_16BIT_FORMAT
+};
+
+
+/* ------------------------------------------------------------------------ */
+
+/* Define maximum numbers of registers for passing arguments.  */
+#define NDS32_MAX_REGS_FOR_ARGS 6
+
+/* Define the register number for first argument.  */
+#define NDS32_GPR_ARG_FIRST_REGNUM 0
+
+/* Define the register number for return value.  */
+#define NDS32_GPR_RET_FIRST_REGNUM 0
+
+
+/* Define double word alignment bits.  */
+#define NDS32_DOUBLE_WORD_ALIGNMENT 64
+
+/* Define alignment checking macros for convenience.  */
+#define NDS32_HALF_WORD_ALIGN_P(value)   (((value) & 0x01) == 0)
+#define NDS32_SINGLE_WORD_ALIGN_P(value) (((value) & 0x03) == 0)
+#define NDS32_DOUBLE_WORD_ALIGN_P(value) (((value) & 0x07) == 0)
+
+/* Round X up to the nearest double word.  */
+#define NDS32_ROUND_UP_DOUBLE_WORD(value)  (((value) + 7) & ~7)
+
+
+/* This macro is used to calculate the numbers of registers for
+   containing 'size' bytes of the argument.
+   The size of a register is a word in nds32 target.
+   So we use UNITS_PER_WORD to do the calculation.  */
+#define NDS32_NEED_N_REGS_FOR_ARG(mode, type)                            \
+  ((mode == BLKmode)                                                     \
+   ? ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)  \
+   : ((GET_MODE_SIZE (mode)     + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
+
+/* This macro is used to return the register number for passing argument.
+   We need to obey the following rules:
+     1. If it is required MORE THAN one register,
+        make sure the register number is a even value.
+     2. If it is required ONLY one register,
+        the register number can be odd or even value.  */
+#define NDS32_AVAILABLE_REGNUM_FOR_ARG(reg_offset, mode, type) \
+  ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1)                \
+   ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1)    \
+   : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
+
+/* This macro is to check if there are still available registers
+   for passing argument.  */
+#define NDS32_ARG_PASS_IN_REG_P(reg_offset, mode, type)      \
+  (((reg_offset) < NDS32_MAX_REGS_FOR_ARGS)                  \
+   && ((reg_offset) + NDS32_NEED_N_REGS_FOR_ARG (mode, type) \
+       <= NDS32_MAX_REGS_FOR_ARGS))
+
+/* This macro is to check if the register is required to be saved on stack.
+   If call_used_regs[regno] == 0, regno is the callee-saved register.
+   If df_regs_ever_live_p(regno) == true, it is used in the current function.
+   As long as the register satisfies both criteria above,
+   it is required to be saved.  */
+#define NDS32_REQUIRED_CALLEE_SAVED_P(regno)                  \
+  ((!call_used_regs[regno]) && (df_regs_ever_live_p (regno)))
+
+/* ------------------------------------------------------------------------ */
+
+/* A C structure for machine-specific, per-function data.
+   This is added to the cfun structure.  */
+struct GTY(()) machine_function
+{
+  /* Number of bytes allocated on the stack for variadic args
+     if we want to push them into stack as pretend arguments by ourself.  */
+  int va_args_size;
+  /* Number of bytes reserved on the stack for
+     local and temporary variables.  */
+  int local_size;
+  /* Number of bytes allocated on the stack for outgoing arguments.  */
+  int out_args_size;
+
+  /* Number of bytes on the stack for saving $fp.  */
+  int fp_size;
+  /* Number of bytes on the stack for saving $gp.  */
+  int gp_size;
+  /* Number of bytes on the stack for saving $lp.  */
+  int lp_size;
+
+  /* Number of bytes on the stack for saving callee-saved registers.  */
+  int callee_saved_regs_size;
+  /* The padding bytes in callee-saved area may be required.  */
+  int callee_saved_area_padding_bytes;
+
+  /* The first required register that should be saved on stack
+     for va_args (one named argument + nameless arguments).  */
+  int va_args_first_regno;
+  /* The last required register that should be saved on stack
+     for va_args (one named argument + nameless arguments).  */
+  int va_args_last_regno;
+
+  /* The first required callee-saved register.  */
+  int callee_saved_regs_first_regno;
+  /* The last required callee-saved register.  */
+  int callee_saved_regs_last_regno;
+
+  /* Indicate that whether this function needs
+     prologue/epilogue code generation.  */
+  int naked_p;
+  /* Indicate that whether this function
+     uses fp_as_gp optimization.  */
+  int fp_as_gp_p;
+};
+
+/* A C structure that contains the arguments information.  */
+typedef struct
+{
+  unsigned int reg_offset;
+} nds32_cumulative_args;
+
+/* ------------------------------------------------------------------------ */
+
+/* The following we define C-ISR related stuff.
+   In nds32 architecture, we have 73 vectors for interrupt/exception.
+   For each vector (except for vector 0, which is used for reset behavior),
+   we allow users to set its register saving scheme and interrupt level.  */
+
+/* There are 73 vectors in nds32 architecture.
+   0 for reset handler,
+   1-8 for exception handler,
+   and 9-72 for interrupt handler.
+   We use an array, which is defined in nds32.c, to record
+   essential information for each vector.  */
+#define NDS32_N_ISR_VECTORS 73
+
+/* Define possible isr category.  */
+enum nds32_isr_category
+{
+  NDS32_ISR_NONE,
+  NDS32_ISR_INTERRUPT,
+  NDS32_ISR_EXCEPTION,
+  NDS32_ISR_RESET
+};
+
+/* Define isr register saving scheme.  */
+enum nds32_isr_save_reg
+{
+  NDS32_SAVE_ALL,
+  NDS32_PARTIAL_SAVE
+};
+
+/* Define isr nested type.  */
+enum nds32_isr_nested_type
+{
+  NDS32_NESTED,
+  NDS32_NOT_NESTED,
+  NDS32_NESTED_READY
+};
+
+/* Define structure to record isr information.
+   The isr vector array 'isr_vectors[]' with this structure
+   is defined in nds32.c.  */
+struct nds32_isr_info
+{
+  /* The field to identify isr category.
+     It should be set to NDS32_ISR_NONE by default.
+     If user specifies a function as isr by using attribute,
+     this field will be set accordingly.  */
+  enum nds32_isr_category category;
+
+  /* A string for the applied function name.
+     It should be set to empty string by default.  */
+  char func_name[100];
+
+  /* The register saving scheme.
+     It should be set to NDS32_PARTIAL_SAVE by default
+     unless user specifies attribute to change it.  */
+  enum nds32_isr_save_reg save_reg;
+
+  /* The nested type.
+     It should be set to NDS32_NOT_NESTED by default
+     unless user specifies attribute to change it.  */
+  enum nds32_isr_nested_type nested_type;
+
+  /* Total vectors.
+     The total vectors = interrupt + exception numbers + reset.
+     It should be set to 0 by default.
+     This field is ONLY used in NDS32_ISR_RESET category.  */
+  unsigned int total_n_vectors;
+
+  /* A string for nmi handler name.
+     It should be set to empty string by default.
+     This field is ONLY used in NDS32_ISR_RESET category.  */
+  char nmi_name[100];
+
+  /* A string for warm handler name.
+     It should be set to empty string by default.
+     This field is ONLY used in NDS32_ISR_RESET category.  */
+  char warm_name[100];
+};
+
+/* ------------------------------------------------------------------------ */
+
+/* Define code for all nds32 builtins.  */
+enum nds32_builtins
+{
+  NDS32_BUILTIN_ISYNC,
+  NDS32_BUILTIN_ISB,
+  NDS32_BUILTIN_MFSR,
+  NDS32_BUILTIN_MFUSR,
+  NDS32_BUILTIN_MTSR,
+  NDS32_BUILTIN_MTUSR,
+  NDS32_BUILTIN_SETGIE_EN,
+  NDS32_BUILTIN_SETGIE_DIS
+};
+
+/* ------------------------------------------------------------------------ */
+
+#define TARGET_ISA_V2   (nds32_arch_option == ARCH_V2)
+#define TARGET_ISA_V3   (nds32_arch_option == ARCH_V3)
+#define TARGET_ISA_V3M  (nds32_arch_option == ARCH_V3M)
+
+/* ------------------------------------------------------------------------ */
+
+/* Controlling the Compilation Driver.  */
+
+#define OPTION_DEFAULT_SPECS \
+  {"arch", "%{!march=*:-march=%(VALUE)}" }
+
+#define CC1_SPEC \
+  ""
+
+#define ASM_SPEC \
+  " %{mbig-endian:-EB} %{mlittle-endian:-EL}"
+
+/* If user issues -mrelax, -mforce-fp-as-gp, or -mex9,
+   we need to pass '--relax' to linker.
+   Besides, for -mex9, we need to further pass '--mex9'.  */
+#define LINK_SPEC \
+  " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
+  " %{mrelax|mforce-fp-as-gp|mex9:--relax}" \
+  " %{mex9:--mex9}"
+
+#define LIB_SPEC \
+  " -lc -lgloss"
+
+/* The option -mno-ctor-dtor can disable constructor/destructor feature
+   by applying different crt stuff.  In the convention, crt0.o is the
+   startup file without constructor/destructor;
+   crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the
+   startup files with constructor/destructor.
+   Note that crt0.o, crt1.o, crti.o, and crtn.o are provided
+   by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are
+   currently provided by GCC for nds32 target.
+
+   For nds32 target so far:
+   If -mno-ctor-dtor, we are going to link
+   "crt0.o [user objects]".
+   If general cases, we are going to link
+   "crt1.o crtbegin1.o [user objects] crtend1.o".  */
+#define STARTFILE_SPEC \
+  " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
+  " %{!mno-ctor-dtor:crtbegin1.o%s}"
+#define ENDFILE_SPEC \
+  " %{!mno-ctor-dtor:crtend1.o%s}"
+
+/* The TARGET_BIG_ENDIAN_DEFAULT is defined if we configure gcc
+   with --target=nds32be-* setting.
+   Check gcc/config.gcc for more information.
+   In addition, currently we only have elf toolchain,
+   where mgp-direct is always the default.  */
+#ifdef TARGET_BIG_ENDIAN_DEFAULT
+#define MULTILIB_DEFAULTS { "mbig-endian", "mgp-direct" }
+#else
+#define MULTILIB_DEFAULTS { "mlittle-endian", "mgp-direct" }
+#endif
+
+
+/* Run-time Target Specification.  */
+
+#define TARGET_CPU_CPP_BUILTINS()                     \
+  do                                                  \
+    {                                                 \
+      builtin_define ("__nds32__");                   \
+                                                      \
+      if (TARGET_ISA_V2)                              \
+        builtin_define ("__NDS32_ISA_V2__");          \
+      if (TARGET_ISA_V3)                              \
+        builtin_define ("__NDS32_ISA_V3__");          \
+      if (TARGET_ISA_V3M)                             \
+        builtin_define ("__NDS32_ISA_V3M__");         \
+                                                      \
+      if (TARGET_BIG_ENDIAN)                          \
+        builtin_define ("__big_endian__");            \
+      if (TARGET_REDUCED_REGS)                        \
+        builtin_define ("__NDS32_REDUCED_REGS__");    \
+      if (TARGET_CMOV)                                \
+        builtin_define ("__NDS32_CMOV__");            \
+      if (TARGET_PERF_EXT)                            \
+        builtin_define ("__NDS32_PERF_EXT__");        \
+      if (TARGET_16_BIT)                              \
+        builtin_define ("__NDS32_16_BIT__");          \
+      if (TARGET_GP_DIRECT)                           \
+        builtin_define ("__NDS32_GP_DIRECT__");       \
+                                                      \
+      builtin_assert ("cpu=nds32");                   \
+      builtin_assert ("machine=nds32");               \
+    } while (0)
+
+
+/* Defining Data Structures for Per-function Information.  */
+
+/* This macro is called once per function,
+   before generation of any RTL has begun.  */
+#define INIT_EXPANDERS  nds32_init_expanders ()
+
+
+/* Storage Layout.  */
+
+#define BITS_BIG_ENDIAN 0
+
+#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
+
+#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
+
+#define UNITS_PER_WORD 4
+
+#define PROMOTE_MODE(m, unsignedp, type)                                    \
+  if (GET_MODE_CLASS (m) == MODE_INT && GET_MODE_SIZE (m) < UNITS_PER_WORD) \
+    {                                                                       \
+      (m) = SImode;                                                         \
+    }
+
+#define PARM_BOUNDARY 32
+
+#define STACK_BOUNDARY 64
+
+#define FUNCTION_BOUNDARY 32
+
+#define BIGGEST_ALIGNMENT 64
+
+#define EMPTY_FIELD_BOUNDARY 32
+
+#define STRUCTURE_SIZE_BOUNDARY 8
+
+#define STRICT_ALIGNMENT 1
+
+#define PCC_BITFIELD_TYPE_MATTERS 1
+
+
+/* Layout of Source Language Data Types.  */
+
+#define INT_TYPE_SIZE           32
+#define SHORT_TYPE_SIZE         16
+#define LONG_TYPE_SIZE          32
+#define LONG_LONG_TYPE_SIZE     64
+
+#define FLOAT_TYPE_SIZE         32
+#define DOUBLE_TYPE_SIZE        64
+#define LONG_DOUBLE_TYPE_SIZE   64
+
+#define DEFAULT_SIGNED_CHAR 1
+
+#define SIZE_TYPE "long unsigned int"
+#define PTRDIFF_TYPE "long int"
+#define WCHAR_TYPE "short unsigned int"
+#define WCHAR_TYPE_SIZE 16
+
+
+/* Register Usage.  */
+
+/* Number of actual hardware registers.
+   The hardware registers are assigned numbers for the compiler
+   from 0 to just below FIRST_PSEUDO_REGISTER.
+   All registers that the compiler knows about must be given numbers,
+   even those that are not normally considered general registers.  */
+#define FIRST_PSEUDO_REGISTER 34
+
+/* An initializer that says which registers are used for fixed
+   purposes all throughout the compiled code and are therefore
+   not available for general allocation.
+
+   $r28 : $fp
+   $r29 : $gp
+   $r30 : $lp
+   $r31 : $sp
+
+   caller-save registers: $r0 ~ $r5, $r16 ~ $r23
+   callee-save registers: $r6 ~ $r10, $r11 ~ $r14
+
+   reserved for assembler : $r15
+   reserved for other use : $r24, $r25, $r26, $r27 */
+#define FIXED_REGISTERS                 \
+{ /* r0  r1  r2  r3  r4  r5  r6  r7  */ \
+      0,  0,  0,  0,  0,  0,  0,  0,    \
+  /* r8  r9  r10 r11 r12 r13 r14 r15 */ \
+      0,  0,  0,  0,  0,  0,  0,  1,    \
+  /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
+      0,  0,  0,  0,  0,  0,  0,  0,    \
+  /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
+      1,  1,  1,  1,  0,  1,  0,  1,    \
+  /* ARG_POINTER:32 */                  \
+      1,                                \
+  /* FRAME_POINTER:33 */                \
+      1                                 \
+}
+
+/* Identifies the registers that are not available for
+   general allocation of values that must live across
+   function calls -- so they are caller-save registers.
+
+   0 : callee-save registers
+   1 : caller-save registers */
+#define CALL_USED_REGISTERS             \
+{ /* r0  r1  r2  r3  r4  r5  r6  r7  */ \
+      1,  1,  1,  1,  1,  1,  0,  0,    \
+  /* r8  r9  r10 r11 r12 r13 r14 r15 */ \
+      0,  0,  0,  0,  0,  0,  0,  1,    \
+  /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
+      1,  1,  1,  1,  1,  1,  1,  1,    \
+  /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
+      1,  1,  1,  1,  0,  1,  0,  1,    \
+  /* ARG_POINTER:32 */                  \
+      1,                                \
+  /* FRAME_POINTER:33 */                \
+      1                                 \
+}
+
+/* In nds32 target, we have three levels of registers:
+     LOW_COST_REGS    : $r0 ~ $r7
+     MIDDLE_COST_REGS : $r8 ~ $r11, $r16 ~ $r19
+     HIGH_COST_REGS   : $r12 ~ $r14, $r20 ~ $r31 */
+#define REG_ALLOC_ORDER           \
+{                                 \
+   0,  1,  2,  3,  4,  5,  6,  7, \
+   8,  9, 10, 11, 16, 17, 18, 19, \
+  12, 13, 14, 15, 20, 21, 22, 23, \
+  24, 25, 26, 27, 28, 29, 30, 31, \
+  32,                             \
+  33                              \
+}
+
+/* Tell IRA to use the order we define rather than messing it up with its
+   own cost calculations.  */
+#define HONOR_REG_ALLOC_ORDER
+
+/* The number of consecutive hard regs needed starting at
+   reg "regno" for holding a value of mode "mode".  */
+#define HARD_REGNO_NREGS(regno, mode) nds32_hard_regno_nregs (regno, mode)
+
+/* Value is 1 if hard register "regno" can hold a value
+   of machine-mode "mode".  */
+#define HARD_REGNO_MODE_OK(regno, mode) nds32_hard_regno_mode_ok (regno, mode)
+
+/* A C expression that is nonzero if a value of mode1
+   is accessible in mode2 without copying.
+   Define this macro to return nonzero in as many cases as possible
+   since doing so will allow GCC to perform better register allocation.
+   We can use general registers to tie QI/HI/SI modes together.  */
+#define MODES_TIEABLE_P(mode1, mode2)          \
+  (GET_MODE_CLASS (mode1) == MODE_INT          \
+   && GET_MODE_CLASS (mode2) == MODE_INT       \
+   && GET_MODE_SIZE (mode1) <= UNITS_PER_WORD  \
+   && GET_MODE_SIZE (mode2) <= UNITS_PER_WORD)
+
+
+/* Register Classes.  */
+
+/* In nds32 target, we have three levels of registers:
+     Low cost regsiters    : $r0 ~ $r7
+     Middle cost registers : $r8 ~ $r11, $r16 ~ $r19
+     High cost registers   : $r12 ~ $r14, $r20 ~ $r31
+
+   In practice, we have MIDDLE_REGS cover LOW_REGS register class contents
+   so that it provides more chance to use low cost registers.  */
+enum reg_class
+{
+  NO_REGS,
+  R15_TA_REG,
+  STACK_REG,
+  LOW_REGS,
+  MIDDLE_REGS,
+  HIGH_REGS,
+  GENERAL_REGS,
+  FRAME_REGS,
+  ALL_REGS,
+  LIM_REG_CLASSES
+};
+
+#define N_REG_CLASSES (int) LIM_REG_CLASSES
+
+#define REG_CLASS_NAMES \
+{                       \
+  "NO_REGS",            \
+  "R15_TA_REG",         \
+  "STACK_REG",          \
+  "LOW_REGS",           \
+  "MIDDLE_REGS",        \
+  "HIGH_REGS",          \
+  "GENERAL_REGS",       \
+  "FRAME_REGS",         \
+  "ALL_REGS"            \
+}
+
+#define REG_CLASS_CONTENTS \
+{                                                            \
+  {0x00000000, 0x00000000}, /* NO_REGS     :              */ \
+  {0x00008000, 0x00000000}, /* R15_TA_REG  : 15           */ \
+  {0x80000000, 0x00000000}, /* STACK_REG   : 31           */ \
+  {0x000000ff, 0x00000000}, /* LOW_REGS    : 0-7          */ \
+  {0x000f0fff, 0x00000000}, /* MIDDLE_REGS : 0-11, 16-19  */ \
+  {0xfff07000, 0x00000000}, /* HIGH_REGS   : 12-14, 20-31 */ \
+  {0xffffffff, 0x00000000}, /* GENERAL_REGS: 0-31         */ \
+  {0x00000000, 0x00000003}, /* FRAME_REGS  : 32, 33       */ \
+  {0xffffffff, 0x00000003}  /* ALL_REGS    : 0-31, 32, 33 */ \
+}
+
+#define REGNO_REG_CLASS(regno) nds32_regno_reg_class (regno)
+
+#define BASE_REG_CLASS GENERAL_REGS
+#define INDEX_REG_CLASS GENERAL_REGS
+
+/* Return nonzero if it is suitable for use as a
+   base register in operand addresses.
+   So far, we return nonzero only if "num" is a hard reg
+   of the suitable class or a pseudo register which is
+   allocated to a suitable hard reg.  */
+#define REGNO_OK_FOR_BASE_P(num) \
+  ((num) < 32 || (unsigned) reg_renumber[num] < 32)
+
+/* Return nonzero if it is suitable for use as a
+   index register in operand addresses.
+   So far, we return nonzero only if "num" is a hard reg
+   of the suitable class or a pseudo register which is
+   allocated to a suitable hard reg.
+   The difference between an index register and a base register is that
+   the index register may be scaled.  */
+#define REGNO_OK_FOR_INDEX_P(num) \
+  ((num) < 32 || (unsigned) reg_renumber[num] < 32)
+
+
+/* Obsolete Macros for Defining Constraints.  */
+
+
+/* Stack Layout and Calling Conventions.  */
+
+#define STACK_GROWS_DOWNWARD
+
+#define FRAME_GROWS_DOWNWARD 1
+
+#define STARTING_FRAME_OFFSET 0
+
+#define STACK_POINTER_OFFSET 0
+
+#define FIRST_PARM_OFFSET(fundecl) 0
+
+#define RETURN_ADDR_RTX(count, frameaddr) \
+  nds32_return_addr_rtx (count, frameaddr)
+
+/* A C expression whose value is RTL representing the location
+   of the incoming return address at the beginning of any function
+   before the prologue.
+   If this RTL is REG, you should also define
+   DWARF_FRAME_RETURN_COLUMN to DWARF_FRAME_REGNUM (REGNO).  */
+#define INCOMING_RETURN_ADDR_RTX    gen_rtx_REG (Pmode, LP_REGNUM)
+#define DWARF_FRAME_RETURN_COLUMN   DWARF_FRAME_REGNUM (LP_REGNUM)
+
+#define STACK_POINTER_REGNUM SP_REGNUM
+
+#define FRAME_POINTER_REGNUM 33
+
+#define HARD_FRAME_POINTER_REGNUM FP_REGNUM
+
+#define ARG_POINTER_REGNUM 32
+
+#define STATIC_CHAIN_REGNUM 16
+
+#define ELIMINABLE_REGS                                \
+{ { ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM },      \
+  { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM }, \
+  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },      \
+  { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM } }
+
+#define INITIAL_ELIMINATION_OFFSET(from_reg, to_reg, offset_var) \
+  (offset_var) = nds32_initial_elimination_offset (from_reg, to_reg)
+
+#define ACCUMULATE_OUTGOING_ARGS 1
+
+#define OUTGOING_REG_PARM_STACK_SPACE(fntype) 1
+
+#define CUMULATIVE_ARGS nds32_cumulative_args
+
+#define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \
+  nds32_init_cumulative_args (&cum, fntype, libname, fndecl, n_named_args)
+
+/* The REGNO is an unsigned integer but NDS32_GPR_ARG_FIRST_REGNUM may be 0.
+   We better cast REGNO into signed integer so that we can avoid
+   'comparison of unsigned expression >= 0 is always true' warning.  */
+#define FUNCTION_ARG_REGNO_P(regno)                                        \
+  (((int) regno - NDS32_GPR_ARG_FIRST_REGNUM >= 0)                         \
+   && ((int) regno - NDS32_GPR_ARG_FIRST_REGNUM < NDS32_MAX_REGS_FOR_ARGS))
+
+#define DEFAULT_PCC_STRUCT_RETURN 0
+
+/* EXIT_IGNORE_STACK should be nonzero if, when returning
+   from a function, the stack pointer does not matter.
+   The value is tested only in functions that have frame pointers.
+   In nds32 target, the function epilogue recovers the
+   stack pointer from the frame.  */
+#define EXIT_IGNORE_STACK 1
+
+#define FUNCTION_PROFILER(file, labelno) \
+  fprintf (file, "/* profiler %d */", (labelno))
+
+
+/* Implementing the Varargs Macros.  */
+
+
+/* Trampolines for Nested Functions.  */
+
+/* Giving A-function and B-function,
+   if B-function wants to call A-function's nested function,
+   we need to fill trampoline code into A-function's stack
+   so that B-function can execute the code in stack to indirectly
+   jump to (like 'trampoline' action) desired nested function.
+
+   The trampoline code for nds32 target must contains following parts:
+
+     1. instructions (4 * 4 = 16 bytes):
+          get $pc first
+          load chain_value to static chain register via $pc
+          load nested function address to $r15 via $pc
+          jump to desired nested function via $r15
+     2. data (4 * 2 = 8 bytes):
+          chain_value
+          nested function address
+
+   Please check nds32.c implementation for more information.  */
+#define TRAMPOLINE_SIZE 24
+
+/* Because all instructions/data in trampoline template are 4-byte size,
+   we set trampoline alignment 8*4=32 bits.  */
+#define TRAMPOLINE_ALIGNMENT 32
+
+
+/* Implicit Calls to Library Routines.  */
+
+
+/* Addressing Modes.  */
+
+/* We can use "LWI.bi  Rt, [Ra], 4" to support post increment.  */
+#define HAVE_POST_INCREMENT 1
+/* We can use "LWI.bi  Rt, [Ra], -4" to support post decrement.  */
+#define HAVE_POST_DECREMENT 1
+
+/* We have "LWI.bi  Rt, [Ra], imm" instruction form.  */
+#define HAVE_POST_MODIFY_DISP 1
+/* We have "LW.bi   Rt, [Ra], Rb" instruction form.  */
+#define HAVE_POST_MODIFY_REG  1
+
+#define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && GET_CODE (x) != CONST_DOUBLE)
+
+#define MAX_REGS_PER_ADDRESS 2
+
+
+/* Anchored Addresses.  */
+
+
+/* Condition Code Status.  */
+
+
+/* Describing Relative Costs of Operations.  */
+
+/* A C expression for the cost of a branch instruction.
+   A value of 1 is the default;
+   other values are interpreted relative to that.  */
+#define BRANCH_COST(speed_p, predictable_p) ((speed_p) ? 2 : 0)
+
+#define SLOW_BYTE_ACCESS 1
+
+#define NO_FUNCTION_CSE
+
+
+/* Adjusting the Instruction Scheduler.  */
+
+
+/* Dividing the Output into Sections (Texts, Data, . . . ).  */
+
+#define TEXT_SECTION_ASM_OP     "\t.text"
+#define DATA_SECTION_ASM_OP     "\t.data"
+
+/* Currently, nds32 assembler does NOT handle '.bss' pseudo-op.
+   So we use '.section .bss' alternatively.  */
+#define BSS_SECTION_ASM_OP      "\t.section\t.bss"
+
+/* Define this macro to be an expression with a nonzero value if jump tables
+   (for tablejump insns) should be output in the text section,
+   along with the assembler instructions.
+   Otherwise, the readonly data section is used.  */
+#define JUMP_TABLES_IN_TEXT_SECTION 1
+
+
+/* Position Independent Code.  */
+
+
+/* Defining the Output Assembler Language.  */
+
+#define ASM_COMMENT_START "!"
+
+#define ASM_APP_ON "! #APP"
+
+#define ASM_APP_OFF "! #NO_APP\n"
+
+#define ASM_OUTPUT_LABELREF(stream, name) \
+  asm_fprintf (stream, "%U%s", (*targetm.strip_name_encoding) (name))
+
+#define ASM_OUTPUT_SYMBOL_REF(stream, sym) \
+  assemble_name (stream, XSTR (sym, 0))
+
+#define ASM_OUTPUT_LABEL_REF(stream, buf) \
+  assemble_name (stream, buf)
+
+#define LOCAL_LABEL_PREFIX "."
+
+#define REGISTER_NAMES                                            \
+{                                                                 \
+  "$r0",  "$r1",  "$r2",  "$r3",  "$r4",  "$r5",  "$r6",  "$r7",  \
+  "$r8",  "$r9",  "$r10", "$r11", "$r12", "$r13", "$r14", "$ta",  \
+  "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \
+  "$r24", "$r25", "$r26", "$r27", "$fp",  "$gp",  "$lp",  "$sp",  \
+  "$AP",                                                          \
+  "$SFP"                                                          \
+}
+
+/* Output normal jump table entry.  */
+#define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
+  asm_fprintf (stream, "\t.word\t%LL%d\n", value)
+
+/* Output pc relative jump table entry.  */
+#define ASM_OUTPUT_ADDR_DIFF_ELT(stream, body, value, rel)              \
+  do                                                                    \
+    {                                                                   \
+      switch (GET_MODE (body))                                          \
+        {                                                               \
+        case QImode:                                                    \
+          asm_fprintf (stream, "\t.byte\t.L%d-.L%d\n", value, rel);     \
+          break;                                                        \
+        case HImode:                                                    \
+          asm_fprintf (stream, "\t.short\t.L%d-.L%d\n", value, rel);    \
+          break;                                                        \
+        case SImode:                                                    \
+          asm_fprintf (stream, "\t.word\t.L%d-.L%d\n", value, rel);     \
+          break;                                                        \
+        default:                                                        \
+          gcc_unreachable();                                            \
+        }                                                               \
+    } while (0)
+
+/* We have to undef it first because elfos.h formerly define it
+   check gcc/config.gcc and gcc/config/elfos.h for more information.  */
+#undef  ASM_OUTPUT_CASE_LABEL
+#define ASM_OUTPUT_CASE_LABEL(stream, prefix, num, table)          \
+  do                                                               \
+    {                                                              \
+      asm_fprintf (stream, "\t! Jump Table Begin\n");              \
+      (*targetm.asm_out.internal_label) (stream, prefix, num);     \
+    } while (0)
+
+#define ASM_OUTPUT_CASE_END(stream, num, table)        \
+  do                                                   \
+    {                                                  \
+      /* Because our jump table is in text section,    \
+         we need to make sure 2-byte alignment after   \
+         the jump table for instructions fetch.  */    \
+      if (GET_MODE (PATTERN (table)) == QImode)        \
+        ASM_OUTPUT_ALIGN (stream, 1);                  \
+      asm_fprintf (stream, "\t! Jump Table End\n");    \
+    }  while (0)
+
+/* This macro is not documented yet.
+   But we do need it to make jump table vector aligned.  */
+#define ADDR_VEC_ALIGN(JUMPTABLE) 2
+
+#define DWARF2_UNWIND_INFO 1
+
+#define JUMP_ALIGN(x) \
+  (align_jumps_log ? align_jumps_log : nds32_target_alignment (x))
+
+#define LOOP_ALIGN(x) \
+  (align_loops_log ? align_loops_log : nds32_target_alignment (x))
+
+#define LABEL_ALIGN(x) \
+  (align_labels_log ? align_labels_log : nds32_target_alignment (x))
+
+#define ASM_OUTPUT_ALIGN(stream, power) \
+  fprintf (stream, "\t.align\t%d\n", power)
+
+
+/* Controlling Debugging Information Format.  */
+
+#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
+
+#define DWARF2_DEBUGGING_INFO 1
+
+#define DWARF2_ASM_LINE_DEBUG_INFO 1
+
+
+/* Cross Compilation and Floating Point.  */
+
+
+/* Mode Switching Instructions.  */
+
+
+/* Defining target-specific uses of __attribute__.  */
+
+
+/* Emulating TLS.  */
+
+
+/* Defining coprocessor specifics for MIPS targets.  */
+
+
+/* Parameters for Precompiled Header Validity Checking.  */
+
+
+/* C++ ABI parameters.  */
+
+
+/* Adding support for named address spaces.  */
+
+
+/* Miscellaneous Parameters.  */
+
+/* This is the machine mode that elements of a jump-table should have.  */
+#define CASE_VECTOR_MODE Pmode
+
+/* Return the preferred mode for and addr_diff_vec when the mininum
+   and maximum offset are known.  */
+#define CASE_VECTOR_SHORTEN_MODE(min_offset, max_offset, body)  \
+   ((min_offset < 0 || max_offset >= 0x2000 ) ? SImode          \
+   : (max_offset >= 100) ? HImode                               \
+   : QImode)
+
+/* Generate pc relative jump table when -fpic or -Os.  */
+#define CASE_VECTOR_PC_RELATIVE (flag_pic || optimize_size)
+
+/* Define this macro if operations between registers with integral mode
+   smaller than a word are always performed on the entire register.  */
+#define WORD_REGISTER_OPERATIONS
+
+/* A C expression indicating when insns that read memory in mem_mode,
+   an integral mode narrower than a word, set the bits outside of mem_mode
+   to be either the sign-extension or the zero-extension of the data read.  */
+#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
+
+/* The maximum number of bytes that a single instruction can move quickly
+   between memory and registers or between two memory locations.  */
+#define MOVE_MAX 4
+
+/* A C expression that is nonzero if on this machine the number of bits
+   actually used for the count of a shift operation is equal to the number
+   of bits needed to represent the size of the object being shifted.  */
+#define SHIFT_COUNT_TRUNCATED 1
+
+/* A C expression which is nonzero if on this machine it is safe to "convert"
+   an integer of 'inprec' bits to one of 'outprec' bits by merely operating
+   on it as if it had only 'outprec' bits.  */
+#define TRULY_NOOP_TRUNCATION(outprec, inprec) 1
+
+/* A C expression describing the value returned by a comparison operator with
+   an integral mode and stored by a store-flag instruction ('cstoremode4')
+   when the condition is true.  */
+#define STORE_FLAG_VALUE 1
+
+/* An alias for the machine mode for pointers.  */
+#define Pmode SImode
+
+/* An alias for the machine mode used for memory references to functions
+   being called, in call RTL expressions.  */
+#define FUNCTION_MODE SImode
+
+/* ------------------------------------------------------------------------ */
diff --git a/gcc/config/nds32/nds32.md b/gcc/config/nds32/nds32.md
new file mode 100644
index 00000000000..4a832eaf86b
--- /dev/null
+++ b/gcc/config/nds32/nds32.md
@@ -0,0 +1,2221 @@
+;; Machine description of Andes NDS32 cpu for GNU compiler
+;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
+;; Contributed by Andes Technology Corporation.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
+
+;; Include predicates definition.
+(include "predicates.md")
+
+;; Include constraints definition.
+(include "constraints.md")
+
+;; Include iterators definition.
+(include "iterators.md")
+
+;; Include pipelines definition.
+(include "pipelines.md")
+
+
+;; Include constants definition.
+(include "constants.md")
+
+
+;; Include intrinsic functions definition.
+(include "nds32-intrinsic.md")
+
+;; Include block move for nds32 multiple load/store behavior.
+(include "nds32-multiple.md")
+
+;; Include DImode/DFmode operations.
+(include "nds32-doubleword.md")
+
+;; Include peephole patterns.
+(include "nds32-peephole2.md")
+
+
+;; Insn type, it is used to default other attribute values.
+(define_attr "type"
+  "unknown,move,load,store,alu,compare,branch,call,misc"
+  (const_string "unknown"))
+
+
+;; Length, in bytes, default is 4-bytes.
+(define_attr "length" "" (const_int 4))
+
+
+;; Enabled, which is used to enable/disable insn alternatives.
+;; Note that we use length and TARGET_16_BIT here as criteria.
+;; If the instruction pattern already check TARGET_16_BIT to
+;; determine the length by itself, its enabled attribute should be
+;; always 1 to avoid the conflict with the settings here.
+(define_attr "enabled" ""
+  (cond [(and (eq_attr "length" "2")
+	      (match_test "!TARGET_16_BIT"))
+	 (const_int 0)]
+	(const_int 1)))
+
+
+;; ----------------------------------------------------------------------------
+
+
+;; Move instructions.
+
+;; For QImode and HImode, the immediate value can be fit in imm20s.
+;; So there is no need to split rtx for QI and HI patterns.
+
+(define_expand "movqi"
+  [(set (match_operand:QI 0 "general_operand" "")
+	(match_operand:QI 1 "general_operand" ""))]
+  ""
+{
+  /* Need to force register if mem <- !reg.  */
+  if (MEM_P (operands[0]) && !REG_P (operands[1]))
+    operands[1] = force_reg (QImode, operands[1]);
+})
+
+(define_expand "movhi"
+  [(set (match_operand:HI 0 "general_operand" "")
+	(match_operand:HI 1 "general_operand" ""))]
+  ""
+{
+  /* Need to force register if mem <- !reg.  */
+  if (MEM_P (operands[0]) && !REG_P (operands[1]))
+    operands[1] = force_reg (HImode, operands[1]);
+})
+
+(define_expand "movsi"
+  [(set (match_operand:SI 0 "general_operand" "")
+	(match_operand:SI 1 "general_operand" ""))]
+  ""
+{
+  /* Need to force register if mem <- !reg.  */
+  if (MEM_P (operands[0]) && !REG_P (operands[1]))
+    operands[1] = force_reg (SImode, operands[1]);
+
+  /* If operands[1] is a large constant and cannot be performed
+     by a single instruction, we need to split it.  */
+  if (CONST_INT_P (operands[1])
+      && !satisfies_constraint_Is20 (operands[1])
+      && !satisfies_constraint_Ihig (operands[1]))
+    {
+      rtx high20_rtx;
+      HOST_WIDE_INT low12_int;
+      rtx tmp_rtx;
+
+      tmp_rtx = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];
+
+      high20_rtx = gen_int_mode ((INTVAL (operands[1]) >> 12) << 12, SImode);
+      low12_int = INTVAL (operands[1]) & 0xfff;
+
+      emit_move_insn (tmp_rtx, high20_rtx);
+      emit_move_insn (operands[0], plus_constant (SImode,
+						  tmp_rtx,
+						  low12_int));
+      DONE;
+    }
+})
+
+(define_insn "*mov<mode>"
+  [(set (match_operand:QIHISI 0 "nonimmediate_operand" "=r, r, U45, U33, U37, U45, m,   l,   l,   l,   d, r,    d,    r,    r,    r")
+	(match_operand:QIHISI 1 "nds32_move_operand"   " r, r,   l,   l,   l,   d, r, U45, U33, U37, U45, m, Ip05, Is05, Is20, Ihig"))]
+  ""
+{
+  switch (which_alternative)
+    {
+    case 0:
+      return "mov55\t%0, %1";
+    case 1:
+      return "ori\t%0, %1, 0";
+    case 2:
+    case 3:
+    case 4:
+    case 5:
+      return nds32_output_16bit_store (operands, <byte>);
+    case 6:
+      return nds32_output_32bit_store (operands, <byte>);
+    case 7:
+    case 8:
+    case 9:
+    case 10:
+      return nds32_output_16bit_load (operands, <byte>);
+    case 11:
+      return nds32_output_32bit_load (operands, <byte>);
+    case 12:
+      return "movpi45\t%0, %1";
+    case 13:
+      return "movi55\t%0, %1";
+    case 14:
+      return "movi\t%0, %1";
+    case 15:
+      return "sethi\t%0, hi20(%1)";
+    default:
+      gcc_unreachable ();
+    }
+}
+  [(set_attr "type"   "alu,alu,store,store,store,store,store,load,load,load,load,load,alu,alu,alu,alu")
+   (set_attr "length" "  2,  4,    2,    2,    2,    2,    4,   2,   2,   2,   2,   4,  2,  2,  4,  4")])
+
+
+;; We use nds32_symbolic_operand to limit that only CONST/SYMBOL_REF/LABEL_REF
+;; are able to match such instruction template.
+(define_insn "*move_addr"
+  [(set (match_operand:SI 0 "register_operand"       "=l, r")
+	(match_operand:SI 1 "nds32_symbolic_operand" " i, i"))]
+  ""
+  "la\t%0, %1"
+  [(set_attr "type" "move")
+   (set_attr "length"  "8")])
+
+
+(define_insn "*sethi"
+  [(set (match_operand:SI 0 "register_operand"                "=r")
+	(high:SI (match_operand:SI 1 "nds32_symbolic_operand" " i")))]
+  ""
+  "sethi\t%0, hi20(%1)"
+  [(set_attr "type" "alu")
+   (set_attr "length" "4")])
+
+
+(define_insn "*lo_sum"
+  [(set (match_operand:SI 0 "register_operand"                  "=r")
+	(lo_sum:SI (match_operand:SI 1 "register_operand"       " r")
+		   (match_operand:SI 2 "nds32_symbolic_operand" " i")))]
+  ""
+  "ori\t%0, %1, lo12(%2)"
+  [(set_attr "type" "alu")
+   (set_attr "length" "4")])
+
+
+;; ----------------------------------------------------------------------------
+
+;; Zero extension instructions.
+
+(define_insn "zero_extend<mode>si2"
+  [(set (match_operand:SI 0 "register_operand"                       "=l, r,   l, *r")
+	(zero_extend:SI (match_operand:QIHI 1 "nonimmediate_operand" " l, r, U33,  m")))]
+  ""
+{
+  switch (which_alternative)
+    {
+    case 0:
+      return "ze<size>33\t%0, %1";
+    case 1:
+      return "ze<size>\t%0, %1";
+    case 2:
+      return nds32_output_16bit_load (operands, <byte>);
+    case 3:
+      return nds32_output_32bit_load (operands, <byte>);
+
+    default:
+      gcc_unreachable ();
+    }
+}
+  [(set_attr "type"   "alu,alu,load,load")
+   (set_attr "length" "  2,  4,   2,   4")])
+
+
+;; Sign extension instructions.
+
+(define_insn "extend<mode>si2"
+  [(set (match_operand:SI 0 "register_operand"                       "=l, r, r")
+	(sign_extend:SI (match_operand:QIHI 1 "nonimmediate_operand" " l, r, m")))]
+  ""
+{
+  switch (which_alternative)
+    {
+    case 0:
+      return "se<size>33\t%0, %1";
+    case 1:
+      return "se<size>\t%0, %1";
+    case 2:
+      return nds32_output_32bit_load_s (operands, <byte>);
+
+    default:
+      gcc_unreachable ();
+    }
+}
+  [(set_attr "type"   "alu,alu,load")
+   (set_attr "length" "  2,  4,   4")])
+
+
+;; ----------------------------------------------------------------------------
+
+;; Arithmetic instructions.
+
+(define_insn "add<mode>3"
+  [(set (match_operand:QIHISI 0 "register_operand"                   "=   d,    l,    d,    l,  d, l,    k,    l,    r, r")
+	(plus:QIHISI (match_operand:QIHISI 1 "register_operand"      "    0,    l,    0,    l, %0, l,    0,    k,    r, r")
+		     (match_operand:QIHISI 2 "nds32_rimm15s_operand" " In05, In03, Iu05, Iu03,  r, l, Is10, Iu06, Is15, r")))]
+  ""
+{
+  switch (which_alternative)
+    {
+    case 0:
+      /* addi Rt4,Rt4,-x  ==>  subi45 Rt4,x
+         where 0 <= x <= 31 */
+      operands[2] = gen_int_mode (-INTVAL (operands[2]), SImode);
+      return "subi45\t%0, %2";
+    case 1:
+      /* addi Rt3,Ra3,-x  ==>  subi333 Rt3,Ra3,x
+         where 0 <= x <= 7 */
+      operands[2] = gen_int_mode (-INTVAL (operands[2]), SImode);
+      return "subi333\t%0, %1, %2";
+    case 2:
+      return "addi45\t%0, %2";
+    case 3:
+      return "addi333\t%0, %1, %2";
+    case 4:
+      return "add45\t%0, %2";
+    case 5:
+      return "add333\t%0, %1, %2";
+    case 6:
+      return "addi10.sp\t%2";
+    case 7:
+      return "addri36.sp\t%0, %2";
+    case 8:
+      return "addi\t%0, %1, %2";
+    case 9:
+      return "add\t%0, %1, %2";
+
+    default:
+      gcc_unreachable ();
+    }
+}
+  [(set_attr "type"   "alu,alu,alu,alu,alu,alu,alu,alu,alu,alu")
+   (set_attr "length" "  2,  2,  2,  2,  2,  2,  2,  2,  4,  4")])
+
+(define_insn "sub<mode>3"
+  [(set (match_operand:QIHISI 0 "register_operand"                    "=d, l,    r, r")
+	(minus:QIHISI (match_operand:QIHISI 1 "nds32_rimm15s_operand" " 0, l, Is15, r")
+		      (match_operand:QIHISI 2 "register_operand"      " r, l,    r, r")))]
+  ""
+  "@
+  sub45\t%0, %2
+  sub333\t%0, %1, %2
+  subri\t%0, %2, %1
+  sub\t%0, %1, %2"
+  [(set_attr "type"   "alu,alu,alu,alu")
+   (set_attr "length" "  2,  2,  4,  4")])
+
+
+;; GCC intends to simplify (plus (ashift ...) (reg))
+;; into (plus (mult ...) (reg)), so our matching pattern takes 'mult'
+;; and needs to ensure it is exact_log2 value.
+(define_insn "*add_slli"
+  [(set (match_operand:SI 0 "register_operand"                    "=r")
+        (plus:SI (mult:SI (match_operand:SI 1 "register_operand"  " r")
+			  (match_operand:SI 2 "immediate_operand" " i"))
+		 (match_operand:SI 3 "register_operand"           " r")))]
+  "TARGET_ISA_V3
+   && (exact_log2 (INTVAL (operands[2])) != -1)
+   && (exact_log2 (INTVAL (operands[2])) <= 31)"
+{
+  /* Get floor_log2 of the immediate value
+     so that we can generate 'add_slli' instruction.  */
+  operands[2] = GEN_INT (floor_log2 (INTVAL (operands[2])));
+
+  return "add_slli\t%0, %3, %1, %2";
+}
+  [(set_attr "type" "alu")
+   (set_attr "length" "4")])
+
+(define_insn "*add_srli"
+  [(set (match_operand:SI 0 "register_operand"                        "=   r")
+	(plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand"  "    r")
+			      (match_operand:SI 2 "immediate_operand" " Iu05"))
+		 (match_operand:SI 3 "register_operand"               "    r")))]
+  "TARGET_ISA_V3"
+  "add_srli\t%0, %3, %1, %2"
+  [(set_attr "type" "alu")
+   (set_attr "length" "4")])
+
+
+;; GCC intends to simplify (minus (reg) (ashift ...))
+;; into (minus (reg) (mult ...)), so our matching pattern takes 'mult'
+;; and needs to ensure it is exact_log2 value.
+(define_insn "*sub_slli"
+  [(set (match_operand:SI 0 "register_operand"                     "=r")
+	(minus:SI (match_operand:SI 1 "register_operand"           " r")
+		  (mult:SI (match_operand:SI 2 "register_operand"  " r")
+			   (match_operand:SI 3 "immediate_operand" " i"))))]
+  "TARGET_ISA_V3
+   && (exact_log2 (INTVAL (operands[3])) != -1)
+   && (exact_log2 (INTVAL (operands[3])) <= 31)"
+{
+  /* Get floor_log2 of the immediate value
+     so that we can generate 'sub_slli' instruction.  */
+  operands[3] = GEN_INT (floor_log2 (INTVAL (operands[3])));
+
+  return "sub_slli\t%0, %1, %2, %3";
+}
+  [(set_attr "type" "alu")
+   (set_attr "length" "4")])
+
+(define_insn "*sub_srli"
+  [(set (match_operand:SI 0 "register_operand"                         "=   r")
+	(minus:SI (match_operand:SI 1 "register_operand"               "    r")
+		  (lshiftrt:SI (match_operand:SI 2 "register_operand"  "    r")
+			       (match_operand:SI 3 "immediate_operand" " Iu05"))))]
+  "TARGET_ISA_V3"
+  "sub_srli\t%0, %1, %2, %3"
+  [(set_attr "type" "alu")
+   (set_attr "length" "4")])
+
+
+;; Multiplication instructions.
+
+(define_insn "mulsi3"
+  [(set (match_operand:SI 0 "register_operand"          "= w, r")
+	(mult:SI (match_operand:SI 1 "register_operand" " %0, r")
+		 (match_operand:SI 2 "register_operand" "  w, r")))]
+  ""
+  "@
+  mul33\t%0, %2
+  mul\t%0, %1, %2"
+  [(set_attr "type"   "alu,alu")
+   (set_attr "length" "  2,  4")])
+
+(define_insn "mulsidi3"
+  [(set (match_operand:DI 0 "register_operand"                          "=r")
+	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " r"))
+		 (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))))]
+  "TARGET_ISA_V2 || TARGET_ISA_V3"
+  "mulsr64\t%0, %1, %2"
+  [(set_attr "type"   "alu")
+   (set_attr "length"   "4")])
+
+(define_insn "umulsidi3"
+  [(set (match_operand:DI 0 "register_operand"                          "=r")
+	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" " r"))
+		 (zero_extend:DI (match_operand:SI 2 "register_operand" " r"))))]
+  "TARGET_ISA_V2 || TARGET_ISA_V3"
+  "mulr64\t%0, %1, %2"
+  [(set_attr "type"   "alu")
+   (set_attr "length"   "4")])
+
+
+;; Multiply-accumulate instructions.
+
+(define_insn "*maddr32_0"
+  [(set (match_operand:SI 0 "register_operand"                   "=r")
+        (plus:SI (match_operand:SI 3 "register_operand"          " 0")
+                 (mult:SI (match_operand:SI 1 "register_operand" " r")
+                          (match_operand:SI 2 "register_operand" " r"))))]
+  ""
+  "maddr32\t%0, %1, %2"
+  [(set_attr "type"   "alu")
+   (set_attr "length"   "4")])
+
+(define_insn "*maddr32_1"
+  [(set (match_operand:SI 0 "register_operand"                   "=r")
+        (plus:SI (mult:SI (match_operand:SI 1 "register_operand" " r")
+                          (match_operand:SI 2 "register_operand" " r"))
+                 (match_operand:SI 3 "register_operand"          " 0")))]
+  ""
+  "maddr32\t%0, %1, %2"
+  [(set_attr "type"   "alu")
+   (set_attr "length"   "4")])
+
+(define_insn "*msubr32"
+  [(set (match_operand:SI 0 "register_operand"                    "=r")
+        (minus:SI (match_operand:SI 3 "register_operand"          " 0")
+                  (mult:SI (match_operand:SI 1 "register_operand" " r")
+                           (match_operand:SI 2 "register_operand" " r"))))]
+  ""
+  "msubr32\t%0, %1, %2"
+  [(set_attr "type"   "alu")
+   (set_attr "length"   "4")])
+
+
+;; Div Instructions.
+
+(define_insn "divmodsi4"
+  [(set (match_operand:SI 0 "register_operand"         "=r")
+        (div:SI (match_operand:SI 1 "register_operand" " r")
+                (match_operand:SI 2 "register_operand" " r")))
+   (set (match_operand:SI 3 "register_operand"         "=r")
+        (mod:SI (match_dup 1) (match_dup 2)))]
+  ""
+  "divsr\t%0, %3, %1, %2"
+  [(set_attr "type"   "alu")
+   (set_attr "length"   "4")])
+
+(define_insn "udivmodsi4"
+  [(set (match_operand:SI 0 "register_operand"          "=r")
+        (udiv:SI (match_operand:SI 1 "register_operand" " r")
+                (match_operand:SI 2 "register_operand"  " r")))
+   (set (match_operand:SI 3 "register_operand"          "=r")
+        (umod:SI (match_dup 1) (match_dup 2)))]
+  ""
+  "divr\t%0, %3, %1, %2"
+  [(set_attr "type"   "alu")
+   (set_attr "length"   "4")])
+
+
+;; ----------------------------------------------------------------------------
+
+;; Boolean instructions.
+;; Note: We define the DImode versions in nds32-doubleword.md.
+
+;; ----------------------------------------------------------------------------
+;; 'AND' operation
+;; ----------------------------------------------------------------------------
+
+(define_insn "bitc"
+  [(set (match_operand:SI 0 "register_operand"                 "=r")
+	(and:SI (not:SI (match_operand:SI 1 "register_operand" " r"))
+		(match_operand:SI 2 "register_operand"         " r")))]
+  "TARGET_ISA_V3"
+  "bitc\t%0, %2, %1"
+  [(set_attr "type" "alu")
+   (set_attr "length" "4")]
+)
+
+(define_insn "andsi3"
+  [(set (match_operand:SI 0 "register_operand"         "= w, r,    l,    l,    l,    l,    l,    l,    r,   r,     r,    r,    r")
+	(and:SI (match_operand:SI 1 "register_operand" " %0, r,    l,    l,    l,    l,    0,    0,    r,   r,     r,    r,    r")
+		(match_operand:SI 2 "general_operand"  "  w, r, Izeb, Izeh, Ixls, Ix11, Ibms, Ifex, Izeb, Izeh, Iu15, Ii15, Ic15")))]
+  ""
+{
+  HOST_WIDE_INT mask = INTVAL (operands[2]);
+  int zero_position;
+
+  /* 16-bit andi instructions:
+     andi Rt3,Ra3,0xff   -> zeb33  Rt3,Ra3
+     andi Rt3,Ra3,0xffff -> zeh33  Rt3,Ra3
+     andi Rt3,Ra3,0x01   -> xlsb33 Rt3,Ra3
+     andi Rt3,Ra3,0x7ff  -> x11b33 Rt3,Ra3
+     andi Rt3,Rt3,2^imm3u          -> bmski33 Rt3,imm3u
+     andi Rt3,Rt3,(2^(imm3u+1))-1  -> fexti33 Rt3,imm3u.  */
+
+  switch (which_alternative)
+    {
+    case 0:
+      return "and33\t%0, %2";
+    case 1:
+      return "and\t%0, %1, %2";
+    case 2:
+      return "zeb33\t%0, %1";
+    case 3:
+      return "zeh33\t%0, %1";
+    case 4:
+      return "xlsb33\t%0, %1";
+    case 5:
+      return "x11b33\t%0, %1";
+    case 6:
+      operands[2] = GEN_INT (floor_log2 (mask));
+      return "bmski33\t%0, %2";
+    case 7:
+      operands[2] = GEN_INT (floor_log2 (mask + 1) - 1);
+      return "fexti33\t%0, %2";
+    case 8:
+      return "zeb\t%0, %1";
+    case 9:
+      return "zeh\t%0, %1";
+    case 10:
+      return "andi\t%0, %1, %2";
+    case 11:
+      operands[2] = GEN_INT (~mask);
+      return "bitci\t%0, %1, %2";
+    case 12:
+      /* If we reach this alternative,
+         it must pass the nds32_can_use_bclr_p() test,
+         so that we can guarantee there is only one 0-bit
+         within the immediate value.  */
+      for (zero_position = 31; zero_position >= 0; zero_position--)
+	{
+	  if ((INTVAL (operands[2]) & (1 << zero_position)) == 0)
+	    {
+	      /* Found the 0-bit position.  */
+	      operands[2] = GEN_INT (zero_position);
+	      break;
+	    }
+	}
+      return "bclr\t%0, %1, %2";
+
+    default:
+      gcc_unreachable ();
+    }
+}
+  [(set_attr "type"   "alu,alu,alu,alu,alu,alu,alu,alu,alu,alu,alu,alu,alu")
+   (set_attr "length" "  2,  4,  2,  2,  2,  2,  2,  2,  4,  4,  4,  4,  4")])
+
+(define_insn "*and_slli"
+  [(set (match_operand:SI 0 "register_operand"                      "=   r")
+	(and:SI (ashift:SI (match_operand:SI 1 "register_operand"   "    r")
+			    (match_operand:SI 2 "immediate_operand" " Iu05"))
+		(match_operand:SI 3 "register_operand"              "    r")))]
+  "TARGET_ISA_V3"
+  "and_slli\t%0, %3, %1, %2"
+  [(set_attr "type" "alu")
+   (set_attr "length" "4")])
+
+(define_insn "*and_srli"
+  [(set (match_operand:SI 0 "register_operand"                       "=   r")
+	(and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand"  "    r")
+			     (match_operand:SI 2 "immediate_operand" " Iu05"))
+		(match_operand:SI 3 "register_operand"               "    r")))]
+  "TARGET_ISA_V3"
+  "and_srli\t%0, %3, %1, %2"
+  [(set_attr "type" "alu")
+   (set_attr "length" "4")])
+
+
+;; ----------------------------------------------------------------------------
+;; 'OR' operation
+;; ----------------------------------------------------------------------------
+
+;; For V3/V3M ISA, we have 'or33' instruction.
+;; So we can identify 'or Rt3,Rt3,Ra3' case and set its length to be 2.
+(define_insn "iorsi3"
+  [(set (match_operand:SI 0 "register_operand"         "= w, r,    r,    r")
+	(ior:SI (match_operand:SI 1 "register_operand" " %0, r,    r,    r")
+		(match_operand:SI 2 "general_operand"  "  w, r, Iu15, Ie15")))]
+  ""
+{
+  int one_position;
+
+  switch (which_alternative)
+    {
+    case 0:
+      return "or33\t%0, %2";
+    case 1:
+      return "or\t%0, %1, %2";
+    case 2:
+      return "ori\t%0, %1, %2";
+    case 3:
+      /* If we reach this alternative,
+         it must pass the nds32_can_use_bset_p() test,
+         so that we can guarantee there is only one 1-bit
+         within the immediate value.  */
+      /* Use exact_log2() to search the 1-bit position.  */
+      one_position = exact_log2 (INTVAL (operands[2]));
+      operands[2] = GEN_INT (one_position);
+      return "bset\t%0, %1, %2";
+
+    default:
+      gcc_unreachable ();
+    }
+}
+  [(set_attr "type"   "alu,alu,alu,alu")
+   (set_attr "length" "  2,  4,  4,  4")])
+
+(define_insn "*or_slli"
+  [(set (match_operand:SI 0 "register_operand"                     "=   r")
+	(ior:SI (ashift:SI (match_operand:SI 1 "register_operand"  "    r")
+			   (match_operand:SI 2 "immediate_operand" " Iu05"))
+		(match_operand:SI 3 "register_operand"             "    r")))]
+  "TARGET_ISA_V3"
+  "or_slli\t%0, %3, %1, %2"
+  [(set_attr "type" "alu")
+   (set_attr "length" "4")])
+
+(define_insn "*or_srli"
+  [(set (match_operand:SI 0 "register_operand"                       "=   r")
+	(ior:SI (lshiftrt:SI (match_operand:SI 1 "register_operand"  "    r")
+			     (match_operand:SI 2 "immediate_operand" " Iu05"))
+		(match_operand:SI 3 "register_operand"               "    r")))]
+  "TARGET_ISA_V3"
+  "or_srli\t%0, %3, %1, %2"
+  [(set_attr "type" "alu")
+   (set_attr "length" "4")])
+
+
+;; ----------------------------------------------------------------------------
+;; 'XOR' operation
+;; ----------------------------------------------------------------------------
+
+;; For V3/V3M ISA, we have 'xor33' instruction.
+;; So we can identify 'xor Rt3,Rt3,Ra3' case and set its length to be 2.
+(define_insn "xorsi3"
+  [(set (match_operand:SI 0 "register_operand"         "= w, r,    r,    r")
+	(xor:SI (match_operand:SI 1 "register_operand" " %0, r,    r,    r")
+		(match_operand:SI 2 "general_operand"  "  w, r, Iu15, It15")))]
+  ""
+{
+  int one_position;
+
+  switch (which_alternative)
+    {
+    case 0:
+      return "xor33\t%0, %2";
+    case 1:
+      return "xor\t%0, %1, %2";
+    case 2:
+      return "xori\t%0, %1, %2";
+    case 3:
+      /* If we reach this alternative,
+         it must pass the nds32_can_use_btgl_p() test,
+         so that we can guarantee there is only one 1-bit
+         within the immediate value.  */
+      /* Use exact_log2() to search the 1-bit position.  */
+      one_position = exact_log2 (INTVAL (operands[2]));
+      operands[2] = GEN_INT (one_position);
+      return "btgl\t%0, %1, %2";
+
+    default:
+      gcc_unreachable ();
+    }
+}
+  [(set_attr "type"   "alu,alu,alu,alu")
+   (set_attr "length" "  2,  4,  4,  4")])
+
+(define_insn "*xor_slli"
+  [(set (match_operand:SI 0 "register_operand"                     "=   r")
+	(xor:SI (ashift:SI (match_operand:SI 1 "register_operand"  "    r")
+			   (match_operand:SI 2 "immediate_operand" " Iu05"))
+		(match_operand:SI 3 "register_operand"             "    r")))]
+  "TARGET_ISA_V3"
+  "xor_slli\t%0, %3, %1, %2"
+  [(set_attr "type" "alu")
+   (set_attr "length" "4")])
+
+(define_insn "*xor_srli"
+  [(set (match_operand:SI 0 "register_operand"                       "=   r")
+	(xor:SI (lshiftrt:SI (match_operand:SI 1 "register_operand"  "    r")
+			     (match_operand:SI 2 "immediate_operand" " Iu05"))
+		(match_operand:SI 3 "register_operand"               "    r")))]
+  "TARGET_ISA_V3"
+  "xor_srli\t%0, %3, %1, %2"
+  [(set_attr "type" "alu")
+   (set_attr "length" "4")])
+
+;; Rotate Right Instructions.
+
+(define_insn "rotrsi3"
+  [(set (match_operand:SI 0 "register_operand"                 "=   r, r")
+	  (rotatert:SI (match_operand:SI 1 "register_operand"  "    r, r")
+		       (match_operand:SI 2 "nonmemory_operand" " Iu05, r")))]
+  ""
+  "@
+  rotri\t%0, %1, %2
+  rotr\t%0, %1, %2"
+  [(set_attr "type"   "alu,alu")
+   (set_attr "length" "  4,  4")])
+
+
+;; ----------------------------------------------------------------------------
+;; 'NEG' operation
+;; ----------------------------------------------------------------------------
+
+;; For V3/V3M ISA, we have 'neg33' instruction.
+;; So we can identify 'xor Rt3,Ra3' case and set its length to be 2.
+;; And for V2 ISA, there is NO 'neg33' instruction.
+;; The only option is to use 'subri A,B,0' (its semantic is 'A = 0 - B').
+(define_insn "negsi2"
+  [(set (match_operand:SI 0 "register_operand"         "=w, r")
+	(neg:SI (match_operand:SI 1 "register_operand" " w, r")))]
+  ""
+  "@
+   neg33\t%0, %1
+   subri\t%0, %1, 0"
+  [(set_attr "type"   "alu,alu")
+   (set_attr "length" "  2,  4")])
+
+
+;; ----------------------------------------------------------------------------
+;; 'ONE_COMPLIMENT' operation
+;; ----------------------------------------------------------------------------
+
+;; For V3/V3M ISA, we have 'not33' instruction.
+;; So we can identify 'not Rt3,Ra3' case and set its length to be 2.
+(define_insn "one_cmplsi2"
+  [(set (match_operand:SI 0 "register_operand"         "=w, r")
+	(not:SI (match_operand:SI 1 "register_operand" " w, r")))]
+  ""
+  "@
+   not33\t%0, %1
+   nor\t%0, %1, %1"
+  [(set_attr "type"   "alu,alu")
+   (set_attr "length" "  2,  4")])
+
+
+;; ----------------------------------------------------------------------------
+
+;; Shift instructions.
+
+(define_insn "ashlsi3"
+  [(set (match_operand:SI 0 "register_operand"             "=   l,    r, r")
+	(ashift:SI (match_operand:SI 1 "register_operand"  "    l,    r, r")
+		   (match_operand:SI 2 "nonmemory_operand" " Iu03, Iu05, r")))]
+  ""
+  "@
+  slli333\t%0, %1, %2
+  slli\t%0, %1, %2
+  sll\t%0, %1, %2"
+  [(set_attr "type"   "alu,alu,alu")
+   (set_attr "length" "  2,  4,  4")])
+
+(define_insn "ashrsi3"
+  [(set (match_operand:SI 0 "register_operand"               "=   d,    r, r")
+	(ashiftrt:SI (match_operand:SI 1 "register_operand"  "    0,    r, r")
+		     (match_operand:SI 2 "nonmemory_operand" " Iu05, Iu05, r")))]
+  ""
+  "@
+  srai45\t%0, %2
+  srai\t%0, %1, %2
+  sra\t%0, %1, %2"
+  [(set_attr "type"   "alu,alu,alu")
+   (set_attr "length" "  2,  4,  4")])
+
+(define_insn "lshrsi3"
+  [(set (match_operand:SI 0 "register_operand"               "=   d,    r, r")
+	(lshiftrt:SI (match_operand:SI 1 "register_operand"  "    0,    r, r")
+		     (match_operand:SI 2 "nonmemory_operand" " Iu05, Iu05, r")))]
+  ""
+  "@
+  srli45\t%0, %2
+  srli\t%0, %1, %2
+  srl\t%0, %1, %2"
+  [(set_attr "type"   "alu,alu,alu")
+   (set_attr "length" "  2,  4,  4")])
+
+
+;; ----------------------------------------------------------------------------
+
+;; ----------------------------------------------------------------------------
+;; Conditional Move patterns
+;; ----------------------------------------------------------------------------
+
+(define_expand "movsicc"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(if_then_else:SI (match_operand 1 "comparison_operator" "")
+			 (match_operand:SI 2 "register_operand" "")
+			 (match_operand:SI 3 "register_operand" "")))]
+  "TARGET_CMOV"
+{
+  if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
+      && GET_MODE (XEXP (operands[1], 0)) == SImode
+      && XEXP (operands[1], 1) == const0_rtx)
+    {
+      /* If the operands[1] rtx is already (eq X 0) or (ne X 0),
+         we have gcc generate original template rtx.  */
+      goto create_template;
+    }
+  else
+    {
+      /* Since there is only 'slt'(Set when Less Than) instruction for
+         comparison in Andes ISA, the major strategy we use here is to
+         convert conditional move into 'LT + EQ' or 'LT + NE' rtx combination.
+         We design constraints properly so that the reload phase will assist
+         to make one source operand to use same register as result operand.
+         Then we can use cmovz/cmovn to catch the other source operand
+         which has different register.  */
+      enum rtx_code code = GET_CODE (operands[1]);
+      enum rtx_code new_code = code;
+      rtx cmp_op0 = XEXP (operands[1], 0);
+      rtx cmp_op1 = XEXP (operands[1], 1);
+      rtx tmp;
+      int reverse = 0;
+
+      /* Main Goal: Use 'LT + EQ' or 'LT + NE' to target "then" part
+         Strategy : Reverse condition and swap comparison operands
+
+         For example:
+
+             a <= b ? P : Q   (LE or LEU)
+         --> a >  b ? Q : P   (reverse condition)
+         --> b <  a ? Q : P   (swap comparison operands to achieve 'LT/LTU')
+
+             a >= b ? P : Q   (GE or GEU)
+         --> a <  b ? Q : P   (reverse condition to achieve 'LT/LTU')
+
+             a <  b ? P : Q   (LT or LTU)
+         --> (NO NEED TO CHANGE, it is already 'LT/LTU')
+
+             a >  b ? P : Q   (GT or GTU)
+         --> b <  a ? P : Q   (swap comparison operands to achieve 'LT/LTU') */
+      switch (code)
+	{
+	case NE:
+	  /*   (a != b ? P : Q)
+	     can be expressed as
+	       (a == b ? Q : P)
+	     so, fall through to reverse condition */
+	case GE: case GEU: case LE: case LEU:
+	  new_code = reverse_condition (code);
+	  reverse = 1;
+	  break;
+	case EQ: case GT: case GTU: case LT: case LTU:
+	  /* no need to reverse condition */
+	  break;
+	default:
+	  FAIL;
+	}
+
+      /* For '>' comparison operator, we swap operands
+         so that we can have 'LT/LTU' operator.  */
+      if (new_code == GT || new_code == GTU)
+	{
+	  tmp     = cmp_op0;
+	  cmp_op0 = cmp_op1;
+	  cmp_op1 = tmp;
+
+	  new_code = swap_condition (new_code);
+	}
+
+      /* Use a temporary register to store slt/slts result.  */
+      tmp = gen_reg_rtx (SImode);
+
+      /* Split EQ and NE because we don't have direct comparison of EQ and NE.
+         If we don't split it, the conditional move transformation will fail
+         when producing (SET A (EQ B C)) or (SET A (NE B C)).  */
+      if (new_code == EQ)
+	{
+	  emit_insn (gen_xorsi3 (tmp, cmp_op0, cmp_op1));
+	  emit_insn (gen_slt_compare (tmp, tmp, GEN_INT (1)));
+	}
+      else if (new_code == NE)
+	{
+	  emit_insn (gen_xorsi3 (tmp, cmp_op0, cmp_op1));
+	  emit_insn (gen_slt_compare (tmp, GEN_INT (0), tmp));
+        }
+      else
+	/* This emit_insn will create corresponding 'slt/slts' insturction.  */
+	emit_insn (gen_rtx_SET (VOIDmode, tmp,
+				gen_rtx_fmt_ee (new_code, SImode,
+						cmp_op0, cmp_op1)));
+
+      /* Change comparison semantic into (eq X 0) or (ne X 0) behavior
+         so that cmovz or cmovn will be matched later.
+
+         For reverse condition cases, we want to create a semantic that:
+           (eq X 0) --> pick up "else" part
+         For normal cases, we want to create a semantic that:
+           (ne X 0) --> pick up "then" part
+
+         Later we will have cmovz/cmovn instruction pattern to
+         match corresponding behavior and output instruction.  */
+      operands[1] = gen_rtx_fmt_ee (reverse ? EQ : NE,
+				    VOIDmode, tmp, const0_rtx);
+    }
+
+create_template:
+  do {} while(0); /* dummy line */
+})
+
+(define_insn "cmovz"
+  [(set (match_operand:SI 0 "register_operand"                      "=r, r")
+        (if_then_else:SI (eq (match_operand:SI 1 "register_operand" " r, r")
+			     (const_int 0))
+			 (match_operand:SI 2 "register_operand"     " r, 0")
+			 (match_operand:SI 3 "register_operand"     " 0, r")))]
+  "TARGET_CMOV"
+  "@
+   cmovz\t%0, %2, %1
+   cmovn\t%0, %3, %1"
+  [(set_attr "type" "move")
+   (set_attr "length"  "4")])
+
+(define_insn "cmovn"
+  [(set (match_operand:SI 0 "register_operand"                      "=r, r")
+	(if_then_else:SI (ne (match_operand:SI 1 "register_operand" " r, r")
+			     (const_int 0))
+			 (match_operand:SI 2 "register_operand"     " r, 0")
+			 (match_operand:SI 3 "register_operand"     " 0, r")))]
+  "TARGET_CMOV"
+  "@
+   cmovn\t%0, %2, %1
+   cmovz\t%0, %3, %1"
+  [(set_attr "type" "move")
+   (set_attr "length"  "4")])
+
+
+;; ----------------------------------------------------------------------------
+;; Conditional Branch patterns
+;; ----------------------------------------------------------------------------
+
+(define_expand "cbranchsi4"
+  [(set (pc)
+	(if_then_else (match_operator 0 "comparison_operator"
+			[(match_operand:SI 1 "register_operand"           "")
+			 (match_operand:SI 2 "nds32_reg_constant_operand" "")])
+		      (label_ref (match_operand 3 "" ""))
+		      (pc)))]
+  ""
+{
+  rtx tmp_reg;
+  enum rtx_code code;
+
+  code = GET_CODE (operands[0]);
+
+  /* If operands[2] is (const_int 0),
+     we can use beqz,bnez,bgtz,bgez,bltz,or blez instructions.
+     So we have gcc generate original template rtx.  */
+  if (GET_CODE (operands[2]) == CONST_INT)
+    if (INTVAL (operands[2]) == 0)
+      if ((code != GTU)
+	  && (code != GEU)
+	  && (code != LTU)
+	  && (code != LEU))
+	goto create_template;
+
+  /* For other comparison, NDS32 ISA only has slt (Set-on-Less-Than)
+     behavior for the comparison, we might need to generate other
+     rtx patterns to achieve same semantic.  */
+  switch (code)
+    {
+    case GT:
+    case GTU:
+      if (GET_CODE (operands[2]) == CONST_INT)
+	{
+	  /* GT  reg_A, const_int  =>  !(LT  reg_A, const_int + 1) */
+	  tmp_reg = gen_rtx_REG (SImode, TA_REGNUM);
+
+	  /* We want to plus 1 into the integer value
+	     of operands[2] to create 'slt' instruction.
+	     This caculation is performed on the host machine,
+	     which may be 64-bit integer.
+	     So the meaning of caculation result may be
+	     different from the 32-bit nds32 target.
+
+	     For example:
+	       0x7fffffff + 0x1 -> 0x80000000,
+	       this value is POSITIVE on 64-bit machine,
+	       but the expected value on 32-bit nds32 target
+	       should be NEGATIVE value.
+
+	     Hence, instead of using GEN_INT(), we use gen_int_mode() to
+	     explicitly create SImode constant rtx.  */
+	  operands[2] = gen_int_mode (INTVAL (operands[2]) + 1, SImode);
+
+	  if (code == GT)
+	    {
+	      /* GT, use slts instruction */
+	      emit_insn (gen_slts_compare (tmp_reg, operands[1], operands[2]));
+	    }
+	  else
+	    {
+	      /* GTU, use slt instruction */
+	      emit_insn (gen_slt_compare  (tmp_reg, operands[1], operands[2]));
+	    }
+
+	  PUT_CODE (operands[0], EQ);
+	  operands[1] = tmp_reg;
+	  operands[2] = const0_rtx;
+	  emit_insn (gen_cbranchsi4 (operands[0], operands[1],
+				     operands[2], operands[3]));
+
+	  DONE;
+	}
+      else
+	{
+	  /* GT  reg_A, reg_B  =>  LT  reg_B, reg_A */
+	  tmp_reg = gen_rtx_REG (SImode, TA_REGNUM);
+
+	  if (code == GT)
+	    {
+	      /* GT, use slts instruction */
+	      emit_insn (gen_slts_compare (tmp_reg, operands[2], operands[1]));
+	    }
+	  else
+	    {
+	      /* GTU, use slt instruction */
+	      emit_insn (gen_slt_compare  (tmp_reg, operands[2], operands[1]));
+	    }
+
+	  PUT_CODE (operands[0], NE);
+	  operands[1] = tmp_reg;
+	  operands[2] = const0_rtx;
+	  emit_insn (gen_cbranchsi4 (operands[0], operands[1],
+				     operands[2], operands[3]));
+
+	  DONE;
+	}
+
+    case GE:
+    case GEU:
+      /* GE  reg_A, reg_B      =>  !(LT  reg_A, reg_B) */
+      /* GE  reg_A, const_int  =>  !(LT  reg_A, const_int) */
+      tmp_reg = gen_rtx_REG (SImode, TA_REGNUM);
+
+      if (code == GE)
+	{
+	  /* GE, use slts instruction */
+	  emit_insn (gen_slts_compare (tmp_reg, operands[1], operands[2]));
+	}
+      else
+	{
+	  /* GEU, use slt instruction */
+	  emit_insn (gen_slt_compare  (tmp_reg, operands[1], operands[2]));
+	}
+
+      PUT_CODE (operands[0], EQ);
+      operands[1] = tmp_reg;
+      operands[2] = const0_rtx;
+      emit_insn (gen_cbranchsi4 (operands[0], operands[1],
+				 operands[2], operands[3]));
+
+      DONE;
+
+    case LT:
+    case LTU:
+      /* LT  reg_A, reg_B      =>  LT  reg_A, reg_B */
+      /* LT  reg_A, const_int  =>  LT  reg_A, const_int */
+      tmp_reg = gen_rtx_REG (SImode, TA_REGNUM);
+
+      if (code == LT)
+	{
+	  /* LT, use slts instruction */
+	  emit_insn (gen_slts_compare (tmp_reg, operands[1], operands[2]));
+	}
+      else
+	{
+	  /* LTU, use slt instruction */
+	  emit_insn (gen_slt_compare  (tmp_reg, operands[1], operands[2]));
+	}
+
+      PUT_CODE (operands[0], NE);
+      operands[1] = tmp_reg;
+      operands[2] = const0_rtx;
+      emit_insn (gen_cbranchsi4 (operands[0], operands[1],
+				 operands[2], operands[3]));
+
+      DONE;
+
+    case LE:
+    case LEU:
+      if (GET_CODE (operands[2]) == CONST_INT)
+	{
+	  /* LE  reg_A, const_int  =>  LT  reg_A, const_int + 1 */
+	  tmp_reg = gen_rtx_REG (SImode, TA_REGNUM);
+
+	  /* Note that (le:SI X INT_MAX) is not the same as (lt:SI X INT_MIN).
+	     We better have an assert here in case GCC does not properly
+	     optimize it away.  The INT_MAX here is 0x7fffffff for target.  */
+	  gcc_assert (code != LE || INTVAL (operands[2]) != 0x7fffffff);
+	  operands[2] = gen_int_mode (INTVAL (operands[2]) + 1, SImode);
+
+	  if (code == LE)
+	    {
+	      /* LE, use slts instruction */
+	      emit_insn (gen_slts_compare (tmp_reg, operands[1], operands[2]));
+	    }
+	  else
+	    {
+	      /* LEU, use slt instruction */
+	      emit_insn (gen_slt_compare  (tmp_reg, operands[1], operands[2]));
+	    }
+
+	  PUT_CODE (operands[0], NE);
+	  operands[1] = tmp_reg;
+	  operands[2] = const0_rtx;
+	  emit_insn (gen_cbranchsi4 (operands[0], operands[1],
+				     operands[2], operands[3]));
+
+	  DONE;
+	}
+      else
+	{
+	  /* LE  reg_A, reg_B  =>  !(LT  reg_B, reg_A) */
+	  tmp_reg = gen_rtx_REG (SImode, TA_REGNUM);
+
+	  if (code == LE)
+	    {
+	      /* LE, use slts instruction */
+	      emit_insn (gen_slts_compare (tmp_reg, operands[2], operands[1]));
+	    }
+	  else
+	    {
+	      /* LEU, use slt instruction */
+	      emit_insn (gen_slt_compare  (tmp_reg, operands[2], operands[1]));
+	    }
+
+	  PUT_CODE (operands[0], EQ);
+	  operands[1] = tmp_reg;
+	  operands[2] = const0_rtx;
+	  emit_insn (gen_cbranchsi4 (operands[0], operands[1],
+				     operands[2], operands[3]));
+
+	  DONE;
+	}
+
+    case EQ:
+    case NE:
+      /* NDS32 ISA has various form for eq/ne behavior no matter
+         what kind of the operand is.
+         So just generate original template rtx.  */
+      goto create_template;
+
+    default:
+      FAIL;
+    }
+
+create_template:
+  do {} while(0); /* dummy line */
+})
+
+
+(define_insn "*cbranchsi4_equality_zero"
+  [(set (pc)
+	(if_then_else (match_operator 0 "nds32_equality_comparison_operator"
+			[(match_operand:SI 1 "register_operand"  "t, l, r")
+			 (const_int 0)])
+		      (label_ref (match_operand 2 "" ""))
+		      (pc)))]
+  ""
+{
+  enum rtx_code code;
+
+  code = GET_CODE (operands[0]);
+
+  /* This zero-comparison conditional branch has two forms:
+       32-bit instruction =>          beqz/bnez           imm16s << 1
+       16-bit instruction => beqzs8/bnezs8/beqz38/bnez38  imm8s << 1
+
+     For 32-bit case,
+     we assume it is always reachable. (but check range -65500 ~ 65500)
+
+     For 16-bit case,
+     it must satisfy { 255 >= (label - pc) >= -256 } condition.
+     However, since the $pc for nds32 is at the beginning of the instruction,
+     we should leave some length space for current insn.
+     So we use range -250 ~ 250.  */
+
+  switch (get_attr_length (insn))
+    {
+    case 2:
+      if (which_alternative == 0)
+	{
+	  /* constraint: t */
+	  return (code == EQ) ? "beqzs8\t%2" : "bnezs8\t%2";
+	}
+      else if (which_alternative == 1)
+	{
+	  /* constraint: l */
+	  return (code == EQ) ? "beqz38\t%1, %2" : "bnez38\t%1, %2";
+	}
+      else
+	{
+	  /* constraint: r */
+	  /* For which_alternative==2, it should not be here.  */
+	  gcc_unreachable ();
+	}
+    case 4:
+      /* including constraints: t, l, and r */
+      return (code == EQ) ? "beqz\t%1, %2" : "bnez\t%1, %2";
+    case 6:
+      if (which_alternative == 0)
+	{
+	  /* constraint: t */
+	  if (code == EQ)
+	    {
+	      /*    beqzs8  .L0
+	          =>
+	            bnezs8  .LCB0
+	            j  .L0
+	          .LCB0:
+	       */
+	      return "bnezs8\t.LCB%=\;j\t%2\n.LCB%=:";
+	    }
+	  else
+	    {
+	      /*    bnezs8  .L0
+	          =>
+	            beqzs8  .LCB0
+	            j  .L0
+	          .LCB0:
+	       */
+	      return "beqzs8\t.LCB%=\;j\t%2\n.LCB%=:";
+	    }
+	}
+      else if (which_alternative == 1)
+	{
+	  /* constraint: l */
+	  if (code == EQ)
+	    {
+	      /*    beqz38  $r0, .L0
+	          =>
+	            bnez38  $r0, .LCB0
+	            j  .L0
+	          .LCB0:
+	       */
+	      return "bnez38\t%1, .LCB%=\;j\t%2\n.LCB%=:";
+	    }
+	  else
+	    {
+	      /*    bnez38  $r0, .L0
+	          =>
+	            beqz38  $r0, .LCB0
+	            j  .L0
+	          .LCB0:
+	       */
+	      return "beqz38\t%1, .LCB%=\;j\t%2\n.LCB%=:";
+	    }
+	}
+      else
+	{
+	  /* constraint: r */
+	  /* For which_alternative==2, it should not be here.  */
+	  gcc_unreachable ();
+	}
+    case 8:
+      /* constraint: t, l, r.  */
+      if (code == EQ)
+	{
+	  /*    beqz  $r8, .L0
+	      =>
+	        bnez  $r8, .LCB0
+	        j  .L0
+	      .LCB0:
+	   */
+	  return "bnez\t%1, .LCB%=\;j\t%2\n.LCB%=:";
+	}
+      else
+	{
+	  /*    bnez  $r8, .L0
+	      =>
+	        beqz  $r8, .LCB0
+	        j  .L0
+	      .LCB0:
+	   */
+	  return "beqz\t%1, .LCB%=\;j\t%2\n.LCB%=:";
+	}
+    default:
+      gcc_unreachable ();
+    }
+}
+  [(set_attr "type" "branch")
+   (set_attr "enabled" "1")
+   (set_attr_alternative "length"
+     [
+       ;; Alternative 0
+       (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -250))
+			  (le (minus (match_dup 2) (pc)) (const_int  250)))
+		     (if_then_else (match_test "TARGET_16_BIT")
+				   (const_int 2)
+				   (const_int 4))
+		     (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -65500))
+					(le (minus (match_dup 2) (pc)) (const_int  65500)))
+				   (const_int 4)
+				   (if_then_else (match_test "TARGET_16_BIT")
+						 (const_int 6)
+						 (const_int 8))))
+       ;; Alternative 1
+       (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -250))
+			  (le (minus (match_dup 2) (pc)) (const_int  250)))
+		     (if_then_else (match_test "TARGET_16_BIT")
+				   (const_int 2)
+				   (const_int 4))
+		     (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -65500))
+					(le (minus (match_dup 2) (pc)) (const_int  65500)))
+				   (const_int 4)
+				   (if_then_else (match_test "TARGET_16_BIT")
+						 (const_int 6)
+						 (const_int 8))))
+       ;; Alternative 2
+       (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -65500))
+			  (le (minus (match_dup 2) (pc)) (const_int  65500)))
+		     (const_int 4)
+		     (const_int 8))
+     ])])
+
+
+;; This pattern is dedicated to V2 ISA,
+;; because V2 DOES NOT HAVE beqc/bnec instruction.
+(define_insn "*cbranchsi4_equality_reg"
+  [(set (pc)
+	(if_then_else (match_operator 0 "nds32_equality_comparison_operator"
+			[(match_operand:SI 1 "register_operand"           "r")
+			 (match_operand:SI 2 "nds32_reg_constant_operand" "r")])
+		      (label_ref (match_operand 3 "" ""))
+		      (pc)))]
+  "TARGET_ISA_V2"
+{
+  enum rtx_code code;
+
+  code = GET_CODE (operands[0]);
+
+  /* This register-comparison conditional branch has one form:
+       32-bit instruction =>          beq/bne           imm14s << 1
+
+     For 32-bit case,
+     we assume it is always reachable. (but check range -16350 ~ 16350).  */
+
+  switch (code)
+    {
+    case EQ:
+      /* r, r */
+      switch (get_attr_length (insn))
+	{
+	case 4:
+	  return "beq\t%1, %2, %3";
+	case 8:
+	  /*    beq  $r0, $r1, .L0
+	      =>
+	        bne  $r0, $r1, .LCB0
+	        j  .L0
+	      .LCB0:
+	   */
+	  return "bne\t%1, %2, .LCB%=\;j\t%3\n.LCB%=:";
+	default:
+	  gcc_unreachable ();
+	}
+
+    case NE:
+      /* r, r */
+      switch (get_attr_length (insn))
+	{
+	case 4:
+	  return "bne\t%1, %2, %3";
+	case 8:
+	  /*    bne  $r0, $r1, .L0
+	      =>
+	        beq  $r0, $r1, .LCB0
+	        j  .L0
+	      .LCB0:
+	   */
+	  return "beq\t%1, %2, .LCB%=\;j\t%3\n.LCB%=:";
+	default:
+	  gcc_unreachable ();
+	}
+
+    default:
+      gcc_unreachable ();
+    }
+}
+  [(set_attr "type"   "branch")
+   (set (attr "length")
+	(if_then_else (and (ge (minus (match_dup 3) (pc)) (const_int -16350))
+			   (le (minus (match_dup 3) (pc)) (const_int  16350)))
+		      (const_int 4)
+		      (const_int 8)))])
+
+
+;; This pattern is dedicated to V3/V3M,
+;; because V3/V3M DO HAVE beqc/bnec instruction.
+(define_insn "*cbranchsi4_equality_reg_or_const_int"
+  [(set (pc)
+	(if_then_else (match_operator 0 "nds32_equality_comparison_operator"
+			[(match_operand:SI 1 "register_operand"           "r,    r")
+			 (match_operand:SI 2 "nds32_reg_constant_operand" "r, Is11")])
+		      (label_ref (match_operand 3 "" ""))
+		      (pc)))]
+  "TARGET_ISA_V3 || TARGET_ISA_V3M"
+{
+  enum rtx_code code;
+
+  code = GET_CODE (operands[0]);
+
+  /* This register-comparison conditional branch has one form:
+       32-bit instruction =>          beq/bne           imm14s << 1
+       32-bit instruction =>         beqc/bnec          imm8s << 1
+
+     For 32-bit case, we assume it is always reachable.
+     (but check range -16350 ~ 16350 and -250 ~ 250).  */
+
+  switch (code)
+    {
+    case EQ:
+      if (which_alternative == 0)
+	{
+	  /* r, r */
+	  switch (get_attr_length (insn))
+	    {
+	    case 4:
+	      return "beq\t%1, %2, %3";
+	    case 8:
+	      /*    beq  $r0, $r1, .L0
+	          =>
+	            bne  $r0, $r1, .LCB0
+	            j  .L0
+	          .LCB0:
+	       */
+	      return "bne\t%1, %2, .LCB%=\;j\t%3\n.LCB%=:";
+	    default:
+	      gcc_unreachable ();
+	    }
+	}
+      else
+	{
+	  /* r, Is11 */
+	  switch (get_attr_length (insn))
+	    {
+	    case 4:
+	      return "beqc\t%1, %2, %3";
+	    case 8:
+	      /*    beqc  $r0, constant, .L0
+	          =>
+	            bnec  $r0, constant, .LCB0
+	            j  .L0
+	          .LCB0:
+	       */
+	      return "bnec\t%1, %2, .LCB%=\;j\t%3\n.LCB%=:";
+	    default:
+	      gcc_unreachable ();
+	    }
+	}
+    case NE:
+      if (which_alternative == 0)
+	{
+	  /* r, r */
+	  switch (get_attr_length (insn))
+	    {
+	    case 4:
+	      return "bne\t%1, %2, %3";
+	    case 8:
+	      /*    bne  $r0, $r1, .L0
+	          =>
+	            beq  $r0, $r1, .LCB0
+	            j  .L0
+	          .LCB0:
+	       */
+	      return "beq\t%1, %2, .LCB%=\;j\t%3\n.LCB%=:";
+	    default:
+	      gcc_unreachable ();
+	    }
+	}
+      else
+	{
+	  /* r, Is11 */
+	  switch (get_attr_length (insn))
+	    {
+	    case 4:
+	      return "bnec\t%1, %2, %3";
+	    case 8:
+	      /*    bnec  $r0, constant, .L0
+	          =>
+	            beqc  $r0, constant, .LCB0
+	            j  .L0
+	          .LCB0:
+	       */
+	      return "beqc\t%1, %2, .LCB%=\;j\t%3\n.LCB%=:";
+	    default:
+	      gcc_unreachable ();
+	    }
+	}
+    default:
+      gcc_unreachable ();
+    }
+}
+  [(set_attr "type"   "branch")
+   (set_attr_alternative "length"
+     [
+       ;; Alternative 0
+       (if_then_else (and (ge (minus (match_dup 3) (pc)) (const_int -16350))
+			  (le (minus (match_dup 3) (pc)) (const_int  16350)))
+		     (const_int 4)
+		     (const_int 8))
+       ;; Alternative 1
+       (if_then_else (and (ge (minus (match_dup 3) (pc)) (const_int -250))
+			  (le (minus (match_dup 3) (pc)) (const_int  250)))
+		     (const_int 4)
+		     (const_int 8))
+     ])])
+
+
+(define_insn "*cbranchsi4_greater_less_zero"
+  [(set (pc)
+	(if_then_else (match_operator 0 "nds32_greater_less_comparison_operator"
+			[(match_operand:SI 1 "register_operand" "r")
+			 (const_int 0)])
+		      (label_ref (match_operand 2 "" ""))
+		      (pc)))]
+  ""
+{
+  enum rtx_code code;
+
+  code = GET_CODE (operands[0]);
+
+  /* This zero-greater-less-comparison conditional branch has one form:
+       32-bit instruction =>      bgtz/bgez/bltz/blez     imm16s << 1
+
+     For 32-bit case, we assume it is always reachable.
+     (but check range -65500 ~ 65500).  */
+
+  if (get_attr_length (insn) == 8)
+    {
+      /* The branch target is too far to simply use one
+         bgtz/bgez/bltz/blez instruction.
+         We need to reverse condition and use 'j' to jump to the target.  */
+      switch (code)
+	{
+	case GT:
+	  /*   bgtz  $r8, .L0
+	     =>
+	       blez  $r8, .LCB0
+	       j  .L0
+	     .LCB0:
+	   */
+	  return "blez\t%1, .LCB%=\;j\t%2\n.LCB%=:";
+	case GE:
+	  /*   bgez  $r8, .L0
+	     =>
+	       bltz  $r8, .LCB0
+	       j  .L0
+	     .LCB0:
+	   */
+	  return "bltz\t%1, .LCB%=\;j\t%2\n.LCB%=:";
+	case LT:
+	  /*   bltz  $r8, .L0
+	     =>
+	       bgez  $r8, .LCB0
+	       j  .L0
+	     .LCB0:
+	   */
+	  return "bgez\t%1, .LCB%=\;j\t%2\n.LCB%=:";
+	case LE:
+	  /*   blez  $r8, .L0
+	     =>
+	       bgtz  $r8, .LCB0
+	       j  .L0
+	     .LCB0:
+	   */
+	  return "bgtz\t%1, .LCB%=\;j\t%2\n.LCB%=:";
+	default:
+	  gcc_unreachable ();
+	}
+    }
+
+  switch (code)
+    {
+    case GT:
+      return "bgtz\t%1, %2";
+    case GE:
+      return "bgez\t%1, %2";
+    case LT:
+      return "bltz\t%1, %2";
+    case LE:
+      return "blez\t%1, %2";
+    default:
+      gcc_unreachable ();
+    }
+}
+  [(set_attr "type"   "branch")
+   (set (attr "length")
+        (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -65500))
+			   (le (minus (match_dup 2) (pc)) (const_int  65500)))
+		      (const_int 4)
+		      (const_int 8)))])
+
+
+(define_expand "cstoresi4"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(match_operator:SI 1 "comparison_operator"
+	  [(match_operand:SI 2 "register_operand" "")
+	   (match_operand:SI 3 "nonmemory_operand" "")]))]
+  ""
+{
+  rtx tmp_reg;
+  enum rtx_code code;
+
+  code = GET_CODE (operands[1]);
+
+  switch (code)
+    {
+    case EQ:
+      if (GET_CODE (operands[3]) == CONST_INT)
+	{
+	  /* reg_R = (reg_A == const_int_B)
+	     --> addi reg_C, reg_A, -const_int_B
+	         slti reg_R, reg_C, const_int_1 */
+	  tmp_reg = gen_reg_rtx (SImode);
+	  operands[3] = gen_int_mode (-INTVAL (operands[3]), SImode);
+	  /* If the integer value is not in the range of imm15s,
+	     we need to force register first because our addsi3 pattern
+	     only accept nds32_rimm15s_operand predicate.  */
+	  if (!satisfies_constraint_Is15 (operands[3]))
+	    operands[3] = force_reg (SImode, operands[3]);
+	  emit_insn (gen_addsi3 (tmp_reg, operands[2], operands[3]));
+	  emit_insn (gen_slt_compare (operands[0], tmp_reg, const1_rtx));
+
+	  DONE;
+	}
+      else
+	{
+	  /* reg_R = (reg_A == reg_B)
+	     --> xor  reg_C, reg_A, reg_B
+	         slti reg_R, reg_C, const_int_1 */
+	  tmp_reg = gen_reg_rtx (SImode);
+	  emit_insn (gen_xorsi3 (tmp_reg, operands[2], operands[3]));
+	  emit_insn (gen_slt_compare (operands[0], tmp_reg, const1_rtx));
+
+	  DONE;
+	}
+
+    case NE:
+      if (GET_CODE (operands[3]) == CONST_INT)
+	{
+	  /* reg_R = (reg_A != const_int_B)
+	     --> addi reg_C, reg_A, -const_int_B
+	         slti reg_R, const_int_0, reg_C */
+	  tmp_reg = gen_reg_rtx (SImode);
+	  operands[3] = gen_int_mode (-INTVAL (operands[3]), SImode);
+	  /* If the integer value is not in the range of imm15s,
+	     we need to force register first because our addsi3 pattern
+	     only accept nds32_rimm15s_operand predicate.  */
+	  if (!satisfies_constraint_Is15 (operands[3]))
+	    operands[3] = force_reg (SImode, operands[3]);
+	  emit_insn (gen_addsi3 (tmp_reg, operands[2], operands[3]));
+	  emit_insn (gen_slt_compare (operands[0], const0_rtx, tmp_reg));
+
+	  DONE;
+	}
+      else
+	{
+	  /* reg_R = (reg_A != reg_B)
+	     --> xor  reg_C, reg_A, reg_B
+	         slti reg_R, const_int_0, reg_C */
+	  tmp_reg = gen_reg_rtx (SImode);
+	  emit_insn (gen_xorsi3 (tmp_reg, operands[2], operands[3]));
+	  emit_insn (gen_slt_compare (operands[0], const0_rtx, tmp_reg));
+
+	  DONE;
+	}
+
+    case GT:
+    case GTU:
+      /* reg_R = (reg_A > reg_B)       --> slt reg_R, reg_B, reg_A */
+      /* reg_R = (reg_A > const_int_B) --> slt reg_R, const_int_B, reg_A */
+      if (code == GT)
+	{
+	  /* GT, use slts instruction */
+	  emit_insn (gen_slts_compare (operands[0], operands[3], operands[2]));
+	}
+      else
+	{
+	  /* GTU, use slt instruction */
+	  emit_insn (gen_slt_compare  (operands[0], operands[3], operands[2]));
+	}
+
+      DONE;
+
+    case GE:
+    case GEU:
+      if (GET_CODE (operands[3]) == CONST_INT)
+	{
+	  /* reg_R = (reg_A >= const_int_B)
+	     --> movi reg_C, const_int_B - 1
+	         slt  reg_R, reg_C, reg_A */
+	  tmp_reg = gen_reg_rtx (SImode);
+
+	  emit_insn (gen_movsi (tmp_reg,
+				gen_int_mode (INTVAL (operands[3]) - 1,
+					      SImode)));
+	  if (code == GE)
+	    {
+	      /* GE, use slts instruction */
+	      emit_insn (gen_slts_compare (operands[0], tmp_reg, operands[2]));
+	    }
+	  else
+	    {
+	      /* GEU, use slt instruction */
+	      emit_insn (gen_slt_compare  (operands[0], tmp_reg, operands[2]));
+	    }
+
+	  DONE;
+	}
+      else
+	{
+	  /* reg_R = (reg_A >= reg_B)
+	     --> slt  reg_R, reg_A, reg_B
+	         xori reg_R, reg_R, const_int_1 */
+	  if (code == GE)
+	    {
+	      /* GE, use slts instruction */
+	      emit_insn (gen_slts_compare (operands[0],
+					   operands[2], operands[3]));
+	    }
+	  else
+	    {
+	      /* GEU, use slt instruction */
+	      emit_insn (gen_slt_compare  (operands[0],
+					   operands[2], operands[3]));
+	    }
+
+	  /* perform 'not' behavior */
+	  emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
+
+	  DONE;
+	}
+
+    case LT:
+    case LTU:
+      /* reg_R = (reg_A < reg_B)       --> slt reg_R, reg_A, reg_B */
+      /* reg_R = (reg_A < const_int_B) --> slt reg_R, reg_A, const_int_B */
+      if (code == LT)
+	{
+	  /* LT, use slts instruction */
+	  emit_insn (gen_slts_compare (operands[0], operands[2], operands[3]));
+	}
+      else
+	{
+	  /* LTU, use slt instruction */
+	  emit_insn (gen_slt_compare  (operands[0], operands[2], operands[3]));
+	}
+
+      DONE;
+
+    case LE:
+    case LEU:
+      if (GET_CODE (operands[3]) == CONST_INT)
+	{
+	  /* reg_R = (reg_A <= const_int_B)
+	     --> movi reg_C, const_int_B + 1
+	         slt  reg_R, reg_A, reg_C */
+	  tmp_reg = gen_reg_rtx (SImode);
+
+	  emit_insn (gen_movsi (tmp_reg,
+				gen_int_mode (INTVAL (operands[3]) + 1,
+						      SImode)));
+	  if (code == LE)
+	    {
+	      /* LE, use slts instruction */
+	      emit_insn (gen_slts_compare (operands[0], operands[2], tmp_reg));
+	    }
+	  else
+	    {
+	      /* LEU, use slt instruction */
+	      emit_insn (gen_slt_compare  (operands[0], operands[2], tmp_reg));
+	    }
+
+	  DONE;
+	}
+      else
+	{
+	  /* reg_R = (reg_A <= reg_B) --> slt  reg_R, reg_B, reg_A
+	                                  xori reg_R, reg_R, const_int_1 */
+	  if (code == LE)
+	    {
+	      /* LE, use slts instruction */
+	      emit_insn (gen_slts_compare (operands[0],
+					   operands[3], operands[2]));
+	    }
+	  else
+	    {
+	      /* LEU, use slt instruction */
+	      emit_insn (gen_slt_compare  (operands[0],
+					   operands[3], operands[2]));
+	    }
+
+	  /* perform 'not' behavior */
+	  emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
+
+	  DONE;
+	}
+
+
+    default:
+      gcc_unreachable ();
+    }
+})
+
+
+(define_insn "slts_compare"
+  [(set (match_operand:SI 0 "register_operand"         "=t,    t, r,    r")
+	(lt:SI (match_operand:SI 1 "nonmemory_operand" " d,    d, r,    r")
+	       (match_operand:SI 2 "nonmemory_operand" " r, Iu05, r, Is15")))]
+  ""
+  "@
+   slts45\t%1, %2
+   sltsi45\t%1, %2
+   slts\t%0, %1, %2
+   sltsi\t%0, %1, %2"
+  [(set_attr "type"   "compare,compare,compare,compare")
+   (set_attr "length" "      2,      2,      4,      4")])
+
+(define_insn "slt_compare"
+  [(set (match_operand:SI 0 "register_operand"          "=t,    t, r,    r")
+	(ltu:SI (match_operand:SI 1 "nonmemory_operand" " d,    d, r,    r")
+		(match_operand:SI 2 "nonmemory_operand" " r, Iu05, r, Is15")))]
+  ""
+  "@
+   slt45\t%1, %2
+   slti45\t%1, %2
+   slt\t%0, %1, %2
+   slti\t%0, %1, %2"
+  [(set_attr "type"   "compare,compare,compare,compare")
+   (set_attr "length" "      2,      2,      4,      4")])
+
+
+;; ----------------------------------------------------------------------------
+
+;; Unconditional and other jump instructions.
+
+(define_insn "jump"
+  [(set (pc) (label_ref (match_operand 0 "" "")))]
+  ""
+{
+  /* This unconditional jump has two forms:
+       32-bit instruction => j   imm24s << 1
+       16-bit instruction => j8  imm8s << 1
+
+     For 32-bit case,
+     we assume it is always reachable.
+     For 16-bit case,
+     it must satisfy { 255 >= (label - pc) >= -256 } condition.
+     However, since the $pc for nds32 is at the beginning of the instruction,
+     we should leave some length space for current insn.
+     So we use range -250 ~ 250.  */
+  switch (get_attr_length (insn))
+    {
+    case 2:
+      return "j8\t%0";
+    case 4:
+      return "j\t%0";
+    default:
+      gcc_unreachable ();
+    }
+}
+  [(set_attr "type" "branch")
+   (set_attr "enabled" "1")
+   (set (attr "length")
+	(if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -250))
+			   (le (minus (match_dup 0) (pc)) (const_int  250)))
+		      (if_then_else (match_test "TARGET_16_BIT")
+				    (const_int 2)
+				    (const_int 4))
+		      (const_int 4)))])
+
+(define_insn "indirect_jump"
+  [(set (pc) (match_operand:SI 0 "register_operand" "r, r"))]
+  ""
+  "@
+  jr5\t%0
+  jr\t%0"
+  [(set_attr "type"   "branch,branch")
+   (set_attr "length" "     2,     4")])
+
+;; Subroutine call instruction returning no value.
+;;   operands[0]: It should be a mem RTX whose address is
+;;                the the address of the function.
+;;   operands[1]: It is the number of bytes of arguments pushed as a const_int.
+;;   operands[2]: It is the number of registers used as operands.
+
+(define_expand "call"
+  [(parallel [(call (match_operand 0 "memory_operand" "")
+		    (match_operand 1))
+	      (clobber (reg:SI LP_REGNUM))])]
+  ""
+  ""
+)
+
+(define_insn "*call_register"
+  [(parallel [(call (mem (match_operand:SI 0 "register_operand" "r, r"))
+		    (match_operand 1))
+	      (clobber (reg:SI LP_REGNUM))])]
+  ""
+  "@
+  jral5\t%0
+  jral\t%0"
+  [(set_attr "type"   "branch,branch")
+   (set_attr "length" "     2,     4")])
+
+(define_insn "*call_immediate"
+  [(parallel [(call (mem (match_operand:SI 0 "immediate_operand" "i"))
+		    (match_operand 1))
+	      (clobber (reg:SI LP_REGNUM))])]
+  ""
+  "jal\t%0"
+  [(set_attr "type"   "branch")
+   (set_attr "length"      "4")])
+
+
+;; Subroutine call instruction returning a value.
+;;   operands[0]: It is the hard regiser in which the value is returned.
+;;   The rest three operands are the same as the
+;;   three operands of the 'call' instruction.
+;;   (but with numbers increased by one)
+
+(define_expand "call_value"
+  [(parallel [(set (match_operand 0)
+		   (call (match_operand 1 "memory_operand" "")
+		         (match_operand 2)))
+	      (clobber (reg:SI LP_REGNUM))])]
+  ""
+  ""
+)
+
+(define_insn "*call_value_register"
+  [(parallel [(set (match_operand 0)
+		   (call (mem (match_operand:SI 1 "register_operand" "r, r"))
+		         (match_operand 2)))
+	      (clobber (reg:SI LP_REGNUM))])]
+  ""
+  "@
+  jral5\t%1
+  jral\t%1"
+  [(set_attr "type"   "branch,branch")
+   (set_attr "length" "     2,     4")])
+
+(define_insn "*call_value_immediate"
+  [(parallel [(set (match_operand 0)
+		   (call (mem (match_operand:SI 1 "immediate_operand" "i"))
+			 (match_operand 2)))
+	      (clobber (reg:SI LP_REGNUM))])]
+  ""
+  "jal\t%1"
+  [(set_attr "type"   "branch")
+   (set_attr "length"      "4")])
+
+
+;; prologue and epilogue.
+
+(define_expand "prologue" [(const_int 0)]
+  ""
+{
+  /* Note that only under V3/V3M ISA, we could use v3push prologue.  */
+  if (TARGET_V3PUSH)
+    nds32_expand_prologue_v3push ();
+  else
+    nds32_expand_prologue ();
+  DONE;
+})
+
+(define_expand "epilogue" [(const_int 0)]
+  ""
+{
+  /* Note that only under V3/V3M ISA, we could use v3pop epilogue.  */
+  if (TARGET_V3PUSH)
+    nds32_expand_epilogue_v3pop ();
+  else
+    nds32_expand_epilogue ();
+  DONE;
+})
+
+
+;; nop instruction.
+
+(define_insn "nop"
+  [(const_int 0)]
+  ""
+{
+  if (TARGET_16_BIT)
+    return "nop16";
+  else
+    return "nop";
+}
+  [(set_attr "type" "misc")
+   (set_attr "enabled" "1")
+   (set (attr "length")
+	(if_then_else (match_test "TARGET_16_BIT")
+		      (const_int 2)
+		      (const_int 4)))])
+
+
+;; ----------------------------------------------------------------------------
+;; Stack push/pop operations
+;; ----------------------------------------------------------------------------
+
+;; The pattern for stack push.
+;; Both stack_push_multiple and stack_v3push use the following pattern.
+;; So we need to use TARGET_V3PUSH to determine the instruction length.
+(define_insn "*stack_push"
+  [(match_parallel 0 "nds32_stack_push_operation"
+     [(set (mem:SI (plus:SI (reg:SI SP_REGNUM)
+			    (match_operand:SI 1 "const_int_operand" "")))
+	   (match_operand:SI 2 "register_operand" ""))
+     ])]
+  ""
+{
+  return nds32_output_stack_push ();
+}
+  [(set_attr "type" "misc")
+   (set_attr "enabled" "1")
+   (set (attr "length")
+	(if_then_else (match_test "TARGET_V3PUSH")
+		      (const_int 2)
+		      (const_int 4)))])
+
+
+;; The pattern for stack pop.
+;; Both stack_pop_multiple and stack_v3pop use the following pattern.
+;; So we need to use TARGET_V3PUSH to determine the instruction length.
+(define_insn "*stack_pop"
+  [(match_parallel 0 "nds32_stack_pop_operation"
+     [(set (match_operand:SI 1 "register_operand" "")
+	   (mem:SI (reg:SI SP_REGNUM)))
+     ])]
+  ""
+{
+  return nds32_output_stack_pop ();
+}
+  [(set_attr "type" "misc")
+   (set_attr "enabled" "1")
+   (set (attr "length")
+	(if_then_else (match_test "TARGET_V3PUSH")
+		      (const_int 2)
+		      (const_int 4)))])
+
+
+;; ----------------------------------------------------------------------------
+;; unspec operation patterns
+;; ----------------------------------------------------------------------------
+
+;; In nds32 target, the 'ret5' instuction is actually 'jr5 $lp'.
+;; This pattern is designed to distinguish function return
+;; from general indirect_jump pattern so that we can directly
+;; generate 'ret5' for readability.
+
+(define_insn "unspec_volatile_func_return"
+  [(set (pc)
+	(unspec_volatile:SI [(reg:SI LP_REGNUM)] UNSPEC_VOLATILE_FUNC_RETURN))]
+  ""
+{
+  if (TARGET_16_BIT)
+    return "ret5";
+  else
+    return "ret";
+}
+  [(set_attr "type" "misc")
+   (set_attr "enabled" "1")
+   (set (attr "length")
+	(if_then_else (match_test "TARGET_16_BIT")
+		      (const_int 2)
+		      (const_int 4)))])
+
+
+;; ----------------------------------------------------------------------------
+;; Jump Table patterns
+;; ----------------------------------------------------------------------------
+;; Need to implement ASM_OUTPUT_ADDR_VEC_ELT (for normal jump table)
+;; or ASM_OUTPUT_ADDR_DIFF_ELT (for pc relative jump table) as well.
+;;
+;; operands[0]: The index to dispatch on.
+;; operands[1]: The lower bound for indices in the table.
+;; operands[2]: The total range of indices int the table.
+;;              i.e. The largest index minus the smallest one.
+;; operands[3]: A label that precedes the table itself.
+;; operands[4]: A label to jump to if the index has a value outside the bounds.
+;;
+;; We need to create following sequences for jump table code generation:
+;;   A) k <-- (plus (operands[0]) (-operands[1]))
+;;   B) if (gtu k operands[2]) then goto operands[4]
+;;   C) t <-- operands[3]
+;;   D) z <-- (mem (plus (k << 0 or 1 or 2) t))
+;;   E) z <-- t + z (NOTE: This is only required for pc relative jump table.)
+;;   F) jump to target with register t or z
+;;
+;; The steps C, D, E, and F are performed by casesi_internal pattern.
+(define_expand "casesi"
+  [(match_operand:SI 0 "register_operand"  "r") ; index to jump on
+   (match_operand:SI 1 "immediate_operand" "i") ; lower bound
+   (match_operand:SI 2 "immediate_operand" "i") ; total range
+   (match_operand:SI 3 "" "")                   ; table label
+   (match_operand:SI 4 "" "")]                  ; Out of range label
+  ""
+{
+  rtx add_tmp;
+  rtx reg, test;
+
+  /* Step A: "k <-- (plus (operands[0]) (-operands[1]))".  */
+  if (operands[1] != const0_rtx)
+    {
+      reg = gen_reg_rtx (SImode);
+      add_tmp = gen_int_mode (-INTVAL (operands[1]), SImode);
+
+      /* If the integer value is not in the range of imm15s,
+         we need to force register first because our addsi3 pattern
+         only accept nds32_rimm15s_operand predicate.  */
+      add_tmp = force_reg (SImode, add_tmp);
+
+      emit_insn (gen_addsi3 (reg, operands[0], add_tmp));
+      operands[0] = reg;
+    }
+
+  /* Step B: "if (gtu k operands[2]) then goto operands[4]".  */
+  test = gen_rtx_GTU (VOIDmode, operands[0], operands[2]);
+  emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2],
+				  operands[4]));
+
+  operands[5] = gen_reg_rtx (SImode);
+  /* Step C, D, E, and F, using another temporary register operands[5].  */
+  emit_jump_insn (gen_casesi_internal (operands[0],
+				       operands[3],
+				       operands[5]));
+  DONE;
+})
+
+;; We are receiving operands from casesi pattern:
+;;
+;; operands[0]: The index that have been substracted with lower bound.
+;; operands[1]: A label that precedes the table itself.
+;; operands[2]: A temporary register to retrieve value in table.
+;;
+;; We need to perform steps C, D, E, and F:
+;;
+;;   C) t <-- operands[1]
+;;   D) z <-- (mem (plus (operands[0] << m) t))
+;;            m is 2 for normal jump table.
+;;            m is 0, 1, or 2 for pc relative jump table based on diff size.
+;;   E) t <-- z + t (NOTE: This is only required for pc relative jump table.)
+;;   F) Jump to target with register t or z.
+;;
+;; The USE in this pattern is needed to tell flow analysis that this is
+;; a CASESI insn.  It has no other purpose.
+(define_insn "casesi_internal"
+  [(parallel [(set (pc)
+		   (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "r")
+					     (const_int 4))
+				    (label_ref (match_operand 1 "" "")))))
+	      (use (label_ref (match_dup 1)))
+	      (clobber (match_operand:SI 2 "register_operand" ""))
+	      (clobber (reg:SI TA_REGNUM))])]
+  ""
+{
+  if (CASE_VECTOR_PC_RELATIVE)
+    return nds32_output_casesi_pc_relative (operands);
+  else
+    return nds32_output_casesi (operands);
+}
+  [(set_attr "length" "20")
+   (set_attr "type" "alu")])
+
+;; ----------------------------------------------------------------------------
+
+;; Performance Extension
+
+(define_insn "clzsi2"
+  [(set (match_operand:SI 0 "register_operand"         "=r")
+	(clz:SI (match_operand:SI 1 "register_operand" " r")))]
+  "TARGET_PERF_EXT"
+  "clz\t%0, %1"
+  [(set_attr "type" "alu")
+   (set_attr "length" "4")])
+
+(define_insn "smaxsi3"
+  [(set (match_operand:SI 0 "register_operand"          "=r")
+	(smax:SI (match_operand:SI 1 "register_operand" " r")
+		 (match_operand:SI 2 "register_operand" " r")))]
+  "TARGET_PERF_EXT"
+  "max\t%0, %1, %2"
+  [(set_attr "type" "alu")
+   (set_attr "length" "4")])
+
+(define_insn "sminsi3"
+  [(set (match_operand:SI 0 "register_operand"          "=r")
+	(smin:SI (match_operand:SI 1 "register_operand" " r")
+		 (match_operand:SI 2 "register_operand" " r")))]
+  "TARGET_PERF_EXT"
+  "min\t%0, %1, %2"
+  [(set_attr "type" "alu")
+   (set_attr "length" "4")])
+
+(define_insn "*btst"
+  [(set (match_operand:SI 0 "register_operand"                   "=   r")
+	(zero_extract:SI (match_operand:SI 1 "register_operand"  "    r")
+			 (const_int 1)
+			 (match_operand:SI 2 "immediate_operand" " Iu05")))]
+  "TARGET_PERF_EXT"
+  "btst\t%0, %1, %2"
+  [(set_attr "type" "alu")
+   (set_attr "length" "4")])
+
+;; ----------------------------------------------------------------------------
diff --git a/gcc/config/nds32/nds32.opt b/gcc/config/nds32/nds32.opt
new file mode 100644
index 00000000000..b2b45bb3e02
--- /dev/null
+++ b/gcc/config/nds32/nds32.opt
@@ -0,0 +1,102 @@
+; Options of Andes NDS32 cpu for GNU compiler
+; Copyright (C) 2012-2013 Free Software Foundation, Inc.
+; Contributed by Andes Technology Corporation.
+;
+; This file is part of GCC.
+;
+; GCC is free software; you can redistribute it and/or modify it
+; under the terms of the GNU General Public License as published
+; by the Free Software Foundation; either version 3, or (at your
+; option) any later version.
+;
+; GCC is distributed in the hope that it will be useful, but WITHOUT
+; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+; License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with GCC; see the file COPYING3.  If not see
+; <http://www.gnu.org/licenses/>.
+
+HeaderInclude
+config/nds32/nds32-opts.h
+
+mbig-endian
+Target Report RejectNegative Negative(mlittle-endian) Mask(BIG_ENDIAN)
+Generate code in big-endian mode.
+
+mlittle-endian
+Target Report RejectNegative Negative(mbig-endian) InverseMask(BIG_ENDIAN)
+Generate code in little-endian mode.
+
+mreduced-regs
+Target Report RejectNegative Negative(mfull-regs) Mask(REDUCED_REGS)
+Use reduced-set registers for register allocation.
+
+mfull-regs
+Target Report RejectNegative Negative(mreduced-regs) InverseMask(REDUCED_REGS)
+Use full-set registers for register allocation.
+
+mcmov
+Target Report Mask(CMOV)
+Generate conditional move instructions.
+
+mperf-ext
+Target Report Mask(PERF_EXT)
+Generate performance extension instructions.
+
+mv3push
+Target Report Mask(V3PUSH)
+Generate v3 push25/pop25 instructions.
+
+m16-bit
+Target Report Mask(16_BIT)
+Generate 16-bit instructions.
+
+mgp-direct
+Target Report Mask(GP_DIRECT)
+Generate GP base instructions directly.
+
+misr-vector-size=
+Target RejectNegative Joined UInteger Var(nds32_isr_vector_size) Init(NDS32_DEFAULT_ISR_VECTOR_SIZE)
+Specify the size of each interrupt vector, which must be 4 or 16.
+
+mcache-block-size=
+Target RejectNegative Joined UInteger Var(nds32_cache_block_size) Init(NDS32_DEFAULT_CACHE_BLOCK_SIZE)
+Specify the size of each cache block, which must be a power of 2 between 4 and 512.
+
+march=
+Target RejectNegative Joined Enum(nds32_arch_type) Var(nds32_arch_option) Init(ARCH_V3)
+Specify the name of the target architecture.
+
+Enum
+Name(nds32_arch_type) Type(enum nds32_arch_type)
+
+EnumValue
+Enum(nds32_arch_type) String(v2) Value(ARCH_V2)
+
+EnumValue
+Enum(nds32_arch_type) String(v3) Value(ARCH_V3)
+
+EnumValue
+Enum(nds32_arch_type) String(v3m) Value(ARCH_V3M)
+
+mforce-fp-as-gp
+Target Report Mask(FORCE_FP_AS_GP)
+Prevent $fp being allocated during register allocation so that compiler is able to force performing fp-as-gp optimization.
+
+mforbid-fp-as-gp
+Target Report Mask(FORBID_FP_AS_GP)
+Forbid using $fp to access static and global variables.  This option strictly forbids fp-as-gp optimization regardless of '-mforce-fp-as-gp'.
+
+mex9
+Target Report Mask(EX9)
+Use special directives to guide linker doing ex9 optimization.
+
+mctor-dtor
+Target Report
+Enable constructor/destructor feature.
+
+mrelax
+Target Report
+Guide linker to relax instructions.
diff --git a/gcc/config/nds32/nds32_intrinsic.h b/gcc/config/nds32/nds32_intrinsic.h
new file mode 100644
index 00000000000..33064a966ed
--- /dev/null
+++ b/gcc/config/nds32/nds32_intrinsic.h
@@ -0,0 +1,37 @@
+/* Intrinsic definitions of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef _NDS32_INTRINSIC_H
+#define _NDS32_INTRINSIC_H
+
+enum nds32_intrinsic_registers
+{
+  __NDS32_REG_PSW__ = 1024,
+  __NDS32_REG_IPSW__,
+  __NDS32_REG_ITYPE__,
+  __NDS32_REG_IPC__
+};
+
+#endif /* nds32_intrinsic.h */
diff --git a/gcc/config/nds32/pipelines.md b/gcc/config/nds32/pipelines.md
new file mode 100644
index 00000000000..9c8c56bab83
--- /dev/null
+++ b/gcc/config/nds32/pipelines.md
@@ -0,0 +1,29 @@
+;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler
+;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
+;; Contributed by Andes Technology Corporation.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_automaton "nds32_machine")
+
+(define_cpu_unit "general_unit" "nds32_machine")
+
+(define_insn_reservation "simple_insn" 1
+			 (eq_attr "type" "unknown,load,store,move,alu,compare,branch,call,misc")
+			 "general_unit")
+
+;; ------------------------------------------------------------------------
diff --git a/gcc/config/nds32/predicates.md b/gcc/config/nds32/predicates.md
new file mode 100644
index 00000000000..df4eccdb891
--- /dev/null
+++ b/gcc/config/nds32/predicates.md
@@ -0,0 +1,92 @@
+;; Predicate definitions of Andes NDS32 cpu for GNU compiler
+;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
+;; Contributed by Andes Technology Corporation.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_predicate "nds32_equality_comparison_operator"
+  (match_code "eq,ne"))
+
+(define_predicate "nds32_greater_less_comparison_operator"
+  (match_code "gt,ge,lt,le"))
+
+(define_special_predicate "nds32_logical_binary_operator"
+  (match_code "and,ior,xor"))
+
+(define_predicate "nds32_symbolic_operand"
+  (match_code "const,symbol_ref,label_ref"))
+
+(define_predicate "nds32_reg_constant_operand"
+  (ior (match_operand 0 "register_operand")
+       (match_operand 0 "const_int_operand")))
+
+(define_predicate "nds32_rimm15s_operand"
+  (ior (match_operand 0 "register_operand")
+       (and (match_operand 0 "const_int_operand")
+	    (match_test "satisfies_constraint_Is15 (op)"))))
+
+(define_predicate "nds32_imm5u_operand"
+  (and (match_operand 0 "const_int_operand")
+       (match_test "satisfies_constraint_Iu05 (op)")))
+
+(define_predicate "nds32_move_operand"
+  (and (match_operand 0 "general_operand")
+       (not (match_code "high,const,symbol_ref,label_ref")))
+{
+  /* If the constant op does NOT satisfy Is20 nor Ihig,
+     we can not perform move behavior by a single instruction.  */
+  if (CONST_INT_P (op)
+      && !satisfies_constraint_Is20 (op)
+      && !satisfies_constraint_Ihig (op))
+    return false;
+
+  return true;
+})
+
+(define_special_predicate "nds32_load_multiple_operation"
+  (match_code "parallel")
+{
+  /* To verify 'load' operation, pass 'true' for the second argument.
+     See the implementation in nds32.c for details.  */
+  return nds32_valid_multiple_load_store (op, true);
+})
+
+(define_special_predicate "nds32_store_multiple_operation"
+  (match_code "parallel")
+{
+  /* To verify 'store' operation, pass 'false' for the second argument.
+     See the implementation in nds32.c for details.  */
+  return nds32_valid_multiple_load_store (op, false);
+})
+
+(define_special_predicate "nds32_stack_push_operation"
+  (match_code "parallel")
+{
+  /* To verify 'push' operation, pass 'true' for the second argument.
+     See the implementation in nds32.c for details.  */
+  return nds32_valid_stack_push_pop (op, true);
+})
+
+(define_special_predicate "nds32_stack_pop_operation"
+  (match_code "parallel")
+{
+  /* To verify 'pop' operation, pass 'false' for the second argument.
+     See the implementation in nds32.c for details.  */
+  return nds32_valid_stack_push_pop (op, false);
+})
+
+;; ------------------------------------------------------------------------
diff --git a/gcc/config/nds32/t-mlibs b/gcc/config/nds32/t-mlibs
new file mode 100644
index 00000000000..ec546e48c1b
--- /dev/null
+++ b/gcc/config/nds32/t-mlibs
@@ -0,0 +1,38 @@
+# The multilib settings of Andes NDS32 cpu for GNU compiler
+# Copyright (C) 2012-2013 Free Software Foundation, Inc.
+# Contributed by Andes Technology Corporation.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published
+# by the Free Software Foundation; either version 3, or (at your
+# option) any later version.
+#
+# GCC is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+# or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+# License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# We need to build following multilibs combinations:
+#
+#   1. <None multilibs>
+#   2. -mlittle-endian
+#   3. -mbig-endian
+#   4. -mgp-direct
+#   5. -mno-gp-direct
+#   6. -mlittle-endian -mgp-direct
+#   7. -mlittle-endian -mno-gp-direct
+#   8. -mbig-endian -mgp-direct
+#   9. -mlittle-endian -mno-gp-direct
+#
+# We also define a macro MULTILIB_DEFAULTS in nds32.h that tells the
+# driver program which options are defaults for this target and thus
+# do not need to be handled specially.
+MULTILIB_OPTIONS = mlittle-endian/mbig-endian mgp-direct/mno-gp-direct
+
+# ------------------------------------------------------------------------
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 1d52e425e33..799ede1ec95 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -2505,6 +2505,12 @@ on data in the eight-bit data area.  Note the eight-bit data area is limited to
 You must use GAS and GLD from GNU binutils version 2.7 or later for
 this attribute to work correctly.
 
+@item exception
+@cindex exception handler functions
+Use this attribute on the NDS32 target to indicate that the specified function
+is an exception handler.  The compiler will generate corresponding sections
+for use in an exception handler.
+
 @item exception_handler
 @cindex exception handler functions on the Blackfin processor
 Use this attribute on the Blackfin to indicate that the specified function
@@ -2965,6 +2971,32 @@ void __attribute__ ((interrupt, use_shadow_register_set,
                      use_debug_exception_return)) v7 ();
 @end smallexample
 
+On NDS32 target, this attribute is to indicate that the specified function
+is an interrupt handler.  The compiler will generate corresponding sections
+for use in an interrupt handler.  You can use the following attributes
+to modify the behavior:
+@table @code
+@item nested
+@cindex @code{nested} attribute
+This interrupt service routine is interruptible.
+@item not_nested
+@cindex @code{not_nested} attribute
+This interrupt service routine is not interruptible.
+@item nested_ready
+@cindex @code{nested_ready} attribute
+This interrupt service routine is interruptible after @code{PSW.GIE}
+(global interrupt enable) is set.  This allows interrupt service routine to
+finish some short critical code before enabling interrupts.
+@item save_all
+@cindex @code{save_all} attribute
+The system will help save all registers into stack before entering
+interrupt handler.
+@item partial_save
+@cindex @code{partial_save} attribute
+The system will help save caller registers into stack before entering
+interrupt handler.
+@end table
+
 On RL78, use @code{brk_interrupt} instead of @code{interrupt} for
 handlers intended to be used with the @code{BRK} opcode (i.e.@: those
 that must end with @code{RETB} instead of @code{RETI}).
@@ -3201,9 +3233,10 @@ and newer.
 
 @item naked
 @cindex function without a prologue/epilogue code
-Use this attribute on the ARM, AVR, MCORE, MSP430, RL78, RX and SPU ports to indicate that
-the specified function does not need prologue/epilogue sequences generated by
-the compiler.  It is up to the programmer to provide these sequences. The
+Use this attribute on the ARM, AVR, MCORE, MSP430, NDS32, RL78, RX and SPU
+ports to indicate that the specified function does not need prologue/epilogue
+sequences generated by the compiler.
+It is up to the programmer to provide these sequences. The
 only statements that can be safely included in naked functions are
 @code{asm} statements that do not have operands.  All other statements,
 including declarations of local variables, @code{if} statements, and so
@@ -3575,6 +3608,21 @@ safe since the loaders there save EAX, EDX and ECX.  (Lazy binding can be
 disabled with the linker or the loader if desired, to avoid the
 problem.)
 
+@item reset
+@cindex reset handler functions
+Use this attribute on the NDS32 target to indicate that the specified function
+is a reset handler.  The compiler will generate corresponding sections
+for use in a reset handler.  You can use the following attributes
+to provide extra exception handling:
+@table @code
+@item nmi
+@cindex @code{nmi} attribute
+Provide a user-defined function to handle NMI exception.
+@item warm
+@cindex @code{warm} attribute
+Provide a user-defined function to handle warm reset exception.
+@end table
+
 @item sseregparm
 @cindex @code{sseregparm} attribute
 On the Intel 386 with SSE support, the @code{sseregparm} attribute
@@ -9131,6 +9179,7 @@ instructions, but allow the compiler to schedule those calls.
 * MIPS Loongson Built-in Functions::
 * Other MIPS Built-in Functions::
 * MSP430 Built-in Functions::
+* NDS32 Built-in Functions::
 * picoChip Built-in Functions::
 * PowerPC Built-in Functions::
 * PowerPC AltiVec/VSX Built-in Functions::
@@ -12584,6 +12633,44 @@ handlers and the changes to the status register will only take affect
 once the handler returns.
 @end table
 
+@node NDS32 Built-in Functions
+@subsection NDS32 Built-in Functions
+
+These built-in functions are available for the NDS32 target:
+
+@deftypefn {Built-in Function} void __builtin_nds32_isync (int *@var{addr})
+Insert an ISYNC instruction into the instruction stream where
+@var{addr} is an instruction address for serialization.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_nds32_isb (void)
+Insert an ISB instruction into the instruction stream.
+@end deftypefn
+
+@deftypefn {Built-in Function} int __builtin_nds32_mfsr (int @var{sr})
+Return the content of a system register which is mapped by @var{sr}.
+@end deftypefn
+
+@deftypefn {Built-in Function} int __builtin_nds32_mfusr (int @var{usr})
+Return the content of a user space register which is mapped by @var{usr}.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_nds32_mtsr (int @var{value}, int @var{sr})
+Move the @var{value} to a system register which is mapped by @var{sr}.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_nds32_mtusr (int @var{value}, int @var{usr})
+Move the @var{value} to a user space register which is mapped by @var{usr}.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_nds32_setgie_en (void)
+Enable global interrupt.
+@end deftypefn
+
+@deftypefn {Built-in Function} void __builtin_nds32_setgie_dis (void)
+Disable global interrupt.
+@end deftypefn
+
 @node picoChip Built-in Functions
 @subsection picoChip Built-in Functions
 
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 308f3e8d3b1..fa5d6e5a611 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -1862,6 +1862,11 @@ This option is only supported for the AVR target.  It is not supported for
 RTEMS configurations, which currently use newlib.  The option is
 supported since version 4.7.2 and is the default in 4.8.0 and newer.
 
+@item --with-nds32-lib=@var{library}
+Specifies that @var{library} setting is used for building @file{libgcc.a}.
+Currently, the valid @var{library} is @samp{newlib} or @samp{mculib}.
+This option is only supported for the NDS32 target.
+
 @item --with-build-time-tools=@var{dir}
 Specifies where to find the set of target tools (assembler, linker, etc.)
 that will be used while building GCC itself.  This option can be useful
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index ef79df3ae66..e84bca30ab2 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -822,6 +822,20 @@ Objective-C and Objective-C++ Dialects}.
 @emph{MSP430 Options}
 @gccoptlist{-msim -masm-hex -mmcu= -mlarge -msmall -mrelax}
 
+@emph{NDS32 Options}
+@gccoptlist{-mbig-endian -mlittle-endian @gol
+-mreduced-regs -mfull-regs @gol
+-mcmov -mno-cmov @gol
+-mperf-ext -mno-perf-ext @gol
+-mv3push -mno-v3push @gol
+-m16bit -mno-16bit @gol
+-mgp-direct -mno-gp-direct @gol
+-misr-vector-size=@var{num} @gol
+-mcache-block-size=@var{num} @gol
+-march=@var{arch} @gol
+-mforce-fp-as-gp -mforbid-fp-as-gp @gol
+-mex9 -mctor-dtor -mrelax}
+
 @emph{PDP-11 Options}
 @gccoptlist{-mfpu  -msoft-float  -mac0  -mno-ac0  -m40  -m45  -m10 @gol
 -mbcopy  -mbcopy-builtin  -mint32  -mno-int16 @gol
@@ -10991,6 +11005,7 @@ platform.
 * MN10300 Options::
 * Moxie Options::
 * MSP430 Options::
+* NDS32 Options::
 * PDP-11 Options::
 * picoChip Options::
 * PowerPC Options::
@@ -17792,6 +17807,108 @@ the final link.
 
 @end table
 
+@node NDS32 Options
+@subsection NDS32 Options
+@cindex NDS32 Options
+
+These options are defined for NDS32 implementations:
+
+@table @gcctabopt
+
+@item -mbig-endian
+@opindex mbig-endian
+Generate code in big-endian mode.
+
+@item -mlittle-endian
+@opindex mlittle-endian
+Generate code in little-endian mode.
+
+@item -mreduced-regs
+@opindex mreduced-regs
+Use reduced-set registers for register allocation.
+
+@item -mfull-regs
+@opindex mfull-regs
+Use full-set registers for register allocation.
+
+@item -mcmov
+@opindex mcmov
+Generate conditional move instructions.
+
+@item -mno-cmov
+@opindex mno-cmov
+Do not generate conditional move instructions.
+
+@item -mperf-ext
+@opindex mperf-ext
+Generate performance extension instructions.
+
+@item -mno-perf-ext
+@opindex mno-perf-ext
+Do not generate performance extension instructions.
+
+@item -mv3push
+@opindex mv3push
+Generate v3 push25/pop25 instructions.
+
+@item -mno-v3push
+@opindex mno-v3push
+Do not generate v3 push25/pop25 instructions.
+
+@item -m16-bit
+@opindex m16-bit
+Generate 16-bit instructions.
+
+@item -mno-16-bit
+@opindex mno-16-bit
+Do not generate 16-bit instructions.
+
+@item -mgp-direct
+@opindex mgp-direct
+Generate GP base instructions directly.
+
+@item -mno-gp-direct
+@opindex mno-gp-direct
+Do no generate GP base instructions directly.
+
+@item -misr-vector-size=@var{num}
+@opindex misr-vector-size
+Specify the size of each interrupt vector, which must be 4 or 16.
+
+@item -mcache-block-size=@var{num}
+@opindex mcache-block-size
+Specify the size of each cache block,
+which must be a power of 2 between 4 and 512.
+
+@item -march=@var{arch}
+@opindex march
+Specify the name of the target architecture.
+
+@item -mforce-fp-as-gp
+@opindex mforce-fp-as-gp
+Prevent $fp being allocated during register allocation so that compiler
+is able to force performing fp-as-gp optimization.
+
+@item -mforbid-fp-as-gp
+@opindex mforbid-fp-as-gp
+Forbid using $fp to access static and global variables.
+This option strictly forbids fp-as-gp optimization
+regardless of @option{-mforce-fp-as-gp}.
+
+@item -mex9
+@opindex mex9
+Use special directives to guide linker doing ex9 optimization.
+
+@item -mctor-dtor
+@opindex mctor-dtor
+Enable constructor/destructor feature.
+
+@item -mrelax
+@opindex mrelax
+Guide linker to relax instructions.
+
+@end table
+
 @node PDP-11 Options
 @subsection PDP-11 Options
 @cindex PDP-11 Options
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 2a5a2e12dda..ac10a0ad03c 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3152,6 +3152,87 @@ Memory reference, stack only.
 
 @end table
 
+@item NDS32---@file{config/nds32/constraints.md}
+@table @code
+@item w
+LOW register class $r0 to $r7 constraint for V3/V3M ISA.
+@item l
+LOW register class $r0 to $r7.
+@item d
+MIDDLE register class $r0 to $r11, $r16 to $r19.
+@item h
+HIGH register class $r12 to $r14, $r20 to $r31.
+@item t
+Temporary assist register $ta (i.e.@: $r15).
+@item k
+Stack register $sp.
+@item Iu03
+Unsigned immediate 3-bit value.
+@item In03
+Negative immediate 3-bit value in the range of @minus{}7--0.
+@item Iu04
+Unsigned immediate 4-bit value.
+@item Is05
+Signed immediate 5-bit value.
+@item Iu05
+Unsigned immediate 5-bit value.
+@item In05
+Negative immediate 5-bit value in the range of @minus{}31--0.
+@item Ip05
+Unsigned immediate 5-bit value for movpi45 instruction with range 16--47.
+@item Iu06
+Unsigned immediate 6-bit value constraint for addri36.sp instruction.
+@item Iu08
+Unsigned immediate 8-bit value.
+@item Iu09
+Unsigned immediate 9-bit value.
+@item Is10
+Signed immediate 10-bit value.
+@item Is11
+Signed immediate 11-bit value.
+@item Is15
+Signed immediate 15-bit value.
+@item Iu15
+Unsigned immediate 15-bit value.
+@item Ic15
+A constant which is not in the range of imm15u but ok for bclr instruction.
+@item Ie15
+A constant which is not in the range of imm15u but ok for bset instruction.
+@item It15
+A constant which is not in the range of imm15u but ok for btgl instruction.
+@item Ii15
+A constant whose compliment value is in the range of imm15u
+and ok for bitci instruction.
+@item Is16
+Signed immediate 16-bit value.
+@item Is17
+Signed immediate 17-bit value.
+@item Is19
+Signed immediate 19-bit value.
+@item Is20
+Signed immediate 20-bit value.
+@item Ihig
+The immediate value that can be simply set high 20-bit.
+@item Izeb
+The immediate value 0xff.
+@item Izeh
+The immediate value 0xffff.
+@item Ixls
+The immediate value 0x01.
+@item Ix11
+The immediate value 0x7ff.
+@item Ibms
+The immediate value with power of 2.
+@item Ifex
+The immediate value with power of 2 minus 1.
+@item U33
+Memory constraint for 333 format.
+@item U45
+Memory constraint for 45 format.
+@item U37
+Memory constraint for 37 format.
+@end table
+
 @item PDP-11---@file{config/pdp11/constraints.md}
 @table @code
 @item a
diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index 742f1034802..650867041d9 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,9 @@
+2013-10-31  Chung-Ju Wu  <jasonwucj@gmail.com>
+	    Shiva Chen  <shiva0217@gmail.com>
+
+	* config.host (nds32*-elf*): Add nds32 target.
+	* config/nds32 : New directory and files.
+
 2013-10-16  Hans-Peter Nilsson  <hp@axis.com>
 
 	For CRIS ports, switch to soft-fp.  Improve arit.c and longlong.h.
diff --git a/libgcc/config.host b/libgcc/config.host
index 6390273bfef..905b816b0dd 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -143,6 +143,9 @@ mips*-*-*)
 	cpu_type=mips
 	tmake_file=mips/t-mips
 	;;
+nds32*-*)
+	cpu_type=nds32
+	;;
 powerpc*-*-*)
 	cpu_type=rs6000
 	;;
@@ -850,6 +853,29 @@ moxie-*-rtems*)
 msp430*-*-elf)
 	tmake_file="$tm_file t-crtstuff t-fdpbit msp430/t-msp430"
 	;;
+nds32*-elf*)
+	# Basic makefile fragment and extra_parts for crt stuff.
+	# We also append c-isr library implementation.
+	tmake_file="${tmake_file} nds32/t-nds32 nds32/t-nds32-isr"
+	extra_parts="crtbegin1.o crtend1.o libnds32_isr.a"
+	# Append library definition makefile fragment according to --with-nds32-lib=X setting.
+	case "${with_nds32_lib}" in
+	"" | newlib)
+		# Append library definition makefile fragment t-nds32-newlib.
+		# Append 'soft-fp' software floating point make rule fragment provided by gcc.
+		tmake_file="${tmake_file} nds32/t-nds32-newlib t-softfp-sfdf t-softfp"
+		;;
+	mculib)
+		# Append library definition makefile fragment t-nds32-mculib.
+		# The software floating point library is included in mculib.
+		tmake_file="${tmake_file} nds32/t-nds32-mculib"
+		;;
+	*)
+		echo "Cannot accept --with-nds32-lib=$with_nds32_lib, available values are: newlib mculib" 1>&2
+		exit 1
+		;;
+	esac
+	;;
 pdp11-*-*)
 	tmake_file="pdp11/t-pdp11 t-fdpbit"
 	;;
diff --git a/libgcc/config/nds32/crtzero.S b/libgcc/config/nds32/crtzero.S
new file mode 100644
index 00000000000..65098698dba
--- /dev/null
+++ b/libgcc/config/nds32/crtzero.S
@@ -0,0 +1,103 @@
+/* The startup code sample of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+!!==============================================================================
+!!
+!!      crtzero.S
+!!
+!!      This is JUST A SAMPLE of nds32 startup code !!
+!!      You can refer this content and implement
+!!      the actual one in newlib/mculib.
+!!
+!!==============================================================================
+
+!!------------------------------------------------------------------------------
+!! Jump to start up code
+!!------------------------------------------------------------------------------
+	.section	.nds32_init, "ax"
+	j	_start
+
+!!------------------------------------------------------------------------------
+!! Startup code implementation
+!!------------------------------------------------------------------------------
+	.section	.text
+	.global	_start
+	.weak	_SDA_BASE_
+	.weak	_FP_BASE_
+	.align	2
+	.func	_start
+	.type	_start, @function
+_start:
+.L_fp_gp_lp_init:
+	la	$fp, _FP_BASE_		! init $fp
+	la	$gp, _SDA_BASE_		! init $gp for small data access
+	movi	$lp, 0			! init $lp
+
+.L_stack_init:
+	la	$sp, _stack		! init $sp
+	movi	$r0, -8			! align $sp to 8-byte (use 0xfffffff8)
+	and	$sp, $sp, $r0		! align $sp to 8-byte (filter out lower 3-bit)
+
+.L_bss_init:
+	! clear BSS, this process can be 4 time faster if data is 4 byte aligned
+	! if so, use swi.p instead of sbi.p
+	! the related stuff are defined in linker script
+	la	$r0, _edata		! get the starting addr of bss
+	la	$r2, _end		! get ending addr of bss
+	beq	$r0, $r2, .L_call_main	! if no bss just do nothing
+	movi	$r1, 0			! should be cleared to 0
+.L_clear_bss:
+	sbi.p	$r1, [$r0], 1		! Set 0 to bss
+	bne	$r0, $r2, .L_clear_bss	! Still bytes left to set
+
+!.L_stack_heap_check:
+!	la	$r0, _end		! init heap_end
+!	s.w	$r0, heap_end		! save it
+
+
+!.L_init_argc_argv:
+!	! argc/argv initialization if necessary; default implementation is in crt1.o
+!	la	$r9, _arg_init		! load address of _arg_init?
+!	beqz	$r9, .L4		! has _arg_init? no, go check main()
+!	addi	$sp, $sp, -512		! allocate space for command line + arguments
+!	move	$r6, $sp		! r6 = buffer addr of cmd line
+!	move	$r0, $r6		! r0 = buffer addr of cmd line
+!	syscall	6002			! get cmd line
+!	move	$r0, $r6		! r0 = buffer addr of cmd line
+!	addi	$r1, $r6, 256		! r1 = argv
+!	jral	$r9			! init argc/argv
+!	addi	$r1, $r6, 256		! r1 = argv
+
+.L_call_main:
+	! call main() if main() is provided
+	la	$r15, main		! load address of main
+	jral	$r15			! call main
+
+.L_terminate_program:
+	syscall	0x1			! use syscall 0x1 to terminate program
+	.size	_start, .-_start
+	.end
+
+!! ------------------------------------------------------------------------
diff --git a/libgcc/config/nds32/initfini.c b/libgcc/config/nds32/initfini.c
new file mode 100644
index 00000000000..7235148c5e3
--- /dev/null
+++ b/libgcc/config/nds32/initfini.c
@@ -0,0 +1,159 @@
+/* .init/.fini section handling + C++ global constructor/destructor
+   handling of Andes NDS32 cpu for GNU compiler.
+   This file is based on crtstuff.c, sol2-crti.asm, sol2-crtn.asm.
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+/*  Declare a pointer to void function type.  */
+typedef void (*func_ptr) (void);
+
+#ifdef CRT_BEGIN
+
+/* NOTE:  In order to be able to support SVR4 shared libraries, we arrange
+   to have one set of symbols { __CTOR_LIST__, __DTOR_LIST__, __CTOR_END__,
+   __DTOR_END__ } per root executable and also one set of these symbols
+   per shared library.  So in any given whole process image, we may have
+   multiple definitions of each of these symbols.  In order to prevent
+   these definitions from conflicting with one another, and in order to
+   ensure that the proper lists are used for the initialization/finalization
+   of each individual shared library (respectively), we give these symbols
+   only internal (i.e. `static') linkage, and we also make it a point to
+   refer to only the __CTOR_END__ symbol in crtfini.o and the __DTOR_LIST__
+   symbol in crtinit.o, where they are defined.  */
+
+static func_ptr __CTOR_LIST__[1] __attribute__ ((section (".ctors")))
+     = { (func_ptr) (-1) };
+
+static func_ptr __DTOR_LIST__[1] __attribute__ ((section (".dtors")))
+     = { (func_ptr) (-1) };
+
+/* Run all the global destructors on exit from the program.  */
+
+/* Some systems place the number of pointers in the first word of the
+   table.  On SVR4 however, that word is -1.  In all cases, the table is
+   null-terminated.  On SVR4, we start from the beginning of the list and
+   invoke each per-compilation-unit destructor routine in order
+   until we find that null.
+
+   Note that this function MUST be static.  There will be one of these
+   functions in each root executable and one in each shared library, but
+   although they all have the same code, each one is unique in that it
+   refers to one particular associated `__DTOR_LIST__' which belongs to the
+   same particular root executable or shared library file.  */
+
+static void __do_global_dtors (void)
+asm ("__do_global_dtors") __attribute__ ((section (".text")));
+
+static void
+__do_global_dtors (void)
+{
+  func_ptr *p;
+  for (p = __DTOR_LIST__ + 1; *p; p++)
+    (*p) ();
+}
+
+/* .init section start.
+   This must appear at the start of the .init section.  */
+
+asm ("\n\
+	.section .init\n\
+	.global _init\n\
+	.type	_init, @function\n\
+_init:\n\
+	! 1. store $fp\n\
+	! 2. adjust $fp by $sp\n\
+	! 3. adjust $sp\n\
+");
+
+/* .fini section start.
+   This must appear at the start of the .fini section.  */
+
+asm ("\n\
+	.section .fini\n\
+	.global _fini\n\
+	.type	_fini, @function\n\
+_fini:\n\
+	! 1. store $fp\n\
+	! 2. adjust $fp by $sp\n\
+	! 3. adjust $sp\n\
+	! 4. call __do_global_dtors\n\
+	j	__do_global_dtors\n\
+");
+
+#endif /* CRT_BEGIN */
+
+#ifdef CRT_END
+
+/* Define __dso_handle which would be needed for C++ library.
+   Since our elf-toolchain only builds programs with static link,
+   we can directly define 'void *__dso_handle = 0'.  */
+void *__dso_handle = 0;
+
+/* Put a word containing zero at the end of each of our two lists of function
+   addresses.  Note that the words defined here go into the .ctors and .dtors
+   sections of the crtend.o file, and since that file is always linked in
+   last, these words naturally end up at the very ends of the two lists
+   contained in these two sections.  */
+
+static func_ptr __CTOR_END__[1] __attribute__ ((section (".ctors")))
+     = { (func_ptr) 0 };
+
+static func_ptr __DTOR_END__[1] __attribute__ ((section (".dtors")))
+     = { (func_ptr) 0 };
+
+/* Run all global constructors for the program.
+   Note that they are run in reverse order.  */
+
+static void __do_global_ctors (void)
+asm ("__do_global_ctors") __attribute__ ((section (".text")));
+
+static void
+__do_global_ctors (void)
+{
+  func_ptr *p;
+  for (p = __CTOR_END__ - 1; *p != (func_ptr) -1; p--)
+    (*p) ();
+}
+
+/* .init section end.
+   This must live at the end of the .init section.  */
+
+asm ("\n\
+	.section .init\n\
+	! 1. call __do_global_ctors\n\
+	! 2. adjust back $sp\n\
+	! 3. restore $fp\n\
+	j	__do_global_ctors\n\
+");
+
+/* .fini section end.
+   This must live at the end of the .fini section.  */
+
+asm ("\n\
+	.section .fini\n\
+	! 1. adjust back $sp\n\
+	! 2. restore $fp\n\
+");
+
+#endif /* CRT_END */
diff --git a/libgcc/config/nds32/isr-library/adj_intr_lvl.inc b/libgcc/config/nds32/isr-library/adj_intr_lvl.inc
new file mode 100644
index 00000000000..6c0c8aaebad
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/adj_intr_lvl.inc
@@ -0,0 +1,38 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+.macro ADJ_INTR_LVL
+#if defined(NDS32_NESTED) /* Nested handler.  */
+	mfsr	$r3, $PSW
+	addi	$r3, $r3, #-0x1
+	mtsr	$r3, $PSW
+#elif defined(NDS32_NESTED_READY) /* Nested ready handler.  */
+	/* Save ipc and ipsw and lower INT level.  */
+	mfsr	$r3, $PSW
+	addi	$r3, $r3, #-0x2
+	mtsr	$r3, $PSW
+#else /* Not nested handler.  */
+#endif
+.endm
diff --git a/libgcc/config/nds32/isr-library/excp_isr.S b/libgcc/config/nds32/isr-library/excp_isr.S
new file mode 100644
index 00000000000..a68a8ec3313
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/excp_isr.S
@@ -0,0 +1,132 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include "save_mac_regs.inc"
+#include "save_fpu_regs.inc"
+#include "save_fpu_regs_00.inc"
+#include "save_fpu_regs_01.inc"
+#include "save_fpu_regs_02.inc"
+#include "save_fpu_regs_03.inc"
+#include "save_all.inc"
+#include "save_partial.inc"
+#include "adj_intr_lvl.inc"
+#include "restore_mac_regs.inc"
+#include "restore_fpu_regs_00.inc"
+#include "restore_fpu_regs_01.inc"
+#include "restore_fpu_regs_02.inc"
+#include "restore_fpu_regs_03.inc"
+#include "restore_fpu_regs.inc"
+#include "restore_all.inc"
+#include "restore_partial.inc"
+	.section .nds32_isr, "ax"       /* Put it in the section of 1st level handler. */
+	.align	1
+/*
+  First Level Handlers
+  1. First Level Handlers are invokded in vector section via jump instruction
+  with specific names for different configurations.
+  2. Naming Format: _nds32_e_SR_NT for exception handlers.
+		    _nds32_i_SR_NT for interrupt handlers.
+  2.1 All upper case letters are replaced with specific lower case letters encodings.
+  2.2 SR: Saved Registers
+      sa: Save All regs (context)
+      ps: Partial Save (all caller-saved regs)
+  2.3 NT: Nested Type
+      ns: nested
+      nn: not nested
+      nr: nested ready
+*/
+
+/*
+  This is original 16-byte vector size version.
+*/
+#ifdef NDS32_SAVE_ALL_REGS
+#if defined(NDS32_NESTED)
+	.globl	_nds32_e_sa_ns
+	.type	_nds32_e_sa_ns, @function
+_nds32_e_sa_ns:
+#elif defined(NDS32_NESTED_READY)
+	.globl	_nds32_e_sa_nr
+	.type	_nds32_e_sa_nr, @function
+_nds32_e_sa_nr:
+#else /* Not nested handler. */
+	.globl	_nds32_e_sa_nn
+	.type	_nds32_e_sa_nn, @function
+_nds32_e_sa_nn:
+#endif /* endif for Nest Type */
+#else /* not NDS32_SAVE_ALL_REGS */
+#if defined(NDS32_NESTED)
+	.globl	_nds32_e_ps_ns
+	.type	_nds32_e_ps_ns, @function
+_nds32_e_ps_ns:
+#elif defined(NDS32_NESTED_READY)
+	.globl	_nds32_e_ps_nr
+	.type	_nds32_e_ps_nr, @function
+_nds32_e_ps_nr:
+#else /* Not nested handler. */
+	.globl	_nds32_e_ps_nn
+	.type	_nds32_e_ps_nn, @function
+_nds32_e_ps_nn:
+#endif /* endif for Nest Type */
+#endif /* not NDS32_SAVE_ALL_REGS */
+
+/*
+  This is 16-byte vector size version.
+  The vector id was restored into $r0 in vector by compiler.
+*/
+#ifdef NDS32_SAVE_ALL_REGS
+        SAVE_ALL
+#else
+        SAVE_PARTIAL
+#endif
+	/* Prepare to call 2nd level handler. */
+	la	$r2, _nds32_jmptbl_00
+	lw	$r2, [$r2 + $r0 << #2]
+	ADJ_INTR_LVL	/* Adjust INTR level. $r3 is clobbered.  */
+	jral    $r2
+	/* Restore used registers. */
+#ifdef NDS32_SAVE_ALL_REGS
+	RESTORE_ALL
+#else
+	RESTORE_PARTIAL
+#endif
+	iret
+
+#ifdef NDS32_SAVE_ALL_REGS
+#if defined(NDS32_NESTED)
+	.size	_nds32_e_sa_ns, .-_nds32_e_sa_ns
+#elif defined(NDS32_NESTED_READY)
+	.size	_nds32_e_sa_nr, .-_nds32_e_sa_nr
+#else /* Not nested handler. */
+	.size	_nds32_e_sa_nn, .-_nds32_e_sa_nn
+#endif /* endif for Nest Type */
+#else /* not NDS32_SAVE_ALL_REGS */
+#if defined(NDS32_NESTED)
+	.size	_nds32_e_ps_ns, .-_nds32_e_ps_ns
+#elif defined(NDS32_NESTED_READY)
+	.size	_nds32_e_ps_nr, .-_nds32_e_ps_nr
+#else /* Not nested handler. */
+	.size	_nds32_e_ps_nn, .-_nds32_e_ps_nn
+#endif /* endif for Nest Type */
+#endif /* not NDS32_SAVE_ALL_REGS */
diff --git a/libgcc/config/nds32/isr-library/excp_isr_4b.S b/libgcc/config/nds32/isr-library/excp_isr_4b.S
new file mode 100644
index 00000000000..e37c2f62dd2
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/excp_isr_4b.S
@@ -0,0 +1,133 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include "save_mac_regs.inc"
+#include "save_fpu_regs.inc"
+#include "save_fpu_regs_00.inc"
+#include "save_fpu_regs_01.inc"
+#include "save_fpu_regs_02.inc"
+#include "save_fpu_regs_03.inc"
+#include "save_all.inc"
+#include "save_partial.inc"
+#include "adj_intr_lvl.inc"
+#include "restore_mac_regs.inc"
+#include "restore_fpu_regs_00.inc"
+#include "restore_fpu_regs_01.inc"
+#include "restore_fpu_regs_02.inc"
+#include "restore_fpu_regs_03.inc"
+#include "restore_fpu_regs.inc"
+#include "restore_all.inc"
+#include "restore_partial.inc"
+	.section .nds32_isr, "ax"       /* Put it in the section of 1st level handler. */
+	.align	1
+/*
+  First Level Handlers
+  1. First Level Handlers are invokded in vector section via jump instruction
+  with specific names for different configurations.
+  2. Naming Format: _nds32_e_SR_NT for exception handlers.
+		    _nds32_i_SR_NT for interrupt handlers.
+  2.1 All upper case letters are replaced with specific lower case letters encodings.
+  2.2 SR: Saved Registers
+      sa: Save All regs (context)
+      ps: Partial Save (all caller-saved regs)
+  2.3 NT: Nested Type
+      ns: nested
+      nn: not nested
+      nr: nested ready
+*/
+
+/*
+  This is 4-byte vector size version.
+  The "_4b" postfix was added for 4-byte version symbol.
+*/
+#ifdef NDS32_SAVE_ALL_REGS
+#if defined(NDS32_NESTED)
+	.globl	_nds32_e_sa_ns_4b
+	.type	_nds32_e_sa_ns_4b, @function
+_nds32_e_sa_ns_4b:
+#elif defined(NDS32_NESTED_READY)
+	.globl	_nds32_e_sa_nr_4b
+	.type	_nds32_e_sa_nr_4b, @function
+_nds32_e_sa_nr_4b:
+#else /* Not nested handler. */
+	.globl	_nds32_e_sa_nn_4b
+	.type	_nds32_e_sa_nn_4b, @function
+_nds32_e_sa_nn_4b:
+#endif /* endif for Nest Type */
+#else /* not NDS32_SAVE_ALL_REGS */
+#if defined(NDS32_NESTED)
+	.globl	_nds32_e_ps_ns_4b
+	.type	_nds32_e_ps_ns_4b, @function
+_nds32_e_ps_ns_4b:
+#elif defined(NDS32_NESTED_READY)
+	.globl	_nds32_e_ps_nr_4b
+	.type	_nds32_e_ps_nr_4b, @function
+_nds32_e_ps_nr_4b:
+#else /* Not nested handler. */
+	.globl	_nds32_e_ps_nn_4b
+	.type	_nds32_e_ps_nn_4b, @function
+_nds32_e_ps_nn_4b:
+#endif /* endif for Nest Type */
+#endif /* not NDS32_SAVE_ALL_REGS */
+
+/*
+  This is 4-byte vector size version.
+  The vector id was restored into $lp in vector by compiler.
+*/
+#ifdef NDS32_SAVE_ALL_REGS
+	SAVE_ALL_4B
+#else
+	SAVE_PARTIAL_4B
+#endif
+	/* Prepare to call 2nd level handler. */
+	la	$r2, _nds32_jmptbl_00
+	lw	$r2, [$r2 + $r0 << #2]
+	ADJ_INTR_LVL	/* Adjust INTR level. $r3 is clobbered.  */
+	jral    $r2
+	/* Restore used registers. */
+#ifdef NDS32_SAVE_ALL_REGS
+	RESTORE_ALL
+#else
+	RESTORE_PARTIAL
+#endif
+	iret
+
+#ifdef NDS32_SAVE_ALL_REGS
+#if defined(NDS32_NESTED)
+	.size	_nds32_e_sa_ns_4b, .-_nds32_e_sa_ns_4b
+#elif defined(NDS32_NESTED_READY)
+	.size	_nds32_e_sa_nr_4b, .-_nds32_e_sa_nr_4b
+#else /* Not nested handler. */
+	.size	_nds32_e_sa_nn_4b, .-_nds32_e_sa_nn_4b
+#endif /* endif for Nest Type */
+#else /* not NDS32_SAVE_ALL_REGS */
+#if defined(NDS32_NESTED)
+	.size	_nds32_e_ps_ns_4b, .-_nds32_e_ps_ns_4b
+#elif defined(NDS32_NESTED_READY)
+	.size	_nds32_e_ps_nr_4b, .-_nds32_e_ps_nr_4b
+#else /* Not nested handler. */
+	.size	_nds32_e_ps_nn_4b, .-_nds32_e_ps_nn_4b
+#endif /* endif for Nest Type */
+#endif /* not NDS32_SAVE_ALL_REGS */
diff --git a/libgcc/config/nds32/isr-library/intr_isr.S b/libgcc/config/nds32/isr-library/intr_isr.S
new file mode 100644
index 00000000000..4d9537474b9
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/intr_isr.S
@@ -0,0 +1,132 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include "save_mac_regs.inc"
+#include "save_fpu_regs.inc"
+#include "save_fpu_regs_00.inc"
+#include "save_fpu_regs_01.inc"
+#include "save_fpu_regs_02.inc"
+#include "save_fpu_regs_03.inc"
+#include "save_all.inc"
+#include "save_partial.inc"
+#include "adj_intr_lvl.inc"
+#include "restore_mac_regs.inc"
+#include "restore_fpu_regs_00.inc"
+#include "restore_fpu_regs_01.inc"
+#include "restore_fpu_regs_02.inc"
+#include "restore_fpu_regs_03.inc"
+#include "restore_fpu_regs.inc"
+#include "restore_all.inc"
+#include "restore_partial.inc"
+	.section .nds32_isr, "ax"       /* Put it in the section of 1st level handler. */
+	.align	1
+/*
+  First Level Handlers
+  1. First Level Handlers are invokded in vector section via jump instruction
+  with specific names for different configurations.
+  2. Naming Format: _nds32_e_SR_NT for exception handlers.
+		    _nds32_i_SR_NT for interrupt handlers.
+  2.1 All upper case letters are replaced with specific lower case letters encodings.
+  2.2 SR: Saved Registers
+      sa: Save All regs (context)
+      ps: Partial Save (all caller-saved regs)
+  2.3 NT: Nested Type
+      ns: nested
+      nn: not nested
+      nr: nested ready
+*/
+
+/*
+  This is original 16-byte vector size version.
+*/
+#ifdef NDS32_SAVE_ALL_REGS
+#if defined(NDS32_NESTED)
+	.globl	_nds32_i_sa_ns
+	.type	_nds32_i_sa_ns, @function
+_nds32_i_sa_ns:
+#elif defined(NDS32_NESTED_READY)
+	.globl	_nds32_i_sa_nr
+	.type	_nds32_i_sa_nr, @function
+_nds32_i_sa_nr:
+#else /* Not nested handler. */
+	.globl	_nds32_i_sa_nn
+	.type	_nds32_i_sa_nn, @function
+_nds32_i_sa_nn:
+#endif /* endif for Nest Type */
+#else /* not NDS32_SAVE_ALL_REGS */
+#if defined(NDS32_NESTED)
+	.globl	_nds32_i_ps_ns
+	.type	_nds32_i_ps_ns, @function
+_nds32_i_ps_ns:
+#elif defined(NDS32_NESTED_READY)
+	.globl	_nds32_i_ps_nr
+	.type	_nds32_i_ps_nr, @function
+_nds32_i_ps_nr:
+#else /* Not nested handler. */
+	.globl	_nds32_i_ps_nn
+	.type	_nds32_i_ps_nn, @function
+_nds32_i_ps_nn:
+#endif /* endif for Nest Type */
+#endif /* not NDS32_SAVE_ALL_REGS */
+
+/*
+  This is 16-byte vector size version.
+  The vector id was restored into $r0 in vector by compiler.
+*/
+#ifdef NDS32_SAVE_ALL_REGS
+        SAVE_ALL
+#else
+        SAVE_PARTIAL
+#endif
+	/* Prepare to call 2nd level handler. */
+	la	$r2, _nds32_jmptbl_09	/* For zero-based vcetor id.  */
+	lw	$r2, [$r2 + $r0 << #2]
+	ADJ_INTR_LVL	/* Adjust INTR level. $r3 is clobbered.  */
+	jral    $r2
+	/* Restore used registers. */
+#ifdef NDS32_SAVE_ALL_REGS
+	RESTORE_ALL
+#else
+	RESTORE_PARTIAL
+#endif
+	iret
+
+#ifdef NDS32_SAVE_ALL_REGS
+#if defined(NDS32_NESTED)
+	.size	_nds32_i_sa_ns, .-_nds32_i_sa_ns
+#elif defined(NDS32_NESTED_READY)
+	.size	_nds32_i_sa_nr, .-_nds32_i_sa_nr
+#else /* Not nested handler. */
+	.size	_nds32_i_sa_nn, .-_nds32_i_sa_nn
+#endif /* endif for Nest Type */
+#else /* not NDS32_SAVE_ALL_REGS */
+#if defined(NDS32_NESTED)
+	.size	_nds32_i_ps_ns, .-_nds32_i_ps_ns
+#elif defined(NDS32_NESTED_READY)
+	.size	_nds32_i_ps_nr, .-_nds32_i_ps_nr
+#else /* Not nested handler. */
+	.size	_nds32_i_ps_nn, .-_nds32_i_ps_nn
+#endif /* endif for Nest Type */
+#endif /* not NDS32_SAVE_ALL_REGS */
diff --git a/libgcc/config/nds32/isr-library/intr_isr_4b.S b/libgcc/config/nds32/isr-library/intr_isr_4b.S
new file mode 100644
index 00000000000..21e60e72ed7
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/intr_isr_4b.S
@@ -0,0 +1,134 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include "save_mac_regs.inc"
+#include "save_fpu_regs.inc"
+#include "save_fpu_regs_00.inc"
+#include "save_fpu_regs_01.inc"
+#include "save_fpu_regs_02.inc"
+#include "save_fpu_regs_03.inc"
+#include "save_all.inc"
+#include "save_partial.inc"
+#include "adj_intr_lvl.inc"
+#include "restore_mac_regs.inc"
+#include "restore_fpu_regs_00.inc"
+#include "restore_fpu_regs_01.inc"
+#include "restore_fpu_regs_02.inc"
+#include "restore_fpu_regs_03.inc"
+#include "restore_fpu_regs.inc"
+#include "restore_all.inc"
+#include "restore_partial.inc"
+	.section .nds32_isr, "ax"       /* Put it in the section of 1st level handler. */
+	.align	1
+/*
+  First Level Handlers
+  1. First Level Handlers are invokded in vector section via jump instruction
+  with specific names for different configurations.
+  2. Naming Format: _nds32_e_SR_NT for exception handlers.
+		    _nds32_i_SR_NT for interrupt handlers.
+  2.1 All upper case letters are replaced with specific lower case letters encodings.
+  2.2 SR: Saved Registers
+      sa: Save All regs (context)
+      ps: Partial Save (all caller-saved regs)
+  2.3 NT: Nested Type
+      ns: nested
+      nn: not nested
+      nr: nested ready
+*/
+
+/*
+  This is 4-byte vector size version.
+  The "_4b" postfix was added for 4-byte version symbol.
+*/
+#ifdef NDS32_SAVE_ALL_REGS
+#if defined(NDS32_NESTED)
+	.globl	_nds32_i_sa_ns_4b
+	.type	_nds32_i_sa_ns_4b, @function
+_nds32_i_sa_ns_4b:
+#elif defined(NDS32_NESTED_READY)
+	.globl	_nds32_i_sa_nr_4b
+	.type	_nds32_i_sa_nr_4b, @function
+_nds32_i_sa_nr_4b:
+#else /* Not nested handler. */
+	.globl	_nds32_i_sa_nn_4b
+	.type	_nds32_i_sa_nn_4b, @function
+_nds32_i_sa_nn_4b:
+#endif /* endif for Nest Type */
+#else /* not NDS32_SAVE_ALL_REGS */
+#if defined(NDS32_NESTED)
+	.globl	_nds32_i_ps_ns_4b
+	.type	_nds32_i_ps_ns_4b, @function
+_nds32_i_ps_ns_4b:
+#elif defined(NDS32_NESTED_READY)
+	.globl	_nds32_i_ps_nr_4b
+	.type	_nds32_i_ps_nr_4b, @function
+_nds32_i_ps_nr_4b:
+#else /* Not nested handler. */
+	.globl	_nds32_i_ps_nn_4b
+	.type	_nds32_i_ps_nn_4b, @function
+_nds32_i_ps_nn_4b:
+#endif /* endif for Nest Type */
+#endif /* not NDS32_SAVE_ALL_REGS */
+
+/*
+  This is 4-byte vector size version.
+  The vector id was restored into $lp in vector by compiler.
+*/
+#ifdef NDS32_SAVE_ALL_REGS
+	SAVE_ALL_4B
+#else
+        SAVE_PARTIAL_4B
+#endif
+	/* Prepare to call 2nd level handler. */
+	la	$r2, _nds32_jmptbl_00
+	lw	$r2, [$r2 + $r0 << #2]
+	addi    $r0, $r0, #-9	/* Make interrput vector id zero-based.  */
+	ADJ_INTR_LVL	/* Adjust INTR level. $r3 is clobbered.  */
+	jral    $r2
+	/* Restore used registers. */
+#ifdef NDS32_SAVE_ALL_REGS
+	RESTORE_ALL
+#else
+	RESTORE_PARTIAL
+#endif
+	iret
+
+#ifdef NDS32_SAVE_ALL_REGS
+#if defined(NDS32_NESTED)
+	.size	_nds32_i_sa_ns_4b, .-_nds32_i_sa_ns_4b
+#elif defined(NDS32_NESTED_READY)
+	.size	_nds32_i_sa_nr_4b, .-_nds32_i_sa_nr_4b
+#else /* Not nested handler. */
+	.size	_nds32_i_sa_nn_4b, .-_nds32_i_sa_nn_4b
+#endif /* endif for Nest Type */
+#else /* not NDS32_SAVE_ALL_REGS */
+#if defined(NDS32_NESTED)
+	.size	_nds32_i_ps_ns_4b, .-_nds32_i_ps_ns_4b
+#elif defined(NDS32_NESTED_READY)
+	.size	_nds32_i_ps_nr_4b, .-_nds32_i_ps_nr_4b
+#else /* Not nested handler. */
+	.size	_nds32_i_ps_nn_4b, .-_nds32_i_ps_nn_4b
+#endif /* endif for Nest Type */
+#endif /* not NDS32_SAVE_ALL_REGS */
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid00.S b/libgcc/config/nds32/isr-library/jmptbl_vid00.S
new file mode 100644
index 00000000000..f0ed85a8275
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid00.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.00, "a"
+	.align	2
+	.weak	_nds32_jmptbl_00
+	.type	_nds32_jmptbl_00, @object
+_nds32_jmptbl_00:
+	.word	0
+	.size	_nds32_jmptbl_00, .-_nds32_jmptbl_00
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid01.S b/libgcc/config/nds32/isr-library/jmptbl_vid01.S
new file mode 100644
index 00000000000..4c6b9c1d73d
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid01.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.01, "a"
+	.align	2
+	.weak	_nds32_jmptbl_01
+	.type	_nds32_jmptbl_01, @object
+_nds32_jmptbl_01:
+	.word	0
+	.size	_nds32_jmptbl_01, .-_nds32_jmptbl_01
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid02.S b/libgcc/config/nds32/isr-library/jmptbl_vid02.S
new file mode 100644
index 00000000000..83ba980ad36
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid02.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.02, "a"
+	.align	2
+	.weak	_nds32_jmptbl_02
+	.type	_nds32_jmptbl_02, @object
+_nds32_jmptbl_02:
+	.word	0
+	.size	_nds32_jmptbl_02, .-_nds32_jmptbl_02
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid03.S b/libgcc/config/nds32/isr-library/jmptbl_vid03.S
new file mode 100644
index 00000000000..47f11a4b86a
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid03.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.03, "a"
+	.align	2
+	.weak	_nds32_jmptbl_03
+	.type	_nds32_jmptbl_03, @object
+_nds32_jmptbl_03:
+	.word	0
+	.size	_nds32_jmptbl_03, .-_nds32_jmptbl_03
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid04.S b/libgcc/config/nds32/isr-library/jmptbl_vid04.S
new file mode 100644
index 00000000000..e3e7fb8c1da
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid04.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.04, "a"
+	.align	2
+	.weak	_nds32_jmptbl_04
+	.type	_nds32_jmptbl_04, @object
+_nds32_jmptbl_04:
+	.word	0
+	.size	_nds32_jmptbl_04, .-_nds32_jmptbl_04
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid05.S b/libgcc/config/nds32/isr-library/jmptbl_vid05.S
new file mode 100644
index 00000000000..32fa7eafd7b
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid05.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.05, "a"
+	.align	2
+	.weak	_nds32_jmptbl_05
+	.type	_nds32_jmptbl_05, @object
+_nds32_jmptbl_05:
+	.word	0
+	.size	_nds32_jmptbl_05, .-_nds32_jmptbl_05
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid06.S b/libgcc/config/nds32/isr-library/jmptbl_vid06.S
new file mode 100644
index 00000000000..df2d83acaa3
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid06.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.06, "a"
+	.align	2
+	.weak	_nds32_jmptbl_06
+	.type	_nds32_jmptbl_06, @object
+_nds32_jmptbl_06:
+	.word	0
+	.size	_nds32_jmptbl_06, .-_nds32_jmptbl_06
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid07.S b/libgcc/config/nds32/isr-library/jmptbl_vid07.S
new file mode 100644
index 00000000000..0070f7f5ae8
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid07.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.07, "a"
+	.align	2
+	.weak	_nds32_jmptbl_07
+	.type	_nds32_jmptbl_07, @object
+_nds32_jmptbl_07:
+	.word	0
+	.size	_nds32_jmptbl_07, .-_nds32_jmptbl_07
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid08.S b/libgcc/config/nds32/isr-library/jmptbl_vid08.S
new file mode 100644
index 00000000000..0b19e60b9df
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid08.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.08, "a"
+	.align	2
+	.weak	_nds32_jmptbl_08
+	.type	_nds32_jmptbl_08, @object
+_nds32_jmptbl_08:
+	.word	0
+	.size	_nds32_jmptbl_08, .-_nds32_jmptbl_08
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid09.S b/libgcc/config/nds32/isr-library/jmptbl_vid09.S
new file mode 100644
index 00000000000..b0e216b7520
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid09.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.09, "a"
+	.align	2
+	.weak	_nds32_jmptbl_09
+	.type	_nds32_jmptbl_09, @object
+_nds32_jmptbl_09:
+	.word	0
+	.size	_nds32_jmptbl_09, .-_nds32_jmptbl_09
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid10.S b/libgcc/config/nds32/isr-library/jmptbl_vid10.S
new file mode 100644
index 00000000000..bd378ed5f7a
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid10.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.10, "a"
+	.align	2
+	.weak	_nds32_jmptbl_10
+	.type	_nds32_jmptbl_10, @object
+_nds32_jmptbl_10:
+	.word	0
+	.size	_nds32_jmptbl_10, .-_nds32_jmptbl_10
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid11.S b/libgcc/config/nds32/isr-library/jmptbl_vid11.S
new file mode 100644
index 00000000000..9648ef347f0
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid11.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.11, "a"
+	.align	2
+	.weak	_nds32_jmptbl_11
+	.type	_nds32_jmptbl_11, @object
+_nds32_jmptbl_11:
+	.word	0
+	.size	_nds32_jmptbl_11, .-_nds32_jmptbl_11
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid12.S b/libgcc/config/nds32/isr-library/jmptbl_vid12.S
new file mode 100644
index 00000000000..0ab14e2249c
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid12.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.12, "a"
+	.align	2
+	.weak	_nds32_jmptbl_12
+	.type	_nds32_jmptbl_12, @object
+_nds32_jmptbl_12:
+	.word	0
+	.size	_nds32_jmptbl_12, .-_nds32_jmptbl_12
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid13.S b/libgcc/config/nds32/isr-library/jmptbl_vid13.S
new file mode 100644
index 00000000000..31664689df4
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid13.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.13, "a"
+	.align	2
+	.weak	_nds32_jmptbl_13
+	.type	_nds32_jmptbl_13, @object
+_nds32_jmptbl_13:
+	.word	0
+	.size	_nds32_jmptbl_13, .-_nds32_jmptbl_13
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid14.S b/libgcc/config/nds32/isr-library/jmptbl_vid14.S
new file mode 100644
index 00000000000..cb8d129d81f
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid14.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.14, "a"
+	.align	2
+	.weak	_nds32_jmptbl_14
+	.type	_nds32_jmptbl_14, @object
+_nds32_jmptbl_14:
+	.word	0
+	.size	_nds32_jmptbl_14, .-_nds32_jmptbl_14
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid15.S b/libgcc/config/nds32/isr-library/jmptbl_vid15.S
new file mode 100644
index 00000000000..bac9bc98407
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid15.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.15, "a"
+	.align	2
+	.weak	_nds32_jmptbl_15
+	.type	_nds32_jmptbl_15, @object
+_nds32_jmptbl_15:
+	.word	0
+	.size	_nds32_jmptbl_15, .-_nds32_jmptbl_15
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid16.S b/libgcc/config/nds32/isr-library/jmptbl_vid16.S
new file mode 100644
index 00000000000..9066f81cfde
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid16.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.16, "a"
+	.align	2
+	.weak	_nds32_jmptbl_16
+	.type	_nds32_jmptbl_16, @object
+_nds32_jmptbl_16:
+	.word	0
+	.size	_nds32_jmptbl_16, .-_nds32_jmptbl_16
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid17.S b/libgcc/config/nds32/isr-library/jmptbl_vid17.S
new file mode 100644
index 00000000000..60a8ba9ac4d
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid17.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.17, "a"
+	.align	2
+	.weak	_nds32_jmptbl_17
+	.type	_nds32_jmptbl_17, @object
+_nds32_jmptbl_17:
+	.word	0
+	.size	_nds32_jmptbl_17, .-_nds32_jmptbl_17
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid18.S b/libgcc/config/nds32/isr-library/jmptbl_vid18.S
new file mode 100644
index 00000000000..a926fecc0b6
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid18.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.18, "a"
+	.align	2
+	.weak	_nds32_jmptbl_18
+	.type	_nds32_jmptbl_18, @object
+_nds32_jmptbl_18:
+	.word	0
+	.size	_nds32_jmptbl_18, .-_nds32_jmptbl_18
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid19.S b/libgcc/config/nds32/isr-library/jmptbl_vid19.S
new file mode 100644
index 00000000000..064ace009bb
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid19.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.19, "a"
+	.align	2
+	.weak	_nds32_jmptbl_19
+	.type	_nds32_jmptbl_19, @object
+_nds32_jmptbl_19:
+	.word	0
+	.size	_nds32_jmptbl_19, .-_nds32_jmptbl_19
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid20.S b/libgcc/config/nds32/isr-library/jmptbl_vid20.S
new file mode 100644
index 00000000000..e75bc71fbb6
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid20.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.20, "a"
+	.align	2
+	.weak	_nds32_jmptbl_20
+	.type	_nds32_jmptbl_20, @object
+_nds32_jmptbl_20:
+	.word	0
+	.size	_nds32_jmptbl_20, .-_nds32_jmptbl_20
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid21.S b/libgcc/config/nds32/isr-library/jmptbl_vid21.S
new file mode 100644
index 00000000000..0c3d2b871c7
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid21.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.21, "a"
+	.align	2
+	.weak	_nds32_jmptbl_21
+	.type	_nds32_jmptbl_21, @object
+_nds32_jmptbl_21:
+	.word	0
+	.size	_nds32_jmptbl_21, .-_nds32_jmptbl_21
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid22.S b/libgcc/config/nds32/isr-library/jmptbl_vid22.S
new file mode 100644
index 00000000000..415bf9f75e8
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid22.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.22, "a"
+	.align	2
+	.weak	_nds32_jmptbl_22
+	.type	_nds32_jmptbl_22, @object
+_nds32_jmptbl_22:
+	.word	0
+	.size	_nds32_jmptbl_22, .-_nds32_jmptbl_22
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid23.S b/libgcc/config/nds32/isr-library/jmptbl_vid23.S
new file mode 100644
index 00000000000..1efe31099c2
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid23.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.23, "a"
+	.align	2
+	.weak	_nds32_jmptbl_23
+	.type	_nds32_jmptbl_23, @object
+_nds32_jmptbl_23:
+	.word	0
+	.size	_nds32_jmptbl_23, .-_nds32_jmptbl_23
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid24.S b/libgcc/config/nds32/isr-library/jmptbl_vid24.S
new file mode 100644
index 00000000000..bb27eaa0812
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid24.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.24, "a"
+	.align	2
+	.weak	_nds32_jmptbl_24
+	.type	_nds32_jmptbl_24, @object
+_nds32_jmptbl_24:
+	.word	0
+	.size	_nds32_jmptbl_24, .-_nds32_jmptbl_24
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid25.S b/libgcc/config/nds32/isr-library/jmptbl_vid25.S
new file mode 100644
index 00000000000..ca64f8c8bad
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid25.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.25, "a"
+	.align	2
+	.weak	_nds32_jmptbl_25
+	.type	_nds32_jmptbl_25, @object
+_nds32_jmptbl_25:
+	.word	0
+	.size	_nds32_jmptbl_25, .-_nds32_jmptbl_25
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid26.S b/libgcc/config/nds32/isr-library/jmptbl_vid26.S
new file mode 100644
index 00000000000..95feab094fd
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid26.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.26, "a"
+	.align	2
+	.weak	_nds32_jmptbl_26
+	.type	_nds32_jmptbl_26, @object
+_nds32_jmptbl_26:
+	.word	0
+	.size	_nds32_jmptbl_26, .-_nds32_jmptbl_26
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid27.S b/libgcc/config/nds32/isr-library/jmptbl_vid27.S
new file mode 100644
index 00000000000..2bb9eabe6a4
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid27.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.27, "a"
+	.align	2
+	.weak	_nds32_jmptbl_27
+	.type	_nds32_jmptbl_27, @object
+_nds32_jmptbl_27:
+	.word	0
+	.size	_nds32_jmptbl_27, .-_nds32_jmptbl_27
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid28.S b/libgcc/config/nds32/isr-library/jmptbl_vid28.S
new file mode 100644
index 00000000000..57772ba494d
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid28.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.28, "a"
+	.align	2
+	.weak	_nds32_jmptbl_28
+	.type	_nds32_jmptbl_28, @object
+_nds32_jmptbl_28:
+	.word	0
+	.size	_nds32_jmptbl_28, .-_nds32_jmptbl_28
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid29.S b/libgcc/config/nds32/isr-library/jmptbl_vid29.S
new file mode 100644
index 00000000000..c69d7398eb1
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid29.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.29, "a"
+	.align	2
+	.weak	_nds32_jmptbl_29
+	.type	_nds32_jmptbl_29, @object
+_nds32_jmptbl_29:
+	.word	0
+	.size	_nds32_jmptbl_29, .-_nds32_jmptbl_29
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid30.S b/libgcc/config/nds32/isr-library/jmptbl_vid30.S
new file mode 100644
index 00000000000..f739c5821d7
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid30.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.30, "a"
+	.align	2
+	.weak	_nds32_jmptbl_30
+	.type	_nds32_jmptbl_30, @object
+_nds32_jmptbl_30:
+	.word	0
+	.size	_nds32_jmptbl_30, .-_nds32_jmptbl_30
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid31.S b/libgcc/config/nds32/isr-library/jmptbl_vid31.S
new file mode 100644
index 00000000000..4997f4e9cc8
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid31.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.31, "a"
+	.align	2
+	.weak	_nds32_jmptbl_31
+	.type	_nds32_jmptbl_31, @object
+_nds32_jmptbl_31:
+	.word	0
+	.size	_nds32_jmptbl_31, .-_nds32_jmptbl_31
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid32.S b/libgcc/config/nds32/isr-library/jmptbl_vid32.S
new file mode 100644
index 00000000000..1cde3fab097
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid32.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.32, "a"
+	.align	2
+	.weak	_nds32_jmptbl_32
+	.type	_nds32_jmptbl_32, @object
+_nds32_jmptbl_32:
+	.word	0
+	.size	_nds32_jmptbl_32, .-_nds32_jmptbl_32
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid33.S b/libgcc/config/nds32/isr-library/jmptbl_vid33.S
new file mode 100644
index 00000000000..84edda36751
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid33.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.33, "a"
+	.align	2
+	.weak	_nds32_jmptbl_33
+	.type	_nds32_jmptbl_33, @object
+_nds32_jmptbl_33:
+	.word	0
+	.size	_nds32_jmptbl_33, .-_nds32_jmptbl_33
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid34.S b/libgcc/config/nds32/isr-library/jmptbl_vid34.S
new file mode 100644
index 00000000000..82dc9f1dc24
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid34.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.34, "a"
+	.align	2
+	.weak	_nds32_jmptbl_34
+	.type	_nds32_jmptbl_34, @object
+_nds32_jmptbl_34:
+	.word	0
+	.size	_nds32_jmptbl_34, .-_nds32_jmptbl_34
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid35.S b/libgcc/config/nds32/isr-library/jmptbl_vid35.S
new file mode 100644
index 00000000000..c99fc6cd996
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid35.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.35, "a"
+	.align	2
+	.weak	_nds32_jmptbl_35
+	.type	_nds32_jmptbl_35, @object
+_nds32_jmptbl_35:
+	.word	0
+	.size	_nds32_jmptbl_35, .-_nds32_jmptbl_35
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid36.S b/libgcc/config/nds32/isr-library/jmptbl_vid36.S
new file mode 100644
index 00000000000..9154d713c40
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid36.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.36, "a"
+	.align	2
+	.weak	_nds32_jmptbl_36
+	.type	_nds32_jmptbl_36, @object
+_nds32_jmptbl_36:
+	.word	0
+	.size	_nds32_jmptbl_36, .-_nds32_jmptbl_36
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid37.S b/libgcc/config/nds32/isr-library/jmptbl_vid37.S
new file mode 100644
index 00000000000..1f3acfd2c49
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid37.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.37, "a"
+	.align	2
+	.weak	_nds32_jmptbl_37
+	.type	_nds32_jmptbl_37, @object
+_nds32_jmptbl_37:
+	.word	0
+	.size	_nds32_jmptbl_37, .-_nds32_jmptbl_37
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid38.S b/libgcc/config/nds32/isr-library/jmptbl_vid38.S
new file mode 100644
index 00000000000..0ff99b02235
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid38.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.38, "a"
+	.align	2
+	.weak	_nds32_jmptbl_38
+	.type	_nds32_jmptbl_38, @object
+_nds32_jmptbl_38:
+	.word	0
+	.size	_nds32_jmptbl_38, .-_nds32_jmptbl_38
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid39.S b/libgcc/config/nds32/isr-library/jmptbl_vid39.S
new file mode 100644
index 00000000000..3fe74367c46
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid39.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.39, "a"
+	.align	2
+	.weak	_nds32_jmptbl_39
+	.type	_nds32_jmptbl_39, @object
+_nds32_jmptbl_39:
+	.word	0
+	.size	_nds32_jmptbl_39, .-_nds32_jmptbl_39
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid40.S b/libgcc/config/nds32/isr-library/jmptbl_vid40.S
new file mode 100644
index 00000000000..fcd05dc627d
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid40.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.40, "a"
+	.align	2
+	.weak	_nds32_jmptbl_40
+	.type	_nds32_jmptbl_40, @object
+_nds32_jmptbl_40:
+	.word	0
+	.size	_nds32_jmptbl_40, .-_nds32_jmptbl_40
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid41.S b/libgcc/config/nds32/isr-library/jmptbl_vid41.S
new file mode 100644
index 00000000000..0ec546a7f5b
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid41.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.41, "a"
+	.align	2
+	.weak	_nds32_jmptbl_41
+	.type	_nds32_jmptbl_41, @object
+_nds32_jmptbl_41:
+	.word	0
+	.size	_nds32_jmptbl_41, .-_nds32_jmptbl_41
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid42.S b/libgcc/config/nds32/isr-library/jmptbl_vid42.S
new file mode 100644
index 00000000000..761ef769089
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid42.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.42, "a"
+	.align	2
+	.weak	_nds32_jmptbl_42
+	.type	_nds32_jmptbl_42, @object
+_nds32_jmptbl_42:
+	.word	0
+	.size	_nds32_jmptbl_42, .-_nds32_jmptbl_42
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid43.S b/libgcc/config/nds32/isr-library/jmptbl_vid43.S
new file mode 100644
index 00000000000..0b2fc0eeedd
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid43.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.43, "a"
+	.align	2
+	.weak	_nds32_jmptbl_43
+	.type	_nds32_jmptbl_43, @object
+_nds32_jmptbl_43:
+	.word	0
+	.size	_nds32_jmptbl_43, .-_nds32_jmptbl_43
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid44.S b/libgcc/config/nds32/isr-library/jmptbl_vid44.S
new file mode 100644
index 00000000000..0fc7e7e1662
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid44.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.44, "a"
+	.align	2
+	.weak	_nds32_jmptbl_44
+	.type	_nds32_jmptbl_44, @object
+_nds32_jmptbl_44:
+	.word	0
+	.size	_nds32_jmptbl_44, .-_nds32_jmptbl_44
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid45.S b/libgcc/config/nds32/isr-library/jmptbl_vid45.S
new file mode 100644
index 00000000000..725d14483bf
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid45.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.45, "a"
+	.align	2
+	.weak	_nds32_jmptbl_45
+	.type	_nds32_jmptbl_45, @object
+_nds32_jmptbl_45:
+	.word	0
+	.size	_nds32_jmptbl_45, .-_nds32_jmptbl_45
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid46.S b/libgcc/config/nds32/isr-library/jmptbl_vid46.S
new file mode 100644
index 00000000000..6b4253ada9d
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid46.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.46, "a"
+	.align	2
+	.weak	_nds32_jmptbl_46
+	.type	_nds32_jmptbl_46, @object
+_nds32_jmptbl_46:
+	.word	0
+	.size	_nds32_jmptbl_46, .-_nds32_jmptbl_46
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid47.S b/libgcc/config/nds32/isr-library/jmptbl_vid47.S
new file mode 100644
index 00000000000..460e8509bcc
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid47.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.47, "a"
+	.align	2
+	.weak	_nds32_jmptbl_47
+	.type	_nds32_jmptbl_47, @object
+_nds32_jmptbl_47:
+	.word	0
+	.size	_nds32_jmptbl_47, .-_nds32_jmptbl_47
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid48.S b/libgcc/config/nds32/isr-library/jmptbl_vid48.S
new file mode 100644
index 00000000000..d481e50e290
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid48.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.48, "a"
+	.align	2
+	.weak	_nds32_jmptbl_48
+	.type	_nds32_jmptbl_48, @object
+_nds32_jmptbl_48:
+	.word	0
+	.size	_nds32_jmptbl_48, .-_nds32_jmptbl_48
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid49.S b/libgcc/config/nds32/isr-library/jmptbl_vid49.S
new file mode 100644
index 00000000000..4cea0b7e434
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid49.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.49, "a"
+	.align	2
+	.weak	_nds32_jmptbl_49
+	.type	_nds32_jmptbl_49, @object
+_nds32_jmptbl_49:
+	.word	0
+	.size	_nds32_jmptbl_49, .-_nds32_jmptbl_49
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid50.S b/libgcc/config/nds32/isr-library/jmptbl_vid50.S
new file mode 100644
index 00000000000..dd15a384570
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid50.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.50, "a"
+	.align	2
+	.weak	_nds32_jmptbl_50
+	.type	_nds32_jmptbl_50, @object
+_nds32_jmptbl_50:
+	.word	0
+	.size	_nds32_jmptbl_50, .-_nds32_jmptbl_50
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid51.S b/libgcc/config/nds32/isr-library/jmptbl_vid51.S
new file mode 100644
index 00000000000..02cf8dfb2f5
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid51.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.51, "a"
+	.align	2
+	.weak	_nds32_jmptbl_51
+	.type	_nds32_jmptbl_51, @object
+_nds32_jmptbl_51:
+	.word	0
+	.size	_nds32_jmptbl_51, .-_nds32_jmptbl_51
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid52.S b/libgcc/config/nds32/isr-library/jmptbl_vid52.S
new file mode 100644
index 00000000000..5bc784611dd
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid52.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.52, "a"
+	.align	2
+	.weak	_nds32_jmptbl_52
+	.type	_nds32_jmptbl_52, @object
+_nds32_jmptbl_52:
+	.word	0
+	.size	_nds32_jmptbl_52, .-_nds32_jmptbl_52
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid53.S b/libgcc/config/nds32/isr-library/jmptbl_vid53.S
new file mode 100644
index 00000000000..94f0dabcb44
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid53.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.53, "a"
+	.align	2
+	.weak	_nds32_jmptbl_53
+	.type	_nds32_jmptbl_53, @object
+_nds32_jmptbl_53:
+	.word	0
+	.size	_nds32_jmptbl_53, .-_nds32_jmptbl_53
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid54.S b/libgcc/config/nds32/isr-library/jmptbl_vid54.S
new file mode 100644
index 00000000000..f13d6895bed
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid54.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.54, "a"
+	.align	2
+	.weak	_nds32_jmptbl_54
+	.type	_nds32_jmptbl_54, @object
+_nds32_jmptbl_54:
+	.word	0
+	.size	_nds32_jmptbl_54, .-_nds32_jmptbl_54
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid55.S b/libgcc/config/nds32/isr-library/jmptbl_vid55.S
new file mode 100644
index 00000000000..521af640669
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid55.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.55, "a"
+	.align	2
+	.weak	_nds32_jmptbl_55
+	.type	_nds32_jmptbl_55, @object
+_nds32_jmptbl_55:
+	.word	0
+	.size	_nds32_jmptbl_55, .-_nds32_jmptbl_55
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid56.S b/libgcc/config/nds32/isr-library/jmptbl_vid56.S
new file mode 100644
index 00000000000..2c01ed2c341
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid56.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.56, "a"
+	.align	2
+	.weak	_nds32_jmptbl_56
+	.type	_nds32_jmptbl_56, @object
+_nds32_jmptbl_56:
+	.word	0
+	.size	_nds32_jmptbl_56, .-_nds32_jmptbl_56
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid57.S b/libgcc/config/nds32/isr-library/jmptbl_vid57.S
new file mode 100644
index 00000000000..58d4c1d72b0
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid57.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.57, "a"
+	.align	2
+	.weak	_nds32_jmptbl_57
+	.type	_nds32_jmptbl_57, @object
+_nds32_jmptbl_57:
+	.word	0
+	.size	_nds32_jmptbl_57, .-_nds32_jmptbl_57
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid58.S b/libgcc/config/nds32/isr-library/jmptbl_vid58.S
new file mode 100644
index 00000000000..ceb7711c3cf
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid58.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.58, "a"
+	.align	2
+	.weak	_nds32_jmptbl_58
+	.type	_nds32_jmptbl_58, @object
+_nds32_jmptbl_58:
+	.word	0
+	.size	_nds32_jmptbl_58, .-_nds32_jmptbl_58
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid59.S b/libgcc/config/nds32/isr-library/jmptbl_vid59.S
new file mode 100644
index 00000000000..527a1f52be6
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid59.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.59, "a"
+	.align	2
+	.weak	_nds32_jmptbl_59
+	.type	_nds32_jmptbl_59, @object
+_nds32_jmptbl_59:
+	.word	0
+	.size	_nds32_jmptbl_59, .-_nds32_jmptbl_59
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid60.S b/libgcc/config/nds32/isr-library/jmptbl_vid60.S
new file mode 100644
index 00000000000..eedd8b88807
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid60.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.60, "a"
+	.align	2
+	.weak	_nds32_jmptbl_60
+	.type	_nds32_jmptbl_60, @object
+_nds32_jmptbl_60:
+	.word	0
+	.size	_nds32_jmptbl_60, .-_nds32_jmptbl_60
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid61.S b/libgcc/config/nds32/isr-library/jmptbl_vid61.S
new file mode 100644
index 00000000000..e9813128491
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid61.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.61, "a"
+	.align	2
+	.weak	_nds32_jmptbl_61
+	.type	_nds32_jmptbl_61, @object
+_nds32_jmptbl_61:
+	.word	0
+	.size	_nds32_jmptbl_61, .-_nds32_jmptbl_61
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid62.S b/libgcc/config/nds32/isr-library/jmptbl_vid62.S
new file mode 100644
index 00000000000..ef66f2b7e07
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid62.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.62, "a"
+	.align	2
+	.weak	_nds32_jmptbl_62
+	.type	_nds32_jmptbl_62, @object
+_nds32_jmptbl_62:
+	.word	0
+	.size	_nds32_jmptbl_62, .-_nds32_jmptbl_62
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid63.S b/libgcc/config/nds32/isr-library/jmptbl_vid63.S
new file mode 100644
index 00000000000..95e38ba5eb1
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid63.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.63, "a"
+	.align	2
+	.weak	_nds32_jmptbl_63
+	.type	_nds32_jmptbl_63, @object
+_nds32_jmptbl_63:
+	.word	0
+	.size	_nds32_jmptbl_63, .-_nds32_jmptbl_63
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid64.S b/libgcc/config/nds32/isr-library/jmptbl_vid64.S
new file mode 100644
index 00000000000..f27b6df9439
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid64.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.64, "a"
+	.align	2
+	.weak	_nds32_jmptbl_64
+	.type	_nds32_jmptbl_64, @object
+_nds32_jmptbl_64:
+	.word	0
+	.size	_nds32_jmptbl_64, .-_nds32_jmptbl_64
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid65.S b/libgcc/config/nds32/isr-library/jmptbl_vid65.S
new file mode 100644
index 00000000000..69d83c67467
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid65.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.65, "a"
+	.align	2
+	.weak	_nds32_jmptbl_65
+	.type	_nds32_jmptbl_65, @object
+_nds32_jmptbl_65:
+	.word	0
+	.size	_nds32_jmptbl_65, .-_nds32_jmptbl_65
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid66.S b/libgcc/config/nds32/isr-library/jmptbl_vid66.S
new file mode 100644
index 00000000000..3474d05a5d9
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid66.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.66, "a"
+	.align	2
+	.weak	_nds32_jmptbl_66
+	.type	_nds32_jmptbl_66, @object
+_nds32_jmptbl_66:
+	.word	0
+	.size	_nds32_jmptbl_66, .-_nds32_jmptbl_66
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid67.S b/libgcc/config/nds32/isr-library/jmptbl_vid67.S
new file mode 100644
index 00000000000..8bbb5163f69
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid67.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.67, "a"
+	.align	2
+	.weak	_nds32_jmptbl_67
+	.type	_nds32_jmptbl_67, @object
+_nds32_jmptbl_67:
+	.word	0
+	.size	_nds32_jmptbl_67, .-_nds32_jmptbl_67
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid68.S b/libgcc/config/nds32/isr-library/jmptbl_vid68.S
new file mode 100644
index 00000000000..fc875055818
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid68.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.68, "a"
+	.align	2
+	.weak	_nds32_jmptbl_68
+	.type	_nds32_jmptbl_68, @object
+_nds32_jmptbl_68:
+	.word	0
+	.size	_nds32_jmptbl_68, .-_nds32_jmptbl_68
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid69.S b/libgcc/config/nds32/isr-library/jmptbl_vid69.S
new file mode 100644
index 00000000000..78847706f51
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid69.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.69, "a"
+	.align	2
+	.weak	_nds32_jmptbl_69
+	.type	_nds32_jmptbl_69, @object
+_nds32_jmptbl_69:
+	.word	0
+	.size	_nds32_jmptbl_69, .-_nds32_jmptbl_69
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid70.S b/libgcc/config/nds32/isr-library/jmptbl_vid70.S
new file mode 100644
index 00000000000..0f41e21d4db
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid70.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.70, "a"
+	.align	2
+	.weak	_nds32_jmptbl_70
+	.type	_nds32_jmptbl_70, @object
+_nds32_jmptbl_70:
+	.word	0
+	.size	_nds32_jmptbl_70, .-_nds32_jmptbl_70
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid71.S b/libgcc/config/nds32/isr-library/jmptbl_vid71.S
new file mode 100644
index 00000000000..5aab1252e1b
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid71.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.71, "a"
+	.align	2
+	.weak	_nds32_jmptbl_71
+	.type	_nds32_jmptbl_71, @object
+_nds32_jmptbl_71:
+	.word	0
+	.size	_nds32_jmptbl_71, .-_nds32_jmptbl_71
diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid72.S b/libgcc/config/nds32/isr-library/jmptbl_vid72.S
new file mode 100644
index 00000000000..6d40bfffb75
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/jmptbl_vid72.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_jmptbl.72, "a"
+	.align	2
+	.weak	_nds32_jmptbl_72
+	.type	_nds32_jmptbl_72, @object
+_nds32_jmptbl_72:
+	.word	0
+	.size	_nds32_jmptbl_72, .-_nds32_jmptbl_72
diff --git a/libgcc/config/nds32/isr-library/nmih.S b/libgcc/config/nds32/isr-library/nmih.S
new file mode 100644
index 00000000000..083ec98023c
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/nmih.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_nmih, "a"
+	.align	2
+	.weak	_nds32_nmih
+	.type	_nds32_nmih, @object
+_nds32_nmih:
+	.word	0
+	.size	_nds32_nmih, .-_nds32_nmih
diff --git a/libgcc/config/nds32/isr-library/reset.S b/libgcc/config/nds32/isr-library/reset.S
new file mode 100644
index 00000000000..3f539de48ea
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/reset.S
@@ -0,0 +1,130 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section .nds32_isr, "ax"	/* Put it in the section of 1st level handler.  */
+	.align	1
+	.weak	_SDA_BASE_	/* For reset handler only.  */
+	.weak	_FP_BASE_	/* For reset handler only.  */
+	.weak	_nds32_init_mem	/* User defined memory initialization function.  */
+	.globl	_start
+	.globl	_nds32_reset
+	.type	_nds32_reset, @function
+_nds32_reset:
+_start:
+#ifdef  NDS32_EXT_EX9
+	.no_ex9_begin
+#endif
+	/* Handle NMI and warm boot if any of them exists.  */
+	beqz	$sp, 1f		/* Reset, NMI or warm boot?  */
+	/* Either NMI or warm boot; save all regs.  */
+
+	/* Preserve registers for context-switching.  */
+#ifdef __NDS32_REDUCED_REGS__
+	/* For 16-reg mode.  */
+	smw.adm $r0, [$sp], $r10, #0x0
+	smw.adm $r15, [$sp], $r15, #0xf
+#else
+	/* For 32-reg mode.  */
+	smw.adm $r0, [$sp], $r27, #0xf
+#endif
+#ifdef NDS32_EXT_IFC
+	mfusr   $r1, $IFC_LP
+	smw.adm $r1, [$sp], $r2, #0x0	/* Save extra $r2 to keep
+					   stack 8-byte alignment.  */
+#endif
+
+	la	$gp, _SDA_BASE_	/* Init GP for small data access.  */
+	move	$r0, $sp	/* Init parameter.  */
+	mfsr	$r1, $ITYPE	/* Check ITYPE for NMI or warm boot.  */
+	andi	$r1, $r1, #0xf
+	addi	$r1, $r1, #-1
+	beqz	$r1, 2f		/* Warm boot if true.  */
+	l.w	$r15, _nds32_nmih	/* Load NMI handler.  */
+	j	3f
+2:
+	l.w	$r15, _nds32_wrh	/* Load warm boot handler.  */
+3:
+	beqz    $r15, 1f	/* If no handler, do cold boot.  */
+	jral    $r15		/* Call handler.  */
+	bnez    $r0, 1f		/* If fail to resume, do cold boot.  */
+
+	/* Restore registers for context-switching.  */
+#ifdef NDS32_EXT_IFC
+	lmw.bim	$r1, [$sp], $r2, #0x0	/* Restore extra $r2 to keep
+					   stack 8-byte alignment.  */
+	mtusr   $r1, $IFC_LP
+#endif
+#ifdef __NDS32_REDUCED_REGS__
+	/* For 16-reg mode.  */
+	lmw.bim	$r15, [$sp], $r15, #0xf
+	lmw.bim	$r0, [$sp], $r10, #0x0
+#else
+	/* For 32-reg mode.  */
+	lmw.bim $r0, [$sp], $r27, #0xf
+#endif
+	iret	/* Resume operation.  */
+
+
+1:	/* Cold boot.  */
+	/* Set IVB.ESZ = 1 (vector table entry size = 16 bytes)  */
+	mfsr    $r0, $IVB
+	li	$r1, #0xffff3fff
+	and	$r0, $r0, $r1
+	ori	$r0, $r0, #0x4000
+	mtsr    $r0, $IVB
+	dsb
+
+	la	$gp, _SDA_BASE_		/* Init $gp.  */
+	la	$fp, _FP_BASE_		/* Init $fp.  */
+	la	$sp, _stack		/* Init $sp.  */
+#ifdef  NDS32_EXT_EX9
+/*
+ *	Initialize the table base of EX9 instruction
+ *	ex9 generation needs to disable before the ITB is set
+ */
+	mfsr    $r0, $MSC_CFG	/* Check if HW support of EX9.  */
+	srli	$r0, $r0, 24
+	andi	$r0, $r0, 0x1
+	beqz	$r0, 4f		/* Zero means HW does not support EX9.  */
+	la      $r0, _ITB_BASE_	/* Init $ITB.  */
+	mtusr   $r0, $ITB
+	.no_ex9_end
+4:
+#endif
+	la	$r15, _nds32_init_mem	/* Call DRAM init. _nds32_init_mem
+					  may written by C language.  */
+	beqz	$r15, 6f
+	jral	$r15
+6:
+	l.w	$r15, _nds32_jmptbl_00	/* Load reset handler.  */
+	jral	$r15
+/* Reset handler() should never return in a RTOS or non-OS system.
+   In case it does return, an exception will be generated.
+   This exception will be caught either by default break handler or by EDM.
+   Default break handle may just do an infinite loop.
+   EDM will notify GDB and GDB will regain control when the ID is 0x7fff. */
+5:
+	break    #0x7fff
+	.size	_nds32_reset, .-_nds32_reset
diff --git a/libgcc/config/nds32/isr-library/reset_4b.S b/libgcc/config/nds32/isr-library/reset_4b.S
new file mode 100644
index 00000000000..23b821a1aaf
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/reset_4b.S
@@ -0,0 +1,131 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section .nds32_isr, "ax"	/* Put it in the section of 1st level handler.  */
+	.align	1
+	.weak	_SDA_BASE_	/* For reset handler only.  */
+	.weak	_FP_BASE_	/* For reset handler only.  */
+	.weak	_nds32_init_mem	/* User defined memory initialization function.  */
+	.globl	_start
+	.globl	_nds32_reset_4b
+	.type	_nds32_reset_4b, @function
+_nds32_reset_4b:
+_start:
+#ifdef  NDS32_EXT_EX9
+	.no_ex9_begin
+#endif
+	/* Handle NMI and warm boot if any of them exists.  */
+	beqz	$sp, 1f		/* Reset, NMI or warm boot?  */
+	/* Either NMI or warm boot; save all regs.  */
+
+	/* Preserve registers for context-switching.  */
+#ifdef __NDS32_REDUCED_REGS__
+	/* For 16-reg mode.  */
+	smw.adm $r0, [$sp], $r10, #0x0
+	smw.adm $r15, [$sp], $r15, #0xf
+#else
+	/* For 32-reg mode.  */
+	smw.adm $r0, [$sp], $r27, #0xf
+#endif
+#ifdef NDS32_EXT_IFC
+	mfusr   $r1, $IFC_LP
+	smw.adm $r1, [$sp], $r2, #0x0	/* Save extra $r2 to keep
+					   stack 8-byte alignment.  */
+#endif
+
+	la	$gp, _SDA_BASE_	/* Init GP for small data access.  */
+	move	$r0, $sp	/* Init parameter.  */
+	mfsr	$r1, $ITYPE	/* Check ITYPE for NMI or warm boot.  */
+	andi	$r1, $r1, #0xf
+	addi	$r1, $r1, #-1
+	beqz	$r1, 2f		/* Warm boot if true.  */
+	l.w	$r15, _nds32_nmih	/* Load NMI handler.  */
+	j	3f
+2:
+	l.w	$r15, _nds32_wrh	/* Load warm boot handler.  */
+3:
+	beqz    $r15, 1f	/* If no handler, do cold boot.  */
+	jral    $r15		/* Call handler.  */
+	bnez    $r0, 1f		/* If fail to resume, do cold boot.  */
+
+	/* Restore registers for context-switching.  */
+#ifdef NDS32_EXT_IFC
+	lmw.bim	$r1, [$sp], $r2, #0x0	/* Restore extra $r2 to keep
+					   stack 8-byte alignment.  */
+	mtusr   $r1, $IFC_LP
+#endif
+#ifdef __NDS32_REDUCED_REGS__
+	/* For 16-reg mode.  */
+	lmw.bim	$r15, [$sp], $r15, #0xf
+	lmw.bim	$r0, [$sp], $r10, #0x0
+#else
+	/* For 32-reg mode.  */
+	lmw.bim $r0, [$sp], $r27, #0xf
+#endif
+	iret	/* Resume operation.  */
+
+
+1:	/* Cold boot.  */
+	/* With vector ID feature, set default vector size to 4B.  */
+	/* Set IVB.ESZ = 0 (vector table entry size = 4 bytes)  */
+	mfsr    $r0, $IVB
+	li      $r1, #0xc000
+	or      $r0, $r0, $r1
+	xor     $r0, $r0, $r1
+	mtsr    $r0, $IVB
+	dsb
+
+	la	$gp, _SDA_BASE_		/* Init $gp.  */
+	la	$fp, _FP_BASE_		/* Init $fp.  */
+	la	$sp, _stack		/* Init $sp.  */
+#ifdef  NDS32_EXT_EX9
+/*
+ *	Initialize the table base of EX9 instruction
+ *	ex9 generation needs to disable before the ITB is set
+ */
+	mfsr    $r0, $MSC_CFG	/* Check if HW support of EX9.  */
+	srli	$r0, $r0, 24
+	andi	$r0, $r0, 0x1
+	beqz	$r0, 4f		/* Zero means HW does not support EX9.  */
+	la      $r0, _ITB_BASE_	/* Init $ITB.  */
+	mtusr   $r0, $ITB
+	.no_ex9_end
+4:
+#endif
+	la	$r15, _nds32_init_mem	/* Call DRAM init. _nds32_init_mem
+					  may written by C language.  */
+	beqz	$r15, 6f
+	jral	$r15
+6:
+	l.w	$r15, _nds32_jmptbl_00	/* Load reset handler.  */
+	jral	$r15
+/* Reset handler() should never return in a RTOS or non-OS system.
+   In case it does return, an exception will be generated.
+   This exception will be caught either by default break handler or by EDM.
+   Default break handle may just do an infinite loop.
+   EDM will notify GDB and GDB will regain control when the ID is 0x7fff. */
+5:
+	break    #0x7fff
+	.size	_nds32_reset_4b, .-_nds32_reset_4b
diff --git a/libgcc/config/nds32/isr-library/restore_all.inc b/libgcc/config/nds32/isr-library/restore_all.inc
new file mode 100644
index 00000000000..a0799540358
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/restore_all.inc
@@ -0,0 +1,45 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+.macro RESTORE_ALL
+	setgie.d
+	dsb
+	lmw.bim $r1, [$sp], $r2, #0x0   /* Restore IPC, IPSW.  */
+	mtsr	$r1, $IPC
+	mtsr	$r2, $IPSW
+	RESTORE_FPU_REGS
+	RESTORE_MAC_REGS
+#ifdef NDS32_EXT_IFC
+	lmw.bim	$r1, [$sp], $r2, #0x0	/* Restore extra $r2 to keep
+					   stack 8-byte alignment.  */
+	mtusr   $r1, $IFC_LP
+#endif
+#ifdef __NDS32_REDUCED_REGS__
+	lmw.bim $r0, [$sp], $r10, #0x0	/* Restore all regs.  */
+	lmw.bim $r15, [$sp], $r15, #0xf
+#else /* not __NDS32_REDUCED_REGS__ */
+	lmw.bim $r0, [$sp], $r27, #0xf	/* Restore all regs.  */
+#endif
+.endm
diff --git a/libgcc/config/nds32/isr-library/restore_fpu_regs.inc b/libgcc/config/nds32/isr-library/restore_fpu_regs.inc
new file mode 100644
index 00000000000..23a86c424a9
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/restore_fpu_regs.inc
@@ -0,0 +1,36 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+.macro RESTORE_FPU_REGS
+#if defined(NDS32_EXT_FPU_CONFIG_0)
+	RESTORE_FPU_REGS_00
+#elif defined(NDS32_EXT_FPU_CONFIG_1)
+	RESTORE_FPU_REGS_01
+#elif defined(NDS32_EXT_FPU_CONFIG_2)
+	RESTORE_FPU_REGS_02
+#elif defined(NDS32_EXT_FPU_CONFIG_3)
+	RESTORE_FPU_REGS_03
+#endif
+.endm
diff --git a/libgcc/config/nds32/isr-library/restore_fpu_regs_00.inc b/libgcc/config/nds32/isr-library/restore_fpu_regs_00.inc
new file mode 100644
index 00000000000..a90a368fecf
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/restore_fpu_regs_00.inc
@@ -0,0 +1,31 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+.macro RESTORE_FPU_REGS_00
+	fldi.bi	$fd0, [$sp], #8
+	fldi.bi	$fd1, [$sp], #8
+	fldi.bi	$fd2, [$sp], #8
+	fldi.bi	$fd3, [$sp], #8
+.endm
diff --git a/libgcc/config/nds32/isr-library/restore_fpu_regs_01.inc b/libgcc/config/nds32/isr-library/restore_fpu_regs_01.inc
new file mode 100644
index 00000000000..615e4530924
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/restore_fpu_regs_01.inc
@@ -0,0 +1,35 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+.macro RESTORE_FPU_REGS_01
+	fldi.bi	$fd0, [$sp], #8
+	fldi.bi	$fd1, [$sp], #8
+	fldi.bi	$fd2, [$sp], #8
+	fldi.bi	$fd3, [$sp], #8
+	fldi.bi	$fd4, [$sp], #8
+	fldi.bi	$fd5, [$sp], #8
+	fldi.bi	$fd6, [$sp], #8
+	fldi.bi	$fd7, [$sp], #8
+.endm
diff --git a/libgcc/config/nds32/isr-library/restore_fpu_regs_02.inc b/libgcc/config/nds32/isr-library/restore_fpu_regs_02.inc
new file mode 100644
index 00000000000..cfeed32451d
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/restore_fpu_regs_02.inc
@@ -0,0 +1,43 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+.macro RESTORE_FPU_REGS_02
+	fldi.bi	$fd0, [$sp], 8
+	fldi.bi	$fd1, [$sp], 8
+	fldi.bi	$fd2, [$sp], 8
+	fldi.bi	$fd3, [$sp], 8
+	fldi.bi	$fd4, [$sp], 8
+	fldi.bi	$fd5, [$sp], 8
+	fldi.bi	$fd6, [$sp], 8
+	fldi.bi	$fd7, [$sp], 8
+	fldi.bi	$fd8, [$sp], 8
+	fldi.bi	$fd9, [$sp], 8
+	fldi.bi	$fd10, [$sp], 8
+	fldi.bi	$fd11, [$sp], 8
+	fldi.bi	$fd12, [$sp], 8
+	fldi.bi	$fd13, [$sp], 8
+	fldi.bi	$fd14, [$sp], 8
+	fldi.bi	$fd15, [$sp], 8
+.endm
diff --git a/libgcc/config/nds32/isr-library/restore_fpu_regs_03.inc b/libgcc/config/nds32/isr-library/restore_fpu_regs_03.inc
new file mode 100644
index 00000000000..61391c91259
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/restore_fpu_regs_03.inc
@@ -0,0 +1,59 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+.macro RESTORE_FPU_REGS_03
+	fldi.bi	$fd0, [$sp], #8
+	fldi.bi	$fd1, [$sp], #8
+	fldi.bi	$fd2, [$sp], #8
+	fldi.bi	$fd3, [$sp], #8
+	fldi.bi	$fd4, [$sp], #8
+	fldi.bi	$fd5, [$sp], #8
+	fldi.bi	$fd6, [$sp], #8
+	fldi.bi	$fd7, [$sp], #8
+	fldi.bi	$fd8, [$sp], #8
+	fldi.bi	$fd9, [$sp], #8
+	fldi.bi	$fd10, [$sp], #8
+	fldi.bi	$fd11, [$sp], #8
+	fldi.bi	$fd12, [$sp], #8
+	fldi.bi	$fd13, [$sp], #8
+	fldi.bi	$fd14, [$sp], #8
+	fldi.bi	$fd15, [$sp], #8
+	fldi.bi	$fd16, [$sp], #8
+	fldi.bi	$fd17, [$sp], #8
+	fldi.bi	$fd18, [$sp], #8
+	fldi.bi	$fd19, [$sp], #8
+	fldi.bi	$fd20, [$sp], #8
+	fldi.bi	$fd21, [$sp], #8
+	fldi.bi	$fd22, [$sp], #8
+	fldi.bi	$fd23, [$sp], #8
+	fldi.bi	$fd24, [$sp], #8
+	fldi.bi	$fd25, [$sp], #8
+	fldi.bi	$fd26, [$sp], #8
+	fldi.bi	$fd27, [$sp], #8
+	fldi.bi	$fd28, [$sp], #8
+	fldi.bi	$fd29, [$sp], #8
+	fldi.bi	$fd30, [$sp], #8
+	fldi.bi	$fd31, [$sp], #8
+.endm
diff --git a/libgcc/config/nds32/isr-library/restore_mac_regs.inc b/libgcc/config/nds32/isr-library/restore_mac_regs.inc
new file mode 100644
index 00000000000..770817dd817
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/restore_mac_regs.inc
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+.macro RESTORE_MAC_REGS
+#ifdef NDS32_DX_REGS
+	lmw.bim	$r1, [$sp], $r4, #0x0
+	mtusr	$r1, $d0.lo
+	mtusr	$r2, $d0.hi
+	mtusr	$r3, $d1.lo
+	mtusr	$r4, $d1.hi
+#endif
+.endm
diff --git a/libgcc/config/nds32/isr-library/restore_partial.inc b/libgcc/config/nds32/isr-library/restore_partial.inc
new file mode 100644
index 00000000000..eeb815f93d6
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/restore_partial.inc
@@ -0,0 +1,47 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+.macro RESTORE_PARTIAL
+#if defined(NDS32_NESTED) || defined(NDS32_NESTED_READY)
+	setgie.d
+	dsb
+	lmw.bim $r1, [$sp], $r2, #0x0	/* Restore IPC, IPSW.  */
+	mtsr $r1, $IPC	/* Set IPC.  */
+	mtsr $r2, $IPSW	/* Set IPSW.  */
+#endif
+	RESTORE_FPU_REGS
+	RESTORE_MAC_REGS
+#ifdef NDS32_EXT_IFC
+	lmw.bim	$r1, [$sp], $r2, #0x0	/* Restore extra $r2 to keep
+					   stack 8-byte alignment.  */
+	mtusr   $r1, $IFC_LP
+#endif
+	lmw.bim $r0, [$sp], $r5, #0x0	/* Restore all regs.  */
+#ifdef __NDS32_REDUCED_REGS__
+	lmw.bim $r15, [$sp], $r15, #0x2
+#else
+	lmw.bim $r15, [$sp], $r27, #0x2	/* Restore all regs.  */
+#endif
+.endm
diff --git a/libgcc/config/nds32/isr-library/save_all.inc b/libgcc/config/nds32/isr-library/save_all.inc
new file mode 100644
index 00000000000..2ac053d71f8
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/save_all.inc
@@ -0,0 +1,67 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+.macro SAVE_ALL_4B
+#ifdef __NDS32_REDUCED_REGS__
+	smw.adm $r15, [$sp], $r15, #0xf
+	smw.adm $r0, [$sp], $r10, #0x0
+#else /* not __NDS32_REDUCED_REGS__ */
+	smw.adm $r0, [$sp], $r27, #0xf
+#endif /* not __NDS32_REDUCED_REGS__ */
+#ifdef NDS32_EXT_IFC
+	mfusr   $r1, $IFC_LP
+	smw.adm $r1, [$sp], $r2, #0x0	/* Save extra $r2 to keep
+					   stack 8-byte alignment.  */
+#endif
+	SAVE_MAC_REGS
+	SAVE_FPU_REGS
+	mfsr	$r1, $IPC	/* Get IPC.  */
+	mfsr	$r2, $IPSW	/* Get IPSW.  */
+	smw.adm	$r1, [$sp], $r2, #0x0	/* Push IPC, IPSW.  */
+	move	$r1, $sp	/* $r1 is ptr to NDS32_CONTEXT.  */
+	mfsr	$r0, $ITYPE	/* Get VID to $r0.  */
+	srli	$r0, $r0, #5
+#ifdef __NDS32_ISA_V2__
+	andi	$r0, $r0, #127
+#else
+	fexti33	$r0, #6
+#endif
+.endm
+
+.macro SAVE_ALL
+/* SAVE_REG_TBL code has been moved to
+   vector table generated by compiler.  */
+#ifdef NDS32_EXT_IFC
+	mfusr   $r1, $IFC_LP
+	smw.adm $r1, [$sp], $r2, #0x0	/* Save extra $r2 to keep
+					   stack 8-byte alignment.  */
+#endif
+	SAVE_MAC_REGS
+	SAVE_FPU_REGS
+	mfsr	$r1, $IPC	/* Get IPC.  */
+	mfsr	$r2, $IPSW	/* Get IPSW.  */
+	smw.adm	$r1, [$sp], $r2, #0x0	/* Push IPC, IPSW.  */
+	move	$r1, $sp	/* $r1 is ptr to NDS32_CONTEXT.  */
+.endm
diff --git a/libgcc/config/nds32/isr-library/save_fpu_regs.inc b/libgcc/config/nds32/isr-library/save_fpu_regs.inc
new file mode 100644
index 00000000000..be3a504e440
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/save_fpu_regs.inc
@@ -0,0 +1,36 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+.macro SAVE_FPU_REGS
+#if defined(NDS32_EXT_FPU_CONFIG_0)
+	SAVE_FPU_REGS_00
+#elif defined(NDS32_EXT_FPU_CONFIG_1)
+	SAVE_FPU_REGS_01
+#elif defined(NDS32_EXT_FPU_CONFIG_2)
+	SAVE_FPU_REGS_02
+#elif defined(NDS32_EXT_FPU_CONFIG_3)
+	SAVE_FPU_REGS_03
+#endif
+.endm
diff --git a/libgcc/config/nds32/isr-library/save_fpu_regs_00.inc b/libgcc/config/nds32/isr-library/save_fpu_regs_00.inc
new file mode 100644
index 00000000000..2514f59b90e
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/save_fpu_regs_00.inc
@@ -0,0 +1,33 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+.macro SAVE_FPU_REGS_00
+	addi	$sp, $sp, #-8
+	fsdi.bi	$fd3, [$sp], #-8
+	fsdi.bi	$fd2, [$sp], #-8
+	fsdi.bi	$fd1, [$sp], #-8
+	fsdi.bi	$fd0, [$sp], #-8
+	addi	$sp, $sp, #8
+.endm
diff --git a/libgcc/config/nds32/isr-library/save_fpu_regs_01.inc b/libgcc/config/nds32/isr-library/save_fpu_regs_01.inc
new file mode 100644
index 00000000000..1d605f2acdd
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/save_fpu_regs_01.inc
@@ -0,0 +1,37 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+.macro SAVE_FPU_REGS_01
+	addi	$sp, $sp, #-8
+	fsdi.bi	$fd7, [$sp], #-8
+	fsdi.bi	$fd6, [$sp], #-8
+	fsdi.bi	$fd5, [$sp], #-8
+	fsdi.bi	$fd4, [$sp], #-8
+	fsdi.bi	$fd3, [$sp], #-8
+	fsdi.bi	$fd2, [$sp], #-8
+	fsdi.bi	$fd1, [$sp], #-8
+	fsdi.bi	$fd0, [$sp], #-8
+	addi	$sp, $sp, #8
+.endm
diff --git a/libgcc/config/nds32/isr-library/save_fpu_regs_02.inc b/libgcc/config/nds32/isr-library/save_fpu_regs_02.inc
new file mode 100644
index 00000000000..30cb833ad0f
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/save_fpu_regs_02.inc
@@ -0,0 +1,45 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+.macro SAVE_FPU_REGS_02
+	addi	$sp, $sp, #-8
+	fsdi.bi	$fd15, [$sp], #-8
+	fsdi.bi	$fd14, [$sp], #-8
+	fsdi.bi	$fd13, [$sp], #-8
+	fsdi.bi	$fd12, [$sp], #-8
+	fsdi.bi	$fd11, [$sp], #-8
+	fsdi.bi	$fd10, [$sp], #-8
+	fsdi.bi	$fd9, [$sp], #-8
+	fsdi.bi	$fd8, [$sp], #-8
+	fsdi.bi	$fd7, [$sp], #-8
+	fsdi.bi	$fd6, [$sp], #-8
+	fsdi.bi	$fd5, [$sp], #-8
+	fsdi.bi	$fd4, [$sp], #-8
+	fsdi.bi	$fd3, [$sp], #-8
+	fsdi.bi	$fd2, [$sp], #-8
+	fsdi.bi	$fd1, [$sp], #-8
+	fsdi.bi	$fd0, [$sp], #-8
+	addi	$sp, $sp, #8
+.endm
diff --git a/libgcc/config/nds32/isr-library/save_fpu_regs_03.inc b/libgcc/config/nds32/isr-library/save_fpu_regs_03.inc
new file mode 100644
index 00000000000..693e051a847
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/save_fpu_regs_03.inc
@@ -0,0 +1,61 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+.macro SAVE_FPU_REGS_03
+	addi	$sp, $sp, #-8
+	fsdi.bi	$fd31, [$sp], #-8
+	fsdi.bi	$fd30, [$sp], #-8
+	fsdi.bi	$fd29, [$sp], #-8
+	fsdi.bi	$fd28, [$sp], #-8
+	fsdi.bi	$fd27, [$sp], #-8
+	fsdi.bi	$fd26, [$sp], #-8
+	fsdi.bi	$fd25, [$sp], #-8
+	fsdi.bi	$fd24, [$sp], #-8
+	fsdi.bi	$fd23, [$sp], #-8
+	fsdi.bi	$fd22, [$sp], #-8
+	fsdi.bi	$fd21, [$sp], #-8
+	fsdi.bi	$fd20, [$sp], #-8
+	fsdi.bi	$fd19, [$sp], #-8
+	fsdi.bi	$fd18, [$sp], #-8
+	fsdi.bi	$fd17, [$sp], #-8
+	fsdi.bi	$fd16, [$sp], #-8
+	fsdi.bi	$fd15, [$sp], #-8
+	fsdi.bi	$fd14, [$sp], #-8
+	fsdi.bi	$fd13, [$sp], #-8
+	fsdi.bi	$fd12, [$sp], #-8
+	fsdi.bi	$fd11, [$sp], #-8
+	fsdi.bi	$fd10, [$sp], #-8
+	fsdi.bi	$fd9, [$sp], #-8
+	fsdi.bi	$fd8, [$sp], #-8
+	fsdi.bi	$fd7, [$sp], #-8
+	fsdi.bi	$fd6, [$sp], #-8
+	fsdi.bi	$fd5, [$sp], #-8
+	fsdi.bi	$fd4, [$sp], #-8
+	fsdi.bi	$fd3, [$sp], #-8
+	fsdi.bi	$fd2, [$sp], #-8
+	fsdi.bi	$fd1, [$sp], #-8
+	fsdi.bi	$fd0, [$sp], #-8
+	addi	$sp, $sp, #8
+.endm
diff --git a/libgcc/config/nds32/isr-library/save_mac_regs.inc b/libgcc/config/nds32/isr-library/save_mac_regs.inc
new file mode 100644
index 00000000000..14c1851736f
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/save_mac_regs.inc
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+.macro SAVE_MAC_REGS
+#ifdef NDS32_DX_REGS
+	mfusr	$r1, $d0.lo
+	mfusr	$r2, $d0.hi
+	mfusr	$r3, $d1.lo
+	mfusr	$r4, $d1.hi
+	smw.adm	$r1, [$sp], $r4, #0x0
+#endif
+.endm
diff --git a/libgcc/config/nds32/isr-library/save_partial.inc b/libgcc/config/nds32/isr-library/save_partial.inc
new file mode 100644
index 00000000000..61df3966d1e
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/save_partial.inc
@@ -0,0 +1,69 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+.macro SAVE_PARTIAL_4B
+#ifdef __NDS32_REDUCED_REGS__
+	smw.adm $r15, [$sp], $r15, #0x2
+#else /* not __NDS32_REDUCED_REGS__ */
+	smw.adm $r15, [$sp], $r27, #0x2
+#endif /* not __NDS32_REDUCED_REGS__ */
+	smw.adm $r0, [$sp], $r5, #0x0
+#ifdef NDS32_EXT_IFC
+	mfusr   $r1, $IFC_LP
+	smw.adm $r1, [$sp], $r2, #0x0	/* Save extra $r2 to keep
+					   stack 8-byte alignment.  */
+#endif
+	SAVE_MAC_REGS
+	SAVE_FPU_REGS
+#if defined(NDS32_NESTED) || defined(NDS32_NESTED_READY)
+       mfsr    $r1, $IPC       /* Get IPC.  */
+       mfsr    $r2, $IPSW      /* Get IPSW.  */
+       smw.adm $r1, [$sp], $r2, #0x0   /* Push IPC, IPSW.  */
+#endif
+	mfsr	$r0, $ITYPE	/* Get VID to $r0.  */
+	srli	$r0, $r0, #5
+#ifdef __NDS32_ISA_V2__
+	andi	$r0, $r0, #127
+#else
+	fexti33	$r0, #6
+#endif
+.endm
+
+.macro SAVE_PARTIAL
+/* SAVE_CALLER_REGS code has been moved to
+   vector table generated by compiler.  */
+#ifdef NDS32_EXT_IFC
+	mfusr   $r1, $IFC_LP
+	smw.adm $r1, [$sp], $r2, #0x0	/* Save extra $r2 to keep
+					   stack 8-byte alignment.  */
+#endif
+	SAVE_MAC_REGS
+	SAVE_FPU_REGS
+#if defined(NDS32_NESTED) || defined(NDS32_NESTED_READY)
+       mfsr    $r1, $IPC       /* Get IPC.  */
+       mfsr    $r2, $IPSW      /* Get IPSW.  */
+       smw.adm $r1, [$sp], $r2, #0x0   /* Push IPC, IPSW.  */
+#endif
+.endm
diff --git a/libgcc/config/nds32/isr-library/vec_vid00.S b/libgcc/config/nds32/isr-library/vec_vid00.S
new file mode 100644
index 00000000000..cef2df23b21
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid00.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.00, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_00
+	.type	_nds32_vector_00, @function
+_nds32_vector_00:
+1:
+	j	1b
+	.size	_nds32_vector_00, .-_nds32_vector_00
diff --git a/libgcc/config/nds32/isr-library/vec_vid00_4b.S b/libgcc/config/nds32/isr-library/vec_vid00_4b.S
new file mode 100644
index 00000000000..957ac485e2a
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid00_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.00, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_00_4b
+	.type	_nds32_vector_00_4b, @function
+_nds32_vector_00_4b:
+1:
+	j	1b
+	.size	_nds32_vector_00_4b, .-_nds32_vector_00_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid01.S b/libgcc/config/nds32/isr-library/vec_vid01.S
new file mode 100644
index 00000000000..319d64bcd20
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid01.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.01, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_01
+	.type	_nds32_vector_01, @function
+_nds32_vector_01:
+1:
+	j	1b
+	.size	_nds32_vector_01, .-_nds32_vector_01
diff --git a/libgcc/config/nds32/isr-library/vec_vid01_4b.S b/libgcc/config/nds32/isr-library/vec_vid01_4b.S
new file mode 100644
index 00000000000..ad52fcb9cc1
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid01_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.01, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_01_4b
+	.type	_nds32_vector_01_4b, @function
+_nds32_vector_01_4b:
+1:
+	j	1b
+	.size	_nds32_vector_01_4b, .-_nds32_vector_01_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid02.S b/libgcc/config/nds32/isr-library/vec_vid02.S
new file mode 100644
index 00000000000..4c98c5cebb5
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid02.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.02, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_02
+	.type	_nds32_vector_02, @function
+_nds32_vector_02:
+1:
+	j	1b
+	.size	_nds32_vector_02, .-_nds32_vector_02
diff --git a/libgcc/config/nds32/isr-library/vec_vid02_4b.S b/libgcc/config/nds32/isr-library/vec_vid02_4b.S
new file mode 100644
index 00000000000..790356bc655
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid02_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.02, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_02_4b
+	.type	_nds32_vector_02_4b, @function
+_nds32_vector_02_4b:
+1:
+	j	1b
+	.size	_nds32_vector_02_4b, .-_nds32_vector_02_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid03.S b/libgcc/config/nds32/isr-library/vec_vid03.S
new file mode 100644
index 00000000000..7cca9aa7544
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid03.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.03, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_03
+	.type	_nds32_vector_03, @function
+_nds32_vector_03:
+1:
+	j	1b
+	.size	_nds32_vector_03, .-_nds32_vector_03
diff --git a/libgcc/config/nds32/isr-library/vec_vid03_4b.S b/libgcc/config/nds32/isr-library/vec_vid03_4b.S
new file mode 100644
index 00000000000..be756bf3d1d
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid03_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.03, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_03_4b
+	.type	_nds32_vector_03_4b, @function
+_nds32_vector_03_4b:
+1:
+	j	1b
+	.size	_nds32_vector_03_4b, .-_nds32_vector_03_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid04.S b/libgcc/config/nds32/isr-library/vec_vid04.S
new file mode 100644
index 00000000000..ec9ea16cc91
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid04.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.04, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_04
+	.type	_nds32_vector_04, @function
+_nds32_vector_04:
+1:
+	j	1b
+	.size	_nds32_vector_04, .-_nds32_vector_04
diff --git a/libgcc/config/nds32/isr-library/vec_vid04_4b.S b/libgcc/config/nds32/isr-library/vec_vid04_4b.S
new file mode 100644
index 00000000000..6883718814e
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid04_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.04, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_04_4b
+	.type	_nds32_vector_04_4b, @function
+_nds32_vector_04_4b:
+1:
+	j	1b
+	.size	_nds32_vector_04_4b, .-_nds32_vector_04_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid05.S b/libgcc/config/nds32/isr-library/vec_vid05.S
new file mode 100644
index 00000000000..38aa4d99d52
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid05.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.05, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_05
+	.type	_nds32_vector_05, @function
+_nds32_vector_05:
+1:
+	j	1b
+	.size	_nds32_vector_05, .-_nds32_vector_05
diff --git a/libgcc/config/nds32/isr-library/vec_vid05_4b.S b/libgcc/config/nds32/isr-library/vec_vid05_4b.S
new file mode 100644
index 00000000000..914287f69d4
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid05_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.05, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_05_4b
+	.type	_nds32_vector_05_4b, @function
+_nds32_vector_05_4b:
+1:
+	j	1b
+	.size	_nds32_vector_05_4b, .-_nds32_vector_05_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid06.S b/libgcc/config/nds32/isr-library/vec_vid06.S
new file mode 100644
index 00000000000..8b1bcfb7ee8
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid06.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.06, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_06
+	.type	_nds32_vector_06, @function
+_nds32_vector_06:
+1:
+	j	1b
+	.size	_nds32_vector_06, .-_nds32_vector_06
diff --git a/libgcc/config/nds32/isr-library/vec_vid06_4b.S b/libgcc/config/nds32/isr-library/vec_vid06_4b.S
new file mode 100644
index 00000000000..c0bd26e2e6e
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid06_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.06, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_06_4b
+	.type	_nds32_vector_06_4b, @function
+_nds32_vector_06_4b:
+1:
+	j	1b
+	.size	_nds32_vector_06_4b, .-_nds32_vector_06_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid07.S b/libgcc/config/nds32/isr-library/vec_vid07.S
new file mode 100644
index 00000000000..b708ada47e9
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid07.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.07, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_07
+	.type	_nds32_vector_07, @function
+_nds32_vector_07:
+1:
+	j	1b
+	.size	_nds32_vector_07, .-_nds32_vector_07
diff --git a/libgcc/config/nds32/isr-library/vec_vid07_4b.S b/libgcc/config/nds32/isr-library/vec_vid07_4b.S
new file mode 100644
index 00000000000..3532551ab5e
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid07_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.07, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_07_4b
+	.type	_nds32_vector_07_4b, @function
+_nds32_vector_07_4b:
+1:
+	j	1b
+	.size	_nds32_vector_07_4b, .-_nds32_vector_07_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid08.S b/libgcc/config/nds32/isr-library/vec_vid08.S
new file mode 100644
index 00000000000..3afb6e6cb1d
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid08.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.08, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_08
+	.type	_nds32_vector_08, @function
+_nds32_vector_08:
+1:
+	j	1b
+	.size	_nds32_vector_08, .-_nds32_vector_08
diff --git a/libgcc/config/nds32/isr-library/vec_vid08_4b.S b/libgcc/config/nds32/isr-library/vec_vid08_4b.S
new file mode 100644
index 00000000000..0493fefde64
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid08_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.08, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_08_4b
+	.type	_nds32_vector_08_4b, @function
+_nds32_vector_08_4b:
+1:
+	j	1b
+	.size	_nds32_vector_08_4b, .-_nds32_vector_08_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid09.S b/libgcc/config/nds32/isr-library/vec_vid09.S
new file mode 100644
index 00000000000..35747ec212d
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid09.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.09, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_09
+	.type	_nds32_vector_09, @function
+_nds32_vector_09:
+1:
+	j	1b
+	.size	_nds32_vector_09, .-_nds32_vector_09
diff --git a/libgcc/config/nds32/isr-library/vec_vid09_4b.S b/libgcc/config/nds32/isr-library/vec_vid09_4b.S
new file mode 100644
index 00000000000..d44f9b22ac0
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid09_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.09, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_09_4b
+	.type	_nds32_vector_09_4b, @function
+_nds32_vector_09_4b:
+1:
+	j	1b
+	.size	_nds32_vector_09_4b, .-_nds32_vector_09_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid10.S b/libgcc/config/nds32/isr-library/vec_vid10.S
new file mode 100644
index 00000000000..71ab8ac056b
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid10.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.10, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_10
+	.type	_nds32_vector_10, @function
+_nds32_vector_10:
+1:
+	j	1b
+	.size	_nds32_vector_10, .-_nds32_vector_10
diff --git a/libgcc/config/nds32/isr-library/vec_vid10_4b.S b/libgcc/config/nds32/isr-library/vec_vid10_4b.S
new file mode 100644
index 00000000000..49fd669f10d
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid10_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.10, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_10_4b
+	.type	_nds32_vector_10_4b, @function
+_nds32_vector_10_4b:
+1:
+	j	1b
+	.size	_nds32_vector_10_4b, .-_nds32_vector_10_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid11.S b/libgcc/config/nds32/isr-library/vec_vid11.S
new file mode 100644
index 00000000000..732559d17e2
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid11.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.11, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_11
+	.type	_nds32_vector_11, @function
+_nds32_vector_11:
+1:
+	j	1b
+	.size	_nds32_vector_11, .-_nds32_vector_11
diff --git a/libgcc/config/nds32/isr-library/vec_vid11_4b.S b/libgcc/config/nds32/isr-library/vec_vid11_4b.S
new file mode 100644
index 00000000000..e878e36c947
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid11_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.11, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_11_4b
+	.type	_nds32_vector_11_4b, @function
+_nds32_vector_11_4b:
+1:
+	j	1b
+	.size	_nds32_vector_11_4b, .-_nds32_vector_11_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid12.S b/libgcc/config/nds32/isr-library/vec_vid12.S
new file mode 100644
index 00000000000..5d78fbb2e68
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid12.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.12, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_12
+	.type	_nds32_vector_12, @function
+_nds32_vector_12:
+1:
+	j	1b
+	.size	_nds32_vector_12, .-_nds32_vector_12
diff --git a/libgcc/config/nds32/isr-library/vec_vid12_4b.S b/libgcc/config/nds32/isr-library/vec_vid12_4b.S
new file mode 100644
index 00000000000..a03e8d89b6d
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid12_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.12, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_12_4b
+	.type	_nds32_vector_12_4b, @function
+_nds32_vector_12_4b:
+1:
+	j	1b
+	.size	_nds32_vector_12_4b, .-_nds32_vector_12_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid13.S b/libgcc/config/nds32/isr-library/vec_vid13.S
new file mode 100644
index 00000000000..3df6a1e4299
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid13.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.13, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_13
+	.type	_nds32_vector_13, @function
+_nds32_vector_13:
+1:
+	j	1b
+	.size	_nds32_vector_13, .-_nds32_vector_13
diff --git a/libgcc/config/nds32/isr-library/vec_vid13_4b.S b/libgcc/config/nds32/isr-library/vec_vid13_4b.S
new file mode 100644
index 00000000000..2117edb43ce
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid13_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.13, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_13_4b
+	.type	_nds32_vector_13_4b, @function
+_nds32_vector_13_4b:
+1:
+	j	1b
+	.size	_nds32_vector_13_4b, .-_nds32_vector_13_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid14.S b/libgcc/config/nds32/isr-library/vec_vid14.S
new file mode 100644
index 00000000000..8a554bebad9
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid14.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.14, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_14
+	.type	_nds32_vector_14, @function
+_nds32_vector_14:
+1:
+	j	1b
+	.size	_nds32_vector_14, .-_nds32_vector_14
diff --git a/libgcc/config/nds32/isr-library/vec_vid14_4b.S b/libgcc/config/nds32/isr-library/vec_vid14_4b.S
new file mode 100644
index 00000000000..1c5bf2dbdaa
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid14_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.14, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_14_4b
+	.type	_nds32_vector_14_4b, @function
+_nds32_vector_14_4b:
+1:
+	j	1b
+	.size	_nds32_vector_14_4b, .-_nds32_vector_14_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid15.S b/libgcc/config/nds32/isr-library/vec_vid15.S
new file mode 100644
index 00000000000..1d49d62f42f
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid15.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.15, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_15
+	.type	_nds32_vector_15, @function
+_nds32_vector_15:
+1:
+	j	1b
+	.size	_nds32_vector_15, .-_nds32_vector_15
diff --git a/libgcc/config/nds32/isr-library/vec_vid15_4b.S b/libgcc/config/nds32/isr-library/vec_vid15_4b.S
new file mode 100644
index 00000000000..ffa8ea9aec8
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid15_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.15, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_15_4b
+	.type	_nds32_vector_15_4b, @function
+_nds32_vector_15_4b:
+1:
+	j	1b
+	.size	_nds32_vector_15_4b, .-_nds32_vector_15_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid16.S b/libgcc/config/nds32/isr-library/vec_vid16.S
new file mode 100644
index 00000000000..70d6ab36592
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid16.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.16, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_16
+	.type	_nds32_vector_16, @function
+_nds32_vector_16:
+1:
+	j	1b
+	.size	_nds32_vector_16, .-_nds32_vector_16
diff --git a/libgcc/config/nds32/isr-library/vec_vid16_4b.S b/libgcc/config/nds32/isr-library/vec_vid16_4b.S
new file mode 100644
index 00000000000..133fe6a2123
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid16_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.16, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_16_4b
+	.type	_nds32_vector_16_4b, @function
+_nds32_vector_16_4b:
+1:
+	j	1b
+	.size	_nds32_vector_16_4b, .-_nds32_vector_16_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid17.S b/libgcc/config/nds32/isr-library/vec_vid17.S
new file mode 100644
index 00000000000..8eb871eb7f5
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid17.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.17, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_17
+	.type	_nds32_vector_17, @function
+_nds32_vector_17:
+1:
+	j	1b
+	.size	_nds32_vector_17, .-_nds32_vector_17
diff --git a/libgcc/config/nds32/isr-library/vec_vid17_4b.S b/libgcc/config/nds32/isr-library/vec_vid17_4b.S
new file mode 100644
index 00000000000..e10e7d65963
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid17_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.17, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_17_4b
+	.type	_nds32_vector_17_4b, @function
+_nds32_vector_17_4b:
+1:
+	j	1b
+	.size	_nds32_vector_17_4b, .-_nds32_vector_17_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid18.S b/libgcc/config/nds32/isr-library/vec_vid18.S
new file mode 100644
index 00000000000..3699454153e
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid18.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.18, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_18
+	.type	_nds32_vector_18, @function
+_nds32_vector_18:
+1:
+	j	1b
+	.size	_nds32_vector_18, .-_nds32_vector_18
diff --git a/libgcc/config/nds32/isr-library/vec_vid18_4b.S b/libgcc/config/nds32/isr-library/vec_vid18_4b.S
new file mode 100644
index 00000000000..e52910210a8
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid18_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.18, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_18_4b
+	.type	_nds32_vector_18_4b, @function
+_nds32_vector_18_4b:
+1:
+	j	1b
+	.size	_nds32_vector_18_4b, .-_nds32_vector_18_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid19.S b/libgcc/config/nds32/isr-library/vec_vid19.S
new file mode 100644
index 00000000000..b572bf9516a
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid19.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.19, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_19
+	.type	_nds32_vector_19, @function
+_nds32_vector_19:
+1:
+	j	1b
+	.size	_nds32_vector_19, .-_nds32_vector_19
diff --git a/libgcc/config/nds32/isr-library/vec_vid19_4b.S b/libgcc/config/nds32/isr-library/vec_vid19_4b.S
new file mode 100644
index 00000000000..49462674f2a
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid19_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.19, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_19_4b
+	.type	_nds32_vector_19_4b, @function
+_nds32_vector_19_4b:
+1:
+	j	1b
+	.size	_nds32_vector_19_4b, .-_nds32_vector_19_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid20.S b/libgcc/config/nds32/isr-library/vec_vid20.S
new file mode 100644
index 00000000000..c8fa4194cfc
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid20.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.20, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_20
+	.type	_nds32_vector_20, @function
+_nds32_vector_20:
+1:
+	j	1b
+	.size	_nds32_vector_20, .-_nds32_vector_20
diff --git a/libgcc/config/nds32/isr-library/vec_vid20_4b.S b/libgcc/config/nds32/isr-library/vec_vid20_4b.S
new file mode 100644
index 00000000000..95ab9170308
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid20_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.20, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_20_4b
+	.type	_nds32_vector_20_4b, @function
+_nds32_vector_20_4b:
+1:
+	j	1b
+	.size	_nds32_vector_20_4b, .-_nds32_vector_20_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid21.S b/libgcc/config/nds32/isr-library/vec_vid21.S
new file mode 100644
index 00000000000..8fc8cc706b7
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid21.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.21, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_21
+	.type	_nds32_vector_21, @function
+_nds32_vector_21:
+1:
+	j	1b
+	.size	_nds32_vector_21, .-_nds32_vector_21
diff --git a/libgcc/config/nds32/isr-library/vec_vid21_4b.S b/libgcc/config/nds32/isr-library/vec_vid21_4b.S
new file mode 100644
index 00000000000..33956bbbc33
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid21_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.21, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_21_4b
+	.type	_nds32_vector_21_4b, @function
+_nds32_vector_21_4b:
+1:
+	j	1b
+	.size	_nds32_vector_21_4b, .-_nds32_vector_21_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid22.S b/libgcc/config/nds32/isr-library/vec_vid22.S
new file mode 100644
index 00000000000..8e71ecb856a
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid22.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.22, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_22
+	.type	_nds32_vector_22, @function
+_nds32_vector_22:
+1:
+	j	1b
+	.size	_nds32_vector_22, .-_nds32_vector_22
diff --git a/libgcc/config/nds32/isr-library/vec_vid22_4b.S b/libgcc/config/nds32/isr-library/vec_vid22_4b.S
new file mode 100644
index 00000000000..5ecd38261e7
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid22_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.22, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_22_4b
+	.type	_nds32_vector_22_4b, @function
+_nds32_vector_22_4b:
+1:
+	j	1b
+	.size	_nds32_vector_22_4b, .-_nds32_vector_22_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid23.S b/libgcc/config/nds32/isr-library/vec_vid23.S
new file mode 100644
index 00000000000..c9f2ae3bfb9
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid23.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.23, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_23
+	.type	_nds32_vector_23, @function
+_nds32_vector_23:
+1:
+	j	1b
+	.size	_nds32_vector_23, .-_nds32_vector_23
diff --git a/libgcc/config/nds32/isr-library/vec_vid23_4b.S b/libgcc/config/nds32/isr-library/vec_vid23_4b.S
new file mode 100644
index 00000000000..eb7ea1f15ee
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid23_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.23, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_23_4b
+	.type	_nds32_vector_23_4b, @function
+_nds32_vector_23_4b:
+1:
+	j	1b
+	.size	_nds32_vector_23_4b, .-_nds32_vector_23_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid24.S b/libgcc/config/nds32/isr-library/vec_vid24.S
new file mode 100644
index 00000000000..dc16e56267d
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid24.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.24, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_24
+	.type	_nds32_vector_24, @function
+_nds32_vector_24:
+1:
+	j	1b
+	.size	_nds32_vector_24, .-_nds32_vector_24
diff --git a/libgcc/config/nds32/isr-library/vec_vid24_4b.S b/libgcc/config/nds32/isr-library/vec_vid24_4b.S
new file mode 100644
index 00000000000..023cee9e83a
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid24_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.24, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_24_4b
+	.type	_nds32_vector_24_4b, @function
+_nds32_vector_24_4b:
+1:
+	j	1b
+	.size	_nds32_vector_24_4b, .-_nds32_vector_24_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid25.S b/libgcc/config/nds32/isr-library/vec_vid25.S
new file mode 100644
index 00000000000..cc0c0623150
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid25.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.25, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_25
+	.type	_nds32_vector_25, @function
+_nds32_vector_25:
+1:
+	j	1b
+	.size	_nds32_vector_25, .-_nds32_vector_25
diff --git a/libgcc/config/nds32/isr-library/vec_vid25_4b.S b/libgcc/config/nds32/isr-library/vec_vid25_4b.S
new file mode 100644
index 00000000000..f9c747829c2
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid25_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.25, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_25_4b
+	.type	_nds32_vector_25_4b, @function
+_nds32_vector_25_4b:
+1:
+	j	1b
+	.size	_nds32_vector_25_4b, .-_nds32_vector_25_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid26.S b/libgcc/config/nds32/isr-library/vec_vid26.S
new file mode 100644
index 00000000000..8afb5f78850
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid26.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.26, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_26
+	.type	_nds32_vector_26, @function
+_nds32_vector_26:
+1:
+	j	1b
+	.size	_nds32_vector_26, .-_nds32_vector_26
diff --git a/libgcc/config/nds32/isr-library/vec_vid26_4b.S b/libgcc/config/nds32/isr-library/vec_vid26_4b.S
new file mode 100644
index 00000000000..51aea6c5ffb
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid26_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.26, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_26_4b
+	.type	_nds32_vector_26_4b, @function
+_nds32_vector_26_4b:
+1:
+	j	1b
+	.size	_nds32_vector_26_4b, .-_nds32_vector_26_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid27.S b/libgcc/config/nds32/isr-library/vec_vid27.S
new file mode 100644
index 00000000000..5babf0761c5
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid27.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.27, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_27
+	.type	_nds32_vector_27, @function
+_nds32_vector_27:
+1:
+	j	1b
+	.size	_nds32_vector_27, .-_nds32_vector_27
diff --git a/libgcc/config/nds32/isr-library/vec_vid27_4b.S b/libgcc/config/nds32/isr-library/vec_vid27_4b.S
new file mode 100644
index 00000000000..7a6e8705f0f
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid27_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.27, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_27_4b
+	.type	_nds32_vector_27_4b, @function
+_nds32_vector_27_4b:
+1:
+	j	1b
+	.size	_nds32_vector_27_4b, .-_nds32_vector_27_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid28.S b/libgcc/config/nds32/isr-library/vec_vid28.S
new file mode 100644
index 00000000000..3600b9c1738
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid28.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.28, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_28
+	.type	_nds32_vector_28, @function
+_nds32_vector_28:
+1:
+	j	1b
+	.size	_nds32_vector_28, .-_nds32_vector_28
diff --git a/libgcc/config/nds32/isr-library/vec_vid28_4b.S b/libgcc/config/nds32/isr-library/vec_vid28_4b.S
new file mode 100644
index 00000000000..5c752956269
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid28_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.28, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_28_4b
+	.type	_nds32_vector_28_4b, @function
+_nds32_vector_28_4b:
+1:
+	j	1b
+	.size	_nds32_vector_28_4b, .-_nds32_vector_28_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid29.S b/libgcc/config/nds32/isr-library/vec_vid29.S
new file mode 100644
index 00000000000..02f8e9ceb62
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid29.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.29, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_29
+	.type	_nds32_vector_29, @function
+_nds32_vector_29:
+1:
+	j	1b
+	.size	_nds32_vector_29, .-_nds32_vector_29
diff --git a/libgcc/config/nds32/isr-library/vec_vid29_4b.S b/libgcc/config/nds32/isr-library/vec_vid29_4b.S
new file mode 100644
index 00000000000..48412f0c6b9
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid29_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.29, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_29_4b
+	.type	_nds32_vector_29_4b, @function
+_nds32_vector_29_4b:
+1:
+	j	1b
+	.size	_nds32_vector_29_4b, .-_nds32_vector_29_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid30.S b/libgcc/config/nds32/isr-library/vec_vid30.S
new file mode 100644
index 00000000000..e08d7e8be0f
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid30.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.30, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_30
+	.type	_nds32_vector_30, @function
+_nds32_vector_30:
+1:
+	j	1b
+	.size	_nds32_vector_30, .-_nds32_vector_30
diff --git a/libgcc/config/nds32/isr-library/vec_vid30_4b.S b/libgcc/config/nds32/isr-library/vec_vid30_4b.S
new file mode 100644
index 00000000000..36265727377
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid30_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.30, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_30_4b
+	.type	_nds32_vector_30_4b, @function
+_nds32_vector_30_4b:
+1:
+	j	1b
+	.size	_nds32_vector_30_4b, .-_nds32_vector_30_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid31.S b/libgcc/config/nds32/isr-library/vec_vid31.S
new file mode 100644
index 00000000000..b6aba1d2c40
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid31.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.31, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_31
+	.type	_nds32_vector_31, @function
+_nds32_vector_31:
+1:
+	j	1b
+	.size	_nds32_vector_31, .-_nds32_vector_31
diff --git a/libgcc/config/nds32/isr-library/vec_vid31_4b.S b/libgcc/config/nds32/isr-library/vec_vid31_4b.S
new file mode 100644
index 00000000000..460bf5266da
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid31_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.31, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_31_4b
+	.type	_nds32_vector_31_4b, @function
+_nds32_vector_31_4b:
+1:
+	j	1b
+	.size	_nds32_vector_31_4b, .-_nds32_vector_31_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid32.S b/libgcc/config/nds32/isr-library/vec_vid32.S
new file mode 100644
index 00000000000..278e191b43e
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid32.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.32, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_32
+	.type	_nds32_vector_32, @function
+_nds32_vector_32:
+1:
+	j	1b
+	.size	_nds32_vector_32, .-_nds32_vector_32
diff --git a/libgcc/config/nds32/isr-library/vec_vid32_4b.S b/libgcc/config/nds32/isr-library/vec_vid32_4b.S
new file mode 100644
index 00000000000..d3b74f8129c
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid32_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.32, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_32_4b
+	.type	_nds32_vector_32_4b, @function
+_nds32_vector_32_4b:
+1:
+	j	1b
+	.size	_nds32_vector_32_4b, .-_nds32_vector_32_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid33.S b/libgcc/config/nds32/isr-library/vec_vid33.S
new file mode 100644
index 00000000000..320289db05e
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid33.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.33, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_33
+	.type	_nds32_vector_33, @function
+_nds32_vector_33:
+1:
+	j	1b
+	.size	_nds32_vector_33, .-_nds32_vector_33
diff --git a/libgcc/config/nds32/isr-library/vec_vid33_4b.S b/libgcc/config/nds32/isr-library/vec_vid33_4b.S
new file mode 100644
index 00000000000..fd3c997697e
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid33_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.33, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_33_4b
+	.type	_nds32_vector_33_4b, @function
+_nds32_vector_33_4b:
+1:
+	j	1b
+	.size	_nds32_vector_33_4b, .-_nds32_vector_33_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid34.S b/libgcc/config/nds32/isr-library/vec_vid34.S
new file mode 100644
index 00000000000..b9a99893386
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid34.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.34, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_34
+	.type	_nds32_vector_34, @function
+_nds32_vector_34:
+1:
+	j	1b
+	.size	_nds32_vector_34, .-_nds32_vector_34
diff --git a/libgcc/config/nds32/isr-library/vec_vid34_4b.S b/libgcc/config/nds32/isr-library/vec_vid34_4b.S
new file mode 100644
index 00000000000..0b726f6790c
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid34_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.34, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_34_4b
+	.type	_nds32_vector_34_4b, @function
+_nds32_vector_34_4b:
+1:
+	j	1b
+	.size	_nds32_vector_34_4b, .-_nds32_vector_34_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid35.S b/libgcc/config/nds32/isr-library/vec_vid35.S
new file mode 100644
index 00000000000..e53017d88da
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid35.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.35, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_35
+	.type	_nds32_vector_35, @function
+_nds32_vector_35:
+1:
+	j	1b
+	.size	_nds32_vector_35, .-_nds32_vector_35
diff --git a/libgcc/config/nds32/isr-library/vec_vid35_4b.S b/libgcc/config/nds32/isr-library/vec_vid35_4b.S
new file mode 100644
index 00000000000..7ac998faa6d
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid35_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.35, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_35_4b
+	.type	_nds32_vector_35_4b, @function
+_nds32_vector_35_4b:
+1:
+	j	1b
+	.size	_nds32_vector_35_4b, .-_nds32_vector_35_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid36.S b/libgcc/config/nds32/isr-library/vec_vid36.S
new file mode 100644
index 00000000000..2d3779c9ef5
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid36.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.36, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_36
+	.type	_nds32_vector_36, @function
+_nds32_vector_36:
+1:
+	j	1b
+	.size	_nds32_vector_36, .-_nds32_vector_36
diff --git a/libgcc/config/nds32/isr-library/vec_vid36_4b.S b/libgcc/config/nds32/isr-library/vec_vid36_4b.S
new file mode 100644
index 00000000000..54230ac22b7
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid36_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.36, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_36_4b
+	.type	_nds32_vector_36_4b, @function
+_nds32_vector_36_4b:
+1:
+	j	1b
+	.size	_nds32_vector_36_4b, .-_nds32_vector_36_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid37.S b/libgcc/config/nds32/isr-library/vec_vid37.S
new file mode 100644
index 00000000000..1b4066f99d3
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid37.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.37, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_37
+	.type	_nds32_vector_37, @function
+_nds32_vector_37:
+1:
+	j	1b
+	.size	_nds32_vector_37, .-_nds32_vector_37
diff --git a/libgcc/config/nds32/isr-library/vec_vid37_4b.S b/libgcc/config/nds32/isr-library/vec_vid37_4b.S
new file mode 100644
index 00000000000..f3a50b2f60e
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid37_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.37, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_37_4b
+	.type	_nds32_vector_37_4b, @function
+_nds32_vector_37_4b:
+1:
+	j	1b
+	.size	_nds32_vector_37_4b, .-_nds32_vector_37_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid38.S b/libgcc/config/nds32/isr-library/vec_vid38.S
new file mode 100644
index 00000000000..d626d3c3703
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid38.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.38, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_38
+	.type	_nds32_vector_38, @function
+_nds32_vector_38:
+1:
+	j	1b
+	.size	_nds32_vector_38, .-_nds32_vector_38
diff --git a/libgcc/config/nds32/isr-library/vec_vid38_4b.S b/libgcc/config/nds32/isr-library/vec_vid38_4b.S
new file mode 100644
index 00000000000..677145fea4d
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid38_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.38, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_38_4b
+	.type	_nds32_vector_38_4b, @function
+_nds32_vector_38_4b:
+1:
+	j	1b
+	.size	_nds32_vector_38_4b, .-_nds32_vector_38_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid39.S b/libgcc/config/nds32/isr-library/vec_vid39.S
new file mode 100644
index 00000000000..bbb376378e0
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid39.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.39, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_39
+	.type	_nds32_vector_39, @function
+_nds32_vector_39:
+1:
+	j	1b
+	.size	_nds32_vector_39, .-_nds32_vector_39
diff --git a/libgcc/config/nds32/isr-library/vec_vid39_4b.S b/libgcc/config/nds32/isr-library/vec_vid39_4b.S
new file mode 100644
index 00000000000..b5cd07e6a6d
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid39_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.39, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_39_4b
+	.type	_nds32_vector_39_4b, @function
+_nds32_vector_39_4b:
+1:
+	j	1b
+	.size	_nds32_vector_39_4b, .-_nds32_vector_39_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid40.S b/libgcc/config/nds32/isr-library/vec_vid40.S
new file mode 100644
index 00000000000..48c2eea7537
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid40.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.40, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_40
+	.type	_nds32_vector_40, @function
+_nds32_vector_40:
+1:
+	j	1b
+	.size	_nds32_vector_40, .-_nds32_vector_40
diff --git a/libgcc/config/nds32/isr-library/vec_vid40_4b.S b/libgcc/config/nds32/isr-library/vec_vid40_4b.S
new file mode 100644
index 00000000000..201988c43db
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid40_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.40, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_40_4b
+	.type	_nds32_vector_40_4b, @function
+_nds32_vector_40_4b:
+1:
+	j	1b
+	.size	_nds32_vector_40_4b, .-_nds32_vector_40_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid41.S b/libgcc/config/nds32/isr-library/vec_vid41.S
new file mode 100644
index 00000000000..7be5dfdf55d
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid41.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.41, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_41
+	.type	_nds32_vector_41, @function
+_nds32_vector_41:
+1:
+	j	1b
+	.size	_nds32_vector_41, .-_nds32_vector_41
diff --git a/libgcc/config/nds32/isr-library/vec_vid41_4b.S b/libgcc/config/nds32/isr-library/vec_vid41_4b.S
new file mode 100644
index 00000000000..1b8b57132ea
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid41_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.41, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_41_4b
+	.type	_nds32_vector_41_4b, @function
+_nds32_vector_41_4b:
+1:
+	j	1b
+	.size	_nds32_vector_41_4b, .-_nds32_vector_41_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid42.S b/libgcc/config/nds32/isr-library/vec_vid42.S
new file mode 100644
index 00000000000..f16127ba843
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid42.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.42, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_42
+	.type	_nds32_vector_42, @function
+_nds32_vector_42:
+1:
+	j	1b
+	.size	_nds32_vector_42, .-_nds32_vector_42
diff --git a/libgcc/config/nds32/isr-library/vec_vid42_4b.S b/libgcc/config/nds32/isr-library/vec_vid42_4b.S
new file mode 100644
index 00000000000..9bf7a5dff32
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid42_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.42, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_42_4b
+	.type	_nds32_vector_42_4b, @function
+_nds32_vector_42_4b:
+1:
+	j	1b
+	.size	_nds32_vector_42_4b, .-_nds32_vector_42_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid43.S b/libgcc/config/nds32/isr-library/vec_vid43.S
new file mode 100644
index 00000000000..eecfa98e5c2
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid43.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.43, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_43
+	.type	_nds32_vector_43, @function
+_nds32_vector_43:
+1:
+	j	1b
+	.size	_nds32_vector_43, .-_nds32_vector_43
diff --git a/libgcc/config/nds32/isr-library/vec_vid43_4b.S b/libgcc/config/nds32/isr-library/vec_vid43_4b.S
new file mode 100644
index 00000000000..0c9e5a44ffb
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid43_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.43, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_43_4b
+	.type	_nds32_vector_43_4b, @function
+_nds32_vector_43_4b:
+1:
+	j	1b
+	.size	_nds32_vector_43_4b, .-_nds32_vector_43_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid44.S b/libgcc/config/nds32/isr-library/vec_vid44.S
new file mode 100644
index 00000000000..47e24a41831
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid44.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.44, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_44
+	.type	_nds32_vector_44, @function
+_nds32_vector_44:
+1:
+	j	1b
+	.size	_nds32_vector_44, .-_nds32_vector_44
diff --git a/libgcc/config/nds32/isr-library/vec_vid44_4b.S b/libgcc/config/nds32/isr-library/vec_vid44_4b.S
new file mode 100644
index 00000000000..43aa995b1e5
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid44_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.44, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_44_4b
+	.type	_nds32_vector_44_4b, @function
+_nds32_vector_44_4b:
+1:
+	j	1b
+	.size	_nds32_vector_44_4b, .-_nds32_vector_44_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid45.S b/libgcc/config/nds32/isr-library/vec_vid45.S
new file mode 100644
index 00000000000..711aba55969
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid45.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.45, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_45
+	.type	_nds32_vector_45, @function
+_nds32_vector_45:
+1:
+	j	1b
+	.size	_nds32_vector_45, .-_nds32_vector_45
diff --git a/libgcc/config/nds32/isr-library/vec_vid45_4b.S b/libgcc/config/nds32/isr-library/vec_vid45_4b.S
new file mode 100644
index 00000000000..96b505ead26
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid45_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.45, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_45_4b
+	.type	_nds32_vector_45_4b, @function
+_nds32_vector_45_4b:
+1:
+	j	1b
+	.size	_nds32_vector_45_4b, .-_nds32_vector_45_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid46.S b/libgcc/config/nds32/isr-library/vec_vid46.S
new file mode 100644
index 00000000000..0c86a8c4eb4
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid46.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.46, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_46
+	.type	_nds32_vector_46, @function
+_nds32_vector_46:
+1:
+	j	1b
+	.size	_nds32_vector_46, .-_nds32_vector_46
diff --git a/libgcc/config/nds32/isr-library/vec_vid46_4b.S b/libgcc/config/nds32/isr-library/vec_vid46_4b.S
new file mode 100644
index 00000000000..1e3dee61f5c
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid46_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.46, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_46_4b
+	.type	_nds32_vector_46_4b, @function
+_nds32_vector_46_4b:
+1:
+	j	1b
+	.size	_nds32_vector_46_4b, .-_nds32_vector_46_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid47.S b/libgcc/config/nds32/isr-library/vec_vid47.S
new file mode 100644
index 00000000000..72954018559
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid47.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.47, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_47
+	.type	_nds32_vector_47, @function
+_nds32_vector_47:
+1:
+	j	1b
+	.size	_nds32_vector_47, .-_nds32_vector_47
diff --git a/libgcc/config/nds32/isr-library/vec_vid47_4b.S b/libgcc/config/nds32/isr-library/vec_vid47_4b.S
new file mode 100644
index 00000000000..e8556c21fbc
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid47_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.47, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_47_4b
+	.type	_nds32_vector_47_4b, @function
+_nds32_vector_47_4b:
+1:
+	j	1b
+	.size	_nds32_vector_47_4b, .-_nds32_vector_47_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid48.S b/libgcc/config/nds32/isr-library/vec_vid48.S
new file mode 100644
index 00000000000..92c583aecb4
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid48.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.48, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_48
+	.type	_nds32_vector_48, @function
+_nds32_vector_48:
+1:
+	j	1b
+	.size	_nds32_vector_48, .-_nds32_vector_48
diff --git a/libgcc/config/nds32/isr-library/vec_vid48_4b.S b/libgcc/config/nds32/isr-library/vec_vid48_4b.S
new file mode 100644
index 00000000000..c998a55f90f
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid48_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.48, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_48_4b
+	.type	_nds32_vector_48_4b, @function
+_nds32_vector_48_4b:
+1:
+	j	1b
+	.size	_nds32_vector_48_4b, .-_nds32_vector_48_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid49.S b/libgcc/config/nds32/isr-library/vec_vid49.S
new file mode 100644
index 00000000000..c1b1677d032
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid49.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.49, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_49
+	.type	_nds32_vector_49, @function
+_nds32_vector_49:
+1:
+	j	1b
+	.size	_nds32_vector_49, .-_nds32_vector_49
diff --git a/libgcc/config/nds32/isr-library/vec_vid49_4b.S b/libgcc/config/nds32/isr-library/vec_vid49_4b.S
new file mode 100644
index 00000000000..0c18eee1761
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid49_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.49, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_49_4b
+	.type	_nds32_vector_49_4b, @function
+_nds32_vector_49_4b:
+1:
+	j	1b
+	.size	_nds32_vector_49_4b, .-_nds32_vector_49_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid50.S b/libgcc/config/nds32/isr-library/vec_vid50.S
new file mode 100644
index 00000000000..910ad028436
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid50.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.50, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_50
+	.type	_nds32_vector_50, @function
+_nds32_vector_50:
+1:
+	j	1b
+	.size	_nds32_vector_50, .-_nds32_vector_50
diff --git a/libgcc/config/nds32/isr-library/vec_vid50_4b.S b/libgcc/config/nds32/isr-library/vec_vid50_4b.S
new file mode 100644
index 00000000000..1ec0b700244
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid50_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.50, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_50_4b
+	.type	_nds32_vector_50_4b, @function
+_nds32_vector_50_4b:
+1:
+	j	1b
+	.size	_nds32_vector_50_4b, .-_nds32_vector_50_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid51.S b/libgcc/config/nds32/isr-library/vec_vid51.S
new file mode 100644
index 00000000000..2053ebccf3a
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid51.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.51, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_51
+	.type	_nds32_vector_51, @function
+_nds32_vector_51:
+1:
+	j	1b
+	.size	_nds32_vector_51, .-_nds32_vector_51
diff --git a/libgcc/config/nds32/isr-library/vec_vid51_4b.S b/libgcc/config/nds32/isr-library/vec_vid51_4b.S
new file mode 100644
index 00000000000..38c02107ce5
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid51_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.51, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_51_4b
+	.type	_nds32_vector_51_4b, @function
+_nds32_vector_51_4b:
+1:
+	j	1b
+	.size	_nds32_vector_51_4b, .-_nds32_vector_51_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid52.S b/libgcc/config/nds32/isr-library/vec_vid52.S
new file mode 100644
index 00000000000..6eaac798038
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid52.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.52, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_52
+	.type	_nds32_vector_52, @function
+_nds32_vector_52:
+1:
+	j	1b
+	.size	_nds32_vector_52, .-_nds32_vector_52
diff --git a/libgcc/config/nds32/isr-library/vec_vid52_4b.S b/libgcc/config/nds32/isr-library/vec_vid52_4b.S
new file mode 100644
index 00000000000..de8a9283042
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid52_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.52, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_52_4b
+	.type	_nds32_vector_52_4b, @function
+_nds32_vector_52_4b:
+1:
+	j	1b
+	.size	_nds32_vector_52_4b, .-_nds32_vector_52_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid53.S b/libgcc/config/nds32/isr-library/vec_vid53.S
new file mode 100644
index 00000000000..8ac761394b1
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid53.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.53, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_53
+	.type	_nds32_vector_53, @function
+_nds32_vector_53:
+1:
+	j	1b
+	.size	_nds32_vector_53, .-_nds32_vector_53
diff --git a/libgcc/config/nds32/isr-library/vec_vid53_4b.S b/libgcc/config/nds32/isr-library/vec_vid53_4b.S
new file mode 100644
index 00000000000..564346c2347
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid53_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.53, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_53_4b
+	.type	_nds32_vector_53_4b, @function
+_nds32_vector_53_4b:
+1:
+	j	1b
+	.size	_nds32_vector_53_4b, .-_nds32_vector_53_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid54.S b/libgcc/config/nds32/isr-library/vec_vid54.S
new file mode 100644
index 00000000000..ef222ada15d
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid54.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.54, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_54
+	.type	_nds32_vector_54, @function
+_nds32_vector_54:
+1:
+	j	1b
+	.size	_nds32_vector_54, .-_nds32_vector_54
diff --git a/libgcc/config/nds32/isr-library/vec_vid54_4b.S b/libgcc/config/nds32/isr-library/vec_vid54_4b.S
new file mode 100644
index 00000000000..104b7e7958e
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid54_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.54, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_54_4b
+	.type	_nds32_vector_54_4b, @function
+_nds32_vector_54_4b:
+1:
+	j	1b
+	.size	_nds32_vector_54_4b, .-_nds32_vector_54_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid55.S b/libgcc/config/nds32/isr-library/vec_vid55.S
new file mode 100644
index 00000000000..c061e69f1b9
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid55.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.55, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_55
+	.type	_nds32_vector_55, @function
+_nds32_vector_55:
+1:
+	j	1b
+	.size	_nds32_vector_55, .-_nds32_vector_55
diff --git a/libgcc/config/nds32/isr-library/vec_vid55_4b.S b/libgcc/config/nds32/isr-library/vec_vid55_4b.S
new file mode 100644
index 00000000000..15fced687f2
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid55_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.55, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_55_4b
+	.type	_nds32_vector_55_4b, @function
+_nds32_vector_55_4b:
+1:
+	j	1b
+	.size	_nds32_vector_55_4b, .-_nds32_vector_55_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid56.S b/libgcc/config/nds32/isr-library/vec_vid56.S
new file mode 100644
index 00000000000..d7c305a8754
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid56.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.56, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_56
+	.type	_nds32_vector_56, @function
+_nds32_vector_56:
+1:
+	j	1b
+	.size	_nds32_vector_56, .-_nds32_vector_56
diff --git a/libgcc/config/nds32/isr-library/vec_vid56_4b.S b/libgcc/config/nds32/isr-library/vec_vid56_4b.S
new file mode 100644
index 00000000000..e8b975c8f41
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid56_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.56, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_56_4b
+	.type	_nds32_vector_56_4b, @function
+_nds32_vector_56_4b:
+1:
+	j	1b
+	.size	_nds32_vector_56_4b, .-_nds32_vector_56_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid57.S b/libgcc/config/nds32/isr-library/vec_vid57.S
new file mode 100644
index 00000000000..b701bbab67f
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid57.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.57, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_57
+	.type	_nds32_vector_57, @function
+_nds32_vector_57:
+1:
+	j	1b
+	.size	_nds32_vector_57, .-_nds32_vector_57
diff --git a/libgcc/config/nds32/isr-library/vec_vid57_4b.S b/libgcc/config/nds32/isr-library/vec_vid57_4b.S
new file mode 100644
index 00000000000..ef29203f607
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid57_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.57, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_57_4b
+	.type	_nds32_vector_57_4b, @function
+_nds32_vector_57_4b:
+1:
+	j	1b
+	.size	_nds32_vector_57_4b, .-_nds32_vector_57_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid58.S b/libgcc/config/nds32/isr-library/vec_vid58.S
new file mode 100644
index 00000000000..211b27dae59
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid58.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.58, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_58
+	.type	_nds32_vector_58, @function
+_nds32_vector_58:
+1:
+	j	1b
+	.size	_nds32_vector_58, .-_nds32_vector_58
diff --git a/libgcc/config/nds32/isr-library/vec_vid58_4b.S b/libgcc/config/nds32/isr-library/vec_vid58_4b.S
new file mode 100644
index 00000000000..9eaefca6c49
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid58_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.58, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_58_4b
+	.type	_nds32_vector_58_4b, @function
+_nds32_vector_58_4b:
+1:
+	j	1b
+	.size	_nds32_vector_58_4b, .-_nds32_vector_58_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid59.S b/libgcc/config/nds32/isr-library/vec_vid59.S
new file mode 100644
index 00000000000..227edf2e097
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid59.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.59, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_59
+	.type	_nds32_vector_59, @function
+_nds32_vector_59:
+1:
+	j	1b
+	.size	_nds32_vector_59, .-_nds32_vector_59
diff --git a/libgcc/config/nds32/isr-library/vec_vid59_4b.S b/libgcc/config/nds32/isr-library/vec_vid59_4b.S
new file mode 100644
index 00000000000..30fccab1ca3
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid59_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.59, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_59_4b
+	.type	_nds32_vector_59_4b, @function
+_nds32_vector_59_4b:
+1:
+	j	1b
+	.size	_nds32_vector_59_4b, .-_nds32_vector_59_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid60.S b/libgcc/config/nds32/isr-library/vec_vid60.S
new file mode 100644
index 00000000000..68889685825
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid60.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.60, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_60
+	.type	_nds32_vector_60, @function
+_nds32_vector_60:
+1:
+	j	1b
+	.size	_nds32_vector_60, .-_nds32_vector_60
diff --git a/libgcc/config/nds32/isr-library/vec_vid60_4b.S b/libgcc/config/nds32/isr-library/vec_vid60_4b.S
new file mode 100644
index 00000000000..26d94ac5f96
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid60_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.60, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_60_4b
+	.type	_nds32_vector_60_4b, @function
+_nds32_vector_60_4b:
+1:
+	j	1b
+	.size	_nds32_vector_60_4b, .-_nds32_vector_60_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid61.S b/libgcc/config/nds32/isr-library/vec_vid61.S
new file mode 100644
index 00000000000..b3111e75c35
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid61.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.61, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_61
+	.type	_nds32_vector_61, @function
+_nds32_vector_61:
+1:
+	j	1b
+	.size	_nds32_vector_61, .-_nds32_vector_61
diff --git a/libgcc/config/nds32/isr-library/vec_vid61_4b.S b/libgcc/config/nds32/isr-library/vec_vid61_4b.S
new file mode 100644
index 00000000000..845125cf3ec
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid61_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.61, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_61_4b
+	.type	_nds32_vector_61_4b, @function
+_nds32_vector_61_4b:
+1:
+	j	1b
+	.size	_nds32_vector_61_4b, .-_nds32_vector_61_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid62.S b/libgcc/config/nds32/isr-library/vec_vid62.S
new file mode 100644
index 00000000000..d6342381b22
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid62.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.62, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_62
+	.type	_nds32_vector_62, @function
+_nds32_vector_62:
+1:
+	j	1b
+	.size	_nds32_vector_62, .-_nds32_vector_62
diff --git a/libgcc/config/nds32/isr-library/vec_vid62_4b.S b/libgcc/config/nds32/isr-library/vec_vid62_4b.S
new file mode 100644
index 00000000000..d4c4413dd73
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid62_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.62, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_62_4b
+	.type	_nds32_vector_62_4b, @function
+_nds32_vector_62_4b:
+1:
+	j	1b
+	.size	_nds32_vector_62_4b, .-_nds32_vector_62_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid63.S b/libgcc/config/nds32/isr-library/vec_vid63.S
new file mode 100644
index 00000000000..8d2770c3f21
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid63.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.63, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_63
+	.type	_nds32_vector_63, @function
+_nds32_vector_63:
+1:
+	j	1b
+	.size	_nds32_vector_63, .-_nds32_vector_63
diff --git a/libgcc/config/nds32/isr-library/vec_vid63_4b.S b/libgcc/config/nds32/isr-library/vec_vid63_4b.S
new file mode 100644
index 00000000000..6403a7b6ed7
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid63_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.63, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_63_4b
+	.type	_nds32_vector_63_4b, @function
+_nds32_vector_63_4b:
+1:
+	j	1b
+	.size	_nds32_vector_63_4b, .-_nds32_vector_63_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid64.S b/libgcc/config/nds32/isr-library/vec_vid64.S
new file mode 100644
index 00000000000..269bdf92f75
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid64.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.64, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_64
+	.type	_nds32_vector_64, @function
+_nds32_vector_64:
+1:
+	j	1b
+	.size	_nds32_vector_64, .-_nds32_vector_64
diff --git a/libgcc/config/nds32/isr-library/vec_vid64_4b.S b/libgcc/config/nds32/isr-library/vec_vid64_4b.S
new file mode 100644
index 00000000000..64691899043
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid64_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.64, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_64_4b
+	.type	_nds32_vector_64_4b, @function
+_nds32_vector_64_4b:
+1:
+	j	1b
+	.size	_nds32_vector_64_4b, .-_nds32_vector_64_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid65.S b/libgcc/config/nds32/isr-library/vec_vid65.S
new file mode 100644
index 00000000000..4fbf3e43b8c
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid65.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.65, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_65
+	.type	_nds32_vector_65, @function
+_nds32_vector_65:
+1:
+	j	1b
+	.size	_nds32_vector_65, .-_nds32_vector_65
diff --git a/libgcc/config/nds32/isr-library/vec_vid65_4b.S b/libgcc/config/nds32/isr-library/vec_vid65_4b.S
new file mode 100644
index 00000000000..25f0a8773f7
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid65_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.65, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_65_4b
+	.type	_nds32_vector_65_4b, @function
+_nds32_vector_65_4b:
+1:
+	j	1b
+	.size	_nds32_vector_65_4b, .-_nds32_vector_65_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid66.S b/libgcc/config/nds32/isr-library/vec_vid66.S
new file mode 100644
index 00000000000..ad8d6d2a475
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid66.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.66, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_66
+	.type	_nds32_vector_66, @function
+_nds32_vector_66:
+1:
+	j	1b
+	.size	_nds32_vector_66, .-_nds32_vector_66
diff --git a/libgcc/config/nds32/isr-library/vec_vid66_4b.S b/libgcc/config/nds32/isr-library/vec_vid66_4b.S
new file mode 100644
index 00000000000..d283d4337cf
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid66_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.66, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_66_4b
+	.type	_nds32_vector_66_4b, @function
+_nds32_vector_66_4b:
+1:
+	j	1b
+	.size	_nds32_vector_66_4b, .-_nds32_vector_66_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid67.S b/libgcc/config/nds32/isr-library/vec_vid67.S
new file mode 100644
index 00000000000..f3a97a6db7e
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid67.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.67, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_67
+	.type	_nds32_vector_67, @function
+_nds32_vector_67:
+1:
+	j	1b
+	.size	_nds32_vector_67, .-_nds32_vector_67
diff --git a/libgcc/config/nds32/isr-library/vec_vid67_4b.S b/libgcc/config/nds32/isr-library/vec_vid67_4b.S
new file mode 100644
index 00000000000..fb8283dcf9f
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid67_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.67, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_67_4b
+	.type	_nds32_vector_67_4b, @function
+_nds32_vector_67_4b:
+1:
+	j	1b
+	.size	_nds32_vector_67_4b, .-_nds32_vector_67_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid68.S b/libgcc/config/nds32/isr-library/vec_vid68.S
new file mode 100644
index 00000000000..815f4368633
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid68.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.68, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_68
+	.type	_nds32_vector_68, @function
+_nds32_vector_68:
+1:
+	j	1b
+	.size	_nds32_vector_68, .-_nds32_vector_68
diff --git a/libgcc/config/nds32/isr-library/vec_vid68_4b.S b/libgcc/config/nds32/isr-library/vec_vid68_4b.S
new file mode 100644
index 00000000000..94959a8cd1d
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid68_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.68, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_68_4b
+	.type	_nds32_vector_68_4b, @function
+_nds32_vector_68_4b:
+1:
+	j	1b
+	.size	_nds32_vector_68_4b, .-_nds32_vector_68_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid69.S b/libgcc/config/nds32/isr-library/vec_vid69.S
new file mode 100644
index 00000000000..cd1d17c605d
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid69.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.69, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_69
+	.type	_nds32_vector_69, @function
+_nds32_vector_69:
+1:
+	j	1b
+	.size	_nds32_vector_69, .-_nds32_vector_69
diff --git a/libgcc/config/nds32/isr-library/vec_vid69_4b.S b/libgcc/config/nds32/isr-library/vec_vid69_4b.S
new file mode 100644
index 00000000000..df0f7d36842
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid69_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.69, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_69_4b
+	.type	_nds32_vector_69_4b, @function
+_nds32_vector_69_4b:
+1:
+	j	1b
+	.size	_nds32_vector_69_4b, .-_nds32_vector_69_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid70.S b/libgcc/config/nds32/isr-library/vec_vid70.S
new file mode 100644
index 00000000000..4a2edce903b
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid70.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.70, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_70
+	.type	_nds32_vector_70, @function
+_nds32_vector_70:
+1:
+	j	1b
+	.size	_nds32_vector_70, .-_nds32_vector_70
diff --git a/libgcc/config/nds32/isr-library/vec_vid70_4b.S b/libgcc/config/nds32/isr-library/vec_vid70_4b.S
new file mode 100644
index 00000000000..cb12f9f3fd2
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid70_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.70, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_70_4b
+	.type	_nds32_vector_70_4b, @function
+_nds32_vector_70_4b:
+1:
+	j	1b
+	.size	_nds32_vector_70_4b, .-_nds32_vector_70_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid71.S b/libgcc/config/nds32/isr-library/vec_vid71.S
new file mode 100644
index 00000000000..9ae82659ce5
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid71.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.71, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_71
+	.type	_nds32_vector_71, @function
+_nds32_vector_71:
+1:
+	j	1b
+	.size	_nds32_vector_71, .-_nds32_vector_71
diff --git a/libgcc/config/nds32/isr-library/vec_vid71_4b.S b/libgcc/config/nds32/isr-library/vec_vid71_4b.S
new file mode 100644
index 00000000000..4f640b9b340
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid71_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.71, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_71_4b
+	.type	_nds32_vector_71_4b, @function
+_nds32_vector_71_4b:
+1:
+	j	1b
+	.size	_nds32_vector_71_4b, .-_nds32_vector_71_4b
diff --git a/libgcc/config/nds32/isr-library/vec_vid72.S b/libgcc/config/nds32/isr-library/vec_vid72.S
new file mode 100644
index 00000000000..ab07fdb0dd3
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid72.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.72, "ax"
+	.vec_size	16
+	.align	4
+	.weak	_nds32_vector_72
+	.type	_nds32_vector_72, @function
+_nds32_vector_72:
+1:
+	j	1b
+	.size	_nds32_vector_72, .-_nds32_vector_72
diff --git a/libgcc/config/nds32/isr-library/vec_vid72_4b.S b/libgcc/config/nds32/isr-library/vec_vid72_4b.S
new file mode 100644
index 00000000000..d3864e1024c
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/vec_vid72_4b.S
@@ -0,0 +1,34 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_vector.72, "ax"
+	.vec_size	4
+	.align	2
+	.weak	_nds32_vector_72_4b
+	.type	_nds32_vector_72_4b, @function
+_nds32_vector_72_4b:
+1:
+	j	1b
+	.size	_nds32_vector_72_4b, .-_nds32_vector_72_4b
diff --git a/libgcc/config/nds32/isr-library/wrh.S b/libgcc/config/nds32/isr-library/wrh.S
new file mode 100644
index 00000000000..fe964a51578
--- /dev/null
+++ b/libgcc/config/nds32/isr-library/wrh.S
@@ -0,0 +1,32 @@
+/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.nds32_wrh, "a"
+	.align	2
+	.weak	_nds32_wrh
+	.type	_nds32_wrh, @object
+_nds32_wrh:
+	.word	0
+	.size	_nds32_wrh, .-_nds32_wrh
diff --git a/libgcc/config/nds32/lib1asmsrc-mculib.S b/libgcc/config/nds32/lib1asmsrc-mculib.S
new file mode 100644
index 00000000000..25295b6a9f2
--- /dev/null
+++ b/libgcc/config/nds32/lib1asmsrc-mculib.S
@@ -0,0 +1,5213 @@
+/* mculib libgcc routines of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.mdebug.abi_nds32
+	.previous
+
+
+/* ------------------------------------------- */
+/* FPBIT floating point operations for libgcc  */
+/* ------------------------------------------- */
+
+#ifdef L_addsub_sf
+
+	.text
+	.align	2
+	.global	__subsf3
+	.type	__subsf3, @function
+__subsf3:
+	push    $lp
+	pushm   $r6, $r9
+
+	move    $r2, #0x80000000
+	xor     $r1, $r1, $r2
+
+	j       .Lsfpadd
+
+	.global	__addsf3
+	.type	__addsf3, @function
+__addsf3:
+	push    $lp
+	pushm   $r6, $r9
+.Lsfpadd:
+	srli    $r5, $r0, #23
+	andi    $r5, $r5, #0xff
+	srli    $r7, $r1, #23
+	andi    $r7, $r7, #0xff
+	move    $r3, #0x80000000
+	slli    $r4, $r0, #8
+	or      $r4, $r4, $r3
+	slli    $r6, $r1, #8
+	or      $r6, $r6, $r3
+
+	addi    $r9, $r5, #-1
+	slti    $r15, $r9, #0xfe
+	beqzs8  .LEspecA
+
+.LElab1:
+	addi    $r9, $r7, #-1
+	slti    $r15, $r9, #0xfe
+	beqzs8  .LEspecB
+
+.LElab2:
+	sub     $r8, $r5, $r7
+	sltsi   $r15, $r8, #0
+	bnezs8  .Li1
+	sltsi   $r15, $r8, #0x20
+	bnezs8  .Li2
+	move    $r6, #2
+	j       .Le1
+.Li2:
+	move    $r2, $r6
+	srl     $r6, $r6, $r8
+	sll     $r9, $r6, $r8
+	beq     $r9, $r2, .Le1
+	ori     $r6, $r6, #2
+	j       .Le1
+.Li1:
+	move    $r5, $r7
+	subri   $r8, $r8, #0
+	sltsi   $r15, $r8, #0x20
+	bnezs8  .Li4
+	move    $r4, #2
+	j       .Le1
+.Li4:
+	move    $r2, $r4
+	srl     $r4, $r4, $r8
+	sll     $r9, $r4, $r8
+	beq     $r9, $r2, .Le1
+	ori     $r4, $r4, #2
+
+.Le1:
+	and     $r8, $r0, $r3
+	xor     $r9, $r8, $r1
+	sltsi   $r15, $r9, #0
+	bnezs8  .LEsub1
+
+	#ADD($r4, $r6)
+	add     $r4, $r4, $r6
+	slt     $r15, $r4, $r6
+	beqzs8  .LEres
+	andi    $r9, $r4, #1
+	beqz    $r9, .Li7
+	ori     $r4, $r4, #2
+.Li7:
+	srli    $r4, $r4, #1
+	addi    $r5, $r5, #1
+	subri   $r15, $r5, #0xff
+	bnezs8  .LEres
+	move    $r4, #0
+	j       .LEres
+
+.LEsub1:
+	#SUB($r4, $r6)
+	move    $r15, $r4
+	sub     $r4, $r4, $r6
+	slt     $r15, $r15, $r4
+	beqzs8  .Li9
+	subri   $r4, $r4, #0
+	xor     $r8, $r8, $r3
+	j       .Le9
+.Li9:
+	beqz    $r4, .LEzer
+.Le9:
+#ifdef __NDS32_PERF_EXT__
+	clz	$r2, $r4
+#else
+	pushm	$r0, $r1
+	pushm	$r3, $r5
+	move	$r0, $r4
+	bal	__clzsi2
+	move	$r2, $r0
+	popm	$r3, $r5
+	popm	$r0, $r1
+#endif
+	sub     $r5, $r5, $r2
+	sll     $r4, $r4, $r2
+
+.LEres:
+	blez    $r5, .LEund
+
+.LElab12:
+	#ADD($r4, $0x80)
+	move    $r15, #0x80
+	add     $r4, $r4, $r15
+	slt     $r15, $r4, $r15
+
+	#ADDC($r5, $0x0)
+	add     $r5, $r5, $r15
+	srli    $r9, $r4, #8
+	andi    $r9, $r9, #1
+	sub     $r4, $r4, $r9
+	slli    $r4, $r4, #1
+	srli    $r4, $r4, #9
+	slli    $r9, $r5, #23
+	or      $r4, $r4, $r9
+	or      $r0, $r4, $r8
+
+.LE999:
+	popm    $r6, $r9
+	pop     $lp
+	ret5    $lp
+
+.LEund:
+	subri   $r2, $r5, #1
+	slti    $r15, $r2, #0x20
+	beqzs8  .LEzer
+	move    $r9, #0x80000000
+	or      $r4, $r4, $r9
+	subri   $r9, $r2, #0x20
+	sll     $r5, $r4, $r9
+	srl     $r4, $r4, $r2
+	beqz    $r5, .Li10
+	ori     $r4, $r4, #1
+.Li10:
+	move    $r5, #0
+	addi    $r9, $r4, #0x80
+	sltsi   $r15, $r9, #0
+	beqzs8  .LElab12
+	move    $r5, #1
+	j       .LElab12
+
+.LEspecA:
+	bnez    $r5, .Li12
+	add     $r4, $r4, $r4
+	beqz    $r4, .Li13
+#ifdef __NDS32_PERF_EXT__
+	clz	$r8, $r4
+#else
+	pushm	$r0, $r5
+	move	$r0, $r4
+	bal	__clzsi2
+	move	$r8, $r0
+	popm	$r0, $r5
+#endif
+	sub     $r5, $r5, $r8
+	sll     $r4, $r4, $r8
+	j       .LElab1
+.Li13:
+	subri   $r15, $r7, #0xff
+	beqzs8  .LEspecB
+	move    $r9, #0x80000000
+	bne     $r1, $r9, .LEretB
+.Li12:
+	add     $r9, $r4, $r4
+	bnez    $r9, .LEnan
+	subri   $r15, $r7, #0xff
+	bnezs8  .LEretA
+	xor     $r9, $r0, $r1
+	sltsi   $r15, $r9, #0
+	bnezs8  .LEnan
+	j       .LEretB
+
+.LEspecB:
+	bnez    $r7, .Li15
+	add     $r6, $r6, $r6
+	beqz    $r6, .LEretA
+#ifdef __NDS32_PERF_EXT__
+	clz	$r8, $r6
+#else
+	pushm	$r0, $r5
+	move	$r0, $r6
+	bal	__clzsi2
+	move	$r8, $r0
+	popm	$r0, $r5
+#endif
+	sub     $r7, $r7, $r8
+	sll     $r6, $r6, $r8
+	j       .LElab2
+.Li15:
+	add     $r9, $r6, $r6
+	bnez    $r9, .LEnan
+
+.LEretB:
+	move    $r0, $r1
+	j       .LE999
+
+.LEretA:
+	j       .LE999
+
+.LEzer:
+	move    $r0, #0
+	j       .LE999
+
+.LEnan:
+	move    $r0, #0xffc00000
+	j       .LE999
+	.size	__subsf3, .-__subsf3
+	.size	__addsf3, .-__addsf3
+#endif /* L_addsub_sf */
+
+
+
+#ifdef L_sf_to_si
+
+	.text
+	.align	2
+	.global	__fixsfsi
+	.type	__fixsfsi, @function
+__fixsfsi:
+	push    $lp
+
+	slli    $r1, $r0, #8
+	move    $r3, #0x80000000
+	or      $r1, $r1, $r3
+	srli    $r3, $r0, #23
+	andi    $r3, $r3, #0xff
+	subri   $r2, $r3, #0x9e
+	blez    $r2, .LJspec
+	sltsi   $r15, $r2, #0x20
+	bnezs8  .Li42
+	move    $r0, #0
+	j       .LJ999
+.Li42:
+	srl     $r1, $r1, $r2
+	sltsi   $r15, $r0, #0
+	beqzs8  .Li43
+	subri   $r1, $r1, #0
+.Li43:
+	move    $r0, $r1
+
+.LJ999:
+	pop     $lp
+	ret5    $lp
+
+.LJspec:
+	move    $r3, #0x7f800000
+	slt     $r15, $r3, $r0
+	beqzs8  .Li44
+	move    $r0, #0x80000000
+	j       .LJ999
+.Li44:
+	move    $r0, #0x7fffffff
+	j       .LJ999
+	.size	__fixsfsi, .-__fixsfsi
+#endif /* L_sf_to_si */
+
+
+
+#ifdef L_divsi3
+
+	.text
+	.align	2
+	.globl	__divsi3
+	.type	__divsi3, @function
+__divsi3:
+	! ---------------------------------------------------------------------
+	! neg = 0;
+	! if (a < 0)
+	! {   a = -a;
+	!     neg = !neg;
+	! }
+	! ---------------------------------------------------------------------
+	sltsi	$r5, $r0, 0			! $r5  <- neg = (a < 0) ? 1 : 0
+	subri	$r4, $r0, 0			! $r4  <- a = -a
+	cmovn	$r0, $r4, $r5			! $r0  <- a = neg ? -a : a
+.L2:
+	! ---------------------------------------------------------------------
+	! if (b < 0)
+	! ---------------------------------------------------------------------
+	bgez	$r1, .L3			! if b >= 0, skip
+	! ---------------------------------------------------------------------
+	! {   b=-b;
+	!     neg=!neg;
+	! }
+	! ---------------------------------------------------------------------
+	subri	$r1, $r1, 0			! $r1  <- b = -b
+	subri	$r5, $r5, 1			! $r5  <- neg = !neg
+.L3:
+	! ---------------------------------------------------------------------
+	!!res = udivmodsi4 (a, b, 1);
+	! res = 0;
+	! if (den != 0)
+	! ---------------------------------------------------------------------
+	movi	$r2, 0				! $r2  <- res = 0
+	beqz	$r1, .L1			! if den == 0, skip
+	! ---------------------------------------------------------------------
+	! bit = 1;
+	! ---------------------------------------------------------------------
+	movi	$r4, 1				! $r4  <- bit = 1
+#ifndef __OPTIMIZE_SIZE__
+.L6:
+#endif
+	! ---------------------------------------------------------------------
+	! while (den < num && bit && !(den & (1L << 31)))
+	! ---------------------------------------------------------------------
+	slt	$ta, $r1, $r0			! $ta  <- den < num ?
+	beqz	$ta, .L5			! if no, skip
+	! ---------------------------------------------------------------------
+	! {   den << = 1;
+	!     bit << = 1;
+	! }
+	! ---------------------------------------------------------------------
+#if defined (__OPTIMIZE_SIZE__) && !defined (__NDS32_ISA_V3M__)
+	clz	$r3, $r1			! $r3  <- leading zero count for den
+	clz	$ta, $r0			! $ta  <- leading zero count for num
+	sub	$r3, $r3, $ta			! $r3  <- number of bits to shift
+	sll	$r1, $r1, $r3			! $r1  <- den
+	sll	$r4, $r4, $r3			! $r2  <- bit
+#else
+	slli	$r1, $r1, 1			! $r1  <- den << = 1
+	slli	$r4, $r4, 1			! $r4  <- bit << = 1
+	b	.L6				! continue loop
+#endif
+.L5:
+	! ---------------------------------------------------------------------
+	! while (bit)
+	! {   if (num >= den)
+	! ---------------------------------------------------------------------
+	slt	$ta, $r0, $r1			! $ta  <- num < den ?
+	bnez	$ta, .L9			! if yes, skip
+	! ---------------------------------------------------------------------
+	!     {   num -= den;
+	!         res |= bit;
+	!     }
+	! ---------------------------------------------------------------------
+	sub	$r0, $r0, $r1			! $r0  <- num -= den
+	or	$r2, $r2, $r4			! $r2  <- res |= bit
+.L9:
+	! ---------------------------------------------------------------------
+	!     bit >> = 1;
+	!     den >> = 1;
+	! }
+	!!if (modwanted)
+	!!    return num;
+	!!return res;
+	! ---------------------------------------------------------------------
+	srli	$r4, $r4, 1			! $r4  <- bit >> = 1
+	srli	$r1, $r1, 1			! $r1  <- den >> = 1
+	bnez	$r4, .L5			! if bit != 0, continue loop
+.L1:
+	! ---------------------------------------------------------------------
+	! if (neg)
+	!     res = -res;
+	! return res;
+	! ---------------------------------------------------------------------
+	subri	$r0, $r2, 0			! $r0  <- -res
+	cmovz	$r0, $r2, $r5			! $r0  <- neg ? -res : res
+	! ---------------------------------------------------------------------
+	ret
+	.size	__divsi3, .-__divsi3
+#endif /* L_divsi3 */
+
+
+
+#ifdef L_divdi3
+
+	!--------------------------------------
+	#ifdef __big_endian__
+		#define  V1H  $r0
+		#define  V1L  $r1
+		#define  V2H  $r2
+		#define  V2L  $r3
+	#else
+		#define  V1H  $r1
+		#define  V1L  $r0
+		#define  V2H  $r3
+		#define  V2L  $r2
+	#endif
+	!--------------------------------------
+	.text
+	.align	2
+	.globl	__divdi3
+	.type	__divdi3, @function
+__divdi3:
+	! prologue
+#ifdef __NDS32_ISA_V3M__
+	push25	$r10, 0
+#else
+	smw.adm	$r6, [$sp], $r10, 2
+#endif
+	! end of prologue
+	move	$r8, V1L
+	move	$r9, V1H
+	move	$r6, V2L
+	move	$r7, V2H
+	movi	$r10, 0
+	bgez	V1H, .L80
+	bal	__negdi2
+	move	$r8, V1L
+	move	$r9, V1H
+	movi	$r10, -1
+.L80:
+	bgez	$r7, .L81
+	move	V1L, $r6
+	move	V1H, $r7
+	bal	__negdi2
+	move	$r6, V1L
+	move	$r7, V1H
+	nor	$r10, $r10, $r10
+.L81:
+	move	V2L, $r6
+	move	V2H, $r7
+	move	V1L, $r8
+	move	V1H, $r9
+	movi	$r4, 0
+	bal	__udivmoddi4
+	beqz	$r10, .L82
+	bal	__negdi2
+.L82:
+	! epilogue
+#ifdef __NDS32_ISA_V3M__
+	pop25	$r10, 0
+#else
+	lmw.bim	$r6, [$sp], $r10, 2
+	ret
+#endif
+	.size	__divdi3, .-__divdi3
+#endif /* L_divdi3 */
+
+
+
+#ifdef L_modsi3
+
+	.text
+	.align	2
+	.globl	__modsi3
+	.type	__modsi3, @function
+__modsi3:
+	! ---------------------------------------------------------------------
+	! neg=0;
+	! if (a<0)
+	! {   a=-a;
+	!     neg=1;
+	! }
+	! ---------------------------------------------------------------------
+	sltsi	$r5, $r0, 0			! $r5  <- neg < 0 ? 1 : 0
+	subri	$r4, $r0, 0			! $r4  <- -a
+	cmovn	$r0, $r4, $r5			! $r0  <- |a|
+	! ---------------------------------------------------------------------
+	! if (b < 0)
+#ifndef __NDS32_PERF_EXT__
+	! ---------------------------------------------------------------------
+	bgez	$r1, .L3			! if b >= 0, skip
+	! ---------------------------------------------------------------------
+	!     b = -b;
+	! ---------------------------------------------------------------------
+	subri	$r1, $r1, 0			! $r1  <- |b|
+.L3:
+	! ---------------------------------------------------------------------
+	!!res = udivmodsi4 (a, b, 1);
+	! if (den != 0)
+	! ---------------------------------------------------------------------
+#else /* __NDS32_PERF_EXT__ */
+	!     b = -b;
+	!!res = udivmodsi4 (a, b, 1);
+	! if (den != 0)
+	! ---------------------------------------------------------------------
+	abs	$r1, $r1			! $r1  <- |b|
+#endif /* __NDS32_PERF_EXT__ */
+	beqz	$r1, .L1			! if den == 0, skip
+	! ---------------------------------------------------------------------
+	! {   bit = 1;
+	!     res = 0;
+	! ---------------------------------------------------------------------
+	movi	$r4, 1				! $r4  <- bit = 1
+#ifndef __OPTIMIZE_SIZE__
+.L6:
+#endif
+	! ---------------------------------------------------------------------
+	!     while (den < num&&bit && !(den & (1L << 31)))
+	! ---------------------------------------------------------------------
+	slt	$ta, $r1, $r0			! $ta  <- den < num ?
+	beqz	$ta, .L5			! if no, skip
+	! ---------------------------------------------------------------------
+	!     {   den << = 1;
+	!         bit << = 1;
+	!     }
+	! ---------------------------------------------------------------------
+#if defined (__OPTIMIZE_SIZE__) && ! defined (__NDS32_ISA_V3M__)
+	clz	$r3, $r1			! $r3  <- leading zero count for den
+	clz	$ta, $r0			! $ta  <- leading zero count for num
+	sub	$r3, $r3, $ta			! $r3  <- number of bits to shift
+	sll	$r1, $r1, $r3			! $r1  <- den
+	sll	$r4, $r4, $r3			! $r2  <- bit
+#else
+	slli	$r1, $r1, 1			! $r1  <- den << = 1
+	slli	$r4, $r4, 1			! $r4  <- bit << = 1
+	b	.L6				! continue loop
+#endif
+.L5:
+	! ---------------------------------------------------------------------
+	!     while (bit)
+	!     {   if (num >= den)
+	!         {   num -= den;
+	!             res |= bit;
+	!         }
+	!         bit >> = 1;
+	!         den >> = 1;
+	!     }
+	! }
+	!!if (modwanted)
+	!!    return num;
+	!!return res;
+	! ---------------------------------------------------------------------
+	sub	$r2, $r0, $r1			! $r2  <- num - den
+	slt	$ta, $r0, $r1			! $ta  <- num < den ?
+	srli	$r4, $r4, 1			! $r4  <- bit >> = 1
+	cmovz	$r0, $r2, $ta			! $r0  <- num = (num < den) ? num : num - den
+	srli	$r1, $r1, 1			! $r1  <- den >> = 1
+	bnez	$r4, .L5			! if bit != 0, continue loop
+.L1:
+	! ---------------------------------------------------------------------
+	! if (neg)
+	!     res = -res;
+	! return res;
+	! ---------------------------------------------------------------------
+	subri	$r3, $r0, 0			! $r3  <- -res
+	cmovn	$r0, $r3, $r5			! $r0  <- neg ? -res : res
+	! ---------------------------------------------------------------------
+	ret
+	.size	__modsi3, .-__modsi3
+#endif /* L_modsi3 */
+
+
+
+#ifdef L_moddi3
+
+	!--------------------------------------
+	#ifdef __big_endian__
+		#define  V1H  $r0
+		#define  V1L  $r1
+		#define  V2H  $r2
+		#define  V2L  $r3
+	#else
+		#define  V1H  $r1
+		#define  V1L  $r0
+		#define  V2H  $r3
+		#define  V2L  $r2
+	#endif
+	!--------------------------------------
+	.text
+	.align	2
+	.globl	__moddi3
+	.type	__moddi3, @function
+__moddi3:
+	! =====================================================================
+	! stack allocation:
+	! sp+32 +-----------------------+
+	!       | $lp                   |
+	! sp+28 +-----------------------+
+	!       | $r6 - $r10            |
+	! sp+8  +-----------------------+
+	!       |                       |
+	! sp+4  +-----------------------+
+	!       |                       |
+	! sp    +-----------------------+
+	! =====================================================================
+	! prologue
+#ifdef __NDS32_ISA_V3M__
+	push25	$r10, 8
+#else
+	smw.adm	$r6, [$sp], $r10, 2
+	addi	$sp, $sp, -8
+#endif
+	! end of prologue
+	!------------------------------------------
+	! 	__moddi3 (DWtype u, DWtype v)
+	!		{
+	!			word_type c = 0;
+	!			DWunion uu = {.ll = u};
+	!			DWunion vv = {.ll = v};
+	!			DWtype w;
+	!		if (uu.s.high < 0)
+	!  		  c = ~c,
+	!		  uu.ll = -uu.ll;
+	!---------------------------------------------
+	move	$r8, V1L
+	move	$r9, V1H
+	move	$r6, V2L
+	move	$r7, V2H
+	movi	$r10, 0        ! r10 = c = 0
+	bgez	V1H, .L80      ! if u > 0 , go L80
+	bal	__negdi2
+	move	$r8, V1L
+	move	$r9, V1H
+	movi	$r10, -1       ! r10 = c = ~c
+	!------------------------------------------------
+	!	 	if (vv.s.high < 0)
+	!		  vv.ll = -vv.ll;
+	!----------------------------------------------
+.L80:
+	bgez	$r7, .L81     !  if v > 0 , go L81
+	move	V1L, $r6
+	move	V1H, $r7
+	bal	__negdi2
+	move	$r6, V1L
+	move	$r7, V1H
+	!------------------------------------------
+	!		(void) __udivmoddi4 (uu.ll, vv.ll, &w);
+	!		if (c)
+	!		  w = -w;
+	!		return w;
+	!-----------------------------------------
+.L81:
+	move	V2L, $r6
+	move	V2H, $r7
+	move	V1L, $r8
+	move	V1H, $r9
+	addi	$r4, $sp, 0
+	bal	__udivmoddi4
+	lwi	$r0, [$sp+(0)]    ! le: sp + 0 is low, be: sp + 0 is high
+	lwi	$r1, [$sp+(4)]    ! le: sp + 4 is low, be: sp + 4 is high
+	beqz	$r10, .L82
+	bal	__negdi2
+.L82:
+	! epilogue
+#ifdef __NDS32_ISA_V3M__
+	pop25	$r10, 8
+#else
+	addi	$sp, $sp, 8
+	lmw.bim	$r6, [$sp], $r10, 2
+	ret
+#endif
+	.size	__moddi3, .-__moddi3
+#endif /* L_moddi3 */
+
+
+
+#ifdef L_mulsi3
+
+	.text
+	.align	2
+	.globl	__mulsi3
+	.type	__mulsi3, @function
+__mulsi3:
+	! ---------------------------------------------------------------------
+	! r = 0;
+	! while (a)
+	! $r0:       r
+	! $r1:       b
+	! $r2:       a
+	! ---------------------------------------------------------------------
+	beqz	$r0, .L7			! if a == 0, done
+	move	$r2, $r0			! $r2  <- a
+	movi	$r0, 0				! $r0  <- r <- 0
+.L8:
+	! ---------------------------------------------------------------------
+	! {   if (a & 1)
+	!         r += b;
+	!     a >> = 1;
+	!     b << = 1;
+	! }
+	! $r0:       r
+	! $r1:       b
+	! $r2:       a
+	! $r3:       scratch
+	! $r4:       scratch
+	! ---------------------------------------------------------------------
+	andi	$r3, $r2, 1			! $r3  <- a & 1
+	add	$r4, $r0, $r1			! $r4  <- r += b
+	cmovn	$r0, $r4, $r3			! $r0  <- r
+	srli	$r2, $r2, 1			! $r2  <- a >> = 1
+	slli	$r1, $r1, 1			! $r1  <- b << = 1
+	bnez	$r2, .L8			! if a != 0, continue loop
+.L7:
+	! ---------------------------------------------------------------------
+	! $r0:       return code
+	! ---------------------------------------------------------------------
+	ret
+	.size	__mulsi3, .-__mulsi3
+#endif /* L_mulsi3 */
+
+
+
+#ifdef L_udivsi3
+
+	.text
+	.align	2
+	.globl	__udivsi3
+	.type	__udivsi3, @function
+__udivsi3:
+	! ---------------------------------------------------------------------
+	!!res=udivmodsi4(a,b,0);
+	! res=0;
+	! if (den!=0)
+	! ---------------------------------------------------------------------
+	movi	$r2, 0				! $r2  <- res=0
+	beqz	$r1, .L1			! if den==0, skip
+	! ---------------------------------------------------------------------
+	! {   bit=1;
+	! ---------------------------------------------------------------------
+	movi	$r4, 1				! $r4  <- bit=1
+#ifndef __OPTIMIZE_SIZE__
+.L6:
+#endif
+	! ---------------------------------------------------------------------
+	!     while (den<num
+	! ---------------------------------------------------------------------
+	slt	$ta, $r1, $r0			! $ta  <- den<num?
+	beqz	$ta, .L5			! if no, skip
+	! ---------------------------------------------------------------------
+	!          &&bit&&!(den&(1L<<31)))
+	! ---------------------------------------------------------------------
+	bltz	$r1, .L5			! if den<0, skip
+	! ---------------------------------------------------------------------
+	!     {   den<<=1;
+	!         bit<<=1;
+	!     }
+	! ---------------------------------------------------------------------
+#if defined (__OPTIMIZE_SIZE__) && ! defined (__NDS32_ISA_V3M__)
+	clz	$r3, $r1			! $r3  <- leading zero count for den
+	clz	$ta, $r0			! $ta  <- leading zero count for num
+	sub	$r3, $r3, $ta			! $r3  <- number of bits to shift
+	sll	$r1, $r1, $r3			! $r1  <- den
+	sll	$r2, $r2, $r3			! $r2  <- bit
+#else
+	slli	$r1, $r1, 1			! $r1  <- den<<=1
+	slli	$r4, $r4, 1			! $r4  <- bit<<=1
+	b	.L6				! continue loop
+#endif
+.L5:
+	! ---------------------------------------------------------------------
+	!     while (bit)
+	!     {   if (num>=den)
+	! ---------------------------------------------------------------------
+	slt	$ta, $r0, $r1			! $ta  <- num<den?
+	bnez	$ta, .L9			! if yes, skip
+	! ---------------------------------------------------------------------
+	!         {   num-=den;
+	!             res|=bit;
+	!         }
+	! ---------------------------------------------------------------------
+	sub	$r0, $r0, $r1			! $r0  <- num-=den
+	or	$r2, $r2, $r4			! $r2  <- res|=bit
+.L9:
+	! ---------------------------------------------------------------------
+	!         bit>>=1;
+	!         den>>=1;
+	!     }
+	! }
+	!!if (modwanted)
+	!!    return num;
+	!!return res;
+	! ---------------------------------------------------------------------
+	srli	$r4, $r4, 1			! $r4  <- bit>>=1
+	srli	$r1, $r1, 1			! $r1  <- den>>=1
+	bnez	$r4, .L5			! if bit!=0, continue loop
+.L1:
+	! ---------------------------------------------------------------------
+	! return res;
+	! ---------------------------------------------------------------------
+	move	$r0, $r2			! $r0  <- return value
+	! ---------------------------------------------------------------------
+	! ---------------------------------------------------------------------
+	ret
+	.size	__udivsi3, .-__udivsi3
+#endif /* L_udivsi3 */
+
+
+
+#ifdef L_udivdi3
+
+	!--------------------------------------
+	#ifdef __big_endian__
+		#define  V1H  $r0
+		#define  V1L  $r1
+		#define  V2H  $r2
+		#define  V2L  $r3
+	#else
+		#define  V1H  $r1
+		#define  V1L  $r0
+		#define  V2H  $r3
+		#define  V2L  $r2
+	#endif
+	!--------------------------------------
+
+	.text
+	.align	2
+	.globl	__udivdi3
+	.type	__udivdi3, @function
+__udivdi3:
+	! prologue
+#ifdef __NDS32_ISA_V3M__
+	push25	$r8, 0
+#else
+	smw.adm	$r6, [$sp], $r8, 2
+#endif
+	! end of prologue
+	movi	$r4, 0
+	bal	__udivmoddi4
+	! epilogue
+#ifdef __NDS32_ISA_V3M__
+	pop25	$r8, 0
+#else
+	lmw.bim	$r6, [$sp], $r8, 2
+	ret
+#endif
+	.size	__udivdi3, .-__udivdi3
+#endif /* L_udivdi3 */
+
+
+
+#ifdef L_udivmoddi4
+
+	.text
+	.align	2
+	.globl	fudiv_qrnnd
+	.type	fudiv_qrnnd, @function
+	#ifdef __big_endian__
+		#define P1H     $r0
+		#define P1L     $r1
+		#define P2H     $r2
+		#define P2L     $r3
+		#define W6H     $r4
+		#define W6L     $r5
+		#define OFFSET_L 4
+		#define OFFSET_H 0
+	#else
+		#define P1H     $r1
+		#define P1L     $r0
+		#define P2H     $r3
+		#define P2L     $r2
+		#define W6H     $r5
+		#define W6L     $r4
+		#define OFFSET_L 0
+		#define OFFSET_H 4
+	#endif
+fudiv_qrnnd:
+	!------------------------------------------------------
+	! function:  fudiv_qrnnd(quotient, remainder, high_numerator, low_numerator, denominator)
+	!            divides a UDWtype, composed by the UWtype integers,HIGH_NUMERATOR (from $r4)
+	!            and LOW_NUMERATOR(from $r5) by DENOMINATOR(from $r6), and places the quotient
+	!            in $r7 and the remainder in $r8.
+	!------------------------------------------------------
+	!  in reg:$r4(n1), $r5(n0), $r6(d0)
+	!  __d1 = ((USItype) (d) >> ((4 * 8) / 2));
+	!  __d0 = ((USItype) (d) & (((USItype) 1 << ((4 * 8) / 2)) - 1));
+	!  __r1 = (n1) % __d1;
+	!  __q1 = (n1) / __d1;
+	!  __m = (USItype) __q1 * __d0;
+	!  __r1 = __r1 * ((USItype) 1 << ((4 * 8) / 2)) | ((USItype) (n0) >> ((4 * 8) / 2));
+	!   if (__r1 < __m)
+	!    {
+	!------------------------------------------------------
+	smw.adm $r0, [$sp], $r4, 2				! store $lp, when use BASELINE_V1,and must store $r0-$r3
+	srli	$r7, $r6, 16					! $r7 = d1 =__ll_highpart (d)
+	movi	$ta, 65535
+	and	  $r8, $r6, $ta       				! $r8 = d0 = __ll_lowpart (d)
+
+	divr	$r9, $r10, $r4, $r7				! $r9 = q1, $r10 = r1
+	and	  $r4, $r5, $ta       				! $r4 = __ll_lowpart (n0)
+	slli	$r10, $r10, 16      				! $r10 = r1 << 16
+	srli	$ta, $r5, 16        				! $ta = __ll_highpart (n0)
+
+	or	$r10, $r10, $ta					! $r10 <- $r0|$r3=__r1
+	mul	$r5, $r9, $r8					! $r5 = m =  __q1*__d0
+	slt	$ta, $r10, $r5					! $ta <- __r1<__m
+	beqz	$ta, .L2					!if yes,skip
+	!------------------------------------------------------
+	!    __q1--, __r1 += (d);
+	!    if (__r1 >= (d))
+	!     {
+	!------------------------------------------------------
+
+	add	$r10, $r10, $r6					!$r10 <- __r1+d=__r1
+	addi	$r9, $r9, -1					!$r9 <- __q1--=__q1
+	slt	$ta, $r10, $r6					!$ta <- __r1<d
+	bnez	$ta, .L2					!if yes,skip
+	!------------------------------------------------------
+	!       if (__r1 < __m)
+	!        {
+	!------------------------------------------------------
+
+	slt	$ta, $r10, $r5					!$ta <- __r1<__m
+	beqz	$ta, .L2					!if yes,skip
+	!------------------------------------------------------
+	!           __q1--, __r1 += (d);
+	!        }
+	!     }
+	!  }
+	!------------------------------------------------------
+
+	addi	$r9, $r9, -1					!$r9 <- __q1--=__q1
+	add	$r10, $r10, $r6					!$r2 <- __r1+d=__r1
+.L2:
+	!------------------------------------------------------
+	!  __r1 -= __m;
+	!  __r0 = __r1 % __d1;
+	!  __q0 = __r1 / __d1;
+	!  __m = (USItype) __q0 * __d0;
+	!  __r0 = __r0 * ((USItype) 1 << ((4 * 8) / 2)) \
+	!        | ((USItype) (n0) & (((USItype) 1 << ((4 * 8) / 2)) - 1));
+	!  if (__r0 < __m)
+	!   {
+	!------------------------------------------------------
+	sub  $r10, $r10, $r5					!$r10 <- __r1-__m=__r1
+	divr	$r7, $r10, $r10, $r7				!$r7 <- r1/__d1=__q0,$r10 <- r1%__d1=__r0
+	slli	$r10, $r10, 16					!$r10 <- __r0<<16
+	mul	$r5, $r8, $r7					!$r5 <- __q0*__d0=__m
+	or	$r10, $r4, $r10					!$r3 <- $r0|__ll_lowpart (n0) =__r0
+	slt	$ta, $r10, $r5					!$ta <- __r0<__m
+	beqz	$ta, .L5					!if yes,skip
+	!------------------------------------------------------
+	!      __q0--, __r0 += (d);
+	!      if (__r0 >= (d))
+	!       {
+	!------------------------------------------------------
+
+	add	$r10, $r10, $r6					!$r10 <- __r0+d=__r0
+	addi	$r7, $r7, -1					!$r7 <- __q0--=__q0
+	slt	$ta, $r10, $r6					!$ta <- __r0<d
+	bnez	$ta, .L5					!if yes,skip
+	!------------------------------------------------------
+	!         if (__r0 < __m)
+	!          {
+	!------------------------------------------------------
+
+	slt	$ta, $r10, $r5					!$ta <- __r0<__m
+	beqz	$ta, .L5					!if yes,skip
+	!------------------------------------------------------
+	!             __q0--, __r0 += (d);
+	!          }
+	!       }
+	!   }
+	!------------------------------------------------------
+
+	add	  $r10, $r10, $r6				!$r3 <- __r0+d=__r0
+	addi	$r7, $r7, -1					!$r2 <- __q0--=__q0
+.L5:
+	!------------------------------------------------------
+	!   __r0 -= __m;
+	!   *q = (USItype) __q1 * ((USItype) 1 << ((4 * 8) / 2)) | __q0;
+	!   *r = __r0;
+	!}
+	!------------------------------------------------------
+
+	sub		$r8, $r10, $r5				!$r8 = r = r0 = __r0-__m
+	slli	$r9, $r9, 16					!$r9 <- __q1<<16
+	or	$r7, $r9, $r7					!$r7 = q = $r9|__q0
+	lmw.bim $r0, [$sp], $r4, 2
+	ret
+	.size	fudiv_qrnnd, .-fudiv_qrnnd
+
+	.align	2
+	.globl	__udivmoddi4
+	.type	__udivmoddi4, @function
+__udivmoddi4:
+	! =====================================================================
+	! stack allocation:
+	! sp+40 +------------------+
+	!       | q1               |
+	! sp+36 +------------------+
+	!       | q0               |
+	! sp+32 +------------------+
+	!       | bm               |
+	! sp+28 +------------------+
+	!       | $lp              |
+	! sp+24 +------------------+
+	!       | $fp              |
+	! sp+20 +------------------+
+	!       | $r6 - $r10       |
+	! sp    +------------------+
+	! =====================================================================
+
+	addi	$sp, $sp, -40
+	smw.bi	$r6, [$sp], $r10, 10
+	!------------------------------------------------------
+	!  d0 = dd.s.low;
+	!  d1 = dd.s.high;
+	!  n0 = nn.s.low;
+	!  n1 = nn.s.high;
+	!  if (d1 == 0)
+	!   {
+	!------------------------------------------------------
+
+	move	$fp, $r4					!$fp <- rp
+	bnez	P2H, .L9					!if yes,skip
+	!------------------------------------------------------
+	!     if (d0 > n1)
+	!      {
+	!------------------------------------------------------
+
+	slt	$ta, P1H, P2L					!$ta <- n1<d0
+	beqz	$ta, .L10					!if yes,skip
+#ifndef __NDS32_PERF_EXT__
+	smw.adm $r0, [$sp], $r5, 0
+	move    $r0, P2L
+	bal __clzsi2
+	move	$r7, $r0
+	lmw.bim $r0, [$sp], $r5, 0
+#else
+	clz  $r7, P2L
+#endif
+	swi     $r7,  [$sp+(28)]
+	beqz	$r7, .L18					!if yes,skip
+	!------------------------------------------------------
+	!         d0 = d0 << bm;
+	!         n1 = (n1 << bm) | (n0 >> ((4 * 8) - bm));
+	!         n0 = n0 << bm;
+	!      }
+	!------------------------------------------------------
+
+	subri	$r5, $r7, 32					!$r5 <- 32-bm
+	srl	$r5, P1L, $r5					!$r5 <- n0>>$r5
+	sll	$r6, P1H, $r7					!$r6 <- n1<<bm
+	or	P1H, $r6, $r5					!P2h <- $r5|$r6=n1
+	sll	P1L, P1L, $r7					!P1H <- n0<<bm=n0
+	sll	P2L, P2L, $r7					!P2L <- d0<<bm=d0
+.L18:
+	!------------------------------------------------------
+	!    fudiv_qrnnd (&q0, &n0, n1, n0, d0);
+	!    q1 = 0;
+	!  } #if (d0 > n1)
+	!------------------------------------------------------
+
+	move 	$r4,P1H						! give fudiv_qrnnd args
+	move 	$r5,P1L						!
+	move 	$r6,P2L						!
+	bal	fudiv_qrnnd					!calcaulte q0 n0
+	movi	$r6, 0						!P1L <- 0
+	swi     $r7,[$sp+32]                                    !q0
+	swi     $r6,[$sp+36]                                    !q1
+	move    P1L,$r8						!n0
+	b	.L19
+.L10:
+	!------------------------------------------------------
+	!  else #if (d0 > n1)
+	!   {
+	!     if(d0 == 0)
+	!------------------------------------------------------
+
+	bnez	P2L, .L20					!if yes,skip
+	!------------------------------------------------------
+	!      d0 = 1 / d0;
+	!------------------------------------------------------
+
+	movi	$r4, 1						!P1L <- 1
+	divr	P2L, $r4, $r4, P2L				!$r9=1/d0,P1L=1%d0
+.L20:
+
+#ifndef __NDS32_PERF_EXT__
+	smw.adm $r0, [$sp], $r5, 0
+	move    $r0, P2L
+	bal __clzsi2
+	move    $r7, $r0
+	lmw.bim $r0, [$sp], $r5, 0
+#else
+	clz  $r7, P2L
+#endif
+	swi     $r7,[$sp+(28)]      ! store bm
+	beqz	$r7, .L28					! if yes,skip
+	!------------------------------------------------------
+	!         b = (4 * 8) - bm;
+	!         d0 = d0 << bm;
+	!         n2 = n1 >> b;
+	!         n1 = (n1 << bm) | (n0 >> b);
+	!         n0 = n0 << bm;
+	!         fudiv_qrnnd (&q1, &n1, n2, n1, d0);
+	!    }
+	!------------------------------------------------------
+
+	subri	$r10, $r7, 32					!$r10 <- 32-bm=b
+	srl	$r4, P1L, $r10					!$r4 <- n0>>b
+	sll	$r5, P1H, $r7					!$r5 <- n1<<bm
+	or	$r5, $r5, $r4					!$r5 <- $r5|$r4=n1  !for fun
+	sll	P2L, P2L, $r7					!P2L <- d0<<bm=d0   !for fun
+	sll	P1L, P1L, $r7					!P1L <- n0<<bm=n0
+	srl	$r4, P1H, $r10					!$r4 <- n1>>b=n2    !for fun
+
+	move    $r6,P2L                     			!for fun
+	bal	fudiv_qrnnd					!caculate q1, n1
+
+	swi  $r7,[$sp+(36)]          ! q1 store
+	move P1H,$r8                 ! n1 store
+
+	move $r4,$r8	             ! prepare for next fudiv_qrnnd()
+	move $r5,P1L
+	move $r6,P2L
+	b	.L29
+.L28:
+	!------------------------------------------------------
+	!    else // bm != 0
+	!     {
+	!        n1 -= d0;
+	!        q1 = 1;
+	!
+	!------------------------------------------------------
+
+	sub	P1H, P1H, P2L					!P1L <- n1-d0=n1
+	movi	$ta, 1						!
+	swi	$ta, [$sp+(36)]	                                !1 -> [$sp+(36)]
+
+	move $r4,P1H						! give fudiv_qrnnd args
+	move $r5,P1L
+	move $r6,P2L
+.L29:
+	!------------------------------------------------------
+	!    fudiv_qrnnd (&q0, &n0, n1, n0, d0);
+	!------------------------------------------------------
+
+	bal	fudiv_qrnnd					!calcuate  q0, n0
+	swi     $r7,[$sp+(32)]  !q0 store
+	move    P1L,$r8		!n0
+.L19:
+	!------------------------------------------------------
+	!    if (rp != 0)
+	!     {
+	!------------------------------------------------------
+
+	beqz	$fp, .L31					!if yes,skip
+	!------------------------------------------------------
+	!         rr.s.low = n0 >> bm;
+	!         rr.s.high = 0;
+	!         *rp = rr.ll;
+	!     }
+	!------------------------------------------------------
+
+	movi    $r5, 0							!$r5 <- 0
+	lwi     $r7,[$sp+(28)]    					!load bm
+	srl	$r4, P1L, $r7     	     				!$r4 <- n0>>bm
+        swi	$r4, [$fp+OFFSET_L]	  !r0				!$r4 -> [$sp+(48)]
+	swi	$r5, [$fp+OFFSET_H]	  !r1				!0 -> [$sp+(52)]
+	b .L31
+.L9:
+	!------------------------------------------------------
+	! else # d1 == 0
+	!  {
+	!     if(d1 > n1)
+	!      {
+	!------------------------------------------------------
+
+	slt	$ta, P1H, P2H					!$ta <- n1<d1
+	beqz	$ta, .L32					!if yes,skip
+	!------------------------------------------------------
+	!         q0 = 0;
+	!	  q1 = 0;
+	!         if (rp != 0)
+	!          {
+	!------------------------------------------------------
+
+	movi	$r5, 0						!$r5 <- 0
+	swi	$r5, [$sp+(32)]	   !q0				!0 -> [$sp+(40)]=q1
+	swi	$r5, [$sp+(36)]    !q1				!0 -> [$sp+(32)]=q0
+	beqz	$fp, .L31					!if yes,skip
+	!------------------------------------------------------
+	!             rr.s.low = n0;
+	!	      rr.s.high = n1;
+	!             *rp = rr.ll;
+	!          }
+	!------------------------------------------------------
+
+	swi	P1L, [$fp+OFFSET_L]					!P1L -> [rp]
+	swi	P1H, [$fp+OFFSET_H]					!P1H -> [rp+4]
+	b	.L31
+.L32:
+#ifndef __NDS32_PERF_EXT__
+	smw.adm $r0, [$sp], $r5, 0
+	move    $r0, P2H
+	bal __clzsi2
+	move    $r7, $r0
+	lmw.bim $r0, [$sp], $r5, 0
+#else
+	clz  $r7,P2H
+#endif
+        swi     $r7,[$sp+(28)] 	                                !$r7=bm  store
+	beqz	$r7, .L42					!if yes,skip
+	!------------------------------------------------------
+	!        USItype m1, m0;
+	!        b = (4 * 8) - bm;
+	!        d1 = (d0 >> b) | (d1 << bm);
+	!        d0 = d0 << bm;
+	!        n2 = n1 >> b;
+	!        n1 = (n0 >> b) | (n1 << bm);
+	!        n0 = n0 << bm;
+	!        fudiv_qrnnd (&q0, &n1, n2, n1, d1);
+	!------------------------------------------------------
+
+	subri	$r10, $r7, 32					!$r10 <- 32-bm=b
+	srl	$r5, P2L, $r10					!$r5 <- d0>>b
+	sll	$r6, P2H, $r7					!$r6 <- d1<<bm
+	or      $r6, $r5, $r6                                   !$r6 <- $r5|$r6=d1  !! func
+	move	P2H, $r6 					!P2H <- d1
+	srl     $r4, P1H, $r10                                  !$r4 <- n1>>b=n2    !!! func
+	srl	$r8, P1L, $r10					!$r8 <- n0>>b       !!$r8
+	sll     $r9, P1H, $r7                                   !$r9 <- n1<<bm
+	or	$r5, $r8, $r9					!$r5 <- $r8|$r9=n1  !func
+	sll     P2L, P2L, $r7                                   !P2L <- d0<<bm=d0
+	sll	P1L, P1L, $r7					!P1L <- n0<<bm=n0
+
+	bal	fudiv_qrnnd					! cal  q0,n1
+	swi     $r7,[$sp+(32)]
+	move    P1H,$r8            ! fudiv_qrnnd (&q0, &n1, n2, n1, d1);
+        move    $r6, $r7           ! from func
+
+	!----------------------------------------------------
+	!       #umul_ppmm (m1, m0, q0, d0);
+	!        do
+	!         {     USItype __x0, __x1, __x2, __x3;
+	!               USItype __ul, __vl, __uh, __vh;
+	!               __ul = ((USItype) (q0) & (((USItype) 1 << ((4 * 8) / 2)) - 1));
+	!               __uh = ((USItype) (q0) >> ((4 * 8) / 2));
+	!               __vl = ((USItype) (d0) & (((USItype) 1 << ((4 * 8) / 2)) - 1));
+	!               __vh = ((USItype) (d0) >> ((4 * 8) / 2));
+	!               __x0 = (USItype) __ul * __vl;
+	!               __x1 = (USItype) __ul * __vh;
+	!               __x2 = (USItype) __uh * __vl;
+	!               __x3 = (USItype) __uh * __vh;
+	!               __x1 += ((USItype) (__x0) >> ((4 * 8) / 2));
+	!               __x1 += __x2;
+	!               if (__x1 < __x2)
+	!                  __x3 += ((USItype) 1 << ((4 * 8) / 2));
+	!               (m1) = __x3 + ((USItype) (__x1) >> ((4 * 8) / 2));
+	!               (m0) = (USItype)(q0*d0);
+	!        }
+	!        if (m1 > n1)
+	!---------------------------------------------------
+#ifdef __NDS32_ISA_V3M__
+        !mulr64  $r4, P2L, $r6
+	smw.adm $r0, [$sp], $r3, 0
+	move	P1L, P2L
+	move	P2L, $r6
+	movi	P1H, 0
+	movi	P2H, 0
+	bal	__muldi3
+	movd44	$r4, $r0
+	lmw.bim $r0, [$sp], $r3, 0
+        move    $r8, W6H
+        move    $r5, W6L
+#else
+        mulr64  $r4, P2L, $r6
+        move    $r8, W6H
+        move    $r5, W6L
+#endif
+	slt	$ta, P1H, $r8					!$ta <- n1<m1
+	bnez	$ta, .L46					!if yes,skip
+	!------------------------------------------------------
+	!   if(m1 == n1)
+	!------------------------------------------------------
+
+	bne	$r8, P1H, .L45					!if yes,skip
+	!------------------------------------------------------
+	!   if(m0 > n0)
+	!------------------------------------------------------
+
+	slt	$ta, P1L, $r5					!$ta <- n0<m0
+	beqz	$ta, .L45					!if yes,skip
+.L46:
+	!------------------------------------------------------
+	!    {
+	!       q0--;
+	!       # sub_ddmmss (m1, m0, m1, m0, d1, d0);
+	!       do
+	!        {   USItype __x;
+	!            __x = (m0) - (d0);
+	!            (m1) = (m1) - (d1) - (__x > (m0));
+	!            (m0) = __x;
+	!        }
+	!    }
+	!------------------------------------------------------
+
+	sub	$r4, $r5, P2L					!$r4 <- m0-d0=__x
+	addi	$r6, $r6, -1					!$r6 <- q0--=q0
+	sub	$r8, $r8, P2H					!$r8 <- m1-d1
+	swi	$r6, [$sp+(32)]	      ! q0			!$r6->[$sp+(32)]
+	slt	$ta, $r5, $r4					!$ta <- m0<__x
+	sub	$r8, $r8, $ta					!$r8 <- P1H-P1L=m1
+	move	$r5, $r4					!$r5 <- __x=m0
+.L45:
+	!------------------------------------------------------
+	!    q1 = 0;
+	!    if (rp != 0)
+	!     {
+	!------------------------------------------------------
+
+	movi	$r4, 0						!$r4 <- 0
+	swi	$r4, [$sp+(36)]					!0 -> [$sp+(40)]=q1
+	beqz	$fp, .L31					!if yes,skip
+	!------------------------------------------------------
+	!      # sub_ddmmss (n1, n0, n1, n0, m1, m0);
+	!      do
+	!       {   USItype __x;
+	!           __x = (n0) - (m0);
+	!           (n1) = (n1) - (m1) - (__x > (n0));
+	!           (n0) = __x;
+	!       }
+	!       rr.s.low = (n1 << b) | (n0 >> bm);
+	!       rr.s.high = n1 >> bm;
+	!       *rp = rr.ll;
+	!------------------------------------------------------
+
+	sub	$r4, P1H, $r8					!$r4 <- n1-m1
+	sub	$r6, P1L, $r5					!$r6 <- n0-m0=__x=n0
+	slt	$ta, P1L, $r6					!$ta <- n0<__x
+	sub	P1H, $r4, $ta					!P1H <- $r4-$ta=n1
+	move    P1L, $r6
+
+	lwi     $r7,[$sp+(28)]         ! load bm
+	subri   $r10,$r7,32
+	sll	$r4, P1H, $r10					!$r4 <- n1<<b
+	srl	$r5, P1L, $r7					!$r5 <- __x>>bm
+	or	$r6, $r5, $r4					!$r6 <- $r5|$r4=rr.s.low
+	srl	$r8, P1H, $r7					!$r8 <- n1>>bm =rr.s.high
+	swi	$r6, [$fp+OFFSET_L]				!
+	swi	$r8, [$fp+OFFSET_H]				!
+	b	.L31
+.L42:
+	!------------------------------------------------------
+	!  else
+	!   {
+	!     if(n1 > d1)
+	!------------------------------------------------------
+
+	slt	$ta, P2H, P1H					!$ta <- P2H<P1H
+	bnez	$ta, .L52					!if yes,skip
+	!------------------------------------------------------
+	!     if (n0 >= d0)
+	!------------------------------------------------------
+
+	slt	$ta, P1L, P2L					!$ta <- P1L<P2L
+	bnez	$ta, .L51					!if yes,skip
+	!------------------------------------------------------
+	!        q0 = 1;
+	!        do
+	!         {   USItype __x;
+	!             __x = (n0) - (d0);
+	!             (n1) = (n1) - (d1) - (__x > (n0));
+	!             (n0) = __x;
+	!         }
+	!------------------------------------------------------
+.L52:
+	sub	$r4, P1H, P2H					!$r4 <- P1H-P2H
+	sub	$r6, P1L, P2L					!$r6 <- no-d0=__x=n0
+	slt	$ta, P1L, $r6					!$ta <- no<__x
+	sub	P1H, $r4, $ta					!P1H <- $r4-$ta=n1
+	move    P1L, $r6					!n0
+	movi	$r5, 1						!
+	swi	$r5, [$sp+(32)]					!1 -> [$sp+(32)]=q0
+	b	.L54
+.L51:
+	!------------------------------------------------------
+	!       q0 = 0;
+	!------------------------------------------------------
+
+	movi    $r5,0
+	swi	$r5, [$sp+(32)]					!$r5=0 -> [$sp+(32)]
+.L54:
+	!------------------------------------------------------
+	!       q1 = 0;
+	!       if (rp != 0)
+	!        {
+	!------------------------------------------------------
+
+	movi	$r5, 0						!
+	swi	$r5, [$sp+(36)]					!0 -> [$sp+(36)]
+	beqz	$fp, .L31
+	!------------------------------------------------------
+	!          rr.s.low = n0;
+	!          rr.s.high = n1;
+	!          *rp = rr.ll;
+	!        }
+	!------------------------------------------------------
+
+	swi	P1L, [$fp+OFFSET_L]				!remainder
+	swi	P1H, [$fp+OFFSET_H]				!
+.L31:
+	!------------------------------------------------------
+	! const DWunion ww = {{.low = q0, .high = q1}};
+	! return ww.ll;
+	!}
+	!------------------------------------------------------
+
+	lwi	P1L, [$sp+(32)]					!quotient
+	lwi	P1H, [$sp+(36)]
+	lmw.bim	$r6, [$sp], $r10, 10
+	addi	$sp, $sp, 12
+	ret
+	.size	__udivmoddi4, .-__udivmoddi4
+#endif /* L_udivmoddi4 */
+
+
+
+#ifdef L_umodsi3
+
+	! =====================================================================
+	.text
+	.align	2
+	.globl	__umodsi3
+	.type	__umodsi3, @function
+__umodsi3:
+	! ---------------------------------------------------------------------
+	!!res=udivmodsi4(a,b,1);
+	! if (den==0)
+	!     return num;
+	! ---------------------------------------------------------------------
+	beqz	$r1, .L1			! if den==0, skip
+	! ---------------------------------------------------------------------
+	! bit=1;
+	! res=0;
+	! ---------------------------------------------------------------------
+	movi	$r4, 1				! $r4  <- bit=1
+#ifndef __OPTIMIZE_SIZE__
+.L6:
+#endif
+	! ---------------------------------------------------------------------
+	! while (den<num
+	! ---------------------------------------------------------------------
+	slt	$ta, $r1, $r0			! $ta  <- den<num?
+	beqz	$ta, .L5			! if no, skip
+	! ---------------------------------------------------------------------
+	!      &&bit&&!(den&(1L<<31)))
+	! ---------------------------------------------------------------------
+	bltz	$r1, .L5			! if den<0, skip
+	! ---------------------------------------------------------------------
+	! {   den<<=1;
+	!     bit<<=1;
+	! }
+	! ---------------------------------------------------------------------
+#if defined (__OPTIMIZE_SIZE__) && ! defined (__NDS32_ISA_V3M__)
+	clz	$r3, $r1			! $r3  <- leading zero count for den
+	clz	$ta, $r0			! $ta  <- leading zero count for num
+	sub	$r3, $r3, $ta			! $r3  <- number of bits to shift
+	sll	$r1, $r1, $r3			! $r1  <- den
+	sll	$r4, $r4, $r3			! $r2  <- bit
+#else
+	slli	$r1, $r1, 1			! $r1  <- den<<=1
+	slli	$r4, $r4, 1			! $r4  <- bit<<=1
+	b	.L6				! continue loop
+#endif
+.L5:
+	! ---------------------------------------------------------------------
+	! while (bit)
+	! {   if (num>=den)
+	!     {   num-=den;
+	!         res|=bit;
+	!     }
+	!     bit>>=1;
+	!     den>>=1;
+	! }
+	!!if (modwanted)
+	!!    return num;
+	!!return res;
+	! ---------------------------------------------------------------------
+	sub	$r2, $r0, $r1			! $r2  <- num-den
+	slt	$ta, $r0, $r1			! $ta  <- num<den?
+	srli	$r4, $r4, 1			! $r4  <- bit>>=1
+	cmovz	$r0, $r2, $ta			! $r0  <- num=(num<den)?num:num-den
+	srli	$r1, $r1, 1			! $r1  <- den>>=1
+	bnez	$r4, .L5			! if bit!=0, continue loop
+.L1:
+	! ---------------------------------------------------------------------
+	! return res;
+	! ---------------------------------------------------------------------
+	ret
+	.size	__umodsi3, .-__umodsi3
+#endif /* L_umodsi3 */
+
+
+
+#ifdef L_umoddi3
+
+	!--------------------------------------
+	#ifdef __big_endian__
+		#define  V1H  $r0
+		#define  V1L  $r1
+		#define  V2H  $r2
+		#define  V2L  $r3
+	#else
+		#define  V1H  $r1
+		#define  V1L  $r0
+		#define  V2H  $r3
+		#define  V2L  $r2
+	#endif
+	!--------------------------------------
+	.text
+	.align	2
+	.globl	__umoddi3
+	.type	__umoddi3, @function
+__umoddi3:
+	! prologue
+	addi	$sp, $sp, -12
+	swi $lp, [$sp+(0)]
+	! end of prologue
+	addi	$r4, $sp, 4
+	bal	__udivmoddi4
+	lwi	$r0, [$sp+(4)]    ! __udivmoddi4 return low when LE mode or return high when BE mode
+	lwi	$r1, [$sp+(8)]    !
+.L82:
+	! epilogue
+	lwi $lp, [$sp+(0)]
+	addi	$sp, $sp, 12
+	ret
+	.size	__umoddi3, .-__umoddi3
+#endif /* L_umoddi3 */
+
+
+
+#ifdef L_muldi3
+
+#ifdef __big_endian__
+	#define P1H	$r0
+	#define P1L	$r1
+	#define P2H	$r2
+	#define P2L	$r3
+
+	#define V2H $r4
+	#define V2L $r5
+#else
+	#define P1H	$r1
+	#define P1L	$r0
+	#define P2H	$r3
+	#define P2L	$r2
+
+	#define V2H $r5
+	#define V2L $r4
+#endif
+
+	! ====================================================================
+	.text
+	.align	2
+	.globl	__muldi3
+	.type	__muldi3, @function
+__muldi3:
+	! parameter passing for libgcc functions normally involves 2 doubles
+	!---------------------------------------
+#ifdef __NDS32_ISA_V3M__
+	! There is no mulr64 instruction in Andes ISA V3M.
+	! So we must provide a sequence of calculations to complete the job.
+	smw.adm   $r6, [$sp], $r9, 0x0
+	zeh33	  $r4, P1L
+	srli      $r7, P1L, 16
+	zeh33     $r5, P2L
+	mul       $r6, $r5, $r4
+	mul33     $r5, $r7
+	srli      $r8, P2L, 16
+	mov55     $r9, $r5
+	maddr32   $r9, $r8, $r4
+	srli      $r4, $r6, 16
+	add       $r4, $r9, $r4
+	slt45     $r4, $r5
+	slli      $r5, $r15, 16
+	maddr32   $r5, $r8, $r7
+	mul       P2L, P1H, P2L
+	srli      $r7, $r4, 16
+	maddr32   P2L, P2H, P1L
+	add333    P1H, $r5, $r7
+	slli      $r4, $r4, 16
+	zeh33     $r6, $r6
+	add333    P1L, $r4, $r6
+	add333    P1H, P2L, P1H
+	lmw.bim   $r6, [$sp], $r9, 0x0
+	ret
+#else /* not  __NDS32_ISA_V3M__ */
+	mul	    $ta, P1L, P2H
+	mulr64	$r4, P1L, P2L
+	maddr32	$ta, P1H, P2L
+	move	  P1L, V2L
+	add	    P1H, $ta, V2H
+	ret
+#endif /* not __NDS32_ISA_V3M__ */
+	.size	__muldi3, .-__muldi3
+#endif /* L_muldi3 */
+
+
+
+#ifdef L_addsub_df
+
+#ifndef __big_endian__
+	#define P1L     $r0
+	#define P1H     $r1
+	#define P2L     $r2
+	#define P2H     $r3
+	#define P3L     $r4
+	#define P3H     $r5
+	#define O1L     $r7
+	#define O1H	$r8
+#else
+	#define P1H     $r0
+	#define P1L     $r1
+	#define P2H     $r2
+	#define P2L     $r3
+	#define P3H     $r4
+	#define P3L     $r5
+	#define O1H     $r7
+	#define O1L	$r8
+#endif
+	.text
+	.align	2
+	.global  __subdf3
+	.type    __subdf3, @function
+__subdf3:
+	push    $lp
+	pushm   $r6, $r10
+
+	move    $r4, #0x80000000
+	xor     P2H, P2H, $r4
+
+	j       .Lsdpadd
+
+	.global  __adddf3
+	.type    __adddf3, @function
+__adddf3:
+	push    $lp
+	pushm   $r6, $r10
+.Lsdpadd:
+	slli    $r6, P1H, #1
+	srli    $r6, $r6, #21
+	slli    P3H, P1H, #11
+	srli    $r10, P1L, #21
+	or      P3H, P3H, $r10
+	slli    P3L, P1L, #11
+	move    O1L, #0x80000000
+	or      P3H, P3H, O1L
+	slli    $r9, P2H, #1
+	srli    $r9, $r9, #21
+	slli    O1H, P2H, #11
+	srli    $r10, P2L, #21
+	or      O1H, O1H, $r10
+	or      O1H, O1H, O1L
+	slli    O1L, P2L, #11
+
+	addi    $r10, $r6, #-1
+	slti    $r15, $r10, #0x7fe
+	beqzs8  .LEspecA
+
+.LElab1:
+	addi    $r10, $r9, #-1
+	slti    $r15, $r10, #0x7fe
+	beqzs8  .LEspecB
+
+.LElab2:
+	#NORMd($r4, P2L, P1L)
+	bnez    P3H, .LL1
+	bnez    P3L, .LL2
+	move    $r6, #0
+	j       .LL3
+.LL2:
+	move    P3H, P3L
+	move    P3L, #0
+	move    P2L, #32
+	sub     $r6, $r6, P2L
+.LL1:
+#ifndef __big_endian__
+#ifdef __NDS32_PERF_EXT__
+	clz	$r2, $r5
+#else
+	pushm	$r0, $r1
+	pushm	$r3, $r5
+	move	$r0, $r5
+	bal	__clzsi2
+	move	$r2, $r0
+	popm	$r3, $r5
+	popm	$r0, $r1
+#endif
+#else /* __big_endian__ */
+#ifdef __NDS32_PERF_EXT__
+	clz	$r3, $r4
+#else
+	pushm	$r0, $r2
+	pushm	$r4, $r5
+	move	$r0, $r4
+	bal	__clzsi2
+	move	$r3, $r0
+	popm	$r4, $r5
+	popm	$r0, $r2
+#endif
+#endif /* __big_endian__ */
+	beqz    P2L, .LL3
+	sub     $r6, $r6, P2L
+	subri   P1L, P2L, #32
+	srl     P1L, P3L, P1L
+	sll     P3L, P3L, P2L
+	sll     P3H, P3H, P2L
+	or      P3H, P3H, P1L
+.LL3:
+	#NORMd End
+
+	#NORMd($r7, P2L, P1L)
+	bnez    O1H, .LL4
+	bnez    O1L, .LL5
+	move    $r9, #0
+	j       .LL6
+.LL5:
+	move    O1H, O1L
+	move    O1L, #0
+	move    P2L, #32
+	sub     $r9, $r9, P2L
+.LL4:
+#ifndef __big_endian__
+#ifdef __NDS32_PERF_EXT__
+	clz	$r2, O1H
+#else
+	pushm	$r0, $r1
+	pushm	$r3, $r5
+	move	$r0, O1H
+	bal	__clzsi2
+	move	$r2, $r0
+	popm	$r3, $r5
+	popm	$r0, $r1
+#endif
+#else /* __big_endian__ */
+#ifdef __NDS32_PERF_EXT__
+	clz	$r3, O1H
+#else
+	pushm	$r0, $r2
+	pushm	$r4, $r5
+	move	$r0, O1H
+	bal	__clzsi2
+	move	$r3, $r0
+	popm	$r4, $r5
+	popm	$r0, $r2
+#endif
+#endif /* __big_endian__ */
+	beqz    P2L, .LL6
+	sub     $r9, $r9, P2L
+	subri   P1L, P2L, #32
+	srl     P1L, O1L, P1L
+	sll     O1L, O1L, P2L
+	sll     O1H, O1H, P2L
+	or      O1H, O1H, P1L
+.LL6:
+	#NORMd End
+
+	move    $r10, #0x80000000
+	and     P1H, P1H, $r10
+
+	beq     $r6, $r9, .LEadd3
+	slts    $r15, $r9, $r6
+	beqzs8  .Li1
+	sub     $r9, $r6, $r9
+	move    P2L, #0
+.LL7:
+	move    $r10, #0x20
+	slt     $r15, $r9, $r10
+	bnezs8  .LL8
+	or      P2L, P2L, O1L
+	move    O1L, O1H
+	move    O1H, #0
+	addi    $r9, $r9, #0xffffffe0
+	bnez    O1L, .LL7
+.LL8:
+	beqz    $r9, .LEadd3
+	move    P1L, O1H
+	move    $r10, O1L
+	srl     O1L, O1L, $r9
+	srl     O1H, O1H, $r9
+	subri   $r9, $r9, #0x20
+	sll     P1L, P1L, $r9
+	or      O1L, O1L, P1L
+	sll     $r10, $r10, $r9
+	or      P2L, P2L, $r10
+	beqz    P2L, .LEadd3
+	ori     O1L, O1L, #1
+	j       .LEadd3
+.Li1:
+	move    $r15, $r6
+	move    $r6, $r9
+	sub     $r9, $r9, $r15
+	move    P2L, #0
+.LL10:
+	move    $r10, #0x20
+	slt     $r15, $r9, $r10
+	bnezs8  .LL11
+	or      P2L, P2L, P3L
+	move    P3L, P3H
+	move    P3H, #0
+	addi    $r9, $r9, #0xffffffe0
+	bnez    P3L, .LL10
+.LL11:
+	beqz    $r9, .LEadd3
+	move    P1L, P3H
+	move    $r10, P3L
+	srl     P3L, P3L, $r9
+	srl     P3H, P3H, $r9
+	subri   $r9, $r9, #0x20
+	sll     P1L, P1L, $r9
+	or      P3L, P3L, P1L
+	sll     $r10, $r10, $r9
+	or      P2L, P2L, $r10
+	beqz    P2L, .LEadd3
+	ori     P3L, P3L, #1
+
+.LEadd3:
+	xor     $r10, P1H, P2H
+	sltsi   $r15, $r10, #0
+	bnezs8  .LEsub1
+
+	#ADD(P3L, O1L)
+	add     P3L, P3L, O1L
+	slt     $r15, P3L, O1L
+
+	#ADDCC(P3H, O1H)
+	beqzs8  .LL13
+	add     P3H, P3H, O1H
+	slt     $r15, P3H, O1H
+	beqzs8  .LL14
+	addi    P3H, P3H, #0x1
+	j       .LL15
+.LL14:
+	move    $r15, #1
+	add     P3H, P3H, $r15
+	slt     $r15, P3H, $r15
+	j       .LL15
+.LL13:
+	add     P3H, P3H, O1H
+	slt     $r15, P3H, O1H
+.LL15:
+
+	beqzs8  .LEres
+	andi    $r10, P3L, #1
+	beqz    $r10, .Li3
+	ori     P3L, P3L, #2
+.Li3:
+	srli    P3L, P3L, #1
+	slli    $r10, P3H, #31
+	or      P3L, P3L, $r10
+	srli    P3H, P3H, #1
+	move    $r10, #0x80000000
+	or      P3H, P3H, $r10
+	addi    $r6, $r6, #1
+	subri   $r15, $r6, #0x7ff
+	bnezs8  .LEres
+	move    $r10, #0x7ff00000
+	or      P1H, P1H, $r10
+	move    P1L, #0
+	j       .LEretA
+
+.LEsub1:
+	#SUB(P3L, O1L)
+	move    $r15, P3L
+	sub     P3L, P3L, O1L
+	slt     $r15, $r15, P3L
+
+	#SUBCC(P3H, O1H)
+	beqzs8  .LL16
+	move    $r15, P3H
+	sub     P3H, P3H, O1H
+	slt     $r15, $r15, P3H
+	beqzs8  .LL17
+	subi333 P3H, P3H, #1
+	j       .LL18
+.LL17:
+	move    $r15, P3H
+	subi333 P3H, P3H, #1
+	slt     $r15, $r15, P3H
+	j       .LL18
+.LL16:
+	move    $r15, P3H
+	sub     P3H, P3H, O1H
+	slt     $r15, $r15, P3H
+.LL18:
+
+	beqzs8  .Li5
+	move    $r10, #0x80000000
+	xor     P1H, P1H, $r10
+
+	subri   P3H, P3H, #0
+	beqz    P3L, .LL19
+	subri   P3L, P3L, #0
+	subi45  P3H, #1
+.LL19:
+
+.Li5:
+	#NORMd($r4, $r9, P1L)
+	bnez    P3H, .LL20
+	bnez    P3L, .LL21
+	move    $r6, #0
+	j       .LL22
+.LL21:
+	move    P3H, P3L
+	move    P3L, #0
+	move    $r9, #32
+	sub     $r6, $r6, $r9
+.LL20:
+#ifdef __NDS32_PERF_EXT__
+	clz	$r9, P3H
+#else
+	pushm	$r0, $r5
+	move	$r0, P3H
+	bal	__clzsi2
+	move	$r9, $r0
+	popm	$r0, $r5
+#endif
+	beqz    $r9, .LL22
+	sub     $r6, $r6, $r9
+	subri   P1L, $r9, #32
+	srl     P1L, P3L, P1L
+	sll     P3L, P3L, $r9
+	sll     P3H, P3H, $r9
+	or      P3H, P3H, P1L
+.LL22:
+	#NORMd End
+
+	or      $r10, P3H, P3L
+	bnez    $r10, .LEres
+	move    P1H, #0
+
+.LEres:
+	blez    $r6, .LEund
+
+.LElab8:
+	#ADD(P3L, $0x400)
+	move    $r15, #0x400
+	add     P3L, P3L, $r15
+	slt     $r15, P3L, $r15
+
+	#ADDCC(P3H, $0x0)
+	beqzs8  .LL25
+	add     P3H, P3H, $r15
+	slt     $r15, P3H, $r15
+.LL25:
+
+	#ADDC($r6, $0x0)
+	add     $r6, $r6, $r15
+	srli    $r10, P3L, #11
+	andi    $r10, $r10, #1
+	sub     P3L, P3L, $r10
+	srli    P1L, P3L, #11
+	slli    $r10, P3H, #21
+	or      P1L, P1L, $r10
+	slli    $r10, P3H, #1
+	srli    $r10, $r10, #12
+	or      P1H, P1H, $r10
+	slli    $r10, $r6, #20
+	or      P1H, P1H, $r10
+
+.LEretA:
+.LE999:
+	popm    $r6, $r10
+	pop     $lp
+	ret5    $lp
+
+.LEspecA:
+	#ADD(P3L, P3L)
+	move    $r15, P3L
+	add     P3L, P3L, P3L
+	slt     $r15, P3L, $r15
+
+	#ADDC(P3H, P3H)
+	add     P3H, P3H, P3H
+	add     P3H, P3H, $r15
+	bnez    $r6, .Li7
+	or      $r10, P3H, P3L
+	beqz    $r10, .Li8
+	j       .LElab1
+.Li8:
+	subri   $r15, $r9, #0x7ff
+	beqzs8  .LEspecB
+	add     P3L, P2H, P2H
+	or      $r10, P3L, P2L
+	bnez    $r10, .LEretB
+	sltsi   $r15, P2H, #0
+	bnezs8  .LEretA
+
+.LEretB:
+	move    P1L, P2L
+	move    P1H, P2H
+	j       .LE999
+.Li7:
+	or      $r10, P3H, P3L
+	bnez    $r10, .LEnan
+	subri   $r15, $r9, #0x7ff
+	bnezs8  .LEretA
+	xor     $r10, P1H, P2H
+	sltsi   $r15, $r10, #0
+	bnezs8  .LEnan
+	j       .LEretB
+
+.LEspecB:
+	#ADD(O1L, O1L)
+	move    $r15, O1L
+	add     O1L, O1L, O1L
+	slt     $r15, O1L, $r15
+
+	#ADDC(O1H, O1H)
+	add     O1H, O1H, O1H
+	add     O1H, O1H, $r15
+	bnez    $r9, .Li11
+	or      $r10, O1H, O1L
+	beqz    $r10, .LEretA
+	j       .LElab2
+.Li11:
+	or      $r10, O1H, O1L
+	beqz    $r10, .LEretB
+
+.LEnan:
+	move    P1H, #0xfff80000
+	move    P1L, #0
+	j       .LEretA
+
+.LEund:
+	subri   $r9, $r6, #1
+	move    P2L, #0
+.LL26:
+	move    $r10, #0x20
+	slt     $r15, $r9, $r10
+	bnezs8  .LL27
+	or      P2L, P2L, P3L
+	move    P3L, P3H
+	move    P3H, #0
+	addi    $r9, $r9, #0xffffffe0
+	bnez    P3L, .LL26
+.LL27:
+	beqz    $r9, .LL28
+	move    P1L, P3H
+	move    $r10, P3L
+	srl     P3L, P3L, $r9
+	srl     P3H, P3H, $r9
+	subri   $r9, $r9, #0x20
+	sll     P1L, P1L, $r9
+	or      P3L, P3L, P1L
+	sll     $r10, $r10, $r9
+	or      P2L, P2L, $r10
+	beqz    P2L, .LL28
+	ori     P3L, P3L, #1
+.LL28:
+	move    $r6, #0
+	j       .LElab8
+	.size   __subdf3, .-__subdf3
+	.size   __adddf3, .-__adddf3
+#endif /* L_addsub_df */
+
+
+
+#ifdef L_mul_sf
+
+#if !defined (__big_endian__)
+	#define P1L     $r0
+	#define P1H     $r1
+	#define P2L     $r2
+	#define P2H     $r3
+#else
+	#define P1H     $r0
+	#define P1L     $r1
+	#define P2H     $r2
+	#define P2L     $r3
+#endif
+	.text
+	.align	2
+	.global	__mulsf3
+	.type	__mulsf3, @function
+__mulsf3:
+	push    $lp
+	pushm   $r6, $r10
+
+	srli    $r3, $r0, #23
+	andi    $r3, $r3, #0xff
+	srli    $r5, $r1, #23
+	andi    $r5, $r5, #0xff
+	move    $r6, #0x80000000
+	slli    $r2, $r0, #8
+	or      $r2, $r2, $r6
+	slli    $r4, $r1, #8
+	or      $r4, $r4, $r6
+	xor     $r8, $r0, $r1
+	and     $r6, $r6, $r8
+
+	addi    $r8, $r3, #-1
+	slti    $r15, $r8, #0xfe
+	beqzs8  .LFspecA
+
+.LFlab1:
+	addi    $r8, $r5, #-1
+	slti    $r15, $r8, #0xfe
+	beqzs8  .LFspecB
+
+.LFlab2:
+	move    $r10, $r3
+/* This is a 64-bit multiple. ($r2, $r7) is (high, low). */
+#ifndef __NDS32_ISA_V3M__
+	mulr64	$r2, $r2, $r4
+#else
+	pushm	$r0, $r1
+	pushm	$r4, $r5
+	move	P1L, $r2
+	movi	P1H, #0
+	move	P2L, $r4
+	movi	P2H, #0
+	bal	__muldi3
+	movd44	$r2, $r0
+	popm	$r4, $r5
+	popm	$r0, $r1
+#endif
+#ifndef __big_endian__
+	move    $r7, $r2
+	move    $r2, $r3
+#else
+	move	$r7, $r3
+#endif
+	move    $r3, $r10
+
+	beqz    $r7, .Li17
+	ori     $r2, $r2, #1
+
+.Li17:
+	sltsi   $r15, $r2, #0
+	bnezs8  .Li18
+	slli    $r2, $r2, #1
+	addi    $r3, $r3, #-1
+.Li18:
+	addi    $r8, $r5, #0xffffff82
+	add     $r3, $r3, $r8
+	addi    $r8, $r3, #-1
+	slti    $r15, $r8, #0xfe
+	beqzs8  .LFoveund
+
+.LFlab8:
+	#ADD($r2, $0x80)
+	move    $r15, #0x80
+	add     $r2, $r2, $r15
+	slt     $r15, $r2, $r15
+
+	#ADDC($r3, $0x0)
+	add     $r3, $r3, $r15
+	srli    $r8, $r2, #8
+	andi    $r8, $r8, #1
+	sub     $r2, $r2, $r8
+	slli    $r2, $r2, #1
+	srli    $r2, $r2, #9
+	slli    $r8, $r3, #23
+	or      $r2, $r2, $r8
+	or      $r0, $r2, $r6
+
+.LF999:
+	popm    $r6, $r10
+	pop     $lp
+	ret5    $lp
+
+.LFspecA:
+	bnez    $r3, .Li19
+	add     $r2, $r2, $r2
+	beqz    $r2, .Li20
+#ifdef __NDS32_PERF_EXT__
+	clz	$r7, $r2
+#else
+	pushm	$r0, $r5
+	move	$r0, $r2
+	bal	__clzsi2
+	move	$r7, $r0
+	popm	$r0, $r5
+#endif
+	sub     $r3, $r3, $r7
+	sll     $r2, $r2, $r7
+	j       .LFlab1
+.Li20:
+	subri   $r15, $r5, #0xff
+	beqzs8  .LFnan
+	j       .LFzer
+.Li19:
+	add     $r8, $r2, $r2
+	bnez    $r8, .LFnan
+	bnez    $r5, .Li21
+	add     $r8, $r4, $r4
+	beqz    $r8, .LFnan
+.Li21:
+	subri   $r15, $r5, #0xff
+	bnezs8  .LFinf
+
+.LFspecB:
+	bnez    $r5, .Li22
+	add     $r4, $r4, $r4
+	beqz    $r4, .LFzer
+#ifdef __NDS32_PERF_EXT__
+	clz	$r7, $r4
+#else
+	pushm	$r0, $r5
+	move	$r0, $r4
+	bal	__clzsi2
+	move	$r7, $r0
+	popm	$r0, $r5
+#endif
+	sub     $r5, $r5, $r7
+	sll     $r4, $r4, $r7
+	j       .LFlab2
+
+.LFzer:
+	move    $r0, $r6
+	j       .LF999
+.Li22:
+	add     $r8, $r4, $r4
+	bnez    $r8, .LFnan
+
+.LFinf:
+	move    $r8, #0x7f800000
+	or      $r0, $r6, $r8
+	j       .LF999
+
+.LFnan:
+	move    $r0, #0xffc00000
+	j       .LF999
+
+.LFoveund:
+	bgtz    $r3, .LFinf
+	subri   $r7, $r3, #1
+	slti    $r15, $r7, #0x20
+	beqzs8  .LFzer
+	subri   $r8, $r7, #0x20
+	sll     $r3, $r2, $r8
+	srl     $r2, $r2, $r7
+	beqz    $r3, .Li25
+	ori     $r2, $r2, #2
+.Li25:
+	move    $r3, #0
+	addi    $r8, $r2, #0x80
+	sltsi   $r15, $r8, #0
+	beqzs8  .LFlab8
+	move    $r3, #1
+	j       .LFlab8
+	.size	__mulsf3, .-__mulsf3
+#endif /* L_mul_sf */
+
+
+
+#ifdef L_mul_df
+
+#ifndef __big_endian__
+	#define P1L     $r0
+	#define P1H     $r1
+	#define P2L     $r2
+	#define P2H     $r3
+	#define P3L     $r4
+	#define P3H     $r5
+	#define O1L     $r7
+	#define O1H	$r8
+#else
+	#define P1H     $r0
+	#define P1L     $r1
+	#define P2H     $r2
+	#define P2L     $r3
+	#define P3H     $r4
+	#define P3L     $r5
+	#define O1H     $r7
+	#define O1L	$r8
+#endif
+	.text
+	.align	2
+	.global	__muldf3
+	.type	__muldf3, @function
+__muldf3:
+	push    $lp
+	pushm   $r6, $r10
+
+	slli    $r6, P1H, #1
+	srli    $r6, $r6, #21
+	slli    P3H, P1H, #11
+	srli    $r10, P1L, #21
+	or      P3H, P3H, $r10
+	slli    P3L, P1L, #11
+	move    O1L, #0x80000000
+	or      P3H, P3H, O1L
+	slli    $r9, P2H, #1
+	srli    $r9, $r9, #21
+	slli    O1H, P2H, #11
+	srli    $r10, P2L, #21
+	or      O1H, O1H, $r10
+	or      O1H, O1H, O1L
+	xor     P1H, P1H, P2H
+	and     P1H, P1H, O1L
+	slli    O1L, P2L, #11
+
+	addi    $r10, $r6, #-1
+	slti    $r15, $r10, #0x7fe
+	beqzs8  .LFspecA
+
+.LFlab1:
+	addi    $r10, $r9, #-1
+	slti    $r15, $r10, #0x7fe
+	beqzs8  .LFspecB
+
+.LFlab2:
+	addi    $r10, $r9, #0xfffffc02
+	add     $r6, $r6, $r10
+
+	move    $r10, $r8
+/* This is a 64-bit multiple. */
+#ifndef __big_endian__
+/* For little endian: ($r9, $r3) is (high, low). */
+#ifndef __NDS32_ISA_V3M__
+	mulr64	$r8, $r5, $r8
+#else
+	pushm	$r0, $r5
+	move	$r0, $r5
+	movi	$r1, #0
+	move	$r2, $r8
+	movi	$r3, #0
+	bal	__muldi3
+	movd44	$r8, $r0
+	popm	$r0, $r5
+#endif
+	move    $r3, $r8
+#else /* __big_endian__ */
+/* For big endain: ($r9, $r2) is (high, low). */
+#ifndef __NDS32_ISA_V3M__
+	mulr64	$r8, $r4, $r7
+#else
+	pushm	$r0, $r5
+	move	$r1, $r4
+	movi	$r0, #0
+	move	$r3, $r7
+	movi	$r2, #0
+	bal	__muldi3
+	movd44	$r8, $r0
+	popm	$r0, $r5
+#endif
+	move    $r2, $r9
+	move    $r9, $r8
+#endif /* __big_endian__ */
+	move    $r8, $r10
+
+	move    $r10, P1H
+/* This is a 64-bit multiple. */
+#ifndef __big_endian__
+/* For little endian: ($r0, $r2) is (high, low). */
+#ifndef __NDS32_ISA_V3M__
+	mulr64	$r0, $r4, $r8
+#else
+	pushm	$r2, $r5
+	move	$r0, $r4
+	movi	$r1, #0
+	move	$r2, $r8
+	movi	$r3, #0
+	bal	__muldi3
+	popm	$r2, $r5
+#endif
+	move    $r2, $r0
+	move    $r0, $r1
+#else /* __big_endian__ */
+/* For big endain: ($r1, $r3) is (high, low). */
+#ifndef __NDS32_ISA_V3M__
+	mulr64	$r0, $r5, $r7
+#else
+	pushm	$r2, $r5
+	move	$r1, $r5
+	movi	$r0, #0
+	move	$r3, $r7
+	movi	$r2, #0
+	bal	__muldi3
+	popm	$r2, $r5
+#endif
+	move    $r3, $r1
+	move    $r1, $r0
+#endif /* __big_endian__ */
+	move    P1H, $r10
+
+	#ADD(P2H, P1L)
+	add     P2H, P2H, P1L
+	slt     $r15, P2H, P1L
+
+	#ADDC($r9, $0x0)
+	add     $r9, $r9, $r15
+
+	move    $r10, P1H
+/* This is a 64-bit multiple. */
+#ifndef __big_endian__
+/* For little endian: ($r0, $r8) is (high, low). */
+#ifndef __NDS32_ISA_V3M__
+	mulr64	$r0, $r5, $r7
+#else
+	pushm	$r2, $r5
+	move	$r0, $r5
+	movi	$r1, #0
+	move	$r2, $r7
+	movi	$r3, #0
+	bal	__muldi3
+	popm	$r2, $r5
+#endif
+	move    $r8, $r0
+	move    $r0, $r1
+#else /* __big_endian__ */
+/* For big endian: ($r1, $r7) is (high, low). */
+#ifndef __NDS32_ISA_V3M__
+	mulr64	$r0, $r4, $r8
+#else
+	pushm	$r2, $r5
+	move	$r1, $r4
+	movi	$r0, #0
+	move	$r3, $r8
+	movi	$r2, #0
+	bal	__muldi3
+	popm	$r2, $r5
+#endif
+	move	$r7, $r1
+	move	$r1, $r0
+#endif /* __big_endian__ */
+	move    P1H, $r10
+
+	#ADD(P2L, O1H)
+	add     P2L, P2L, O1H
+	slt     $r15, P2L, O1H
+
+
+	#ADDCC(P2H, P1L)
+	beqzs8  .LL29
+	add     P2H, P2H, P1L
+	slt     $r15, P2H, P1L
+	beqzs8  .LL30
+	addi    P2H, P2H, #0x1
+	j       .LL31
+.LL30:
+	move    $r15, #1
+	add     P2H, P2H, $r15
+	slt     $r15, P2H, $r15
+	j       .LL31
+.LL29:
+	add     P2H, P2H, P1L
+	slt     $r15, P2H, P1L
+.LL31:
+
+	#ADDC($r9, $0x0)
+	add     $r9, $r9, $r15
+
+/* This is a 64-bit multiple. */
+#ifndef __big_endian__
+/* For little endian: ($r8, $r0) is (high, low). */
+	move    $r10, $r9
+#ifndef __NDS32_ISA_V3M__
+	mulr64	$r8, $r4, $r7
+#else
+	pushm	$r0, $r5
+	move	$r0, $r4
+	movi	$r1, #0
+	move	$r2, $r7
+	movi	$r3, #0
+	bal	__muldi3
+	movd44	$r8, $r0
+	popm	$r0, $r5
+#endif
+	move    $r0, $r8
+	move    $r8, $r9
+	move    $r9, $r10
+#else /* __big_endian__ */
+/* For big endian: ($r7, $r1) is (high, low). */
+	move	$r10, $r6
+#ifndef __NDS32_ISA_V3M__
+	mulr64	$r6, $r5, $r8
+#else
+	pushm	$r0, $r5
+	move	$r1, $r5
+	movi	$r0, #0
+	move	$r3, $r8
+	movi	$r2, #0
+	bal	__muldi3
+	movd44	$r6, $r0
+	popm	$r0, $r5
+#endif
+	move	$r1, $r7
+	move	$r7, $r6
+	move	$r6, $r10
+#endif /* __big_endian__ */
+
+	#ADD(P2L, O1H)
+	add     P2L, P2L, O1H
+	slt     $r15, P2L, O1H
+
+
+	#ADDCC(P2H, $0x0)
+	beqzs8  .LL34
+	add     P2H, P2H, $r15
+	slt     $r15, P2H, $r15
+.LL34:
+
+	#ADDC($r9, $0x0)
+	add     $r9, $r9, $r15
+	or      $r10, P1L, P2L
+	beqz    $r10, .Li13
+	ori     P2H, P2H, #1
+.Li13:
+	move    P3H, $r9
+	move    P3L, P2H
+	sltsi   $r15, P3H, #0
+	bnezs8  .Li14
+
+	move    $r15, P3L
+	add     P3L, P3L, P3L
+	slt     $r15, P3L, $r15
+	add     P3H, P3H, P3H
+	add     P3H, P3H, $r15
+	addi    $r6, $r6, #-1
+.Li14:
+	addi    $r10, $r6, #-1
+	slti    $r15, $r10, #0x7fe
+	beqzs8  .LFoveund
+
+	#ADD(P3L, $0x400)
+	move    $r15, #0x400
+	add     P3L, P3L, $r15
+	slt     $r15, P3L, $r15
+
+
+	#ADDCC(P3H, $0x0)
+	beqzs8  .LL37
+	add     P3H, P3H, $r15
+	slt     $r15, P3H, $r15
+.LL37:
+
+	#ADDC($r6, $0x0)
+	add     $r6, $r6, $r15
+
+.LFlab8:
+	srli    $r10, P3L, #11
+	andi    $r10, $r10, #1
+	sub     P3L, P3L, $r10
+	srli    P1L, P3L, #11
+	slli    $r10, P3H, #21
+	or      P1L, P1L, $r10
+	slli    $r10, P3H, #1
+	srli    $r10, $r10, #12
+	or      P1H, P1H, $r10
+	slli    $r10, $r6, #20
+	or      P1H, P1H, $r10
+
+.LFret:
+.LF999:
+	popm    $r6, $r10
+	pop     $lp
+	ret5    $lp
+
+.LFspecA:
+	#ADD(P3L, P3L)
+	move    $r15, P3L
+	add     P3L, P3L, P3L
+	slt     $r15, P3L, $r15
+
+	#ADDC(P3H, P3H)
+	add     P3H, P3H, P3H
+	add     P3H, P3H, $r15
+	bnez    $r6, .Li15
+	or      $r10, P3H, P3L
+	beqz    $r10, .Li16
+
+
+	#NORMd($r4, P1L, P2H)
+	bnez    P3H, .LL38
+	bnez    P3L, .LL39
+	move    $r6, #0
+	j       .LL40
+.LL39:
+	move    P3H, P3L
+	move    P3L, #0
+	move    P1L, #32
+	sub     $r6, $r6, P1L
+.LL38:
+#ifndef __big_endian__
+#ifdef __NDS32_PERF_EXT__
+	clz	$r0, P3H
+#else
+	pushm	$r1, P3H
+	move	$r0, P3H
+	bal	__clzsi2
+	popm	$r1, $r5
+#endif
+#else /* __big_endian__ */
+#ifdef __NDS32_PERF_EXT__
+	clz	$r1, $r4
+#else
+	push	$r0
+	pushm	$r2, $r5
+	move	$r0, $r4
+	bal	__clzsi2
+	move	$r1, $r0
+	popm	$r2, $r5
+	pop	$r0
+#endif
+#endif /* __big_endian__ */
+	beqz    P1L, .LL40
+	sub     $r6, $r6, P1L
+	subri   P2H, P1L, #32
+	srl     P2H, P3L, P2H
+	sll     P3L, P3L, P1L
+	sll     P3H, P3H, P1L
+	or      P3H, P3H, P2H
+.LL40:
+	#NORMd End
+
+	j       .LFlab1
+.Li16:
+	subri   $r15, $r9, #0x7ff
+	beqzs8  .LFnan
+	j       .LFret
+.Li15:
+	or      $r10, P3H, P3L
+	bnez    $r10, .LFnan
+	bnez    $r9, .Li17
+	slli    $r10, O1H, #1
+	or      $r10, $r10, O1L
+	beqz    $r10, .LFnan
+.Li17:
+	subri   $r15, $r9, #0x7ff
+	bnezs8  .LFinf
+
+.LFspecB:
+	#ADD(O1L, O1L)
+	move    $r15, O1L
+	add     O1L, O1L, O1L
+	slt     $r15, O1L, $r15
+
+	#ADDC(O1H, O1H)
+	add     O1H, O1H, O1H
+	add     O1H, O1H, $r15
+	bnez    $r9, .Li18
+	or      $r10, O1H, O1L
+	beqz    $r10, .Li19
+
+
+	#NORMd($r7, P2L, P1L)
+	bnez    O1H, .LL41
+	bnez    O1L, .LL42
+	move    $r9, #0
+	j       .LL43
+.LL42:
+	move    O1H, O1L
+	move    O1L, #0
+	move    P2L, #32
+	sub     $r9, $r9, P2L
+.LL41:
+#ifndef __big_endian__
+#ifdef __NDS32_PERF_EXT__
+	clz	$r2, $r8
+#else
+	pushm	$r0, $r1
+	pushm	$r3, $r5
+	move	$r0, $r8
+	bal	__clzsi2
+	move	$r2, $r0
+	popm	$r3, $r5
+	popm	$r0, $r1
+#endif
+#else /* __big_endian__ */
+#ifdef __NDS32_PERF_EXT__
+	clz	$r3, $r7
+#else
+	pushm	$r0, $r2
+	pushm	$r4, $r5
+	move	$r0, $r7
+	bal	__clzsi2
+	move	$r3, $r0
+	popm	$r4, $r5
+	popm	$r0, $r2
+#endif
+#endif /* __big_endian__ */
+	beqz    P2L, .LL43
+	sub     $r9, $r9, P2L
+	subri   P1L, P2L, #32
+	srl     P1L, O1L, P1L
+	sll     O1L, O1L, P2L
+	sll     O1H, O1H, P2L
+	or      O1H, O1H, P1L
+.LL43:
+	#NORMd End
+
+	j       .LFlab2
+.Li19:
+	move    P1L, #0
+	j       .LFret
+.Li18:
+	or      $r10, O1H, O1L
+	bnez    $r10, .LFnan
+
+.LFinf:
+	move    $r10, #0x7ff00000
+	or      P1H, P1H, $r10
+	move    P1L, #0
+	j       .LFret
+
+.LFnan:
+	move    P1H, #0xfff80000
+	move    P1L, #0
+	j       .LFret
+
+.LFoveund:
+	bgtz    $r6, .LFinf
+	subri   P1L, $r6, #1
+	move    P2L, #0
+.LL44:
+	move    $r10, #0x20
+	slt     $r15, P1L, $r10
+	bnezs8  .LL45
+	or      P2L, P2L, P3L
+	move    P3L, P3H
+	move    P3H, #0
+	addi    P1L, P1L, #0xffffffe0
+	bnez    P3L, .LL44
+.LL45:
+	beqz    P1L, .LL46
+	move    P2H, P3H
+	move    $r10, P3L
+	srl     P3L, P3L, P1L
+	srl     P3H, P3H, P1L
+	subri   P1L, P1L, #0x20
+	sll     P2H, P2H, P1L
+	or      P3L, P3L, P2H
+	sll     $r10, $r10, P1L
+	or      P2L, P2L, $r10
+	beqz    P2L, .LL46
+	ori     P3L, P3L, #1
+.LL46:
+	#ADD(P3L, $0x400)
+	move    $r15, #0x400
+	add     P3L, P3L, $r15
+	slt     $r15, P3L, $r15
+
+	#ADDC(P3H, $0x0)
+	add     P3H, P3H, $r15
+	srli    $r6, P3H, #31
+	j       .LFlab8
+	.size __muldf3, .-__muldf3
+#endif /* L_mul_df */
+
+
+
+#ifdef L_div_sf
+
+	.text
+	.align	2
+	.global	__divsf3
+	.type	__divsf3, @function
+__divsf3:
+	push    $lp
+	pushm   $r6, $r10
+
+	move    $r7, #0x80000000
+	srli    $r4, $r0, #23
+	andi    $r4, $r4, #0xff
+	srli    $r6, $r1, #23
+	andi    $r6, $r6, #0xff
+	slli    $r3, $r0, #8
+	or      $r3, $r3, $r7
+	slli    $r5, $r1, #8
+	or      $r5, $r5, $r7
+	xor     $r10, $r0, $r1
+	and     $r7, $r7, $r10
+
+	addi    $r10, $r4, #-1
+	slti    $r15, $r10, #0xfe
+	beqzs8  .LGspecA
+
+.LGlab1:
+	addi    $r10, $r6, #-1
+	slti    $r15, $r10, #0xfe
+	beqzs8  .LGspecB
+
+.LGlab2:
+	slt     $r15, $r3, $r5
+	bnezs8  .Li27
+	srli    $r3, $r3, #1
+	addi    $r4, $r4, #1
+.Li27:
+	srli    $r8, $r5, #14
+	divr    $r0, $r2, $r3, $r8
+	andi    $r9, $r5, #0x3fff
+	mul     $r1, $r9, $r0
+	slli    $r2, $r2, #14
+
+	#SUB($r2, $r1)
+	move    $r15, $r2
+	sub     $r2, $r2, $r1
+	slt     $r15, $r15, $r2
+	beqzs8  .Li28
+	addi    $r0, $r0, #-1
+
+	#ADD($r2, $r5)
+	add     $r2, $r2, $r5
+	slt     $r15, $r2, $r5
+.Li28:
+	divr    $r3, $r2, $r2, $r8
+	mul     $r1, $r9, $r3
+	slli    $r2, $r2, #14
+
+	#SUB($r2, $r1)
+	move    $r15, $r2
+	sub     $r2, $r2, $r1
+	slt     $r15, $r15, $r2
+	beqzs8  .Li29
+	addi    $r3, $r3, #-1
+
+	#ADD($r2, $r5)
+	add     $r2, $r2, $r5
+	slt     $r15, $r2, $r5
+.Li29:
+	slli    $r10, $r0, #14
+	add     $r3, $r3, $r10
+	slli    $r3, $r3, #4
+	beqz    $r2, .Li30
+	ori     $r3, $r3, #1
+.Li30:
+	subri   $r10, $r6, #0x7e
+	add     $r4, $r4, $r10
+	addi    $r10, $r4, #-1
+	slti    $r15, $r10, #0xfe
+	beqzs8  .LGoveund
+
+.LGlab8:
+	#ADD($r3, $0x80)
+	move    $r15, #0x80
+	add     $r3, $r3, $r15
+	slt     $r15, $r3, $r15
+
+	#ADDC($r4, $0x0)
+	add     $r4, $r4, $r15
+	srli    $r10, $r3, #8
+	andi    $r10, $r10, #1
+	sub     $r3, $r3, $r10
+	slli    $r3, $r3, #1
+	srli    $r3, $r3, #9
+	slli    $r10, $r4, #23
+	or      $r3, $r3, $r10
+	or      $r0, $r3, $r7
+
+.LG999:
+	popm    $r6, $r10
+	pop     $lp
+	ret5    $lp
+
+.LGspecA:
+	bnez    $r4, .Li31
+	add     $r3, $r3, $r3
+	beqz    $r3, .Li31
+#ifdef __NDS32_PERF_EXT__
+	clz	$r8, $r3
+#else
+	pushm	$r0, $r5
+	move	$r0, $r3
+	bal	__clzsi2
+	move	$r8, $r0
+	popm	$r0, $r5
+#endif
+	sub     $r4, $r4, $r8
+	sll     $r3, $r3, $r8
+	j       .LGlab1
+.Li31:
+	bne     $r6, $r4, .Li33
+	add     $r10, $r5, $r5
+	beqz    $r10, .LGnan
+.Li33:
+	subri   $r15, $r6, #0xff
+	beqzs8  .LGspecB
+	beqz    $r4, .LGzer
+	add     $r10, $r3, $r3
+	bnez    $r10, .LGnan
+	j       .LGinf
+
+.LGspecB:
+	bnez    $r6, .Li34
+	add     $r5, $r5, $r5
+	beqz    $r5, .LGinf
+#ifdef __NDS32_PERF_EXT__
+	clz	$r8, $r5
+#else
+	pushm	$r0, $r5
+	move	$r0, $r5
+	bal	__clzsi2
+	move	$r8, $r0
+	popm	$r0, $r5
+#endif
+	sub     $r6, $r6, $r8
+	sll     $r5, $r5, $r8
+	j       .LGlab2
+.Li34:
+	add     $r10, $r5, $r5
+	bnez    $r10, .LGnan
+
+.LGzer:
+	move    $r0, $r7
+	j       .LG999
+
+.LGoveund:
+	bgtz    $r4, .LGinf
+	subri   $r8, $r4, #1
+	slti    $r15, $r8, #0x20
+	beqzs8  .LGzer
+	subri   $r10, $r8, #0x20
+	sll     $r4, $r3, $r10
+	srl     $r3, $r3, $r8
+	beqz    $r4, .Li37
+	ori     $r3, $r3, #2
+.Li37:
+	move    $r4, #0
+	addi    $r10, $r3, #0x80
+	sltsi   $r15, $r10, #0
+	beqzs8  .LGlab8
+	move    $r4, #1
+	j       .LGlab8
+
+.LGinf:
+	move    $r10, #0x7f800000
+	or      $r0, $r7, $r10
+	j       .LG999
+
+.LGnan:
+	move    $r0, #0xffc00000
+	j       .LG999
+	.size	__divsf3, .-__divsf3
+#endif /* L_div_sf */
+
+
+
+#ifdef L_div_df
+
+#ifndef __big_endian__
+	#define P1L     $r0
+	#define P1H     $r1
+	#define P2L     $r2
+	#define P2H     $r3
+	#define P3L     $r4
+	#define P3H     $r5
+	#define O1L     $r7
+	#define O1H	$r8
+#else
+	#define P1H     $r0
+	#define P1L     $r1
+	#define P2H     $r2
+	#define P2L     $r3
+	#define P3H     $r4
+	#define P3L     $r5
+	#define O1H     $r7
+	#define O1L	$r8
+#endif
+	.text
+	.align	2
+	.global	__divdf3
+	.type	__divdf3, @function
+__divdf3:
+	push    $lp
+	pushm   $r6, $r10
+
+	slli    $r6, P1H, #1
+	srli    $r6, $r6, #21
+	slli    P3H, P1H, #11
+	srli    $r10, P1L, #21
+	or      P3H, P3H, $r10
+	slli    P3L, P1L, #11
+	move    O1L, #0x80000000
+	or      P3H, P3H, O1L
+	slli    $r9, P2H, #1
+	srli    $r9, $r9, #21
+	slli    O1H, P2H, #11
+	srli    $r10, P2L, #21
+	or      O1H, O1H, $r10
+	or      O1H, O1H, O1L
+	xor     P1H, P1H, P2H
+	and     P1H, P1H, O1L
+	slli    O1L, P2L, #11
+
+	addi    $r10, $r6, #-1
+	slti    $r15, $r10, #0x7fe
+	beqzs8  .LGspecA
+
+.LGlab1:
+	addi    $r10, $r9, #-1
+	slti    $r15, $r10, #0x7fe
+	beqzs8  .LGspecB
+
+.LGlab2:
+	sub     $r6, $r6, $r9
+	addi    $r6, $r6, #0x3ff
+	srli    P3L, P3L, #1
+	slli    $r10, P3H, #31
+	or      P3L, P3L, $r10
+	srli    P3H, P3H, #1
+	srli    $r9, O1H, #16
+	divr    P2H, P3H, P3H, $r9
+	move    $r10, #0xffff
+	and     P2L, O1H, $r10
+	mul     P1L, P2L, P2H
+	slli    P3H, P3H, #16
+	srli    $r10, P3L, #16
+	or      P3H, P3H, $r10
+
+	#SUB(P3H, P1L)
+	move    $r15, P3H
+	sub     P3H, P3H, P1L
+	slt     $r15, $r15, P3H
+	beqzs8  .Li20
+
+.Lb21:
+	addi    P2H, P2H, #-1
+	add     P3H, P3H, O1H
+	slt     $r15, P3H, O1H
+	beqzs8  .Lb21
+.Li20:
+	divr    $r9, P3H, P3H, $r9
+	mul     P1L, P2L, $r9
+	slli    P3H, P3H, #16
+	move    $r15, #0xffff
+	and     $r10, P3L, $r15
+	or      P3H, P3H, $r10
+
+	#SUB(P3H, P1L)
+	move    $r15, P3H
+	sub     P3H, P3H, P1L
+	slt     $r15, $r15, P3H
+	beqzs8  .Li22
+
+.Lb23:
+	addi    $r9, $r9, #-1
+	add     P3H, P3H, O1H
+	slt     $r15, P3H, O1H
+	beqzs8  .Lb23
+.Li22:
+	slli    P2H, P2H, #16
+	add     P2H, P2H, $r9
+
+/* This is a 64-bit multiple. */
+#ifndef __big_endian__
+/* For little endian: ($r0, $r9) is (high, low). */
+	move    $r10, $r1
+#ifndef __NDS32_ISA_V3M__
+	mulr64	$r0, $r3, $r7
+#else
+	pushm	$r2, $r5
+	move	$r0, $r3
+	movi	$r1, #0
+	move	$r2, $r7
+	movi	$r3, #0
+	bal	__muldi3
+	popm	$r2, $r5
+#endif
+	move    $r9, $r0
+	move    $r0, $r1
+	move    $r1, $r10
+#else /* __big_endian__ */
+/* For big endian: ($r1, $r9) is (high, low). */
+	move    $r10, $r0
+#ifndef __NDS32_ISA_V3M__
+	mulr64	$r0, $r2, $r8
+#else
+	pushm	$r2, $r5
+	move	$r1, $r2
+	movi	$r0, #0
+	move	$r3, $r8
+	movi	$r2, #0
+	bal	__muldi3
+	popm	$r2, $r5
+#endif
+	move    $r9, $r1
+	move    $r1, $r0
+	move    $r0, $r10
+#endif /* __big_endian__ */
+
+	move    P3L, #0
+
+	#SUB(P3L, $r9)
+	move    $r15, P3L
+	sub     P3L, P3L, $r9
+	slt     $r15, $r15, P3L
+
+
+	#SUBCC(P3H, P1L)
+	beqzs8  .LL47
+	move    $r15, P3H
+	sub     P3H, P3H, P1L
+	slt     $r15, $r15, P3H
+	beqzs8  .LL48
+	subi333 P3H, P3H, #1
+	j       .LL49
+.LL48:
+	move    $r15, P3H
+	subi333 P3H, P3H, #1
+	slt     $r15, $r15, P3H
+	j       .LL49
+.LL47:
+	move    $r15, P3H
+	sub     P3H, P3H, P1L
+	slt     $r15, $r15, P3H
+.LL49:
+
+	beqzs8  .Li24
+
+.LGlab3:
+	addi    P2H, P2H, #-1
+
+	#ADD(P3L, O1L)
+	add     P3L, P3L, O1L
+	slt     $r15, P3L, O1L
+
+
+	#ADDCC(P3H, O1H)
+	beqzs8  .LL50
+	add     P3H, P3H, O1H
+	slt     $r15, P3H, O1H
+	beqzs8  .LL51
+	addi    P3H, P3H, #0x1
+	j       .LL52
+.LL51:
+	move    $r15, #1
+	add     P3H, P3H, $r15
+	slt     $r15, P3H, $r15
+	j       .LL52
+.LL50:
+	add     P3H, P3H, O1H
+	slt     $r15, P3H, O1H
+.LL52:
+
+	beqzs8  .LGlab3
+.Li24:
+	bne     P3H, O1H, .Li25
+	move    P1L, O1L
+	move    P3H, P3L
+	move    $r9, #0
+	move    P2L, $r9
+	j       .Le25
+.Li25:
+	srli    P2L, O1H, #16
+	divr    $r9, P3H, P3H, P2L
+	move    $r10, #0xffff
+	and     $r10, O1H, $r10
+	mul     P1L, $r10, $r9
+	slli    P3H, P3H, #16
+	srli    $r15, P3L, #16
+	or      P3H, P3H, $r15
+
+	#SUB(P3H, P1L)
+	move    $r15, P3H
+	sub     P3H, P3H, P1L
+	slt     $r15, $r15, P3H
+	beqzs8  .Li26
+
+.Lb27:
+	addi    $r9, $r9, #-1
+	add     P3H, P3H, O1H
+	slt     $r15, P3H, O1H
+	beqzs8  .Lb27
+.Li26:
+	divr    P2L, P3H, P3H, P2L
+	mul     P1L, $r10, P2L
+	slli    P3H, P3H, #16
+	move    $r10, #0xffff
+	and     $r10, P3L, $r10
+	or      P3H, P3H, $r10
+
+	#SUB(P3H, P1L)
+	move    $r15, P3H
+	sub     P3H, P3H, P1L
+	slt     $r15, $r15, P3H
+	beqzs8  .Li28
+
+.Lb29:
+	addi    P2L, P2L, #-1
+	add     P3H, P3H, O1H
+	slt     $r15, P3H, O1H
+	beqzs8  .Lb29
+.Li28:
+	slli    $r9, $r9, #16
+	add     $r9, $r9, P2L
+
+/* This is a 64-bit multiple. */
+#ifndef __big_endian__
+/* For little endian: ($r0, $r2) is (high, low). */
+	move    $r10, $r1
+#ifndef __NDS32_ISA_V3M__
+	mulr64	$r0, $r9, $r7
+#else
+	pushm	$r2, $r5
+	move	$r0, $r9
+	movi	$r1, #0
+	move	$r2, $r7
+	movi	$r3, #0
+	bal	__muldi3
+	popm	$r2, $r5
+#endif
+	move    $r2, $r0
+	move    $r0, $r1
+	move    $r1, $r10
+#else /* __big_endian__ */
+/* For big endian: ($r1, $r3) is (high, low). */
+	move	$r10, $r0
+#ifndef __NDS32_ISA_V3M__
+	mulr64	$r0, $r9, $r8
+#else
+	pushm	$r2, $r5
+	move	$r0, $r9
+	movi	$r1, #0
+	move	$r2, $r7
+	movi	$r3, #0
+	bal	__muldi3
+	popm	$r2, $r5
+#endif
+	move	$r3, $r1
+	move	$r1, $r0
+	move	$r0, $r10
+#endif /* __big_endian__ */
+
+.Le25:
+	move    P3L, #0
+
+	#SUB(P3L, P2L)
+	move    $r15, P3L
+	sub     P3L, P3L, P2L
+	slt     $r15, $r15, P3L
+
+
+	#SUBCC(P3H, P1L)
+	beqzs8  .LL53
+	move    $r15, P3H
+	sub     P3H, P3H, P1L
+	slt     $r15, $r15, P3H
+	beqzs8  .LL54
+	subi333 P3H, P3H, #1
+	j       .LL55
+.LL54:
+	move    $r15, P3H
+	subi333 P3H, P3H, #1
+	slt     $r15, $r15, P3H
+	j       .LL55
+.LL53:
+	move    $r15, P3H
+	sub     P3H, P3H, P1L
+	slt     $r15, $r15, P3H
+.LL55:
+
+	beqzs8  .Li30
+
+.LGlab4:
+	addi    $r9, $r9, #-1
+
+	#ADD(P3L, O1L)
+	add     P3L, P3L, O1L
+	slt     $r15, P3L, O1L
+
+
+	#ADDCC(P3H, O1H)
+	beqzs8  .LL56
+	add     P3H, P3H, O1H
+	slt     $r15, P3H, O1H
+	beqzs8  .LL57
+	addi    P3H, P3H, #0x1
+	j       .LL58
+.LL57:
+	move    $r15, #1
+	add     P3H, P3H, $r15
+	slt     $r15, P3H, $r15
+	j       .LL58
+.LL56:
+	add     P3H, P3H, O1H
+	slt     $r15, P3H, O1H
+.LL58:
+
+	beqzs8  .LGlab4
+.Li30:
+	sltsi   $r15, P2H, #0
+	bnezs8  .Li31
+
+	#ADD($r9, $r9)
+	move    $r15, $r9
+	add     $r9, $r9, $r9
+	slt     $r15, $r9, $r15
+
+	#ADDC(P2H, P2H)
+	add     P2H, P2H, P2H
+	add     P2H, P2H, $r15
+	addi    $r6, $r6, #-1
+.Li31:
+	or      $r10, P3H, P3L
+	beqz    $r10, .Li32
+	ori     $r9, $r9, #1
+.Li32:
+	move    P3H, P2H
+	move    P3L, $r9
+	addi    $r10, $r6, #-1
+	slti    $r15, $r10, #0x7fe
+	beqzs8  .LGoveund
+
+	#ADD(P3L, $0x400)
+	move    $r15, #0x400
+	add     P3L, P3L, $r15
+	slt     $r15, P3L, $r15
+
+
+	#ADDCC(P3H, $0x0)
+	beqzs8  .LL61
+	add     P3H, P3H, $r15
+	slt     $r15, P3H, $r15
+.LL61:
+
+	#ADDC($r6, $0x0)
+	add     $r6, $r6, $r15
+
+.LGlab8:
+	srli    $r10, P3L, #11
+	andi    $r10, $r10, #1
+	sub     P3L, P3L, $r10
+	srli    P1L, P3L, #11
+	slli    $r10, P3H, #21
+	or      P1L, P1L, $r10
+	slli    $r10, P3H, #1
+	srli    $r10, $r10, #12
+	or      P1H, P1H, $r10
+	slli    $r10, $r6, #20
+	or      P1H, P1H, $r10
+
+.LGret:
+.LG999:
+	popm    $r6, $r10
+	pop     $lp
+	ret5    $lp
+
+.LGoveund:
+	bgtz    $r6, .LGinf
+	subri   P2H, $r6, #1
+	move    P1L, #0
+.LL62:
+	move    $r10, #0x20
+	slt     $r15, P2H, $r10
+	bnezs8  .LL63
+	or      P1L, P1L, P3L
+	move    P3L, P3H
+	move    P3H, #0
+	addi    P2H, P2H, #0xffffffe0
+	bnez    P3L, .LL62
+.LL63:
+	beqz    P2H, .LL64
+	move    P2L, P3H
+	move    $r10, P3L
+	srl     P3L, P3L, P2H
+	srl     P3H, P3H, P2H
+	subri   P2H, P2H, #0x20
+	sll     P2L, P2L, P2H
+	or      P3L, P3L, P2L
+	sll     $r10, $r10, P2H
+	or      P1L, P1L, $r10
+	beqz    P1L, .LL64
+	ori     P3L, P3L, #1
+.LL64:
+	#ADD(P3L, $0x400)
+	move    $r15, #0x400
+	add     P3L, P3L, $r15
+	slt     $r15, P3L, $r15
+
+	#ADDC(P3H, $0x0)
+	add     P3H, P3H, $r15
+	srli    $r6, P3H, #31
+	j       .LGlab8
+
+.LGspecA:
+	#ADD(P3L, P3L)
+	move    $r15, P3L
+	add     P3L, P3L, P3L
+	slt     $r15, P3L, $r15
+
+	#ADDC(P3H, P3H)
+	add     P3H, P3H, P3H
+	add     P3H, P3H, $r15
+	bnez    $r6, .Li33
+	or      $r10, P3H, P3L
+	beqz    $r10, .Li33
+
+
+	#NORMd($r4, P2H, P2L)
+	bnez    P3H, .LL65
+	bnez    P3L, .LL66
+	move    $r6, #0
+	j       .LL67
+.LL66:
+	move    P3H, P3L
+	move    P3L, #0
+	move    P2H, #32
+	sub     $r6, $r6, P2H
+.LL65:
+#ifndef __big_endian__
+#ifdef __NDS32_PERF_EXT__
+	clz	$r3, $r5
+#else
+	pushm	$r0, $r2
+	pushm	$r4, $r5
+	move	$r0, $r5
+	bal	__clzsi2
+	move	$r3, $r0
+	popm	$r4, $r5
+	popm	$r0, $r2
+#endif
+#else /* __big_endian__ */
+#ifdef __NDS32_PERF_EXT__
+	clz	$r2, $r4
+#else
+	pushm	$r0, $r1
+	pushm	$r3, $r5
+	move	$r0, $r4
+	bal	__clzsi2
+	move	$r2, $r0
+	popm	$r3, $r5
+	popm	$r0, $r1
+#endif
+#endif /* __big_endian_ */
+	beqz    P2H, .LL67
+	sub     $r6, $r6, P2H
+	subri   P2L, P2H, #32
+	srl     P2L, P3L, P2L
+	sll     P3L, P3L, P2H
+	sll     P3H, P3H, P2H
+	or      P3H, P3H, P2L
+.LL67:
+	#NORMd End
+
+	j       .LGlab1
+.Li33:
+	bne     $r6, $r9, .Li35
+	slli    $r10, O1H, #1
+	or      $r10, $r10, O1L
+	beqz    $r10, .LGnan
+.Li35:
+	subri   $r15, $r9, #0x7ff
+	beqzs8  .LGspecB
+	beqz    $r6, .LGret
+	or      $r10, P3H, P3L
+	bnez    $r10, .LGnan
+
+.LGinf:
+	move    $r10, #0x7ff00000
+	or      P1H, P1H, $r10
+	move    P1L, #0
+	j       .LGret
+
+.LGspecB:
+	#ADD(O1L, O1L)
+	move    $r15, O1L
+	add     O1L, O1L, O1L
+	slt     $r15, O1L, $r15
+
+	#ADDC(O1H, O1H)
+	add     O1H, O1H, O1H
+	add     O1H, O1H, $r15
+	bnez    $r9, .Li36
+	or      $r10, O1H, O1L
+	beqz    $r10, .LGinf
+
+
+	#NORMd($r7, P2H, P2L)
+	bnez    O1H, .LL68
+	bnez    O1L, .LL69
+	move    $r9, #0
+	j       .LL70
+.LL69:
+	move    O1H, O1L
+	move    O1L, #0
+	move    P2H, #32
+	sub     $r9, $r9, P2H
+.LL68:
+#ifndef __big_endian__
+#ifdef __NDS32_PERF_EXT__
+	clz	$r3, $r8
+#else
+	pushm	$r0, $r2
+	pushm	$r4, $r5
+	move	$r0, $r8
+	bal	__clzsi2
+	move	$r3, $r0
+	popm	$r4, $r5
+	popm	$r0, $r2
+#endif
+#else /* __big_endian__ */
+#ifdef __NDS32_PERF_EXT__
+	clz	$r2, $r7
+#else
+	pushm	$r0, $r1
+	pushm	$r3, $r5
+	move	$r0, $r7
+	bal	__clzsi2
+	move	$r2, $r0
+	popm	$r3, $r5
+	popm	$r0, $r1
+#endif
+#endif /* __big_endian__ */
+	beqz    P2H, .LL70
+	sub     $r9, $r9, P2H
+	subri   P2L, P2H, #32
+	srl     P2L, O1L, P2L
+	sll     O1L, O1L, P2H
+	sll     O1H, O1H, P2H
+	or      O1H, O1H, P2L
+.LL70:
+	#NORMd End
+
+	j       .LGlab2
+.Li36:
+	or      $r10, O1H, O1L
+	beqz    $r10, .Li38
+
+.LGnan:
+	move    P1H, #0xfff80000
+.Li38:
+	move    P1L, #0
+	j       .LGret
+	.size __divdf3, .-__divdf3
+#endif /* L_div_df */
+
+
+
+#ifdef L_negate_sf
+
+	.text
+	.align	2
+	.global	__negsf2
+	.type	__negsf2, @function
+__negsf2:
+	push    $lp
+
+	move    $r1, #0x80000000
+	xor     $r0, $r0, $r1
+
+.LN999:
+	pop     $lp
+	ret5    $lp
+	.size __negsf2, .-__negsf2
+#endif /* L_negate_sf */
+
+
+
+#ifdef L_negate_df
+
+#ifndef __big_endian__
+	#define P1H     $r1
+#else
+	#define P1H     $r0
+#endif
+	.text
+	.align	2
+	.global	__negdf2
+	.type	__negdf2, @function
+__negdf2:
+	push    $lp
+
+	move    $r2, #0x80000000
+	xor     P1H, P1H, $r2
+
+.LP999:
+	pop     $lp
+	ret5    $lp
+	.size __negdf2, .-__negdf2
+#endif /* L_negate_df */
+
+
+
+#ifdef L_sf_to_df
+
+#ifndef __big_endian__
+	#define O1L     $r1
+	#define O1H     $r2
+#else
+	#define O1H     $r1
+	#define O1L     $r2
+#endif
+	.text
+	.align	2
+	.global	__extendsfdf2
+	.type	__extendsfdf2, @function
+__extendsfdf2:
+	push    $lp
+
+	srli    $r3, $r0, #23
+	andi    $r3, $r3, #0xff
+	move    $r5, #0x80000000
+	and     O1H, $r0, $r5
+	addi    $r5, $r3, #-1
+	slti    $r15, $r5, #0xfe
+	beqzs8  .LJspec
+
+.LJlab1:
+	addi    $r3, $r3, #0x380
+	slli    $r5, $r0, #9
+	srli    $r5, $r5, #12
+	or      O1H, O1H, $r5
+	slli    O1L, $r0, #29
+
+.LJret:
+	slli    $r5, $r3, #20
+	or      O1H, O1H, $r5
+	move    $r0, $r1
+	move    $r1, $r2
+
+.LJ999:
+	pop     $lp
+	ret5    $lp
+
+.LJspec:
+	move    O1L, #0
+	add     $r0, $r0, $r0
+	beqz    $r0, .LJret
+	bnez    $r3, .Li42
+
+.Lb43:
+	addi    $r3, $r3, #-1
+	add     $r0, $r0, $r0
+	move    $r5, #0x800000
+	slt     $r15, $r0, $r5
+	bnezs8  .Lb43
+	j       .LJlab1
+.Li42:
+	move    $r3, #0x7ff
+	move    $r5, #0xff000000
+	slt     $r15, $r5, $r0
+	beqzs8  .LJret
+	move    O1H, #0xfff80000
+	j       .LJret
+	.size __extendsfdf2, .-__extendsfdf2
+#endif /* L_sf_to_df */
+
+
+
+#ifdef L_df_to_sf
+
+#ifndef __big_endian__
+	#define P1L     $r0
+	#define P1H     $r1
+	#define P2L     $r2
+	#define P2H     $r3
+#else
+	#define P1H     $r0
+	#define P1L     $r1
+	#define P2H     $r2
+	#define P2L     $r3
+#endif
+	.text
+	.align	2
+	.global	__truncdfsf2
+	.type	__truncdfsf2, @function
+__truncdfsf2:
+	push    $lp
+	pushm   $r6, $r8
+
+	slli    P2H, P1H, #11
+	srli    $r7, P1L, #21
+	or      P2H, P2H, $r7
+	slli    P2L, P1L, #11
+	move    $r7, #0x80000000
+	or      P2H, P2H, $r7
+	and     $r5, P1H, $r7
+	slli    $r4, P1H, #1
+	srli    $r4, $r4, #21
+	addi    $r4, $r4, #0xfffffc80
+	addi    $r7, $r4, #-1
+	slti    $r15, $r7, #0xfe
+	beqzs8  .LKspec
+
+.LKlab1:
+	beqz    P2L, .Li45
+	ori     P2H, P2H, #1
+.Li45:
+	#ADD(P2H, $0x80)
+	move    $r15, #0x80
+	add     P2H, P2H, $r15
+	slt     $r15, P2H, $r15
+
+	#ADDC($r4, $0x0)
+	add     $r4, $r4, $r15
+	srli    $r7, P2H, #8
+	andi    $r7, $r7, #1
+	sub     P2H, P2H, $r7
+	slli    P2H, P2H, #1
+	srli    P2H, P2H, #9
+	slli    $r7, $r4, #23
+	or      P2H, P2H, $r7
+	or      $r0, P2H, $r5
+
+.LK999:
+	popm    $r6, $r8
+	pop     $lp
+	ret5    $lp
+
+.LKspec:
+	subri   $r15, $r4, #0x47f
+	bnezs8  .Li46
+	slli    $r7, P2H, #1
+	or      $r7, $r7, P2L
+	beqz    $r7, .Li46
+	move    $r0, #0xffc00000
+	j       .LK999
+.Li46:
+	sltsi   $r15, $r4, #0xff
+	bnezs8  .Li48
+	move    $r7, #0x7f800000
+	or      $r0, $r5, $r7
+	j       .LK999
+.Li48:
+	subri   $r6, $r4, #1
+	move    $r7, #0x20
+	slt     $r15, $r6, $r7
+	bnezs8  .Li49
+	move    $r0, $r5
+	j       .LK999
+.Li49:
+	subri   $r8, $r6, #0x20
+	sll     $r7, P2H, $r8
+	or      P2L, P2L, $r7
+	srl     P2H, P2H, $r6
+	move    $r4, #0
+	move    $r7, #0x80000000
+	or      P2H, P2H, $r7
+	j       .LKlab1
+	.size __truncdfsf2, .-__truncdfsf2
+#endif /* L_df_to_sf */
+
+
+
+#ifdef L_df_to_si
+
+#ifndef __big_endian__
+	#define P1L     $r0
+	#define P1H     $r1
+#else
+	#define P1H     $r0
+	#define P1L     $r1
+#endif
+	.global	__fixdfsi
+	.type	__fixdfsi, @function
+__fixdfsi:
+	push    $lp
+	pushm   $r6, $r6
+
+	slli    $r3, P1H, #11
+	srli    $r6, P1L, #21
+	or      $r3, $r3, $r6
+	move    $r6, #0x80000000
+	or      $r3, $r3, $r6
+	slli    $r6, P1H, #1
+	srli    $r6, $r6, #21
+	subri   $r2, $r6, #0x41e
+	blez    $r2, .LLnaninf
+	move    $r6, #0x20
+	slt     $r15, $r2, $r6
+	bnezs8  .LL72
+	move    $r3, #0
+.LL72:
+	srl     $r3, $r3, $r2
+	sltsi   $r15, P1H, #0
+	beqzs8  .Li50
+	subri   $r3, $r3, #0
+.Li50:
+	move    $r0, $r3
+
+.LL999:
+	popm    $r6, $r6
+	pop     $lp
+	ret5    $lp
+
+.LLnaninf:
+	beqz    P1L, .Li51
+	ori     P1H, P1H, #1
+.Li51:
+	move    $r6, #0x7ff00000
+	slt     $r15, $r6, P1H
+	beqzs8  .Li52
+	move    $r0, #0x80000000
+	j       .LL999
+.Li52:
+	move    $r0, #0x7fffffff
+	j       .LL999
+	.size __fixdfsi, .-__fixdfsi
+#endif /* L_df_to_si */
+
+
+
+#ifdef L_fixsfdi
+
+#ifndef __big_endian__
+	#define O1L     $r1
+	#define O1H     $r2
+#else
+	#define O1H     $r1
+	#define O1L     $r2
+#endif
+	.text
+	.align	2
+	.global	__fixsfdi
+	.type	__fixsfdi, @function
+__fixsfdi:
+	push    $lp
+
+	srli    $r3, $r0, #23
+	andi    $r3, $r3, #0xff
+	slli    O1H, $r0, #8
+	move    $r5, #0x80000000
+	or      O1H, O1H, $r5
+	move    O1L, #0
+	sltsi   $r15, $r3, #0xbe
+	beqzs8  .LCinfnan
+	subri   $r3, $r3, #0xbe
+.LL8:
+	move    $r5, #0x20
+	slt     $r15, $r3, $r5
+	bnezs8  .LL9
+	move    O1L, O1H
+	move    O1H, #0
+	addi    $r3, $r3, #0xffffffe0
+	bnez    O1L, .LL8
+.LL9:
+	beqz    $r3, .LL10
+	move    $r4, O1H
+	srl     O1L, O1L, $r3
+	srl     O1H, O1H, $r3
+	subri   $r3, $r3, #0x20
+	sll     $r4, $r4, $r3
+	or      O1L, O1L, $r4
+.LL10:
+	sltsi   $r15, $r0, #0
+	beqzs8  .LCret
+
+	subri   O1H, O1H, #0
+	beqz    O1L, .LL11
+	subri   O1L, O1L, #0
+	subi45  O1H, #1
+.LL11:
+
+.LCret:
+	move    $r0, $r1
+	move    $r1, $r2
+
+.LC999:
+	pop     $lp
+	ret5    $lp
+
+.LCinfnan:
+	sltsi   $r15, $r0, #0
+	bnezs8  .LCret3
+	subri   $r15, $r3, #0xff
+	bnezs8  .Li7
+	slli    $r5, O1H, #1
+	beqz    $r5, .Li7
+
+.LCret3:
+	move    O1H, #0x80000000
+	j       .LCret
+.Li7:
+	move    O1H, #0x7fffffff
+	move    O1L, #-1
+	j       .LCret
+	.size	__fixsfdi, .-__fixsfdi
+#endif /* L_fixsfdi */
+
+
+
+#ifdef L_fixdfdi
+
+#ifndef __big_endian__
+	#define P1L     $r0
+	#define P1H     $r1
+	#define O1L     $r3
+	#define O1H     $r4
+#else
+	#define P1H     $r0
+	#define P1L     $r1
+	#define O1H     $r3
+	#define O1L     $r4
+#endif
+	.text
+	.align	2
+	.global	__fixdfdi
+	.type	__fixdfdi, @function
+__fixdfdi:
+	push    $lp
+	pushm   $r6, $r6
+
+	slli    $r5, P1H, #1
+	srli    $r5, $r5, #21
+	slli    O1H, P1H, #11
+	srli    $r6, P1L, #21
+	or      O1H, O1H, $r6
+	slli    O1L, P1L, #11
+	move    $r6, #0x80000000
+	or      O1H, O1H, $r6
+	slti    $r15, $r5, #0x43e
+	beqzs8  .LCnaninf
+	subri   $r2, $r5, #0x43e
+.LL14:
+	move    $r6, #0x20
+	slt     $r15, $r2, $r6
+	bnezs8  .LL15
+	move    O1L, O1H
+	move    O1H, #0
+	addi    $r2, $r2, #0xffffffe0
+	bnez    O1L, .LL14
+.LL15:
+	beqz    $r2, .LL16
+	move    P1L, O1H
+	srl     O1L, O1L, $r2
+	srl     O1H, O1H, $r2
+	subri   $r2, $r2, #0x20
+	sll     P1L, P1L, $r2
+	or      O1L, O1L, P1L
+.LL16:
+	sltsi   $r15, P1H, #0
+	beqzs8  .LCret
+
+	subri   O1H, O1H, #0
+	beqz    O1L, .LL17
+	subri   O1L, O1L, #0
+	subi45  O1H, #1
+.LL17:
+
+.LCret:
+	move    P1L, O1L
+	move    P1H, O1H
+
+.LC999:
+	popm    $r6, $r6
+	pop     $lp
+	ret5    $lp
+
+.LCnaninf:
+	sltsi   $r15, P1H, #0
+	bnezs8  .LCret3
+	subri   $r15, $r5, #0x7ff
+	bnezs8  .Li5
+	slli    $r6, O1H, #1
+	or      $r6, $r6, O1L
+	beqz    $r6, .Li5
+
+.LCret3:
+	move    O1H, #0x80000000
+	move    O1L, #0
+	j       .LCret
+.Li5:
+	move    O1H, #0x7fffffff
+	move    O1L, #-1
+	j       .LCret
+	.size	__fixdfdi, .-__fixdfdi
+#endif /* L_fixdfdi */
+
+
+
+#ifdef L_fixunssfsi
+
+	.global	__fixunssfsi
+	.type	__fixunssfsi, @function
+__fixunssfsi:
+	push    $lp
+
+	slli    $r1, $r0, #8
+	move    $r3, #0x80000000
+	or      $r1, $r1, $r3
+	srli    $r3, $r0, #23
+	andi    $r3, $r3, #0xff
+	subri   $r2, $r3, #0x9e
+	sltsi   $r15, $r2, #0
+	bnezs8  .LLspec
+	sltsi   $r15, $r2, #0x20
+	bnezs8  .Li45
+	move    $r0, #0
+	j       .LL999
+.Li45:
+	srl     $r1, $r1, $r2
+	sltsi   $r15, $r0, #0
+	beqzs8  .Li46
+	subri   $r1, $r1, #0
+.Li46:
+	move    $r0, $r1
+
+.LL999:
+	pop     $lp
+	ret5    $lp
+
+.LLspec:
+	move    $r3, #0x7f800000
+	slt     $r15, $r3, $r0
+	beqzs8  .Li47
+	move    $r0, #0x80000000
+	j       .LL999
+.Li47:
+	move    $r0, #-1
+	j       .LL999
+	.size	__fixunssfsi, .-__fixunssfsi
+#endif /* L_fixunssfsi */
+
+
+
+#ifdef L_fixunsdfsi
+
+#ifndef __big_endian__
+	#define P1L     $r0
+	#define P1H     $r1
+#else
+	#define P1H     $r0
+	#define P1L     $r1
+#endif
+	.text
+	.align	2
+	.global	__fixunsdfsi
+	.type	__fixunsdfsi, @function
+__fixunsdfsi:
+	push    $lp
+	pushm   $r6, $r6
+
+	slli    $r3, P1H, #11
+	srli    $r6, P1L, #21
+	or      $r3, $r3, $r6
+	move    $r6, #0x80000000
+	or      $r3, $r3, $r6
+	slli    $r6, P1H, #1
+	srli    $r6, $r6, #21
+	subri   $r2, $r6, #0x41e
+	sltsi   $r15, $r2, #0
+	bnezs8  .LNnaninf
+	move    $r6, #0x20
+	slt     $r15, $r2, $r6
+	bnezs8  .LL73
+	move    $r3, #0
+.LL73:
+	srl     $r3, $r3, $r2
+	sltsi   $r15, P1H, #0
+	beqzs8  .Li53
+	subri   $r3, $r3, #0
+.Li53:
+	move    $r0, $r3
+
+.LN999:
+	popm    $r6, $r6
+	pop     $lp
+	ret5    $lp
+
+.LNnaninf:
+	beqz    P1L, .Li54
+	ori     P1H, P1H, #1
+.Li54:
+	move    $r6, #0x7ff00000
+	slt     $r15, $r6, P1H
+	beqzs8  .Li55
+	move    $r0, #0x80000000
+	j       .LN999
+.Li55:
+	move    $r0, #-1
+	j       .LN999
+	.size __fixunsdfsi, .-__fixunsdfsi
+#endif /* L_fixunsdfsi */
+
+
+
+#ifdef L_fixunssfdi
+
+#ifndef __big_endian__
+	#define O1L     $r1
+	#define O1H     $r2
+#else
+	#define O1H     $r1
+	#define O1L     $r2
+#endif
+	.text
+	.align	2
+	.global	__fixunssfdi
+	.type	__fixunssfdi, @function
+__fixunssfdi:
+	push    $lp
+
+	srli    $r3, $r0, #23
+	andi    $r3, $r3, #0xff
+	slli    O1H, $r0, #8
+	move    $r5, #0x80000000
+	or      O1H, O1H, $r5
+	move    O1L, #0
+	sltsi   $r15, $r3, #0xbe
+	beqzs8  .LDinfnan
+	subri   $r3, $r3, #0xbe
+.LL12:
+	move    $r5, #0x20
+	slt     $r15, $r3, $r5
+	bnezs8  .LL13
+	move    O1L, O1H
+	move    O1H, #0
+	addi    $r3, $r3, #0xffffffe0
+	bnez    O1L, .LL12
+.LL13:
+	beqz    $r3, .LL14
+	move    $r4, O1H
+	srl     O1L, O1L, $r3
+	srl     O1H, O1H, $r3
+	subri   $r3, $r3, #0x20
+	sll     $r4, $r4, $r3
+	or      O1L, O1L, $r4
+.LL14:
+	sltsi   $r15, $r0, #0
+	beqzs8  .LDret
+
+	subri   O1H, O1H, #0
+	beqz    O1L, .LL15
+	subri   O1L, O1L, #0
+	subi45  O1H, #1
+.LL15:
+
+.LDret:
+	move    $r0, $r1
+	move    $r1, $r2
+
+.LD999:
+	pop     $lp
+	ret5    $lp
+
+.LDinfnan:
+	move    O1H, #0x80000000
+	move    O1L, #0
+	j       .LDret
+	.size	__fixunssfdi, .-__fixunssfdi
+#endif /* L_fixunssfdi */
+
+
+
+#ifdef L_fixunsdfdi
+
+#ifndef __big_endian__
+	#define P1L     $r0
+	#define P1H     $r1
+	#define O1L     $r3
+	#define O1H     $r4
+#else
+	#define P1H     $r0
+	#define P1L     $r1
+	#define O1H     $r3
+	#define O1L     $r4
+#endif
+	.text
+	.align	2
+	.global	__fixunsdfdi
+	.type	__fixunsdfdi, @function
+__fixunsdfdi:
+	push    $lp
+	pushm   $r6, $r6
+
+	slli    $r5, P1H, #1
+	srli    $r5, $r5, #21
+	slli    O1H, P1H, #11
+	srli    $r6, P1L, #21
+	or      O1H, O1H, $r6
+	slli    O1L, P1L, #11
+	move    $r6, #0x80000000
+	or      O1H, O1H, $r6
+	slti    $r15, $r5, #0x43e
+	beqzs8  .LDnaninf
+	subri   $r2, $r5, #0x43e
+.LL18:
+	move    $r6, #0x20
+	slt     $r15, $r2, $r6
+	bnezs8  .LL19
+	move    O1L, O1H
+	move    O1H, #0
+	addi    $r2, $r2, #0xffffffe0
+	bnez    O1L, .LL18
+.LL19:
+	beqz    $r2, .LL20
+	move    P1L, O1H
+	srl     O1L, O1L, $r2
+	srl     O1H, O1H, $r2
+	subri   $r2, $r2, #0x20
+	sll     P1L, P1L, $r2
+	or      O1L, O1L, P1L
+.LL20:
+	sltsi   $r15, P1H, #0
+	beqzs8  .LDret
+
+	subri   O1H, O1H, #0
+	beqz    O1L, .LL21
+	subri   O1L, O1L, #0
+	subi45  O1H, #1
+.LL21:
+
+.LDret:
+	move    P1L, O1L
+	move    P1H, O1H
+
+.LD999:
+	popm    $r6, $r6
+	pop     $lp
+	ret5    $lp
+
+.LDnaninf:
+	move    O1H, #0x80000000
+	move    O1L, #0
+	j       .LDret
+	.size	__fixunsdfdi, .-__fixunsdfdi
+#endif /* L_fixunsdfdi */
+
+
+
+#ifdef L_si_to_sf
+
+	.text
+	.align	2
+	.global	__floatsisf
+	.type	__floatsisf, @function
+__floatsisf:
+	push    $lp
+
+	move    $r4, #0x80000000
+	and     $r2, $r0, $r4
+	beqz    $r0, .Li39
+	sltsi   $r15, $r0, #0
+	beqzs8  .Li40
+	subri   $r0, $r0, #0
+.Li40:
+	move    $r1, #0x9e
+#ifdef __NDS32_PERF_EXT__
+	clz	$r3, $r0
+#else
+	pushm	$r0, $r2
+	pushm	$r4, $r5
+	bal	__clzsi2
+	move	$r3, $r0
+	popm	$r4, $r5
+	popm	$r0, $r2
+#endif
+	sub     $r1, $r1, $r3
+	sll     $r0, $r0, $r3
+
+	#ADD($r0, $0x80)
+	move    $r15, #0x80
+	add     $r0, $r0, $r15
+	slt     $r15, $r0, $r15
+
+	#ADDC($r1, $0x0)
+	add     $r1, $r1, $r15
+	srai    $r4, $r0, #8
+	andi    $r4, $r4, #1
+	sub     $r0, $r0, $r4
+	slli    $r0, $r0, #1
+	srli    $r0, $r0, #9
+	slli    $r4, $r1, #23
+	or      $r0, $r0, $r4
+.Li39:
+	or      $r0, $r0, $r2
+
+.LH999:
+	pop     $lp
+	ret5    $lp
+	.size	__floatsisf, .-__floatsisf
+#endif /* L_si_to_sf */
+
+
+
+#ifdef L_si_to_df
+
+#ifndef __big_endian__
+	#define O1L     $r1
+	#define O1H     $r2
+	#define O2L     $r4
+	#define O2H	$r5
+#else
+	#define O1H     $r1
+	#define O1L     $r2
+	#define O2H     $r4
+	#define O2L	$r5
+#endif
+	.text
+	.align	2
+	.global	__floatsidf
+	.type	__floatsidf, @function
+__floatsidf:
+	push    $lp
+	pushm   $r6, $r6
+
+	move    O1L, #0
+	move    O2H, O1L
+	move    $r3, O1L
+	move    O1H, $r0
+	beqz    O1H, .Li39
+	sltsi   $r15, O1H, #0
+	beqzs8  .Li40
+	move    O2H, #0x80000000
+
+	subri   O1H, O1H, #0
+	beqz    O1L, .LL71
+	subri   O1L, O1L, #0
+	subi45  O1H, #1
+.LL71:
+.Li40:
+	move    $r3, #0x41e
+#ifndef __big_endian__
+#ifdef __NDS32_PERF_EXT__
+	clz	$r4, $r2
+#else
+	pushm	$r0, $r3
+	push	$r5
+	move	$r0, $r2
+	bal	__clzsi2
+	move	$r4, $r0
+	pop	$r5
+	popm	$r0, $r3
+#endif
+#else /* __big_endian__ */
+#ifdef __NDS32_PERF_EXT__
+	clz	$r5, $r1
+#else
+	pushm	$r0, $r4
+	move	$r0, $r1
+	bal	__clzsi2
+	move	$r5, $r0
+	popm	$r0, $r4
+#endif
+#endif /* __big_endian__ */
+	sub     $r3, $r3, O2L
+	sll     O1H, O1H, O2L
+.Li39:
+	srli    O2L, O1L, #11
+	slli    $r6, O1H, #21
+	or      O2L, O2L, $r6
+	slli    $r6, O1H, #1
+	srli    $r6, $r6, #12
+	or      O2H, O2H, $r6
+	slli    $r6, $r3, #20
+	or      O2H, O2H, $r6
+	move    $r0, $r4
+	move    $r1, $r5
+
+.LH999:
+	popm    $r6, $r6
+	pop     $lp
+	ret5    $lp
+	.size __floatsidf, .-__floatsidf
+#endif /* L_si_to_df */
+
+
+
+#ifdef L_floatdisf
+
+#ifndef __big_endian__
+	#define P1L     $r0
+	#define P1H     $r1
+	#define P2L     $r2
+	#define P2H     $r3
+#else
+	#define P1H     $r0
+	#define P1L     $r1
+	#define P2H     $r2
+	#define P2L     $r3
+#endif
+	.text
+	.align	2
+	.global	__floatdisf
+	.type	__floatdisf, @function
+__floatdisf:
+	push    $lp
+	pushm   $r6, $r7
+
+	move    $r7, #0x80000000
+	and     $r5, P1H, $r7
+	move    P2H, P1H
+	move    P2L, P1L
+	or      $r7, P1H, P1L
+	beqz    $r7, .Li1
+	sltsi   $r15, P1H, #0
+	beqzs8  .Li2
+
+	subri   P2H, P2H, #0
+	beqz    P2L, .LL1
+	subri   P2L, P2L, #0
+	subi45  P2H, #1
+.LL1:
+.Li2:
+	move    $r4, #0xbe
+
+
+	#NORMd($r2, $r6, P1L)
+	bnez    P2H, .LL2
+	bnez    P2L, .LL3
+	move    $r4, #0
+	j       .LL4
+.LL3:
+	move    P2H, P2L
+	move    P2L, #0
+	move    $r6, #32
+	sub     $r4, $r4, $r6
+.LL2:
+#ifdef __NDS32_PERF_EXT__
+	clz	$r6, P2H
+#else
+	pushm	$r0, $r5
+	move	$r0, P2H
+	bal	__clzsi2
+	move	$r6, $r0
+	popm	$r0, $r5
+#endif
+	beqz    $r6, .LL4
+	sub     $r4, $r4, $r6
+	subri   P1L, $r6, #32
+	srl     P1L, P2L, P1L
+	sll     P2L, P2L, $r6
+	sll     P2H, P2H, $r6
+	or      P2H, P2H, P1L
+.LL4:
+	#NORMd End
+
+	beqz    P2L, .Li3
+	ori     P2H, P2H, #1
+.Li3:
+	#ADD(P2H, $0x80)
+	move    $r15, #0x80
+	add     P2H, P2H, $r15
+	slt     $r15, P2H, $r15
+
+	#ADDC($r4, $0x0)
+	add     $r4, $r4, $r15
+	srli    $r7, P2H, #8
+	andi    $r7, $r7, #1
+	sub     P2H, P2H, $r7
+	slli    P2H, P2H, #1
+	srli    P2H, P2H, #9
+	slli    $r7, $r4, #23
+	or      P2H, P2H, $r7
+.Li1:
+	or      $r0, P2H, $r5
+
+.LA999:
+	popm    $r6, $r7
+	pop     $lp
+	ret5    $lp
+	.size	__floatdisf, .-__floatdisf
+#endif /* L_floatdisf */
+
+
+
+#ifdef L_floatdidf
+
+#ifndef __big_endian__
+	#define P1L     $r0
+	#define P1H     $r1
+	#define P2L     $r2
+	#define P2H     $r3
+	#define O1L     $r5
+	#define O1H     $r6
+#else
+	#define P1H     $r0
+	#define P1L     $r1
+	#define P2H     $r2
+	#define P2L     $r3
+	#define O1H     $r5
+	#define O1L     $r6
+#endif
+	.text
+	.align	2
+	.global	__floatdidf
+	.type	__floatdidf, @function
+__floatdidf:
+	push    $lp
+	pushm   $r6, $r8
+
+	move    $r4, #0
+	move    $r7, $r4
+	move    P2H, P1H
+	move    P2L, P1L
+	or      $r8, P1H, P1L
+	beqz    $r8, .Li1
+	move    $r4, #0x43e
+	sltsi   $r15, P1H, #0
+	beqzs8  .Li2
+	move    $r7, #0x80000000
+
+	subri   P2H, P2H, #0
+	beqz    P2L, .LL1
+	subri   P2L, P2L, #0
+	subi45  P2H, #1
+.LL1:
+
+.Li2:
+	#NORMd($r2, O1H, O1L)
+	bnez    P2H, .LL2
+	bnez    P2L, .LL3
+	move    $r4, #0
+	j       .LL4
+.LL3:
+	move    P2H, P2L
+	move    P2L, #0
+	move    O1H, #32
+	sub     $r4, $r4, O1H
+.LL2:
+#ifdef __NDS32_PERF_EXT__
+	clz	O1H, P2H
+#else /* not __NDS32_PERF_EXT__ */
+/*
+  Replace clz with function call.
+	clz     O1H, P2H
+  EL:	clz     $r6, $r3
+  EB:	clz	$r5, $r2
+*/
+#ifndef __big_endian__
+	pushm	$r0, $r5
+	move	$r0, $r3
+	bal	__clzsi2
+	move	$r6, $r0
+	popm	$r0, $r5
+#else
+	pushm	$r0, $r4
+	move	$r0, $r2
+	bal	__clzsi2
+	move	$r5, $r0
+	popm	$r0, $r4
+#endif
+#endif /* not __NDS32_PERF_EXT__ */
+	beqz    O1H, .LL4
+	sub     $r4, $r4, O1H
+	subri   O1L, O1H, #32
+	srl     O1L, P2L, O1L
+	sll     P2L, P2L, O1H
+	sll     P2H, P2H, O1H
+	or      P2H, P2H, O1L
+.LL4:
+	#NORMd End
+
+	#ADD(P2L, $0x400)
+	move    $r15, #0x400
+	add     P2L, P2L, $r15
+	slt     $r15, P2L, $r15
+
+
+	#ADDCC(P2H, $0x0)
+	beqzs8  .LL7
+	add     P2H, P2H, $r15
+	slt     $r15, P2H, $r15
+.LL7:
+
+	#ADDC($r4, $0x0)
+	add     $r4, $r4, $r15
+	srli    $r8, P2L, #11
+	andi    $r8, $r8, #1
+	sub     P2L, P2L, $r8
+.Li1:
+	srli    O1L, P2L, #11
+	slli    $r8, P2H, #21
+	or      O1L, O1L, $r8
+	slli    O1H, P2H, #1
+	srli    O1H, O1H, #12
+	slli    $r8, $r4, #20
+	or      O1H, O1H, $r8
+	or      O1H, O1H, $r7
+	move    P1L, O1L
+	move    P1H, O1H
+
+.LA999:
+	popm    $r6, $r8
+	pop     $lp
+	ret5    $lp
+	.size	__floatdidf, .-__floatdidf
+#endif /* L_floatdidf */
+
+
+
+#ifdef L_floatunsisf
+
+	.text
+	.align	2
+	.global	__floatunsisf
+	.type	__floatunsisf, @function
+__floatunsisf:
+	push    $lp
+
+	beqz    $r0, .Li41
+	move    $r2, #0x9e
+#ifdef __NDS32_PERF_EXT__
+	clz	$r1, $r0
+#else
+	push	$r0
+	pushm	$r2, $r5
+	bal	__clzsi2
+	move	$r1, $r0
+	popm	$r2, $r5
+	pop	$r0
+#endif
+
+	sub     $r2, $r2, $r1
+	sll     $r0, $r0, $r1
+
+	#ADD($r0, $0x80)
+	move    $r15, #0x80
+	add     $r0, $r0, $r15
+	slt     $r15, $r0, $r15
+
+	#ADDC($r2, $0x0)
+	add     $r2, $r2, $r15
+	srli    $r3, $r0, #8
+	andi    $r3, $r3, #1
+	sub     $r0, $r0, $r3
+	slli    $r0, $r0, #1
+	srli    $r0, $r0, #9
+	slli    $r3, $r2, #23
+	or      $r0, $r0, $r3
+
+.Li41:
+.LI999:
+	pop     $lp
+	ret5    $lp
+	.size	__floatunsisf, .-__floatunsisf
+#endif /* L_floatunsisf */
+
+
+
+#ifdef L_floatunsidf
+
+#ifndef __big_endian__
+	#define O1L     $r1
+	#define O1H     $r2
+	#define O2L     $r4
+	#define O2H	$r5
+#else
+	#define O1H     $r1
+	#define O1L     $r2
+	#define O2H     $r4
+	#define O2L	$r5
+#endif
+	.text
+	.align	2
+	.global	__floatunsidf
+	.type	__floatunsidf, @function
+__floatunsidf:
+	push    $lp
+	pushm   $r6, $r6
+
+	move    O1L, #0
+	move    $r3, O1L
+	move    O1H, $r0
+	beqz    O1H, .Li41
+	move    $r3, #0x41e
+#ifndef __big_endian__
+#ifdef __NDS32_PERF_EXT__
+	clz	$r5, $r2
+#else
+	pushm	$r0, $r4
+	move	$r0, $r2
+	bal	__clzsi2
+	move	$r5, $r0
+	popm	$r0, $r4
+#endif
+#else /* __big_endian__ */
+#ifdef __NDS32_PERF_EXT__
+	clz	$r4, $r1
+#else
+	pushm	$r0, $r3
+	push	$r5
+	move	$r0, $r1
+	bal	__clzsi2
+	move	$r4, $r0
+	pop	$r5
+	popm	$r0, $r3
+#endif
+#endif /* __big_endian__ */
+	sub     $r3, $r3, O2H
+	sll     O1H, O1H, O2H
+.Li41:
+	srli    O2L, O1L, #11
+	slli    $r6, O1H, #21
+	or      O2L, O2L, $r6
+	slli    O2H, O1H, #1
+	srli    O2H, O2H, #12
+	slli    $r6, $r3, #20
+	or      O2H, O2H, $r6
+	move    $r0, $r4
+	move    $r1, $r5
+
+.LI999:
+	popm    $r6, $r6
+	pop     $lp
+	ret5    $lp
+	.size __floatunsidf, .-__floatunsidf
+#endif /* L_floatunsidf */
+
+
+
+#ifdef L_floatundisf
+
+#ifndef __big_endian__
+	#define P1L     $r0
+	#define P1H     $r1
+	#define P2L     $r2
+	#define P2H     $r3
+#else
+	#define P1H     $r0
+	#define P1L     $r1
+	#define P2H     $r2
+	#define P2L     $r3
+#endif
+	.text
+	.align	2
+	.global	__floatundisf
+	.type	__floatundisf, @function
+__floatundisf:
+	push    $lp
+	pushm   $r6, $r6
+
+	move    P2H, P1H
+	move    P2L, P1L
+	or      $r6, P1H, P1L
+	beqz    $r6, .Li4
+	move    $r4, #0xbe
+
+
+	#NORMd($r2, $r5, P1L)
+	bnez    P2H, .LL5
+	bnez    P2L, .LL6
+	move    $r4, #0
+	j       .LL7
+.LL6:
+	move    P2H, P2L
+	move    P2L, #0
+	move    $r5, #32
+	sub     $r4, $r4, $r5
+.LL5:
+#ifdef __NDS32_PERF_EXT__
+	clz	$r5, P2H
+#else
+	pushm	$r0, $r4
+	move	$r0, P2H
+	bal	__clzsi2
+	move	$r5, $r0
+	popm	$r0, $r4
+#endif
+	beqz    $r5, .LL7
+	sub     $r4, $r4, $r5
+	subri   P1L, $r5, #32
+	srl     P1L, P2L, P1L
+	sll     P2L, P2L, $r5
+	sll     P2H, P2H, $r5
+	or      P2H, P2H, P1L
+.LL7:
+	#NORMd End
+
+	beqz    P2L, .Li5
+	ori     P2H, P2H, #1
+.Li5:
+	#ADD(P2H, $0x80)
+	move    $r15, #0x80
+	add     P2H, P2H, $r15
+	slt     $r15, P2H, $r15
+
+	#ADDC($r4, $0x0)
+	add     $r4, $r4, $r15
+	srli    $r6, P2H, #8
+	andi    $r6, $r6, #1
+	sub     P2H, P2H, $r6
+	slli    P2H, P2H, #1
+	srli    P2H, P2H, #9
+	slli    $r6, $r4, #23
+	or      P2H, P2H, $r6
+.Li4:
+	move    $r0, P2H
+
+.LB999:
+	popm    $r6, $r6
+	pop     $lp
+	ret5    $lp
+	.size	__floatundisf, .-__floatundisf
+#endif /* L_floatundisf */
+
+
+
+#ifdef L_floatundidf
+
+#ifndef __big_endian__
+	#define P1L     $r0
+	#define P1H     $r1
+	#define P2L     $r2
+	#define P2H     $r3
+	#define O1L     $r5
+	#define O1H     $r6
+#else
+	#define P1H     $r0
+	#define P1L     $r1
+	#define P2H     $r2
+	#define P2L     $r3
+	#define O1H     $r5
+	#define O1L     $r6
+#endif
+	.text
+	.align	2
+	.global	__floatundidf
+	.type	__floatundidf, @function
+__floatundidf:
+	push    $lp
+	pushm   $r6, $r7
+
+	move    $r4, #0
+	move    P2H, P1H
+	move    P2L, P1L
+	or      $r7, P1H, P1L
+	beqz    $r7, .Li3
+	move    $r4, #0x43e
+
+
+	#NORMd($r2, O1H, O1L)
+	bnez    P2H, .LL8
+	bnez    P2L, .LL9
+	move    $r4, #0
+	j       .LL10
+.LL9:
+	move    P2H, P2L
+	move    P2L, #0
+	move    O1H, #32
+	sub     $r4, $r4, O1H
+.LL8:
+#ifdef __NDS32_PERF_EXT__
+	clz	O1H, P2H
+#else /* not __NDS32_PERF_EXT__ */
+/*
+  Replace clz with function call.
+	clz     O1H, P2H
+  EL:	clz     $r6, $r3
+  EB:	clz	$r5, $r2
+*/
+#ifndef __big_endian__
+	pushm	$r0, $r5
+	move	$r0, $r3
+	bal	__clzsi2
+	move	$r6, $r0
+	popm	$r0, $r5
+#else
+	pushm	$r0, $r4
+	move	$r0, $r2
+	bal	__clzsi2
+	move	$r5, $r0
+	popm	$r0, $r4
+#endif
+#endif /* not __NDS32_PERF_EXT__ */
+	beqz    O1H, .LL10
+	sub     $r4, $r4, O1H
+	subri   O1L, O1H, #32
+	srl     O1L, P2L, O1L
+	sll     P2L, P2L, O1H
+	sll     P2H, P2H, O1H
+	or      P2H, P2H, O1L
+.LL10:
+	#NORMd End
+
+	#ADD(P2L, $0x400)
+	move    $r15, #0x400
+	add     P2L, P2L, $r15
+	slt     $r15, P2L, $r15
+
+
+	#ADDCC(P2H, $0x0)
+	beqzs8  .LL13
+	add     P2H, P2H, $r15
+	slt     $r15, P2H, $r15
+.LL13:
+
+	#ADDC($r4, $0x0)
+	add     $r4, $r4, $r15
+	srli    $r7, P2L, #11
+	andi    $r7, $r7, #1
+	sub     P2L, P2L, $r7
+.Li3:
+	srli    O1L, P2L, #11
+	slli    $r7, P2H, #21
+	or      O1L, O1L, $r7
+	slli    O1H, P2H, #1
+	srli    O1H, O1H, #12
+	slli    $r7, $r4, #20
+	or      O1H, O1H, $r7
+	move    P1L, O1L
+	move    P1H, O1H
+
+.LB999:
+	popm    $r6, $r7
+	pop     $lp
+	ret5    $lp
+	.size	__floatundidf, .-__floatundidf
+#endif /* L_floatundidf */
+
+
+
+#ifdef L_compare_sf
+
+	.text
+	.align	2
+	.global	__cmpsf2
+	.type	__cmpsf2, @function
+__cmpsf2:
+	.global	__eqsf2
+	.type	__eqsf2, @function
+__eqsf2:
+	.global	__ltsf2
+	.type	__ltsf2, @function
+__ltsf2:
+	.global	__lesf2
+	.type	__lesf2, @function
+__lesf2:
+	.global	__nesf2
+	.type	__nesf2, @function
+__nesf2:
+	move    $r4, #1
+	j	.LA
+
+	.global	__gesf2
+	.type	__gesf2, @function
+__gesf2:
+	.global	__gtsf2
+	.type	__gtsf2, @function
+__gtsf2:
+	move	$r4, #-1
+.LA:
+	push    $lp
+
+	slli    $r2, $r0, #1
+	slli    $r3, $r1, #1
+	or      $r5, $r2, $r3
+	beqz    $r5, .LMequ
+	move    $r5, #0xff000000
+	slt     $r15, $r5, $r2
+	bnezs8  .LMnan
+	slt     $r15, $r5, $r3
+	bnezs8  .LMnan
+	srli    $r2, $r2, #1
+	sltsi   $r15, $r0, #0
+	beqzs8  .Li48
+	subri   $r2, $r2, #0
+.Li48:
+	srli    $r3, $r3, #1
+	sltsi   $r15, $r1, #0
+	beqzs8  .Li49
+	subri   $r3, $r3, #0
+.Li49:
+	slts    $r15, $r2, $r3
+	beqzs8  .Li50
+	move    $r0, #-1
+	j       .LM999
+.Li50:
+	slts    $r15, $r3, $r2
+	beqzs8  .LMequ
+	move    $r0, #1
+	j       .LM999
+
+.LMequ:
+	move    $r0, #0
+
+.LM999:
+	pop     $lp
+	ret5    $lp
+
+.LMnan:
+	move    $r0, $r4
+	j       .LM999
+	.size   __cmpsf2, .-__cmpsf2
+	.size   __eqsf2, .-__eqsf2
+	.size   __ltsf2, .-__ltsf2
+	.size   __lesf2, .-__lesf2
+	.size   __nesf2, .-__nesf2
+	.size   __gesf2, .-__gesf2
+	.size   __gtsf2, .-__gtsf2
+#endif /* L_compare_sf */
+
+
+
+#ifdef L_compare_df
+
+#ifdef __big_endian__
+	#define P1H     $r0
+	#define P1L     $r1
+	#define P2H     $r2
+	#define P2L     $r3
+#else
+	#define P1H     $r1
+	#define P1L     $r0
+	#define P2H     $r3
+	#define P2L     $r2
+#endif
+	.align	2
+	.globl	__gtdf2
+	.globl	__gedf2
+	.globl	__ltdf2
+	.globl	__ledf2
+	.globl	__eqdf2
+	.globl	__nedf2
+	.globl	__cmpdf2
+	.type	__gtdf2, @function
+	.type	__gedf2, @function
+	.type	__ltdf2, @function
+	.type	__ledf2, @function
+	.type	__eqdf2, @function
+	.type	__nedf2, @function
+	.type	__cmpdf2, @function
+__gtdf2:
+__gedf2:
+	movi	$r4, -1
+	b	.L1
+
+__ltdf2:
+__ledf2:
+__cmpdf2:
+__nedf2:
+__eqdf2:
+	movi	$r4, 1
+.L1:
+#if defined (__NDS32_ISA_V3M__)
+	push25	$r10, 0
+#else
+	smw.adm	$r6, [$sp], $r9, 0
+#endif
+
+	sethi	$r5, 0x7ff00
+	and	$r6, P1H, $r5	! r6=aExp
+	and	$r7, P2H, $r5	! r7=bExp
+	slli	$r8, P1H, 12	! r8=aSig0
+	slli	$r9, P2H, 12	! r9=bSig0
+	beq	$r6, $r5, .L11	! aExp==0x7ff
+	beq	$r7, $r5, .L12	! bExp==0x7ff
+.L2:
+	slli	$ta, P1H, 1	! ta=ahigh<<1
+	or	$ta, P1L, $ta	!
+	xor	$r5, P1H, P2H	! r5=ahigh^bhigh
+	beqz	$ta, .L3	! if(ahigh<<1)==0,go .L3
+	!-------------------------------
+	! (ahigh<<1)!=0 || (bhigh<<1)!=0
+	!-------------------------------
+.L4:
+	beqz	$r5, .L5	! ahigh==bhigh, go .L5
+	!--------------------
+	! a != b
+	!--------------------
+.L6:
+	bltz	$r5, .L7	! if(aSign!=bSign), go .L7
+	!--------------------
+	! aSign==bSign
+	!--------------------
+	slt	$ta, $r6, $r7	! ta=(aExp<bExp)
+	bne	$r6, $r7, .L8	! if(aExp!=bExp),go .L8
+	slt	$ta, $r8, $r9	! ta=(aSig0<bSig0)
+	bne	$r8, $r9, .L8	! if(aSig0!=bSig0),go .L8
+	slt	$ta, P1L, P2L	! ta=(aSig1<bSig1)
+.L8:
+	beqz	$ta, .L10	! if(|a|>|b|), go .L10
+	nor	$r0, P2H, P2H	! if(|a|<|b|),return (~yh)
+.L14:
+#if defined (__NDS32_ISA_V3M__)
+	pop25	$r10, 0
+#else
+	lmw.bim	$r6, [$sp], $r9, 0
+	ret
+#endif
+.L10:
+	ori	$r0, P2H, 1	! return (yh|1)
+	b	.L14
+	!--------------------
+	! (ahigh<<1)=0
+	!--------------------
+.L3:
+	slli	$ta, P2H, 1	! ta=bhigh<<1
+	or	$ta, P2L, $ta	!
+	bnez	$ta, .L4	! ta=(bhigh<<1)!=0,go .L4
+.L5:
+	xor	$ta, P1L, P2L	! ta=alow^blow
+	bnez	$ta, .L6	! alow!=blow,go .L6
+	movi	$r0, 0		! a==b, return 0
+	b	.L14
+	!--------------------
+	! aExp=0x7ff;
+	!--------------------
+.L11:
+	or	P1L, P1L, $r8	! x1=(aSig0|aSig1)
+	bnez	P1L, .L13	! if(a=nan), go.L13
+	xor	$ta, $r7, $r5	! ta=(bExp^0x7ff)
+	bnez	$ta, .L2	! if(bExp!=0x7ff), go .L2
+	!--------------------
+	! bExp=0x7ff;
+	!--------------------
+.L12:
+	or	$ta, P2L, $r9	! ta=(bSig0|bSig1)
+	beqz	$ta, .L2	! if(b!=nan), go .L2
+.L13:
+	move	$r0, $r4
+	b	.L14
+	!--------------------
+	! aSign!=bSign
+	!--------------------
+.L7:
+	ori	$r0, P1H, 1	! if(aSign!=bSign), return (ahigh|1)
+	b	.L14
+
+	.size	__gtdf2, .-__gtdf2
+	.size	__gedf2, .-__gedf2
+	.size	__ltdf2, .-__ltdf2
+	.size	__ledf2, .-__ledf2
+	.size	__eqdf2, .-__eqdf2
+	.size	__nedf2, .-__nedf2
+	.size	__cmpdf2, .-__cmpdf2
+#endif /* L_compare_df */
+
+
+
+#ifdef L_unord_sf
+
+	.text
+	.align	2
+	.global	__unordsf2
+	.type	__unordsf2, @function
+__unordsf2:
+	push    $lp
+
+	slli    $r2, $r0, #1
+	move    $r3, #0xff000000
+	slt     $r15, $r3, $r2
+	beqzs8  .Li52
+	move    $r0, #1
+	j       .LP999
+.Li52:
+	slli    $r2, $r1, #1
+	move    $r3, #0xff000000
+	slt     $r15, $r3, $r2
+	beqzs8  .Li53
+	move    $r0, #1
+	j       .LP999
+.Li53:
+	move    $r0, #0
+
+.LP999:
+	pop     $lp
+	ret5    $lp
+	.size	__unordsf2, .-__unordsf2
+#endif /* L_unord_sf */
+
+
+
+#ifdef L_unord_df
+
+#ifndef __big_endian__
+	#define P1L     $r0
+	#define P1H     $r1
+	#define P2L     $r2
+	#define P2H     $r3
+#else
+	#define P1H     $r0
+	#define P1L     $r1
+	#define P2H     $r2
+	#define P2L     $r3
+#endif
+	.text
+	.align	2
+	.global	__unorddf2
+	.type	__unorddf2, @function
+__unorddf2:
+	push    $lp
+
+	slli    $r4, P1H, #1
+	beqz    P1L, .Li66
+	addi    $r4, $r4, #1
+.Li66:
+	move    $r5, #0xffe00000
+	slt     $r15, $r5, $r4
+	beqzs8  .Li67
+	move    $r0, #1
+	j       .LR999
+.Li67:
+	slli    $r4, P2H, #1
+	beqz    P2L, .Li68
+	addi    $r4, $r4, #1
+.Li68:
+	move    $r5, #0xffe00000
+	slt     $r15, $r5, $r4
+	beqzs8  .Li69
+	move    $r0, #1
+	j       .LR999
+.Li69:
+	move    $r0, #0
+
+.LR999:
+	pop     $lp
+	ret5    $lp
+	.size __unorddf2, .-__unorddf2
+#endif /* L_unord_df */
+/* ------------------------------------------- */
+/* DPBIT floating point operations for libgcc  */
+/* ------------------------------------------- */
diff --git a/libgcc/config/nds32/lib1asmsrc-newlib.S b/libgcc/config/nds32/lib1asmsrc-newlib.S
new file mode 100644
index 00000000000..6eb3fb0a753
--- /dev/null
+++ b/libgcc/config/nds32/lib1asmsrc-newlib.S
@@ -0,0 +1,204 @@
+/* newlib libgcc routines of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+	.section	.mdebug.abi_nds32
+	.previous
+
+#ifdef L_divsi3
+
+	.text
+	.align	2
+	.globl	__divsi3
+	.type	__divsi3, @function
+__divsi3:
+	movi	$r5, 0		! res = 0
+	xor	$r4, $r0, $r1	! neg
+	bltz	$r0, .L1
+	bltz	$r1, .L2
+.L3:
+	movi	$r2, 1		! bit = 1
+	slt	$r3, $r1, $r0	! test if dividend is smaller than or equal to divisor
+	beqz	$r3, .L5
+	bltz	$r1, .L5
+
+.L4:
+	slli	$r2, $r2, 1
+	beqz	$r2, .L6
+	slli	$r1, $r1, 1
+	slt	$r3, $r1, $r0
+	beqz	$r3, .L5
+	bgez	$r1, .L4
+
+.L5:
+	slt	$r3, $r0, $r1
+	bnez	$r3, .L8
+	sub	$r0, $r0, $r1
+	or	$r5, $r5, $r2
+.L8:
+	srli	$r1, $r1, 1
+	srli	$r2, $r2, 1
+	bnez	$r2, .L5
+.L6:
+	bgez	$r4, .L7
+	subri	$r5, $r5, 0	! negate if $r4 < 0
+.L7:
+	move	$r0, $r5
+	ret
+.L1:
+	subri	$r0, $r0, 0	! change neg to pos
+	bgez	$r1, .L3
+.L2:
+	subri	$r1, $r1, 0	! change neg to pos
+	j	.L3
+	.size	__divsi3, .-__divsi3
+
+#endif /* L_divsi3 */
+
+
+#ifdef L_modsi3
+
+	.text
+	.align	2
+	.globl	__modsi3
+	.type	__modsi3, @function
+__modsi3:
+	movi	$r5, 0		! res = 0
+	move	$r4, $r0	! neg
+	bltz	$r0, .L1
+	bltz	$r1, .L2
+.L3:
+	movi	$r2, 1		! bit = 1
+	slt	$r3, $r1, $r0	! test if dividend is smaller than or equal to divisor
+	beqz	$r3, .L5
+	bltz	$r1, .L5
+
+.L4:
+	slli	$r2, $r2, 1
+	beqz	$r2, .L6
+	slli	$r1, $r1, 1
+	slt	$r3, $r1, $r0
+	beqz	$r3, .L5
+	bgez	$r1, .L4
+
+.L5:
+	slt	$r3, $r0, $r1
+	bnez	$r3, .L8
+	sub	$r0, $r0, $r1
+	or	$r5, $r5, $r2
+.L8:
+	srli	$r1, $r1, 1
+	srli	$r2, $r2, 1
+	bnez	$r2, .L5
+.L6:
+	bgez	$r4, .L7
+	subri	$r0, $r0, 0	! negate if $r4 < 0
+.L7:
+	ret
+.L1:
+	subri	$r0, $r0, 0	! change neg to pos
+	bgez	$r1, .L3
+.L2:
+	subri	$r1, $r1, 0	! change neg to pos
+	j	.L3
+	.size	__modsi3, .-__modsi3
+
+#endif /* L_modsi3  */
+
+
+#ifdef L_udivsi3
+
+	.text
+	.align	2
+	.globl	__udivsi3
+	.type	__udivsi3, @function
+__udivsi3:
+	movi	$r5, 0		! res = 0
+	movi	$r2, 1		! bit = 1
+	slt	$r3, $r1, $r0	! test if dividend is smaller than or equal to divisor
+	beqz	$r3, .L5
+	bltz	$r1, .L5
+
+.L4:
+	slli	$r2, $r2, 1
+	beqz	$r2, .L6
+	slli	$r1, $r1, 1
+	slt	$r3, $r1, $r0
+	beqz	$r3, .L5
+	bgez	$r1, .L4
+
+.L5:
+	slt	$r3, $r0, $r1
+	bnez	$r3, .L8
+	sub	$r0, $r0, $r1
+	or	$r5, $r5, $r2
+.L8:
+	srli	$r1, $r1, 1
+	srli	$r2, $r2, 1
+	bnez	$r2, .L5
+.L6:
+	move	$r0, $r5
+	ret
+	.size	__udivsi3, .-__udivsi3
+
+#endif /* L_udivsi3  */
+
+
+#ifdef L_umodsi3
+
+	.text
+	.align	2
+	.globl	__umodsi3
+	.type	__umodsi3, @function
+__umodsi3:
+	movi	$r5, 0		! res = 0
+	movi	$r2, 1		! bit = 1
+	slt	$r3, $r1, $r0	! test if dividend is smaller than or equal to divisor
+	beqz	$r3, .L5
+	bltz	$r1, .L5
+
+.L4:
+	slli	$r2, $r2, 1
+	beqz	$r2, .L6
+	slli	$r1, $r1, 1
+	slt	$r3, $r1, $r0
+	beqz	$r3, .L5
+	bgez	$r1, .L4
+
+.L5:
+	slt	$r3, $r0, $r1
+	bnez	$r3, .L8
+	sub	$r0, $r0, $r1
+	or	$r5, $r5, $r2
+.L8:
+	srli	$r1, $r1, 1
+	srli	$r2, $r2, 1
+	bnez	$r2, .L5
+.L6:
+	ret
+	.size	__umodsi3, .-__umodsi3
+
+#endif /* L_umodsi3  */
+
+/* ----------------------------------------------------------- */
diff --git a/libgcc/config/nds32/lib2csrc-mculib/_clzdi2.c b/libgcc/config/nds32/lib2csrc-mculib/_clzdi2.c
new file mode 100644
index 00000000000..7d39ea85b7a
--- /dev/null
+++ b/libgcc/config/nds32/lib2csrc-mculib/_clzdi2.c
@@ -0,0 +1,38 @@
+/* mculib libgcc routines of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+extern int __clzsi2 (int val);
+int
+__clzdi2 (long long val)
+{
+  if (val >> 32)
+    {
+      return __clzsi2 (val >> 32);
+    }
+  else
+    {
+      return __clzsi2 (val) + 32;
+    }
+}
diff --git a/libgcc/config/nds32/lib2csrc-mculib/_clzsi2.c b/libgcc/config/nds32/lib2csrc-mculib/_clzsi2.c
new file mode 100644
index 00000000000..9d0bdd96d80
--- /dev/null
+++ b/libgcc/config/nds32/lib2csrc-mculib/_clzsi2.c
@@ -0,0 +1,49 @@
+/* mculib libgcc routines of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+int
+__clzsi2 (int val)
+{
+  int i = 32;
+  int j = 16;
+  int temp;
+
+  for (; j; j >>= 1)
+    {
+      if (temp = val >> j)
+	{
+	  if (j == 1)
+	    {
+	      return (i - 2);
+	    }
+	  else
+	    {
+	      i -= j;
+	      val = temp;
+	    }
+	}
+    }
+  return (i - val);
+}
diff --git a/libgcc/config/nds32/sfp-machine.h b/libgcc/config/nds32/sfp-machine.h
new file mode 100644
index 00000000000..62a1532de60
--- /dev/null
+++ b/libgcc/config/nds32/sfp-machine.h
@@ -0,0 +1,91 @@
+/* Machine settings for software floating-point emulation
+   of Andes NDS32 cpu for GNU compiler
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   In addition to the permissions in the GNU Lesser General Public
+   License, the Free Software Foundation gives you unlimited
+   permission to link the compiled version of this file into
+   combinations with other programs, and to distribute those
+   combinations without any restriction coming from the use of this
+   file.  (The Lesser General Public License restrictions do apply in
+   other respects; for example, they cover modification of the file,
+   and distribution when not linked into a combine executable.)
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#define _FP_W_TYPE_SIZE		32
+#define _FP_W_TYPE		unsigned long
+#define _FP_WS_TYPE		signed long
+#define _FP_I_TYPE		long
+
+/* The type of the result of a floating point comparison.  This must
+   match `__libgcc_cmp_return__' in GCC for the target.  */
+typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__)));
+#define CMPtype __gcc_CMPtype
+
+#define _FP_MUL_MEAT_S(R,X,Y)				\
+  _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
+#define _FP_MUL_MEAT_D(R,X,Y)				\
+  _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
+#define _FP_MUL_MEAT_Q(R,X,Y)				\
+  _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
+
+#define _FP_DIV_MEAT_S(R,X,Y)	_FP_DIV_MEAT_1_loop(S,R,X,Y)
+#define _FP_DIV_MEAT_D(R,X,Y)	_FP_DIV_MEAT_2_udiv(D,R,X,Y)
+#define _FP_DIV_MEAT_Q(R,X,Y)	_FP_DIV_MEAT_4_udiv(Q,R,X,Y)
+
+#define _FP_NANFRAC_S		((_FP_QNANBIT_S << 1) - 1)
+#define _FP_NANFRAC_D		((_FP_QNANBIT_D << 1) - 1), -1
+#define _FP_NANFRAC_Q		((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1
+#define _FP_NANSIGN_S		0
+#define _FP_NANSIGN_D		0
+#define _FP_NANSIGN_Q		0
+
+#define _FP_KEEPNANFRACP 1
+#define _FP_QNANNEGATEDP 0
+
+/* Someone please check this.  */
+#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP)			\
+  do {								\
+    if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs)		\
+	&& !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs))	\
+      {								\
+	R##_s = Y##_s;						\
+	_FP_FRAC_COPY_##wc(R,Y);				\
+      }								\
+    else							\
+      {								\
+	R##_s = X##_s;						\
+	_FP_FRAC_COPY_##wc(R,X);				\
+      }								\
+    R##_c = FP_CLS_NAN;						\
+  } while (0)
+
+#define	__LITTLE_ENDIAN	1234
+#define	__BIG_ENDIAN	4321
+
+#if defined __big_endian__
+# define __BYTE_ORDER __BIG_ENDIAN
+#else
+# define __BYTE_ORDER __LITTLE_ENDIAN
+#endif
+
+/* Define ALIASNAME as a strong alias for NAME.  */
+# define strong_alias(name, aliasname) _strong_alias(name, aliasname)
+# define _strong_alias(name, aliasname) \
+  extern __typeof (name) aliasname __attribute__ ((alias (#name)));
diff --git a/libgcc/config/nds32/t-nds32 b/libgcc/config/nds32/t-nds32
new file mode 100644
index 00000000000..25c184aa2a9
--- /dev/null
+++ b/libgcc/config/nds32/t-nds32
@@ -0,0 +1,58 @@
+# Rules of libgcc and crtstuff of Andes NDS32 cpu for GNU compiler
+# Copyright (C) 2012-2013 Free Software Foundation, Inc.
+# Contributed by Andes Technology Corporation.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published
+# by the Free Software Foundation; either version 3, or (at your
+# option) any later version.
+#
+# GCC is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+# or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+# License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+
+# Note:
+#   Because GCC has its own make rules for crtbegin.o and crtend.o,
+#   we cannot use crtbegin.o and crtend.o rules.
+#   So we create crtbegin1.o and crtend1.o instead.
+#   Make sure the linker script include these two objects
+#   for building .ctors/.dtors sections.
+
+# Use -DCRT_BEGIN to create beginning parts of .init and .fini content
+# Make sure you are building crtbegin1.o with -O0 optimization,
+# otherwise the static function will be optimized out
+crtbegin1.o: $(srcdir)/config/nds32/initfini.c $(GCC_PASSES) $(CONFIG_H)
+	$(GCC_FOR_TARGET) $(INCLUDES) \
+	$(CFLAGS) \
+	-DCRT_BEGIN \
+	-finhibit-size-directive -fno-inline-functions \
+	-O0 -c $(srcdir)/config/nds32/initfini.c -o crtbegin1.o
+
+# Use -DCRT_END to create ending parts of .init and .fini content
+# Make sure you are building crtend1.o with -O0 optimization,
+# otherwise the static function will be optimized out
+crtend1.o: $(srcdir)/config/nds32/initfini.c $(GCC_PASSES) $(CONFIG_H)
+	$(GCC_FOR_TARGET) $(INCLUDES) \
+	$(CFLAGS) \
+	-DCRT_END \
+	-finhibit-size-directive -fno-inline-functions \
+	-O0 -c $(srcdir)/config/nds32/initfini.c -o crtend1.o
+
+# Use this rule if and only if your crt0.o does not come from library
+# Also, be sure to add 'crtzero.o' in extra_parts in libgcc/config.host
+# and change STARTFILE_SPEC in nds32.h
+#
+#crtzero.o: $(srcdir)/config/nds32/crtzero.S $(GCC_PASSES) $(CONFIG_H)
+#	$(GCC_FOR_TARGET) $(INCLUDES) \
+#	-c $(srcdir)/config/nds32/crtzero.S -o crtzero.o
+
+
+# ------------------------------------------------------------------------
diff --git a/libgcc/config/nds32/t-nds32-isr b/libgcc/config/nds32/t-nds32-isr
new file mode 100644
index 00000000000..24f798c3a56
--- /dev/null
+++ b/libgcc/config/nds32/t-nds32-isr
@@ -0,0 +1,212 @@
+# Rules of c-isr library stuff of Andes NDS32 cpu for GNU compiler
+# Copyright (C) 2012-2013 Free Software Foundation, Inc.
+# Contributed by Andes Technology Corporation.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published
+# by the Free Software Foundation; either version 3, or (at your
+# option) any later version.
+#
+# GCC is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+# or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+# License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+
+###############################################################################
+# Makfile fragment rules for libnds32_isr.a to support ISR attribute extension
+###############################################################################
+
+# basic flags setting
+ISR_CFLAGS = $(CFLAGS) -c
+
+# the object files we would like to create
+LIBNDS32_ISR_16B_OBJS = \
+		vec_vid00.o vec_vid01.o vec_vid02.o vec_vid03.o \
+		vec_vid04.o vec_vid05.o vec_vid06.o vec_vid07.o \
+		vec_vid08.o vec_vid09.o vec_vid10.o vec_vid11.o \
+		vec_vid12.o vec_vid13.o vec_vid14.o vec_vid15.o \
+		vec_vid16.o vec_vid17.o vec_vid18.o vec_vid19.o \
+		vec_vid20.o vec_vid21.o vec_vid22.o vec_vid23.o \
+		vec_vid24.o vec_vid25.o vec_vid26.o vec_vid27.o \
+		vec_vid28.o vec_vid29.o vec_vid30.o vec_vid31.o \
+		vec_vid32.o vec_vid33.o vec_vid34.o vec_vid35.o \
+		vec_vid36.o vec_vid37.o vec_vid38.o vec_vid39.o \
+		vec_vid40.o vec_vid41.o vec_vid42.o vec_vid43.o \
+		vec_vid44.o vec_vid45.o vec_vid46.o vec_vid47.o \
+		vec_vid48.o vec_vid49.o vec_vid50.o vec_vid51.o \
+		vec_vid52.o vec_vid53.o vec_vid54.o vec_vid55.o \
+		vec_vid56.o vec_vid57.o vec_vid58.o vec_vid59.o \
+		vec_vid60.o vec_vid61.o vec_vid62.o vec_vid63.o \
+		vec_vid64.o vec_vid65.o vec_vid66.o vec_vid67.o \
+		vec_vid68.o vec_vid69.o vec_vid70.o vec_vid71.o \
+		vec_vid72.o \
+		excp_isr_ps_nn.o excp_isr_ps_ns.o excp_isr_ps_nr.o \
+		excp_isr_sa_nn.o excp_isr_sa_ns.o excp_isr_sa_nr.o \
+		intr_isr_ps_nn.o intr_isr_ps_ns.o intr_isr_ps_nr.o \
+		intr_isr_sa_nn.o intr_isr_sa_ns.o intr_isr_sa_nr.o \
+		reset.o
+
+LIBNDS32_ISR_4B_OBJS = \
+		vec_vid00_4b.o vec_vid01_4b.o vec_vid02_4b.o vec_vid03_4b.o \
+		vec_vid04_4b.o vec_vid05_4b.o vec_vid06_4b.o vec_vid07_4b.o \
+		vec_vid08_4b.o vec_vid09_4b.o vec_vid10_4b.o vec_vid11_4b.o \
+		vec_vid12_4b.o vec_vid13_4b.o vec_vid14_4b.o vec_vid15_4b.o \
+		vec_vid16_4b.o vec_vid17_4b.o vec_vid18_4b.o vec_vid19_4b.o \
+		vec_vid20_4b.o vec_vid21_4b.o vec_vid22_4b.o vec_vid23_4b.o \
+		vec_vid24_4b.o vec_vid25_4b.o vec_vid26_4b.o vec_vid27_4b.o \
+		vec_vid28_4b.o vec_vid29_4b.o vec_vid30_4b.o vec_vid31_4b.o \
+		vec_vid32_4b.o vec_vid33_4b.o vec_vid34_4b.o vec_vid35_4b.o \
+		vec_vid36_4b.o vec_vid37_4b.o vec_vid38_4b.o vec_vid39_4b.o \
+		vec_vid40_4b.o vec_vid41_4b.o vec_vid42_4b.o vec_vid43_4b.o \
+		vec_vid44_4b.o vec_vid45_4b.o vec_vid46_4b.o vec_vid47_4b.o \
+		vec_vid48_4b.o vec_vid49_4b.o vec_vid50_4b.o vec_vid51_4b.o \
+		vec_vid52_4b.o vec_vid53_4b.o vec_vid54_4b.o vec_vid55_4b.o \
+		vec_vid56_4b.o vec_vid57_4b.o vec_vid58_4b.o vec_vid59_4b.o \
+		vec_vid60_4b.o vec_vid61_4b.o vec_vid62_4b.o vec_vid63_4b.o \
+		vec_vid64_4b.o vec_vid65_4b.o vec_vid66_4b.o vec_vid67_4b.o \
+		vec_vid68_4b.o vec_vid69_4b.o vec_vid70_4b.o vec_vid71_4b.o \
+		vec_vid72_4b.o \
+		excp_isr_ps_nn_4b.o excp_isr_ps_ns_4b.o excp_isr_ps_nr_4b.o \
+		excp_isr_sa_nn_4b.o excp_isr_sa_ns_4b.o excp_isr_sa_nr_4b.o \
+		intr_isr_ps_nn_4b.o intr_isr_ps_ns_4b.o intr_isr_ps_nr_4b.o \
+		intr_isr_sa_nn_4b.o intr_isr_sa_ns_4b.o intr_isr_sa_nr_4b.o \
+		reset_4b.o
+
+LIBNDS32_ISR_COMMON_OBJS = \
+		jmptbl_vid00.o jmptbl_vid01.o jmptbl_vid02.o jmptbl_vid03.o \
+		jmptbl_vid04.o jmptbl_vid05.o jmptbl_vid06.o jmptbl_vid07.o \
+		jmptbl_vid08.o jmptbl_vid09.o jmptbl_vid10.o jmptbl_vid11.o \
+		jmptbl_vid12.o jmptbl_vid13.o jmptbl_vid14.o jmptbl_vid15.o \
+		jmptbl_vid16.o jmptbl_vid17.o jmptbl_vid18.o jmptbl_vid19.o \
+		jmptbl_vid20.o jmptbl_vid21.o jmptbl_vid22.o jmptbl_vid23.o \
+		jmptbl_vid24.o jmptbl_vid25.o jmptbl_vid26.o jmptbl_vid27.o \
+		jmptbl_vid28.o jmptbl_vid29.o jmptbl_vid30.o jmptbl_vid31.o \
+		jmptbl_vid32.o jmptbl_vid33.o jmptbl_vid34.o jmptbl_vid35.o \
+		jmptbl_vid36.o jmptbl_vid37.o jmptbl_vid38.o jmptbl_vid39.o \
+		jmptbl_vid40.o jmptbl_vid41.o jmptbl_vid42.o jmptbl_vid43.o \
+		jmptbl_vid44.o jmptbl_vid45.o jmptbl_vid46.o jmptbl_vid47.o \
+		jmptbl_vid48.o jmptbl_vid49.o jmptbl_vid50.o jmptbl_vid51.o \
+		jmptbl_vid52.o jmptbl_vid53.o jmptbl_vid54.o jmptbl_vid55.o \
+		jmptbl_vid56.o jmptbl_vid57.o jmptbl_vid58.o jmptbl_vid59.o \
+		jmptbl_vid60.o jmptbl_vid61.o jmptbl_vid62.o jmptbl_vid63.o \
+		jmptbl_vid64.o jmptbl_vid65.o jmptbl_vid66.o jmptbl_vid67.o \
+		jmptbl_vid68.o jmptbl_vid69.o jmptbl_vid70.o jmptbl_vid71.o \
+		jmptbl_vid72.o \
+		nmih.o \
+		wrh.o
+
+LIBNDS32_ISR_COMPLETE_OBJS = $(LIBNDS32_ISR_16B_OBJS) $(LIBNDS32_ISR_4B_OBJS) $(LIBNDS32_ISR_COMMON_OBJS)
+
+
+# Build common objects for ISR library
+nmih.o: $(srcdir)/config/nds32/isr-library/nmih.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/nmih.S -o nmih.o
+
+wrh.o: $(srcdir)/config/nds32/isr-library/wrh.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/wrh.S -o wrh.o
+
+jmptbl_vid%.o: $(srcdir)/config/nds32/isr-library/jmptbl_vid%.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@
+
+
+
+# Build 16b version objects for ISR library. (no "_4b" postfix string)
+vec_vid%.o: $(srcdir)/config/nds32/isr-library/vec_vid%.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@
+
+excp_isr_ps_nn.o: $(srcdir)/config/nds32/isr-library/excp_isr.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/excp_isr.S -o excp_isr_ps_nn.o
+
+excp_isr_ps_ns.o: $(srcdir)/config/nds32/isr-library/excp_isr.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/excp_isr.S -o excp_isr_ps_ns.o
+
+excp_isr_ps_nr.o: $(srcdir)/config/nds32/isr-library/excp_isr.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/excp_isr.S -o excp_isr_ps_nr.o
+
+excp_isr_sa_nn.o: $(srcdir)/config/nds32/isr-library/excp_isr.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS $(srcdir)/config/nds32/isr-library/excp_isr.S -o excp_isr_sa_nn.o
+
+excp_isr_sa_ns.o: $(srcdir)/config/nds32/isr-library/excp_isr.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/excp_isr.S -o excp_isr_sa_ns.o
+
+excp_isr_sa_nr.o: $(srcdir)/config/nds32/isr-library/excp_isr.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/excp_isr.S -o excp_isr_sa_nr.o
+
+intr_isr_ps_nn.o: $(srcdir)/config/nds32/isr-library/intr_isr.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/intr_isr.S -o intr_isr_ps_nn.o
+
+intr_isr_ps_ns.o: $(srcdir)/config/nds32/isr-library/intr_isr.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/intr_isr.S -o intr_isr_ps_ns.o
+
+intr_isr_ps_nr.o: $(srcdir)/config/nds32/isr-library/intr_isr.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/intr_isr.S -o intr_isr_ps_nr.o
+
+intr_isr_sa_nn.o: $(srcdir)/config/nds32/isr-library/intr_isr.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS $(srcdir)/config/nds32/isr-library/intr_isr.S -o intr_isr_sa_nn.o
+
+intr_isr_sa_ns.o: $(srcdir)/config/nds32/isr-library/intr_isr.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/intr_isr.S -o intr_isr_sa_ns.o
+
+intr_isr_sa_nr.o: $(srcdir)/config/nds32/isr-library/intr_isr.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/intr_isr.S -o intr_isr_sa_nr.o
+
+reset.o: $(srcdir)/config/nds32/isr-library/reset.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/reset.S -o reset.o
+
+# Build 4b version objects for ISR library.
+vec_vid%_4b.o: $(srcdir)/config/nds32/isr-library/vec_vid%_4b.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@
+
+excp_isr_ps_nn_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_ps_nn_4b.o
+
+excp_isr_ps_ns_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_ps_ns_4b.o
+
+excp_isr_ps_nr_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_ps_nr_4b.o
+
+excp_isr_sa_nn_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_sa_nn_4b.o
+
+excp_isr_sa_ns_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_sa_ns_4b.o
+
+excp_isr_sa_nr_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_sa_nr_4b.o
+
+intr_isr_ps_nn_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_ps_nn_4b.o
+
+intr_isr_ps_ns_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_ps_ns_4b.o
+
+intr_isr_ps_nr_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_ps_nr_4b.o
+
+intr_isr_sa_nn_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_sa_nn_4b.o
+
+intr_isr_sa_ns_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_sa_ns_4b.o
+
+intr_isr_sa_nr_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_sa_nr_4b.o
+
+reset_4b.o: $(srcdir)/config/nds32/isr-library/reset_4b.S
+	$(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/reset_4b.S -o reset_4b.o
+
+
+# The rule to create libnds32_isr.a file
+libnds32_isr.a: $(LIBNDS32_ISR_COMPLETE_OBJS)
+	$(AR) rc libnds32_isr.a $(LIBNDS32_ISR_COMPLETE_OBJS)
+
+
+# ------------------------------------------------------------------------
diff --git a/libgcc/config/nds32/t-nds32-mculib b/libgcc/config/nds32/t-nds32-mculib
new file mode 100644
index 00000000000..4fbcf4ff52e
--- /dev/null
+++ b/libgcc/config/nds32/t-nds32-mculib
@@ -0,0 +1,77 @@
+# Rules of mculib library makefile of Andes NDS32 cpu for GNU compiler
+# Copyright (C) 2012-2013 Free Software Foundation, Inc.
+# Contributed by Andes Technology Corporation.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published
+# by the Free Software Foundation; either version 3, or (at your
+# option) any later version.
+#
+# GCC is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+# or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+# License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# Compiler flags to use when compiling 'libgcc2.c'
+HOST_LIBGCC2_CFLAGS = -Os
+
+
+LIB1ASMSRC   = nds32/lib1asmsrc-mculib.S
+
+LIB1ASMFUNCS =   \
+	_addsub_sf   \
+	_sf_to_si    \
+	_divsi3      \
+	_divdi3      \
+	_modsi3      \
+	_moddi3      \
+	_mulsi3      \
+	_udivsi3     \
+	_udivdi3     \
+	_udivmoddi4  \
+	_umodsi3     \
+	_umoddi3     \
+	_muldi3      \
+	_addsub_df   \
+	_mul_sf      \
+	_mul_df      \
+	_div_sf      \
+	_div_df      \
+	_negate_sf   \
+	_negate_df   \
+	_sf_to_df    \
+	_df_to_sf    \
+	_df_to_si    \
+	_fixsfdi     \
+	_fixdfdi     \
+	_fixunssfsi  \
+	_fixunsdfsi  \
+	_fixunssfdi  \
+	_fixunsdfdi  \
+	_si_to_sf    \
+	_si_to_df    \
+	_floatdisf   \
+	_floatdidf   \
+	_floatunsisf \
+	_floatunsidf \
+	_floatundisf \
+	_floatundidf \
+	_compare_sf  \
+	_compare_df  \
+	_unord_sf    \
+	_unord_df
+
+# List of functions not to build from libgcc2.c.
+LIB2FUNCS_EXCLUDE = _clzsi2 _clzdi2
+
+# List of extra C and assembler files(*.S) to add to static libgcc2.
+LIB2ADD_ST += $(srcdir)/config/nds32/lib2csrc-mculib/_clzsi2.c
+LIB2ADD_ST += $(srcdir)/config/nds32/lib2csrc-mculib/_clzdi2.c
+
+# ------------------------------------------------------------------------
diff --git a/libgcc/config/nds32/t-nds32-newlib b/libgcc/config/nds32/t-nds32-newlib
new file mode 100644
index 00000000000..b2549a084e9
--- /dev/null
+++ b/libgcc/config/nds32/t-nds32-newlib
@@ -0,0 +1,34 @@
+# Rules of newlib library makefile of Andes NDS32 cpu for GNU compiler
+# Copyright (C) 2012-2013 Free Software Foundation, Inc.
+# Contributed by Andes Technology Corporation.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published
+# by the Free Software Foundation; either version 3, or (at your
+# option) any later version.
+#
+# GCC is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+# or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+# License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# Compiler flags to use when compiling 'libgcc2.c'
+HOST_LIBGCC2_CFLAGS = -O2
+
+
+#LIB1ASMSRC   = nds32/lib1asmsrc-newlib.S
+#LIB1ASMFUNCS = _divsi3 _modsi3 _udivsi3 _umodsi3
+
+# List of functions not to build from libgcc2.c.
+#LIB2FUNCS_EXCLUDE = _clzsi2
+
+# List of extra C and assembler files(*.S) to add to static libgcc2.
+#LIB2ADD_ST += $(srcdir)/config/nds32/lib2csrc-newlib/_clzsi2.c
+
+# ------------------------------------------------------------------------