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| author | Roger Sayle <roger@nextmovesoftware.com> | 2020-08-16 19:20:27 +0100 |
|---|---|---|
| committer | Giuliano Belinassi <giuliano.belinassi@usp.br> | 2020-08-17 15:08:16 -0300 |
| commit | 114c0f9c0a364641bcdc608879236c418ae9837d (patch) | |
| tree | 19e5135313e10f3b513a6ef4d944ecb9346e4199 | |
| parent | 1603043d391f82fe92c65fe76232f64cb4dc5d84 (diff) | |
| download | gcc-114c0f9c0a364641bcdc608879236c418ae9837d.tar.gz | |
middle-end: Simplify (sign_extend:HI (truncate:QI (ashiftrt:HI X 8)))
The combination of several my recent nvptx patches has revealed an
interesting RTL optimization opportunity. This patch to simplify-rtx.c
simplifies (sign_extend:HI (truncate:QI (?shiftrt:HI x 8))) to just
(ashiftrt:HI x 8), as the inner shift already sets the high bits
appropriately. The equivalent zero_extend variant appears to already
be implemented in simplify_unary_operation_1.
These result from RTL expansion generating a reasonable arithmetic right
shift and truncation to char, only to then discover the backend doesn't
support QImode comparisons, so the next optab widens this result/operand
back to HImode. In this sequence the truncate and sign extend are
redundant as the original arithmetic shift has already set the high
bits appropriately. The one oddity of the patch is that it tests for
LSHIFTRT as inner shift, as simplify/combine has already canonicalized
this to a logical shift, assuming that the distinction is unimportant
following the truncatation.
2020-08-16 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
* simplify-rtx.c (simplify_unary_operation_1) [SIGN_EXTEND]:
Simplify (sign_extend:M (truncate:N (lshiftrt:M x C))) to
(ashiftrt:M x C) when the shift sets the high bits appropriately.
| -rw-r--r-- | gcc/simplify-rtx.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c index 4f0652f553e..869f0d11b2e 100644 --- a/gcc/simplify-rtx.c +++ b/gcc/simplify-rtx.c @@ -1527,6 +1527,38 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op) && XEXP (op, 1) != const0_rtx) return simplify_gen_unary (ZERO_EXTEND, mode, op, GET_MODE (op)); + /* (sign_extend:M (truncate:N (lshiftrt:O <X> (const_int I)))) where + I is GET_MODE_PRECISION(O) - GET_MODE_PRECISION(N), simplifies to + (ashiftrt:M <X> (const_int I)) if modes M and O are the same, and + (truncate:M (ashiftrt:O <X> (const_int I))) if M is narrower than + O, and (sign_extend:M (ashiftrt:O <X> (const_int I))) if M is + wider than O. */ + if (GET_CODE (op) == TRUNCATE + && GET_CODE (XEXP (op, 0)) == LSHIFTRT + && CONST_INT_P (XEXP (XEXP (op, 0), 1))) + { + scalar_int_mode m_mode, n_mode, o_mode; + rtx old_shift = XEXP (op, 0); + if (is_a <scalar_int_mode> (mode, &m_mode) + && is_a <scalar_int_mode> (GET_MODE (op), &n_mode) + && is_a <scalar_int_mode> (GET_MODE (old_shift), &o_mode) + && GET_MODE_PRECISION (o_mode) - GET_MODE_PRECISION (n_mode) + == INTVAL (XEXP (old_shift, 1))) + { + rtx new_shift = simplify_gen_binary (ASHIFTRT, + GET_MODE (old_shift), + XEXP (old_shift, 0), + XEXP (old_shift, 1)); + if (GET_MODE_PRECISION (m_mode) > GET_MODE_PRECISION (o_mode)) + return simplify_gen_unary (SIGN_EXTEND, mode, new_shift, + GET_MODE (new_shift)); + if (mode != GET_MODE (new_shift)) + return simplify_gen_unary (TRUNCATE, mode, new_shift, + GET_MODE (new_shift)); + return new_shift; + } + } + #if defined(POINTERS_EXTEND_UNSIGNED) /* As we do not know which address space the pointer is referring to, we can do this only if the target does not support different pointer |