Improve code generation for edge and pixel-compare, specifically avoid

sign and zero extensions on 64-bit and allow such instructions to be
placed in delay slots.

gcc/

	* config/sparc/sparc.md (edge{8,16,32}{,l}): Return Pmode.
	(fcmp{le,ne,gt,eq}{16,32}): Likewise.
	* config/sparc/visintrin.h: Update edge and pixel-compare
	intrinsics to return 'long' instead of 'int'.
	* doc/extend.texi: Update documentation to match.
	* config/sparc/sparc.c (eligible_for_return_delay): When leaf or
	flat, allow any instruction.  Otherwise, when V9 allow parallels
	which consist only of sets to registers outside of %o0 to %o5.
	(sparc_vis_init_builtins): Update VIS builtin types for edge
	and pixel-compare.

gcc/testsuite/

	* gcc.target/sparc/edge.c: Update for new return types.
	* gcc.target/sparc/fcmp.c: Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@179227 138bc75d-0d04-0410-961f-82ee72b054a4

8 files changed, 185 insertions, 112 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 53afbd97fc7..ecdb26beb35 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,16 @@
 2011-09-26  David S. Miller  <davem@davemloft.net>
 
+	* config/sparc/sparc.md (edge{8,16,32}{,l}): Return Pmode.
+	(fcmp{le,ne,gt,eq}{16,32}): Likewise.
+	* config/sparc/visintrin.h: Update edge and pixel-compare
+	intrinsics to return 'long' instead of 'int'.
+	* doc/extend.texi: Update documentation to match.
+	* config/sparc/sparc.c (eligible_for_return_delay): When leaf or
+	flat, allow any instruction.  Otherwise, when V9 allow parallels
+	which consist only of sets to registers outside of %o0 to %o5.
+	(sparc_vis_init_builtins): Update VIS builtin types for edge
+	and pixel-compare.
+
 	* config/sparc/sparc.c (sparc_conditional_register_usage): When VIS
 	is enabled, mark %gsr as global.
 	* config/sparc/sparc.md (UNSPEC_WRGSR): Delete.
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index a395321dd3e..d1d83556495 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -2857,9 +2857,10 @@ eligible_for_restore_insn (rtx trial, bool return_p)
 int
 eligible_for_return_delay (rtx trial)
 {
+  int regno;
   rtx pat;
 
-  if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
+  if (GET_CODE (trial) != INSN)
     return 0;
 
   if (get_attr_length (trial) != 1)
@@ -2876,17 +2877,45 @@ eligible_for_return_delay (rtx trial)
       get_attr_in_uncond_branch_delay (trial) == IN_UNCOND_BRANCH_DELAY_TRUE;
 
   pat = PATTERN (trial);
+  if (GET_CODE (pat) == PARALLEL)
+    {
+      int i;
+
+      if (! TARGET_V9)
+	return 0;
+      for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
+	{
+	  rtx expr = XVECEXP (pat, 0, i);
+	  if (GET_CODE (expr) != SET)
+	    return 0;
+	  if (GET_CODE (SET_DEST (expr)) != REG)
+	    return 0;
+	  regno = REGNO (SET_DEST (expr));
+	  if (regno >= 8 && regno < 24)
+	    return 0;
+	}
+      return !epilogue_renumber (&pat, 1)
+	&& (get_attr_in_uncond_branch_delay (trial)
+	    == IN_UNCOND_BRANCH_DELAY_TRUE);
+    }
+
+  if (GET_CODE (pat) != SET)
+    return 0;
+
+  if (GET_CODE (SET_DEST (pat)) != REG)
+    return 0;
+
+  regno = REGNO (SET_DEST (pat));
 
   /* Otherwise, only operations which can be done in tandem with
      a `restore' or `return' insn can go into the delay slot.  */
-  if (GET_CODE (SET_DEST (pat)) != REG
-      || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24))
+  if (regno >= 8 && regno < 24)
     return 0;
 
   /* If this instruction sets up floating point register and we have a return
      instruction, it can probably go in.  But restore will not work
      with FP_REGS.  */
-  if (REGNO (SET_DEST (pat)) >= 32)
+  if (regno >= 32)
     return (TARGET_V9
 	    && !epilogue_renumber (&pat, 1)
 	    && get_attr_in_uncond_branch_delay (trial)
@@ -9172,10 +9201,17 @@ sparc_vis_init_builtins (void)
   tree si_ftype_ptr_ptr = build_function_type_list (intSI_type_node,
 		        			    ptr_type_node,
 					            ptr_type_node, 0);
+  tree di_ftype_ptr_ptr = build_function_type_list (intDI_type_node,
+		        			    ptr_type_node,
+					            ptr_type_node, 0);
   tree si_ftype_v4hi_v4hi = build_function_type_list (intSI_type_node,
 						      v4hi, v4hi, 0);
   tree si_ftype_v2si_v2si = build_function_type_list (intSI_type_node,
 						      v2si, v2si, 0);
+  tree di_ftype_v4hi_v4hi = build_function_type_list (intDI_type_node,
+						      v4hi, v4hi, 0);
+  tree di_ftype_v2si_v2si = build_function_type_list (intDI_type_node,
+						      v2si, v2si, 0);
   tree void_ftype_di = build_function_type_list (void_type_node,
 						 intDI_type_node, 0);
   tree di_ftype_void = build_function_type_list (intDI_type_node,
@@ -9247,17 +9283,17 @@ sparc_vis_init_builtins (void)
   if (TARGET_ARCH64)
     {
       def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8di_vis,
-			 si_ftype_ptr_ptr);
+			 di_ftype_ptr_ptr);
       def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8ldi_vis,
-			 si_ftype_ptr_ptr);
+			 di_ftype_ptr_ptr);
       def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16di_vis,
-			 si_ftype_ptr_ptr);
+			 di_ftype_ptr_ptr);
       def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16ldi_vis,
-			 si_ftype_ptr_ptr);
+			 di_ftype_ptr_ptr);
       def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32di_vis,
-			 si_ftype_ptr_ptr);
+			 di_ftype_ptr_ptr);
       def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32ldi_vis,
-			 si_ftype_ptr_ptr);
+			 di_ftype_ptr_ptr);
     }
   else
     {
@@ -9275,22 +9311,45 @@ sparc_vis_init_builtins (void)
 			 si_ftype_ptr_ptr);
     }
 
-  def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16_vis,
-		     si_ftype_v4hi_v4hi);
-  def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32_vis,
-		     si_ftype_v2si_v2si);
-  def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16_vis,
-		     si_ftype_v4hi_v4hi);
-  def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32_vis,
-		     si_ftype_v2si_v2si);
-  def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16_vis,
-		     si_ftype_v4hi_v4hi);
-  def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32_vis,
-		     si_ftype_v2si_v2si);
-  def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16_vis,
-		     si_ftype_v4hi_v4hi);
-  def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32_vis,
-		     si_ftype_v2si_v2si);
+  /* Pixel compare.  */
+  if (TARGET_ARCH64)
+    {
+      def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16di_vis,
+			 di_ftype_v4hi_v4hi);
+      def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32di_vis,
+			 di_ftype_v2si_v2si);
+      def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16di_vis,
+			 di_ftype_v4hi_v4hi);
+      def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32di_vis,
+			 di_ftype_v2si_v2si);
+      def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16di_vis,
+			 di_ftype_v4hi_v4hi);
+      def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32di_vis,
+			 di_ftype_v2si_v2si);
+      def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16di_vis,
+			 di_ftype_v4hi_v4hi);
+      def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32di_vis,
+			 di_ftype_v2si_v2si);
+    }
+  else
+    {
+      def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16si_vis,
+			 si_ftype_v4hi_v4hi);
+      def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32si_vis,
+			 si_ftype_v2si_v2si);
+      def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16si_vis,
+			 si_ftype_v4hi_v4hi);
+      def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32si_vis,
+			 si_ftype_v2si_v2si);
+      def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16si_vis,
+			 si_ftype_v4hi_v4hi);
+      def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32si_vis,
+			 si_ftype_v2si_v2si);
+      def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16si_vis,
+			 si_ftype_v4hi_v4hi);
+      def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32si_vis,
+			 si_ftype_v2si_v2si);
+    }
 }
 
 /* Handle TARGET_EXPAND_BUILTIN target hook.
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index e79e842eade..6e38298e5a3 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -8088,8 +8088,8 @@
         (compare:CC_NOOV (minus:P (match_operand:P 1 "register_operand" "rJ")
 			  	  (match_operand:P 2 "register_operand" "rJ"))
 			 (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-        (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_EDGE8))]
+   (set (match_operand:P 0 "register_operand" "=r")
+        (unspec:P [(match_dup 1) (match_dup 2)] UNSPEC_EDGE8))]
   "TARGET_VIS"
   "edge8\t%r1, %r2, %0"
   [(set_attr "type" "edge")])
@@ -8099,8 +8099,8 @@
         (compare:CC_NOOV (minus:P (match_operand:P 1 "register_operand" "rJ")
 			  	  (match_operand:P 2 "register_operand" "rJ"))
 			 (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-        (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_EDGE8L))]
+   (set (match_operand:P 0 "register_operand" "=r")
+        (unspec:P [(match_dup 1) (match_dup 2)] UNSPEC_EDGE8L))]
   "TARGET_VIS"
   "edge8l\t%r1, %r2, %0"
   [(set_attr "type" "edge")])
@@ -8110,8 +8110,8 @@
         (compare:CC_NOOV (minus:P (match_operand:P 1 "register_operand" "rJ")
 			  	  (match_operand:P 2 "register_operand" "rJ"))
 			 (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-        (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_EDGE16))]
+   (set (match_operand:P 0 "register_operand" "=r")
+        (unspec:P [(match_dup 1) (match_dup 2)] UNSPEC_EDGE16))]
   "TARGET_VIS"
   "edge16\t%r1, %r2, %0"
   [(set_attr "type" "edge")])
@@ -8121,8 +8121,8 @@
         (compare:CC_NOOV (minus:P (match_operand:P 1 "register_operand" "rJ")
 			  	  (match_operand:P 2 "register_operand" "rJ"))
 			 (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-        (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_EDGE16L))]
+   (set (match_operand:P 0 "register_operand" "=r")
+        (unspec:P [(match_dup 1) (match_dup 2)] UNSPEC_EDGE16L))]
   "TARGET_VIS"
   "edge16l\t%r1, %r2, %0"
   [(set_attr "type" "edge")])
@@ -8132,8 +8132,8 @@
         (compare:CC_NOOV (minus:P (match_operand:P 1 "register_operand" "rJ")
 			  	  (match_operand:P 2 "register_operand" "rJ"))
 			 (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-        (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_EDGE32))]
+   (set (match_operand:P 0 "register_operand" "=r")
+        (unspec:P [(match_dup 1) (match_dup 2)] UNSPEC_EDGE32))]
   "TARGET_VIS"
   "edge32\t%r1, %r2, %0"
   [(set_attr "type" "edge")])
@@ -8143,85 +8143,85 @@
         (compare:CC_NOOV (minus:P (match_operand:P 1 "register_operand" "rJ")
 			  	  (match_operand:P 2 "register_operand" "rJ"))
 			 (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-        (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_EDGE32L))]
+   (set (match_operand:P 0 "register_operand" "=r")
+        (unspec:P [(match_dup 1) (match_dup 2)] UNSPEC_EDGE32L))]
   "TARGET_VIS"
   "edge32l\t%r1, %r2, %0"
   [(set_attr "type" "edge")])
 
-(define_insn "fcmple16_vis"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-  	(unspec:SI [(match_operand:V4HI 1 "register_operand" "e")
-		    (match_operand:V4HI 2 "register_operand" "e")]
+(define_insn "fcmple16<P:mode>_vis"
+  [(set (match_operand:P 0 "register_operand" "=r")
+  	(unspec:P [(match_operand:V4HI 1 "register_operand" "e")
+		   (match_operand:V4HI 2 "register_operand" "e")]
 	 UNSPEC_FCMPLE))]
   "TARGET_VIS"
   "fcmple16\t%1, %2, %0"
   [(set_attr "type" "fpmul")
    (set_attr "fptype" "double")])
 
-(define_insn "fcmple32_vis"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-  	(unspec:SI [(match_operand:V2SI 1 "register_operand" "e")
-		    (match_operand:V2SI 2 "register_operand" "e")]
+(define_insn "fcmple32<P:mode>_vis"
+  [(set (match_operand:P 0 "register_operand" "=r")
+  	(unspec:P [(match_operand:V2SI 1 "register_operand" "e")
+		   (match_operand:V2SI 2 "register_operand" "e")]
 	 UNSPEC_FCMPLE))]
   "TARGET_VIS"
   "fcmple32\t%1, %2, %0"
   [(set_attr "type" "fpmul")
    (set_attr "fptype" "double")])
 
-(define_insn "fcmpne16_vis"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-  	(unspec:SI [(match_operand:V4HI 1 "register_operand" "e")
-		    (match_operand:V4HI 2 "register_operand" "e")]
+(define_insn "fcmpne16<P:mode>_vis"
+  [(set (match_operand:P 0 "register_operand" "=r")
+  	(unspec:P [(match_operand:V4HI 1 "register_operand" "e")
+		   (match_operand:V4HI 2 "register_operand" "e")]
 	 UNSPEC_FCMPNE))]
   "TARGET_VIS"
   "fcmpne16\t%1, %2, %0"
   [(set_attr "type" "fpmul")
    (set_attr "fptype" "double")])
 
-(define_insn "fcmpne32_vis"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-  	(unspec:SI [(match_operand:V2SI 1 "register_operand" "e")
-		    (match_operand:V2SI 2 "register_operand" "e")]
+(define_insn "fcmpne32<P:mode>_vis"
+  [(set (match_operand:P 0 "register_operand" "=r")
+  	(unspec:P [(match_operand:V2SI 1 "register_operand" "e")
+		   (match_operand:V2SI 2 "register_operand" "e")]
 	 UNSPEC_FCMPNE))]
   "TARGET_VIS"
   "fcmpne32\t%1, %2, %0"
   [(set_attr "type" "fpmul")
    (set_attr "fptype" "double")])
 
-(define_insn "fcmpgt16_vis"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-  	(unspec:SI [(match_operand:V4HI 1 "register_operand" "e")
-		    (match_operand:V4HI 2 "register_operand" "e")]
+(define_insn "fcmpgt16<P:mode>_vis"
+  [(set (match_operand:P 0 "register_operand" "=r")
+  	(unspec:P [(match_operand:V4HI 1 "register_operand" "e")
+		   (match_operand:V4HI 2 "register_operand" "e")]
 	 UNSPEC_FCMPGT))]
   "TARGET_VIS"
   "fcmpgt16\t%1, %2, %0"
   [(set_attr "type" "fpmul")
    (set_attr "fptype" "double")])
 
-(define_insn "fcmpgt32_vis"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-  	(unspec:SI [(match_operand:V2SI 1 "register_operand" "e")
-		    (match_operand:V2SI 2 "register_operand" "e")]
+(define_insn "fcmpgt32<P:mode>_vis"
+  [(set (match_operand:P 0 "register_operand" "=r")
+  	(unspec:P [(match_operand:V2SI 1 "register_operand" "e")
+		   (match_operand:V2SI 2 "register_operand" "e")]
 	 UNSPEC_FCMPGT))]
   "TARGET_VIS"
   "fcmpgt32\t%1, %2, %0"
   [(set_attr "type" "fpmul")
    (set_attr "fptype" "double")])
 
-(define_insn "fcmpeq16_vis"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-  	(unspec:SI [(match_operand:V4HI 1 "register_operand" "e")
-		    (match_operand:V4HI 2 "register_operand" "e")]
+(define_insn "fcmpeq16<P:mode>_vis"
+  [(set (match_operand:P 0 "register_operand" "=r")
+  	(unspec:P [(match_operand:V4HI 1 "register_operand" "e")
+		   (match_operand:V4HI 2 "register_operand" "e")]
 	 UNSPEC_FCMPEQ))]
   "TARGET_VIS"
   "fcmpeq16\t%1, %2, %0"
   [(set_attr "type" "fpmul")
    (set_attr "fptype" "double")])
 
-(define_insn "fcmpeq32_vis"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-  	(unspec:SI [(match_operand:V2SI 1 "register_operand" "e")
+(define_insn "fcmpeq32<P:mode>_vis"
+  [(set (match_operand:P 0 "register_operand" "=r")
+  	(unspec:P [(match_operand:V2SI 1 "register_operand" "e")
 		    (match_operand:V2SI 2 "register_operand" "e")]
 	 UNSPEC_FCMPEQ))]
   "TARGET_VIS"
diff --git a/gcc/config/sparc/visintrin.h b/gcc/config/sparc/visintrin.h
index e3a58180fe2..d37bd95188d 100644
--- a/gcc/config/sparc/visintrin.h
+++ b/gcc/config/sparc/visintrin.h
@@ -178,98 +178,98 @@ __vis_pdist (__v8qi __A, __v8qi __B, __i64 __C)
   return __builtin_vis_pdist (__A, __B, __C);
 }
 
-extern __inline int
+extern __inline long
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 __vis_edge8 (void *__A, void *__B)
 {
   return __builtin_vis_edge8 (__A, __B);
 }
 
-extern __inline int
+extern __inline long
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 __vis_edge8l (void *__A, void *__B)
 {
   return __builtin_vis_edge8l (__A, __B);
 }
 
-extern __inline int
+extern __inline long
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 __vis_edge16 (void *__A, void *__B)
 {
   return __builtin_vis_edge16 (__A, __B);
 }
 
-extern __inline int
+extern __inline long
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 __vis_edge16l (void *__A, void *__B)
 {
   return __builtin_vis_edge16l (__A, __B);
 }
 
-extern __inline int
+extern __inline long
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 __vis_edge32 (void *__A, void *__B)
 {
   return __builtin_vis_edge32 (__A, __B);
 }
 
-extern __inline int
+extern __inline long
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 __vis_edge32l (void *__A, void *__B)
 {
   return __builtin_vis_edge32l (__A, __B);
 }
 
-extern __inline int
+extern __inline long
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 __vis_fcmple16 (__v4hi __A, __v4hi __B)
 {
   return __builtin_vis_fcmple16 (__A, __B);
 }
 
-extern __inline int
+extern __inline long
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 __vis_fcmple32 (__v2si __A, __v2si __B)
 {
   return __builtin_vis_fcmple32 (__A, __B);
 }
 
-extern __inline int
+extern __inline long
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 __vis_fcmpne16 (__v4hi __A, __v4hi __B)
 {
   return __builtin_vis_fcmpne16 (__A, __B);
 }
 
-extern __inline int
+extern __inline long
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 __vis_fcmpne32 (__v2si __A, __v2si __B)
 {
   return __builtin_vis_fcmpne32 (__A, __B);
 }
 
-extern __inline int
+extern __inline long
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 __vis_fcmpgt16 (__v4hi __A, __v4hi __B)
 {
   return __builtin_vis_fcmpgt16 (__A, __B);
 }
 
-extern __inline int
+extern __inline long
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 __vis_fcmpgt32 (__v2si __A, __v2si __B)
 {
   return __builtin_vis_fcmpgt32 (__A, __B);
 }
 
-extern __inline int
+extern __inline long
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 __vis_fcmpeq16 (__v4hi __A, __v4hi __B)
 {
   return __builtin_vis_fcmpeq16 (__A, __B);
 }
 
-extern __inline int
+extern __inline long
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 __vis_fcmpeq32 (__v2si __A, __v2si __B)
 {
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index d5106aaeee8..e9d0bc7d8a3 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -12962,21 +12962,21 @@ v8qi __builtin_vis_fpmerge (v4qi, v4qi);
 
 int64_t __builtin_vis_pdist (v8qi, v8qi, int64_t);
 
-int __builtin_vis_edge8 (void *, void *);
-int __builtin_vis_edge8l (void *, void *);
-int __builtin_vis_edge16 (void *, void *);
-int __builtin_vis_edge16l (void *, void *);
-int __builtin_vis_edge32 (void *, void *);
-int __builtin_vis_edge32l (void *, void *);
-
-int __builtin_vis_fcmple16 (v4hi, v4hi);
-int __builtin_vis_fcmple32 (v2si, v2si);
-int __builtin_vis_fcmpne16 (v4hi, v4hi);
-int __builtin_vis_fcmpne32 (v2si, v2si);
-int __builtin_vis_fcmpgt16 (v4hi, v4hi);
-int __builtin_vis_fcmpgt32 (v2si, v2si);
-int __builtin_vis_fcmpeq16 (v4hi, v4hi);
-int __builtin_vis_fcmpeq32 (v2si, v2si);
+long __builtin_vis_edge8 (void *, void *);
+long __builtin_vis_edge8l (void *, void *);
+long __builtin_vis_edge16 (void *, void *);
+long __builtin_vis_edge16l (void *, void *);
+long __builtin_vis_edge32 (void *, void *);
+long __builtin_vis_edge32l (void *, void *);
+
+long __builtin_vis_fcmple16 (v4hi, v4hi);
+long __builtin_vis_fcmple32 (v2si, v2si);
+long __builtin_vis_fcmpne16 (v4hi, v4hi);
+long __builtin_vis_fcmpne32 (v2si, v2si);
+long __builtin_vis_fcmpgt16 (v4hi, v4hi);
+long __builtin_vis_fcmpgt32 (v2si, v2si);
+long __builtin_vis_fcmpeq16 (v4hi, v4hi);
+long __builtin_vis_fcmpeq32 (v2si, v2si);
 @end smallexample
 
 @node SPU Built-in Functions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 7832453f47d..ebc9385a111 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -11,6 +11,9 @@
 	* gcc.target/sparc/edge.c: New test.
 	* gcc.target/sparc/fcmp.c: New test.
 
+	* gcc.target/sparc/edge.c: Update for new return types.
+	* gcc.target/sparc/fcmp.c: Likewise.
+
 2011-09-26  Janus Weil  <janus@gcc.gnu.org>
 
 	PR fortran/50515
diff --git a/gcc/testsuite/gcc.target/sparc/edge.c b/gcc/testsuite/gcc.target/sparc/edge.c
index fcd7104d7d9..81d8d88563c 100644
--- a/gcc/testsuite/gcc.target/sparc/edge.c
+++ b/gcc/testsuite/gcc.target/sparc/edge.c
@@ -1,32 +1,32 @@
 /* { dg-do compile } */
 /* { dg-options "-O -mcpu=ultrasparc -mvis" } */
 
-int test_edge8 (void *p1, void *p2)
+long test_edge8 (void *p1, void *p2)
 {
   return __builtin_vis_edge8 (p1, p2);
 }
 
-int test_edge8l (void *p1, void *p2)
+long test_edge8l (void *p1, void *p2)
 {
   return __builtin_vis_edge8l (p1, p2);
 }
 
-int test_edge16 (void *p1, void *p2)
+long test_edge16 (void *p1, void *p2)
 {
   return __builtin_vis_edge16 (p1, p2);
 }
 
-int test_edge16l (void *p1, void *p2)
+long test_edge16l (void *p1, void *p2)
 {
   return __builtin_vis_edge16l (p1, p2);
 }
 
-int test_edge32 (void *p1, void *p2)
+long test_edge32 (void *p1, void *p2)
 {
   return __builtin_vis_edge32 (p1, p2);
 }
 
-int test_edge32l (void *p1, void *p2)
+long test_edge32l (void *p1, void *p2)
 {
   return __builtin_vis_edge32l (p1, p2);
 }
diff --git a/gcc/testsuite/gcc.target/sparc/fcmp.c b/gcc/testsuite/gcc.target/sparc/fcmp.c
index 42b5bdcad3d..959a674e1e7 100644
--- a/gcc/testsuite/gcc.target/sparc/fcmp.c
+++ b/gcc/testsuite/gcc.target/sparc/fcmp.c
@@ -3,42 +3,42 @@
 typedef int vec32 __attribute__((vector_size(8)));
 typedef short vec16 __attribute__((vector_size(8)));
 
-int test_fcmple16 (vec16 a, vec16 b)
+long test_fcmple16 (vec16 a, vec16 b)
 {
   return __builtin_vis_fcmple16 (a, b);
 }
 
-int test_fcmple32 (vec32 a, vec32 b)
+long test_fcmple32 (vec32 a, vec32 b)
 {
   return __builtin_vis_fcmple32 (a, b);
 }
 
-int test_fcmpne16 (vec16 a, vec16 b)
+long test_fcmpne16 (vec16 a, vec16 b)
 {
   return __builtin_vis_fcmpne16 (a, b);
 }
 
-int test_fcmpne32 (vec32 a, vec32 b)
+long test_fcmpne32 (vec32 a, vec32 b)
 {
   return __builtin_vis_fcmpne32 (a, b);
 }
 
-int test_fcmpgt16 (vec16 a, vec16 b)
+long test_fcmpgt16 (vec16 a, vec16 b)
 {
   return __builtin_vis_fcmpgt16 (a, b);
 }
 
-int test_fcmpgt32 (vec32 a, vec32 b)
+long test_fcmpgt32 (vec32 a, vec32 b)
 {
   return __builtin_vis_fcmpgt32 (a, b);
 }
 
-int test_fcmpeq16 (vec16 a, vec16 b)
+long test_fcmpeq16 (vec16 a, vec16 b)
 {
   return __builtin_vis_fcmpeq16 (a, b);
 }
 
-int test_fcmpeq32 (vec32 a, vec32 b)
+long test_fcmpeq32 (vec32 a, vec32 b)
 {
   return __builtin_vis_fcmpeq32 (a, b);
 }