diff options
| author | belagod <belagod@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-01-08 16:23:38 +0000 |
|---|---|---|
| committer | belagod <belagod@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-01-08 16:23:38 +0000 |
| commit | 3de3342f56968f13b265d28d6a555c8d3b16fa94 (patch) | |
| tree | 10be05fb65446a435e87d960e17fddfe8668ff76 | |
| parent | b3f1c89d027aea4f902b1339c99ba118d0592f01 (diff) | |
| download | gcc-3de3342f56968f13b265d28d6a555c8d3b16fa94.tar.gz | |
2013-01-08 Tejas Belagod <tejas.belagod@arm.com>
* gcc.target/aarch64/vect-mull-compile.c: Explicitly scan for
instructions generated instead of number of occurances.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@195024 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/vect-mull-compile.c | 16 |
2 files changed, 17 insertions, 4 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 303a4bca1ae..eab4c351b29 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2013-01-08 Tejas Belagod <tejas.belagod@arm.com> + + * gcc.target/aarch64/vect-mull-compile.c: Explicitly scan for + instructions generated instead of number of occurances. + 2013-01-08 James Greenhalgh <james.greenhalgh@arm.com> * gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c: New. diff --git a/gcc/testsuite/gcc.target/aarch64/vect-mull-compile.c b/gcc/testsuite/gcc.target/aarch64/vect-mull-compile.c index e51eaee5429..e90c97ff326 100644 --- a/gcc/testsuite/gcc.target/aarch64/vect-mull-compile.c +++ b/gcc/testsuite/gcc.target/aarch64/vect-mull-compile.c @@ -10,7 +10,15 @@ DEF_MULL2 (DEF_MULLB) DEF_MULL2 (DEF_MULLH) DEF_MULL2 (DEF_MULLS) -/* { dg-final { scan-assembler-times "smull v" 3 } } */ -/* { dg-final { scan-assembler-times "smull2 v" 3 } } */ -/* { dg-final { scan-assembler-times "umull v" 3 } } */ -/* { dg-final { scan-assembler-times "umull2 v" 3 } } */ +/* { dg-final { scan-assembler "smull\\tv\[0-9\]+\.8h"} } */ +/* { dg-final { scan-assembler "smull\\tv\[0-9\]+\.4s"} } */ +/* { dg-final { scan-assembler "smull\\tv\[0-9\]+\.2d"} } */ +/* { dg-final { scan-assembler "umull\\tv\[0-9\]+\.8h"} } */ +/* { dg-final { scan-assembler "umull\\tv\[0-9\]+\.4s"} } */ +/* { dg-final { scan-assembler "umull\\tv\[0-9\]+\.2d"} } */ +/* { dg-final { scan-assembler "smull2\\tv\[0-9\]+\.8h"} } */ +/* { dg-final { scan-assembler "smull2\\tv\[0-9\]+\.4s"} } */ +/* { dg-final { scan-assembler "smull2\\tv\[0-9\]+\.2d"} } */ +/* { dg-final { scan-assembler "umull2\\tv\[0-9\]+\.8h"} } */ +/* { dg-final { scan-assembler "umull2\\tv\[0-9\]+\.4s"} } */ +/* { dg-final { scan-assembler "umull2\\tv\[0-9\]+\.2d"} } */ |