Merge branch 'john/erts/fix-ic-dc-config-test/OTP-18554' into maint-25

* john/erts/fix-ic-dc-config-test/OTP-18554:
  Update configure scripts
  erts: Fix ic/dc config tests and usage

5 files changed, 53 insertions, 14 deletions

diff --git a/erts/configure b/erts/configure
index a84ffe4342..fbdb6baba8 100755
--- a/erts/configure
+++ b/erts/configure
@@ -13973,7 +13973,7 @@ int
 main (void)
 {
 
-						__asm__ __volatile__("isb sy" : : : "memory");
+						__asm__ __volatile__("isb sy\n" : : : "memory");
 
   ;
   return 0;
@@ -14007,7 +14007,7 @@ int
 main (void)
 {
 
-						char data[512]; __asm__ __volatile__("dc cvau, %0" : "r" (data) : : "memory");
+						char data[512]; __asm__ __volatile__("dc cvau, %0\n" :: "r" (data) : "memory");
 
   ;
   return 0;
@@ -14041,7 +14041,7 @@ int
 main (void)
 {
 
-						char data[512]; __asm__ __volatile__("ic ivau, %0" : "r" (data) : : "memory");
+						char data[512]; __asm__ __volatile__("ic ivau, %0\n" :: "r" (data) : "memory");
 
   ;
   return 0;
@@ -24313,7 +24313,27 @@ then :
            JIT_ARCH=x86
            ;;
         arm64)
-           JIT_ARCH=arm
+           case "$OPSYS" in
+              win32|darwin)
+                # These platforms have dedicated system calls for clearing
+                # instruction cache, and don't require us to manually issue
+                # instruction barriers on all threads.
+                JIT_ARCH=arm
+              ;;
+              *)
+                # We need to use `DC CVAU`, `IC IVAU`, and `ISB SY` to clear
+                # instruction cache. These have already been tested as part of
+                # ETHR_CHK_GCC_ATOMIC_OPS([]).
+
+                if test "$ethr_arm_isb_sy_instr_val$ethr_arm_dc_cvau_instr_val$ethr_arm_ic_ivau_instr_val" = "111"; then
+                  JIT_ARCH=arm
+                else
+                  enable_jit=no
+                  { printf "%s\n" "$as_me:${as_lineno-$LINENO}: WARNING: JIT disabled due to lack of cache-clearing instructions" >&5
+printf "%s\n" "$as_me: WARNING: JIT disabled due to lack of cache-clearing instructions" >&2;}
+                fi
+              ;;
+           esac
            ;;
         *)
            if test ${enable_jit} = yes; then
diff --git a/erts/configure.ac b/erts/configure.ac
index ab2ee78acd..a052c319ba 100644
--- a/erts/configure.ac
+++ b/erts/configure.ac
@@ -2855,7 +2855,26 @@ AS_IF([test ${enable_jit} != no],
            JIT_ARCH=x86
            ;;
         arm64)
-           JIT_ARCH=arm
+           case "$OPSYS" in
+              win32|darwin)
+                # These platforms have dedicated system calls for clearing
+                # instruction cache, and don't require us to manually issue
+                # instruction barriers on all threads.
+                JIT_ARCH=arm
+              ;;
+              *)
+                # We need to use `DC CVAU`, `IC IVAU`, and `ISB SY` to clear
+                # instruction cache. These have already been tested as part of
+                # ETHR_CHK_GCC_ATOMIC_OPS([]).
+
+                if test "$ethr_arm_isb_sy_instr_val$ethr_arm_dc_cvau_instr_val$ethr_arm_ic_ivau_instr_val" = "111"; then
+                  JIT_ARCH=arm
+                else
+                  enable_jit=no
+                  AC_MSG_WARN([JIT disabled due to lack of cache-clearing instructions])
+                fi
+              ;;
+           esac
            ;;
         *)
            if test ${enable_jit} = yes; then
diff --git a/erts/emulator/beam/jit/beam_jit_main.cpp b/erts/emulator/beam/jit/beam_jit_main.cpp
index 2ddde35511..ef0ad6943a 100644
--- a/erts/emulator/beam/jit/beam_jit_main.cpp
+++ b/erts/emulator/beam/jit/beam_jit_main.cpp
@@ -377,9 +377,9 @@ extern "C"
         /* Issues full memory/instruction barriers on all threads for us. */
         sys_icache_invalidate((char *)address, size);
 #elif defined(__aarch64__) && defined(__GNUC__) &&                             \
-        defined(ETHR_HAVE_GCC_ASM_ARM_IC_IVAU_INSTRUCTION) &&                  \
-        defined(ETHR_HAVE_GCC_ASM_ARM_DC_CVAU_INSTRUCTION) &&                  \
-        defined(ERTS_THR_INSTRUCTION_BARRIER)
+        defined(ERTS_THR_INSTRUCTION_BARRIER) &&                               \
+        ETHR_HAVE_GCC_ASM_ARM_IC_IVAU_INSTRUCTION &&                           \
+        ETHR_HAVE_GCC_ASM_ARM_DC_CVAU_INSTRUCTION
         /* Note that we do not issue any barriers here, whether instruction or
          * memory. This is on purpose as we must issue those on all schedulers
          * and not just the calling thread, and the chances of us forgetting to
diff --git a/lib/erl_interface/configure b/lib/erl_interface/configure
index acfd569e30..049c3371fc 100755
--- a/lib/erl_interface/configure
+++ b/lib/erl_interface/configure
@@ -8718,7 +8718,7 @@ int
 main (void)
 {
 
-						__asm__ __volatile__("isb sy" : : : "memory");
+						__asm__ __volatile__("isb sy\n" : : : "memory");
 
   ;
   return 0;
@@ -8752,7 +8752,7 @@ int
 main (void)
 {
 
-						char data[512]; __asm__ __volatile__("dc cvau, %0" : "r" (data) : : "memory");
+						char data[512]; __asm__ __volatile__("dc cvau, %0\n" :: "r" (data) : "memory");
 
   ;
   return 0;
@@ -8786,7 +8786,7 @@ int
 main (void)
 {
 
-						char data[512]; __asm__ __volatile__("ic ivau, %0" : "r" (data) : : "memory");
+						char data[512]; __asm__ __volatile__("ic ivau, %0\n" :: "r" (data) : "memory");
 
   ;
   return 0;
diff --git a/make/autoconf/otp.m4 b/make/autoconf/otp.m4
index 98b8ea5f61..a522fae3bd 100644
--- a/make/autoconf/otp.m4
+++ b/make/autoconf/otp.m4
@@ -1458,7 +1458,7 @@ AC_DEFUN(ETHR_CHK_GCC_ATOMIC_OPS,
 			   [
 				ethr_cv_arm_isb_sy_instr=no
 				AC_LINK_IFELSE([AC_LANG_PROGRAM([[]], [[
-						__asm__ __volatile__("isb sy" : : : "memory");
+						__asm__ __volatile__("isb sy\n" : : : "memory");
 					    ]])],[ethr_cv_arm_isb_sy_instr=yes],[])
 			   ])
 	    if test $ethr_cv_arm_isb_sy_instr = yes; then
@@ -1468,7 +1468,7 @@ AC_DEFUN(ETHR_CHK_GCC_ATOMIC_OPS,
 			   [
 				ethr_cv_arm_dc_cvau_instr=no
 				AC_LINK_IFELSE([AC_LANG_PROGRAM([[]], [[
-						char data[512]; __asm__ __volatile__("dc cvau, %0" : "r" (data) : : "memory");
+						char data[512]; __asm__ __volatile__("dc cvau, %0\n" :: "r" (data) : "memory");
 					    ]])],[ethr_cv_arm_dc_cvau_instr=yes],[])
 			   ])
 	    if test $ethr_cv_arm_dc_cvau_instr = yes; then
@@ -1478,7 +1478,7 @@ AC_DEFUN(ETHR_CHK_GCC_ATOMIC_OPS,
 			   [
 				ethr_cv_arm_ic_ivau_instr=no
 				AC_LINK_IFELSE([AC_LANG_PROGRAM([[]], [[
-						char data[512]; __asm__ __volatile__("ic ivau, %0" : "r" (data) : : "memory");
+						char data[512]; __asm__ __volatile__("ic ivau, %0\n" :: "r" (data) : "memory");
 					    ]])],[ethr_cv_arm_ic_ivau_instr=yes],[])
 			   ])
 	    if test $ethr_cv_arm_ic_ivau_instr = yes; then