Merge branch 'rickard/armv8-further-membar-improvements/OTP-17195' into maint

* rickard/armv8-further-membar-improvements/OTP-17195:
  Improve memory barrier usage on 64-bit ARM when compiling with gcc
  Remove unnecessary data dependency read barrier on ARM when identified as aarch64
  Fix configure test for arm memory barrier instructions

3 files changed, 19 insertions, 7 deletions

diff --git a/erts/aclocal.m4 b/erts/aclocal.m4
index cf22456518..fae4254ae3 100644
--- a/erts/aclocal.m4
+++ b/erts/aclocal.m4
@@ -1378,7 +1378,7 @@ AC_DEFUN(ETHR_CHK_GCC_ATOMIC_OPS,
     ethr_arm_dbm_st_instr_val=0
     ethr_arm_dbm_ld_instr_val=0
     case "$GCC-$host_cpu" in
-	yes-arm*)
+	yes-arm*|yes-aarch*)
 	    AC_CACHE_CHECK([for ARM 'dmb sy' instruction], ethr_cv_arm_dbm_sy_instr,
 			   [
 				ethr_cv_arm_dbm_sy_instr=no
@@ -1389,7 +1389,7 @@ AC_DEFUN(ETHR_CHK_GCC_ATOMIC_OPS,
 					    [ethr_cv_arm_dbm_sy_instr=yes])
 			   ])
 	    if test $ethr_cv_arm_dbm_sy_instr = yes; then
-		ethr_arm_dbm_instr_val=1
+		ethr_arm_dbm_sy_instr_val=1
 		test $ethr_cv_64bit___atomic_compare_exchange_n = yes &&
 		    ethr_have_gcc_native_atomics=yes
 	    fi
@@ -1402,7 +1402,7 @@ AC_DEFUN(ETHR_CHK_GCC_ATOMIC_OPS,
 					    ],
 					    [ethr_cv_arm_dbm_st_instr=yes])
 			   ])
-	    if test $ethr_cv_arm_dbm_sy_instr = yes; then
+	    if test $ethr_cv_arm_dbm_st_instr = yes; then
 		ethr_arm_dbm_st_instr_val=1
 	    fi
 	    AC_CACHE_CHECK([for ARM 'dmb ld' instruction], ethr_cv_arm_dbm_ld_instr,
@@ -1420,7 +1420,7 @@ AC_DEFUN(ETHR_CHK_GCC_ATOMIC_OPS,
 	*)
 	    ;;
     esac
-    AC_DEFINE_UNQUOTED([ETHR_HAVE_GCC_ASM_ARM_DMB_INSTRUCTION], [$ethr_arm_dbm_instr_val], [Define as a boolean indicating whether you have a gcc compatible compiler capable of generating the ARM 'dmb sy' instruction, and are compiling for an ARM processor with ARM DMB instruction support, or not])
+    AC_DEFINE_UNQUOTED([ETHR_HAVE_GCC_ASM_ARM_DMB_INSTRUCTION], [$ethr_arm_dbm_sy_instr_val], [Define as a boolean indicating whether you have a gcc compatible compiler capable of generating the ARM 'dmb sy' instruction, and are compiling for an ARM processor with ARM DMB instruction support, or not])
     AC_DEFINE_UNQUOTED([ETHR_HAVE_GCC_ASM_ARM_DMB_ST_INSTRUCTION], [$ethr_arm_dbm_st_instr_val], [Define as a boolean indicating whether you have a gcc compatible compiler capable of generating the ARM 'dmb st' instruction, and are compiling for an ARM processor with ARM DMB instruction support, or not])
     AC_DEFINE_UNQUOTED([ETHR_HAVE_GCC_ASM_ARM_DMB_LD_INSTRUCTION], [$ethr_arm_dbm_ld_instr_val], [Define as a boolean indicating whether you have a gcc compatible compiler capable of generating the ARM 'dmb ld' instruction, and are compiling for an ARM processor with ARM DMB instruction support, or not])
     test $ethr_cv_32bit___sync_val_compare_and_swap = yes &&
@@ -2889,6 +2889,9 @@ AC_DEFUN([LM_HARDWARE_ARCH], [
     armv6hl)	ARCH=arm;;
     armv7l)	ARCH=arm;;
     armv7hl)	ARCH=arm;;
+    armv8*)	ARCH=arm;;
+    aarch64)	ARCH=arm64;;
+    aarch*)	ARCH=arm;;
     tile)	ARCH=tile;;
     e2k)        ARCH=e2k;;
     *)	 	ARCH=noarch;;
@@ -2926,8 +2929,8 @@ AC_DEFUN([LM_HARDWARE_ARCH], [
 	ARCH=ppc64
 	;;
     arm-8)
-	AC_MSG_RESULT(yes: adjusting ARCH=arm to ARCH=noarch)
-	ARCH=noarch
+	AC_MSG_RESULT(yes: adjusting ARCH=arm to ARCH=arm64)
+	ARCH=arm64
 	;;
     *)
 	AC_MSG_RESULT(no: ARCH is $ARCH)
diff --git a/erts/include/internal/gcc/ethr_membar.h b/erts/include/internal/gcc/ethr_membar.h
index 4e1eb1117e..aeef8115a3 100644
--- a/erts/include/internal/gcc/ethr_membar.h
+++ b/erts/include/internal/gcc/ethr_membar.h
@@ -247,7 +247,8 @@ ethr_full_fence__(void)
  * Add more archs as needed...
  */
 
-#if !defined(__ia64__) && !defined(__arm__) && !defined(__arm64__)
+#if !defined(__ia64__) && !defined(__arm__) && !defined(__arm64__) \
+    && !defined(__aarch32__) && !defined(__aarch64__)
 #  define ETHR_READ_DEPEND_MEMORY_BARRIER ETHR_MEMBAR(ETHR_LoadLoad)
 #endif
 
diff --git a/erts/include/internal/gcc/ethread.h b/erts/include/internal/gcc/ethread.h
index 300a8c6922..5584648614 100644
--- a/erts/include/internal/gcc/ethread.h
+++ b/erts/include/internal/gcc/ethread.h
@@ -80,6 +80,14 @@
 #elif !ETHR_AT_LEAST_GCC_VSN__(4, 8, 0)
 /* True gcc of version < 4.8, i.e., bug exist... */
 #  define ETHR___atomic_load_ACQUIRE_barrier_bug ETHR_GCC_VERSIONS_MASK__
+#elif ETHR_AT_LEAST_GCC_VSN__(8, 3, 0) \
+    && (defined(__arm64__) || defined(__aarch64__) || defined(__arm__)) \
+    && ETHR_SIZEOF_PTR == 8
+/* Verified not to have this bug */
+#    define ETHR___atomic_load_ACQUIRE_barrier_bug 0
+/* Also trust builtin barriers */
+#    undef ETHR_TRUST_GCC_ATOMIC_BUILTINS_MEMORY_BARRIERS__
+#    define ETHR_TRUST_GCC_ATOMIC_BUILTINS_MEMORY_BARRIERS__ 1
 #elif ETHR_AT_LEAST_GCC_VSN__(9, 3, 0) \
     && (defined(__powerpc__) || defined(__ppc__) || defined(__powerpc64__)) \
     && ETHR_SIZEOF_PTR == 8