diff options
Diffstat (limited to 'lisp/progmodes/verilog-mode.el')
| -rw-r--r-- | lisp/progmodes/verilog-mode.el | 281 |
1 files changed, 162 insertions, 119 deletions
diff --git a/lisp/progmodes/verilog-mode.el b/lisp/progmodes/verilog-mode.el index 2b88120eb9c..14f252b42d4 100644 --- a/lisp/progmodes/verilog-mode.el +++ b/lisp/progmodes/verilog-mode.el @@ -1,15 +1,15 @@ -;;; verilog-mode.el --- major mode for editing verilog source in Emacs +;;; verilog-mode.el --- major mode for editing verilog source in Emacs -*- lexical-binding: t; -*- ;; Copyright (C) 1996-2021 Free Software Foundation, Inc. ;; Author: Michael McNamara <mac@verilog.com> ;; Wilson Snyder <wsnyder@wsnyder.org> -;; X-URL: https://www.veripool.org +;; URL: https://www.veripool.org ;; Created: 3 Jan 1996 ;; Keywords: languages ;; The "Version" is the date followed by the decimal rendition of the Git ;; commit hex. -;; Version: 2021.04.12.188864585 +;; Version: 2021.10.14.127365406 ;; Yoni Rabkin <yoni@rabkins.net> contacted the maintainer of this ;; file on 19/3/2008, and the maintainer agreed that when a bug is @@ -87,7 +87,7 @@ ;; ;; If you want to customize Verilog mode to fit your needs better, ;; you may add the below lines (the values of the variables presented -;; here are the defaults). Note also that if you use an Emacs that +;; here are the defaults). Note also that if you use an Emacs that ;; supports custom, it's probably better to use the custom menu to ;; edit these. If working as a member of a large team these settings ;; should be common across all users (in a site-start file), or set @@ -124,7 +124,7 @@ ;; ;; This variable will always hold the version number of the mode -(defconst verilog-mode-version "2021-04-12-b41d849-vpo-GNU" +(defconst verilog-mode-version "2021-10-14-797711e-vpo-GNU" "Version of this Verilog mode.") (defconst verilog-mode-release-emacs t "If non-nil, this version of Verilog mode was released with Emacs itself.") @@ -414,7 +414,7 @@ wherever possible, since it is slow." ;; "----" ["MB" nil :help "Help MB"])) (defun verilog-define-abbrev-table (tablename definitions &optional docstring &rest props) - "Filter `define-abbrev-table' TABLENAME DEFINITIONS + "Filter `define-abbrev-table' TABLENAME DEFINITIONS. Provides DOCSTRING PROPS in newer Emacs (23.1)." (condition-case nil (apply #'define-abbrev-table tablename definitions docstring props) @@ -591,19 +591,19 @@ If `all' is selected, then all line ups described below are done. If `declarations', then just declarations are lined up with any preceding declarations, taking into account widths and the like, so or example the code: - reg [31:0] a; - reg b; + reg [31:0] a; + reg b; would become - reg [31:0] a; - reg b; + reg [31:0] a; + reg b; If `assignment', then assignments are lined up with any preceding assignments, so for example the code - a_long_variable <= b + c; - d = e + f; + a_long_variable <= b + c; + d = e + f; would become - a_long_variable <= b + c; - d = e + f; + a_long_variable <= b + c; + d = e + f; In order to speed up editing, large blocks of statements are lined up only when a \\[verilog-pretty-expr] is typed; and large blocks of declarations @@ -641,13 +641,13 @@ Set to 0 to get them list right under containing block." (defcustom verilog-indent-declaration-macros nil "How to treat macro expansions in a declaration. If nil, indent as: - input [31:0] a; - input \\=`CP; - output c; + input [31:0] a; + input \\=`CP; + output c; If non-nil, treat as: - input [31:0] a; - input \\=`CP ; - output c;" + input [31:0] a; + input \\=`CP ; + output c;" :group 'verilog-mode-indent :type 'boolean) (put 'verilog-indent-declaration-macros 'safe-local-variable #'verilog-booleanp) @@ -655,12 +655,12 @@ If non-nil, treat as: (defcustom verilog-indent-lists t "How to treat indenting items in a list. If t (the default), indent as: - always @( posedge a or - reset ) begin + always @( posedge a or + reset ) begin If nil, treat as: - always @( posedge a or - reset ) begin" + always @( posedge a or + reset ) begin" :group 'verilog-mode-indent :type 'boolean) (put 'verilog-indent-lists 'safe-local-variable #'verilog-booleanp) @@ -829,7 +829,7 @@ The name of the function or case will be set between the braces." (defcustom verilog-auto-ignore-concat nil "Non-nil means ignore signals in {...} concatenations for AUTOWIRE etc. This will exclude signals referenced as pin connections in {...} -or (...) from AUTOWIRE, AUTOOUTPUT and friends." +or (...) from AUTOWIRE, AUTOOUTPUT and friends. See also AUTONOHOOKUP." :group 'verilog-mode-actions :type 'boolean) (put 'verilog-auto-ignore-concat 'safe-local-variable #'verilog-booleanp) @@ -1264,7 +1264,9 @@ See `verilog-auto-inst-param-value'." Also affects AUTOINSTPARAM. Declaration order is the default for backward compatibility, and as some teams prefer signals that are declared together to remain together. Sorted order reduces -changes when declarations are moved around in a file. +changes when declarations are moved around in a file. Sorting is +within input/output/inout groupings, there is intentionally no +option to intermix between input/output/inouts. See also `verilog-auto-arg-sort'." :version "24.1" ; rev688 @@ -1529,8 +1531,8 @@ If set will become buffer local.") "Keymap used in Verilog mode.") ;; menus -(easy-menu-define - verilog-menu verilog-mode-map "Menu for Verilog mode" +(easy-menu-define verilog-menu verilog-mode-map + "Menu for Verilog mode." (verilog-easy-menu-filter `("Verilog" ("Choose Compilation Action" @@ -2077,8 +2079,7 @@ find the errors." (if (boundp 'compilation-error-regexp-systems-alist) (if (and (not (equal compilation-error-regexp-systems-list 'all)) - ;; eval required due to bug1700, XEmacs otherwise errors on compile - (not (eval "(member compilation-error-regexp-systems-list 'verilog)"))) + (not (member 'verilog compilation-error-regexp-systems-list))) (push 'verilog compilation-error-regexp-systems-list))) (if (boundp 'compilation-error-regexp-alist-alist) (if (not (assoc 'verilog compilation-error-regexp-alist-alist)) @@ -2505,7 +2506,7 @@ find the errors." (defconst verilog-no-indent-begin-re (eval-when-compile (verilog-regexp-words - '("always" "always_comb" "always_ff" "always_latch" "initial" "final" ; procedural blocks + '("always" "always_comb" "always_ff" "always_latch" "analog" "initial" "final" ; procedural blocks "if" "else" ; conditional statements "while" "for" "foreach" "repeat" "do" "forever" )))) ; loop statements @@ -2651,6 +2652,7 @@ find the errors." "\\(\\<end\\>\\s-+\\<else\\>\\)\\|" ; 3 "\\(\\<always\\(?:_ff\\)?\\>\\(?:[ \t]*@\\)\\)\\|" ; 4 (matches always or always_ff w/ @...) "\\(\\<always\\(?:_comb\\|_latch\\)?\\>\\)\\|" ; 5 (matches always, always_comb, always_latch w/o @...) + "\\(\\<analog\\>\\)\\|" ; 6 "\\(\\<fork\\>\\)\\|" ; 7 "\\(\\<if\\>\\)\\|" verilog-property-re "\\|" @@ -2853,7 +2855,7 @@ find the errors." (eval-when-compile (verilog-regexp-words '("Outputs" "Inouts" "Inputs" "Interfaces" "Interfaced")))) (defconst verilog-behavioral-block-beg-re - (eval-when-compile (verilog-regexp-words '("initial" "final" "always" "always_comb" "always_latch" "always_ff" + (eval-when-compile (verilog-regexp-words '("initial" "final" "always" "always_comb" "always_latch" "always_ff" "analog" "function" "task")))) (defconst verilog-coverpoint-re "\\w+\\s-*:\\s-*\\(coverpoint\\|cross\\|constraint\\)") (defconst verilog-in-constraint-re ; keywords legal in constraint blocks starting a statement/block @@ -2864,7 +2866,7 @@ find the errors." (verilog-regexp-words '( "{" - "always" "always_latch" "always_ff" "always_comb" + "always" "always_latch" "always_ff" "always_comb" "analog" "begin" "end" ;; "unique" "priority" "case" "casex" "casez" "randcase" "endcase" @@ -2956,13 +2958,13 @@ find the errors." '( "connectmodule" "module" "macromodule" "primitive" "class" "program" "interface" "package" "config") '( "initial" "final" "always" "always_comb" "always_ff" - "always_latch" "endtask" "endfunction" ))))) + "always_latch" "analog" "endtask" "endfunction" ))))) (defconst verilog-defun-level-generate-only-re (eval-when-compile (verilog-regexp-words '( "initial" "final" "always" "always_comb" "always_ff" - "always_latch" "endtask" "endfunction" )))) + "always_latch" "analog" "endtask" "endfunction" )))) (defconst verilog-cpp-level-re (eval-when-compile @@ -2989,7 +2991,7 @@ find the errors." (eval-when-compile (verilog-regexp-words '( - "always" "assign" "always_latch" "always_ff" "always_comb" "connectmodule" "constraint" + "always" "assign" "always_latch" "always_ff" "always_comb" "analog" "connectmodule" "constraint" "import" "initial" "final" "module" "macromodule" "repeat" "randcase" "while" "if" "for" "forever" "foreach" "else" "parameter" "do" "localparam" "assert" )))) @@ -3066,7 +3068,7 @@ find the errors." (defconst verilog-keywords (append verilog-compiler-directives '( - "after" "alias" "always" "always_comb" "always_ff" "always_latch" "and" + "after" "alias" "always" "always_comb" "always_ff" "always_latch" "analog" "and" "assert" "assign" "assume" "automatic" "before" "begin" "bind" "bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1" "byte" "case" "casex" "casez" "cell" "chandle" "class" "clocking" "cmos" @@ -3283,7 +3285,7 @@ See also `verilog-font-lock-extra-types'.") "use" "wait" "while" ;; 1800-2005 "alias" "always_comb" "always_ff" "always_latch" "assert" - "assume" "before" "bind" "bins" "binsof" "break" "class" + "assume" "analog" "before" "bind" "bins" "binsof" "break" "class" "clocking" "constraint" "context" "continue" "cover" "covergroup" "coverpoint" "cross" "dist" "do" "endclass" "endclocking" "endgroup" "endinterface" "endpackage" @@ -3563,7 +3565,7 @@ either is ok to parse as a non-comment, or `verilog-insert' was used." (defun verilog-scan-debug () "For debugging, show with display face results of `verilog-scan'." (font-lock-mode 0) - ;;(if dbg (setq dbg (concat dbg (format "verilog-scan-debug\n")))) + ;;(if dbg (setq dbg (concat dbg "verilog-scan-debug\n"))) (save-excursion (goto-char (point-min)) (remove-text-properties (point-min) (point-max) '(face nil)) @@ -3610,19 +3612,19 @@ inserted using a single call to `verilog-insert'." (search-forward ";" nil t)) (defun verilog-single-declaration-end (limit) - "Returns pos where current (single) declaration statement ends. + "Return pos where current (single) declaration statement ends. Also, this function moves POINT forward to the start of a variable name (skipping the range-part and whitespace). Function expected to be called with POINT just after a declaration keyword. -LIMIT sets the max POINT for searching and moving to. No such limit if LIMIT +LIMIT sets the max POINT for searching and moving to. No such limit if LIMIT is 0. Meaning of *single* declaration: - Eg. In a module's port-list - + E.g. In a module's port-list - module test(input clk, rst, x, output [1:0] y); Here 'input clk, rst, x' is 1 *single* declaration statement, and 'output [1:0] y' is the other single declaration. In the 1st single -declaration, POINT is moved to start of 'clk'. And in the 2nd declaration, +declaration, POINT is moved to start of 'clk'. And in the 2nd declaration, POINT is moved to 'y'." @@ -4038,9 +4040,12 @@ Some other functions are: \\[verilog-sk-repeat] Insert a repeat (..) begin .. end block. \\[verilog-sk-specify] Insert a specify .. endspecify block. \\[verilog-sk-task] Insert a task .. begin .. end endtask block. - \\[verilog-sk-while] Insert a while (...) begin .. end block, prompting for details. - \\[verilog-sk-casex] Insert a casex (...) item: begin.. end endcase block, prompting for details. - \\[verilog-sk-casez] Insert a casez (...) item: begin.. end endcase block, prompting for details. + \\[verilog-sk-while] Insert a while (...) begin .. end block, + prompting for details. + \\[verilog-sk-casex] Insert a casex (...) item: begin.. end endcase block, + prompting for details. + \\[verilog-sk-casez] Insert a casez (...) item: begin.. end endcase block, + prompting for details. \\[verilog-sk-if] Insert an if (..) begin .. end block. \\[verilog-sk-else-if] Insert an else if (..) begin .. end block. \\[verilog-sk-comment] Insert a comment block. @@ -4759,7 +4764,7 @@ More specifically, after a generate and before an endgenerate." (while (and (/= nest 0) (verilog-re-search-backward - "\\<\\(module\\)\\|\\(connectmodule\\)\\|\\(generate\\)\\|\\(endgenerate\\)\\>" nil 'move) + "\\<\\(module\\)\\|\\(connectmodule\\)\\|\\(generate\\)\\|\\(endgenerate\\)\\|\\(if\\)\\|\\(case\\)\\|\\(for\\)\\>" nil 'move) (cond ((match-end 1) ; module - we have crawled out (throw 'done 1)) @@ -4768,7 +4773,13 @@ More specifically, after a generate and before an endgenerate." ((match-end 3) ; generate (setq nest (1- nest))) ((match-end 4) ; endgenerate - (setq nest (1+ nest)))))))) + (setq nest (1+ nest))) + ((match-end 5) ; if + (setq nest (1- nest))) + ((match-end 6) ; case + (setq nest (1- nest))) + ((match-end 7) ; for + (setq nest (1- nest)))))))) (= nest 0) )) ; return nest (defun verilog-in-fork-region-p () @@ -4818,7 +4829,7 @@ Limit search to point LIM." ((match-end 1) ; [ (setq colon (1+ colon)) (if (>= colon 0) - (error "%s: unbalanced [" (verilog-point-text)))) + (error "%s: Unbalanced [" (verilog-point-text)))) ((match-end 2) ; ] (setq colon (1- colon))) @@ -5104,7 +5115,7 @@ primitive or interface named NAME." (throw 'skip 1))))))))) (; always, always_comb, always_latch w/o @... - (match-end 5) + (or (match-end 5) (match-end 6)) (goto-char (match-end 0)) (setq there (point)) (setq err nil) @@ -5112,7 +5123,6 @@ primitive or interface named NAME." (;- task/function/initial et cetera t - (match-end 0) (goto-char (match-end 0)) (setq there (point)) (setq err nil) @@ -5420,7 +5430,7 @@ Useful for creating tri's and other expanded fields." (defun verilog-lint-off () "Convert a Verilog linter warning line into a disable statement. For example: - pci_bfm_null.v, line 46: Unused input: pci_rst_ + pci_bfm_null.v, line 46: Unused input: pci_rst_ becomes a comment for the appropriate tool. The first word of the `compile-command' or `verilog-linter' @@ -5444,9 +5454,9 @@ Run from Verilog source window; assumes there is a *compile* buffer with point set appropriately. For example: - WARNING [STD-UDDONX]: xx.v, line 8: output out is never assigned. + WARNING [STD-UDDONX]: xx.v, line 8: output out is never assigned. becomes: - // surefire lint_line_off UDDONX" + // surefire lint_line_off UDDONX" (interactive) (let ((buff (if (boundp 'next-error-last-buffer) next-error-last-buffer @@ -5470,8 +5480,11 @@ becomes: (let* ((pop-up-windows t)) (let ((name (expand-file-name (read-file-name - (format "Find this error in: (default %s) " - file) + ;; `format-prompt' is new in Emacs 28.1. + (if (fboundp 'format-prompt) + (format-prompt "Find this error in" file) + (format "Find this error in (default %s): " + file)) nil ;; dir file t)))) (setq buffer @@ -5505,9 +5518,9 @@ becomes: "Convert a Verilint warning line into a disable statement. For example: - (W240) pci_bfm_null.v, line 46: Unused input: pci_rst_ + (W240) pci_bfm_null.v, line 46: Unused input: pci_rst_ becomes: - //Verilint 240 off // WARNING: Unused input" + //Verilint 240 off // WARNING: Unused input" (interactive) (save-excursion (beginning-of-line) @@ -6575,7 +6588,8 @@ Return >0 for nested struct." nil)))) (defun verilog-at-constraint-p () - "If at the { of a constraint or coverpoint definition, return true, moving point to constraint." + "If at the { of a constraint or coverpoint definition, return true. +Also move point to constraint." (if (save-excursion (let ((p (point))) (and @@ -6589,7 +6603,8 @@ Return >0 for nested struct." (equal (char-before) ?\;) (equal (char-before) ?\})) ;; skip what looks like bus repetition operator {#{ - (not (string-match "^{\\s-*[0-9a-zA-Z_]+\\s-*{" (buffer-substring p (point))))))))) + (not (string-match "^{\\s-*[()0-9a-zA-Z_\\]*\\s-*{" + (buffer-substring p (point))))))))) (progn (let ( (pt (point)) (pass 0)) (verilog-backward-ws&directives) @@ -6806,6 +6821,8 @@ Only look at a few lines to determine indent level." (verilog-do-indent (verilog-calculate-indent))) (defun verilog-do-indent (indent-str) + ;; `ind' is used in expressions stored in `verilog-indent-alist'. + (verilog--suppressed-warnings ((lexical ind)) (defvar ind)) (let ((type (car indent-str)) (ind (car (cdr indent-str)))) (cond @@ -7158,11 +7175,11 @@ Be verbose about progress unless optional QUIET set." (forward-char -1) (just-one-space) (goto-char (marker-position m1)) - (just-one-space) - (indent-to ind)) + (delete-horizontal-space) + (indent-to ind 1)) (progn - (just-one-space) - (indent-to ind))))) + (delete-horizontal-space) + (indent-to ind 1))))) ((verilog-continued-line-1 (marker-position startpos)) (goto-char e) (indent-line-to ind)) @@ -7287,6 +7304,8 @@ If QUIET is non-nil, do not print messages showing the progress of line-up." Line up the variable names based on previous declaration's indentation. BASEIND is the base indent to offset everything." (interactive) + ;; `ind' is used in expressions stored in `verilog-indent-alist'. + (verilog--suppressed-warnings ((lexical ind)) (defvar ind)) (let ((pos (point-marker)) (lim (save-excursion ;; (verilog-re-search-backward verilog-declaration-opener nil 'move) @@ -7325,12 +7344,10 @@ BASEIND is the base indent to offset everything." (forward-char -1) (just-one-space) (goto-char (marker-position m1)) - (just-one-space) - (indent-to ind)) - (if (/= (current-column) ind) - (progn - (just-one-space) - (indent-to ind))))) + (delete-horizontal-space) + (indent-to ind 1)) + (delete-horizontal-space) + (indent-to ind 1))) (if (looking-at verilog-declaration-re-2-no-macro) (let ((p (match-end 0))) (set-marker m1 p) @@ -7339,12 +7356,10 @@ BASEIND is the base indent to offset everything." (forward-char -1) (just-one-space) (goto-char (marker-position m1)) - (just-one-space) - (indent-to ind)) - (if (/= (current-column) ind) - (progn - (just-one-space) - (indent-to ind)))))))))) + (delete-horizontal-space) + (indent-to ind 1)) + (delete-horizontal-space) + (indent-to ind 1)))))))) (goto-char pos))) (defun verilog-get-lineup-indent (b edpos) @@ -7458,7 +7473,7 @@ will be completed at runtime and should not be added to this list.") (defvar verilog-defun-keywords (append '( - "always" "always_comb" "always_ff" "always_latch" "assign" + "always" "always_comb" "always_ff" "always_latch" "analog" "assign" "begin" "end" "connectmodule" "endconnectmodule" "generate" "endgenerate" "module" "endmodule" "specify" "endspecify" "function" "endfunction" "initial" "final" "task" "endtask" "primitive" "endprimitive" @@ -7854,14 +7869,14 @@ If search fails, other files are checked based on (let* ((default (verilog-get-default-symbol)) ;; The following variable is used in verilog-comp-function (verilog-buffer-to-use (current-buffer)) - (label (if (not (string= default "")) - ;; Do completion with default - (completing-read (concat "Goto-Label: (default " - default ") ") - #'verilog-comp-defun nil nil "") - ;; There is no default value. Complete without it - (completing-read "Goto-Label: " - #'verilog-comp-defun nil nil ""))) + (label + (completing-read (cond ((fboundp 'format-prompt) + ;; `format-prompt' is new in Emacs 28.1. + (format-prompt "Goto-Label" default)) + ((not (string= default "")) + (concat "Goto-Label (default " default "): ")) + (t "Goto-Label: ")) + #'verilog-comp-defun nil nil "")) pt) ;; Make sure library paths are correct, in case need to resolve module (verilog-auto-reeval-locals) @@ -8644,6 +8659,13 @@ Optional NUM-PARAM and MAX-PARAM check for a specific number of parameters." (defun verilog-read-decls () "Compute signal declaration information for the current module at point. Return an array of [outputs inouts inputs wire reg assign const gparam intf]." + (verilog--suppressed-warnings + ((lexical sigs-intf sigs-var sigs-const sigs-assign sigs-var + sigs-gparam sigs-inout sigs-out sigs-in)) + ;; The local variable below are accessed via (symbol-value expect-signal). + (defvar sigs-intf) (defvar sigs-var) (defvar sigs-const) + (defvar sigs-assign) (defvar sigs-var) (defvar sigs-gparam) + (defvar sigs-inout) (defvar sigs-out) (defvar sigs-in)) (let ((end-mod-point (or (verilog-get-end-of-defun) (point-max))) (functask 0) (paren 0) (sig-paren 0) (v2kargs-ok t) in-modport in-clocking in-ign-to-semi ptype ign-prop @@ -9107,9 +9129,7 @@ Inserts the list of signals found, using submodi to look up each port." ;; We intentionally ignore (non-escaped) signals with .s in them ;; this prevents AUTOWIRE etc from noticing hierarchical sigs. (when port - (cond ((and verilog-auto-ignore-concat - (looking-at "[({]")) - nil) ; {...} or (...) historically ignored with auto-ignore-concat + (cond ((looking-at "[^\n]*AUTONOHOOKUP")) ((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*)") (verilog-read-sub-decls-sig submoddecls par-values comment port @@ -9326,6 +9346,9 @@ Must call `verilog-read-auto-lisp-present' before this function." EXIT-KEYWD is expression to stop at, nil if top level. RVALUE is true if at right hand side of equal. TEMP-NEXT is true to ignore next token, fake from inside case statement." + (verilog--suppressed-warnings ((lexical sigs-temp sigs-in sigs-out-unk)) + ;; The local variable below are accessed via (symbol-value got-list). + (defvar sigs-temp) (defvar sigs-in) (defvar sigs-out-unk)) (let* ((semi-rvalue (equal "endcase" exit-keywd)) ; true if after a ; we are looking for rvalue keywd last-keywd sig-tolk sig-last-tolk gotend got-sig got-list end-else-check ignore-next) @@ -9556,7 +9579,10 @@ Returns REGEXP and list of ( (signal_name connection_name)... )." (cons (list (match-string-no-properties 1) (match-string-no-properties 2) - templateno lineno) + templateno lineno + (save-excursion + (goto-char (match-end 0)) + (looking-at "[^\n]*AUTONOHOOKUP"))) tpl-sig-list)) (goto-char (match-end 0))) ;; Regexp form?? @@ -9572,7 +9598,10 @@ Returns REGEXP and list of ( (signal_name connection_name)... )." (match-string 1)) "$") rep - templateno lineno) + templateno lineno + (save-excursion + (goto-char (match-end 0)) + (looking-at "[^\n]*AUTONOHOOKUP"))) tpl-wild-list))) ((looking-at "[ \t\f]+") (goto-char (match-end 0))) @@ -9746,6 +9775,9 @@ warning message, you need to add to your init file: (while (re-search-forward "^\\s-*\\(parameter\\|localparam\\)\\(\\s-*\\[[^]]*\\]\\)?\\s-*" nil t) (let (enumname) + ;; Advance over parameter's type if present + (if (looking-at "\\([a-zA-Z0-9_]+\\s-+\\)[a-zA-Z0-9_]+") + (goto-char (match-end 1))) ;; The primary way of getting defines is verilog-read-decls ;; However, that isn't called yet for included files, so we'll add another scheme (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)") @@ -9790,11 +9822,11 @@ variable over and over when many modules are compiled together, put a test around the inside each include file: foo.v (an include file): - \\=`ifdef _FOO_V // include if not already included - \\=`else - \\=`define _FOO_V - ... contents of file - \\=`endif // _FOO_V" + \\=`ifdef _FOO_V // include if not already included + \\=`else + \\=`define _FOO_V + ... contents of file + \\=`endif // _FOO_V" ;;slow: (verilog-read-defines nil t) (save-excursion (verilog-getopt-flags) @@ -11041,7 +11073,7 @@ Intended for internal use inside a 'verilog-delete-auto-star-all) ;; Remove template comments ... anywhere in case was pasted after AUTOINST removed (goto-char (point-min)) - (while (re-search-forward "\\s-*// \\(Templated\\|Implicit \\.\\*\\)\\([ \tLT0-9]*\\| LHS: .*\\)$" nil t) + (while (re-search-forward "\\s-*// \\(Templated\\(\\s-*AUTONOHOOKUP\\)?\\|Implicit \\.\\*\\)\\([ \tLT0-9]*\\| LHS: .*\\)$" nil t) (replace-match "")) ;; Final customize @@ -11559,6 +11591,7 @@ See the example in `verilog-auto-inout-modport'." (defun verilog-auto-inst-port-map (_port-st) nil) +;; These are used by user's AUTO_TEMPLATE Lisp expressions (defvar vl-cell-type nil "See `verilog-auto-inst'.") ; Prevent compile warning (defvar vl-cell-name nil "See `verilog-auto-inst'.") ; Prevent compile warning (defvar vl-memory nil "See `verilog-auto-inst'.") ; Prevent compile warning @@ -11690,15 +11723,14 @@ If PAR-VALUES replace final strings with these parameter values." ;; verilog-insert requires the complete comment in one call - including the newline (cond ((equal verilog-auto-inst-template-numbers 'lhs) (verilog-insert " // Templated" - " LHS: " (nth 0 tpl-ass) - "\n")) + " LHS: " (nth 0 tpl-ass))) (verilog-auto-inst-template-numbers (verilog-insert " // Templated" " T" (int-to-string (nth 2 tpl-ass)) - " L" (int-to-string (nth 3 tpl-ass)) - "\n")) + " L" (int-to-string (nth 3 tpl-ass)))) (t - (verilog-insert " // Templated\n")))) + (verilog-insert " // Templated"))) + (verilog-insert (if (nth 4 tpl-ass) " AUTONOHOOKUP\n" "\n"))) (for-star (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16) verilog-auto-inst-column)) @@ -12088,6 +12120,16 @@ Lisp Templates: After the evaluation is completed, @ substitution and [] substitution occur. + +Ignoring Hookup: + + AUTOWIRE and related AUTOs will read the signals created by a template. + To specify that a signal should not be parsed to participate in this + hookup, add a AUTONOHOOKUP comment to the template. For example: + + .pci_req_l (pci_req_not_to_wire), //AUTONOHOOKUP + + For more information see the \\[verilog-faq] and forums at URL `https://www.veripool.org'." (save-excursion @@ -12564,7 +12606,7 @@ You may also provide an optional regular expression, in which case only signals matching the regular expression will be included. For example the same expansion will result from only extracting outputs starting with ov: - /*AUTOOUTPUT(\"^ov\")*/" + /*AUTOOUTPUT(\"^ov\")*/" (save-excursion ;; Point must be at insertion point. (let* ((indent-pt (current-indentation)) @@ -12715,7 +12757,7 @@ included. or excluded if the regexp begins with expansion will result from only extracting inputs starting with i: - /*AUTOINPUT(\"^i\")*/" + /*AUTOINPUT(\"^i\")*/" (save-excursion (let* ((indent-pt (current-indentation)) (params (verilog-read-auto-params 0 1)) @@ -13429,7 +13471,7 @@ Constant signals: is put into the AUTOSENSE list and is not desired, use the AUTO_CONSTANT declaration anywhere in the module (parenthesis are required): - /* AUTO_CONSTANT ( \\=`this_is_really_constant_dont_autosense_it ) */ + /* AUTO_CONSTANT( \\=`this_is_really_constant_dont_autosense_it ) */ Better yet, use a parameter, which will be understood to be constant automatically. @@ -13445,7 +13487,7 @@ OOps! An example: always @ (/*AS*/) begin - /*AUTO_CONSTANT (\\=`constant) */ + /*AUTO_CONSTANT(\\=`constant) */ outin = ina | inb | \\=`constant; out = outin; end @@ -13453,7 +13495,7 @@ An example: Typing \\[verilog-auto] will make this into: always @ (/*AS*/ina or inb) begin - /*AUTO_CONSTANT (\\=`constant) */ + /*AUTO_CONSTANT(\\=`constant) */ outin = ina | inb | \\=`constant; out = outin; end @@ -13626,7 +13668,7 @@ signals to deasserted. the same input/output list as another module, but no internals. Specifically, it finds all outputs in the module, and if that input is not otherwise declared as a register or wire, nor comes -from a AUTOINST submodule's output, creates a tieoff. AUTOTIEOFF +from a AUTOINST submodule's output, creates a tieoff. AUTOTIEOFF does not examine assignments to determine what is already driven. AUTORESET ties signals to deasserted, which is presumed to be zero. @@ -14109,14 +14151,14 @@ For example: endmodule You can also update the AUTOs from the shell using: - emacs --batch <filenames.v> -f verilog-batch-auto + emacs --batch <filenames.v> -f verilog-batch-auto Or fix indentation with: - emacs --batch <filenames.v> -f verilog-batch-indent + emacs --batch <filenames.v> -f verilog-batch-indent Likewise, you can delete or inject AUTOs with: - emacs --batch <filenames.v> -f verilog-batch-delete-auto - emacs --batch <filenames.v> -f verilog-batch-inject-auto + emacs --batch <filenames.v> -f verilog-batch-delete-auto + emacs --batch <filenames.v> -f verilog-batch-inject-auto Or check if AUTOs have the same expansion - emacs --batch <filenames.v> -f verilog-batch-diff-auto + emacs --batch <filenames.v> -f verilog-batch-diff-auto Using \\[describe-function], see also: `verilog-auto-arg' for AUTOARG module instantiations @@ -14403,7 +14445,7 @@ See also `verilog-header' for an alternative format." ;; ------------------------------------------------------------------------ (define-skeleton verilog-sk-ovm-class - "Insert a class definition" + "Insert a class definition." () > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n > _ \n @@ -14417,7 +14459,7 @@ See also `verilog-header' for an alternative format." > "endclass" (progn (electric-verilog-terminate-line) nil)) (define-skeleton verilog-sk-uvm-object - "Insert a class definition" + "Insert a class definition." () > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n > _ \n @@ -14431,7 +14473,7 @@ See also `verilog-header' for an alternative format." > "endclass" (progn (electric-verilog-terminate-line) nil)) (define-skeleton verilog-sk-uvm-component - "Insert a class definition" + "Insert a class definition." () > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n > _ \n @@ -14472,8 +14514,7 @@ See also `verilog-header' for an alternative format." > (- verilog-indent-level-behavioral) "endfunction" (progn (electric-verilog-terminate-line) nil)) (define-skeleton verilog-sk-always - "Insert always block. Uses the minibuffer to prompt -for sensitivity list." + "Insert always block. Prompt for sensitivity list." () > "always @ ( /*AUTOSENSE*/ ) begin\n" > _ \n @@ -14488,14 +14529,14 @@ for sensitivity list." > (- verilog-indent-level-behavioral) "end" \n > ) (define-skeleton verilog-sk-specify - "Insert specify block. " + "Insert specify block." () > "specify\n" > _ \n > (- verilog-indent-level-behavioral) "endspecify" \n > ) (define-skeleton verilog-sk-generate - "Insert generate block. " + "Insert generate block." () > "generate\n" > _ \n @@ -14954,7 +14995,9 @@ but instead, [[Fill in here]] happens!. (provide 'verilog-mode) +;;TODO: Could `byte-compile-docstring-max-column' be decreased? ;; Local Variables: +;; byte-compile-docstring-max-column: 90 ;; checkdoc-permit-comma-termination-flag:t ;; checkdoc-force-docstrings-flag:nil ;; indent-tabs-mode:nil |