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+{imm} only parameter:
+ - is {s} in opcode: {s} == 0, unsigned (8/)16/32 bit immediate
+ {s} == 1, signed 8 bit immediate
+
+{es:di}: segment register normally %es, can be overwritten
+ edi/di depending on apfx
+
+{ds:si}: segment register normally %ds, can be overwritten
+ esi/si depending on apfx
+
+{ax} al/ax/eax depending of dpfx and w
+
+{dx} (%edx) or (%dx) depending on apfx
+
+
+{w} 0 = b, 1 = { no dpfx = l, dpfx = w }
+
+{W} no dpfx = <empty>, dpfx = w
+{WW} no dpfx = l, dpfx = w
+
+{R} rep prefix possible
+{RE} repe or repne prefix possible
+
+{ccc} CRx registers
+{ddd} DRx registers
+
+{gg} 00 = b, 01 = w, 10 = d, 11 = <illegal>
+{0g} 00 = b, 01 = w, 10 = <illegal>, 11 = <illegal>
+{GG} 00 = <illegal>, 01 = w, 10 = d, 11 = q
+{gG} 00 = <illegal>, 01 = w, 10 = d, 11 = <illegal>
+
+{modr/m} normal registers
+{MODR/M} MMX registers
+{ModR/m} XMM registers
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Special opcodes (prefixes):
+
+
+01100111:{apfx}
+01100110:{dpfx}
+
+00101110:{cs}
+00111110:{ds}
+00100110:{es}
+01100100:{fs}
+01100101:{gs}
+
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+table format
+
+1bit RE flag
+1bit R flag
+16bit mnemonic
+3bit suffix
+
+5bit fct
+2bit string
+6bit offset1
+5bit offset2
+
+4bit fct
+1bit string
+6bit offset1
+4bit offset2
+
+2bit fct
+1bit string
+3bit offset1
+1bit offset2
+
+61bit