diff options
| author | Roland McGrath <roland@redhat.com> | 2006-08-03 08:52:46 +0000 |
|---|---|---|
| committer | Roland McGrath <roland@redhat.com> | 2006-08-03 08:52:46 +0000 |
| commit | 19db85901e6d3b620749386f1c5692661dcb74d8 (patch) | |
| tree | 6ab731b34736d9fdcf9b80daf8d998fc69cc69ed /tests/run-allregs.sh | |
| parent | 42a177cb418af47f974856ca9b28c9b884d00fb7 (diff) | |
| download | elfutils-19db85901e6d3b620749386f1c5692661dcb74d8.tar.gz | |
backends/
2006-08-03 Roland McGrath <roland@redhat.com>
* sparc_regs.c (sparc_register_name): List 32 FPU regs only for
EM_SPARC. EM_SPARC32PLUS also has 64.
tests/
2006-08-03 Roland McGrath <roland@redhat.com>
* run-allregs.sh: Add sparc cases.
* testfile30.bz2: New data file.
* testfile31.bz2: New data file.
* Makefile.am (EXTRA_DIST): Add them.
Diffstat (limited to 'tests/run-allregs.sh')
| -rwxr-xr-x | tests/run-allregs.sh | 170 |
1 files changed, 170 insertions, 0 deletions
diff --git a/tests/run-allregs.sh b/tests/run-allregs.sh index 480a8029..bdd1ca23 100755 --- a/tests/run-allregs.sh +++ b/tests/run-allregs.sh @@ -1238,4 +1238,174 @@ control registers: 65: %pswa (pswa) EOF +regs_test testfile30 <<\EOF +integer registers: + 0: %g0 (g0) + 1: %g1 (g1) + 2: %g2 (g2) + 3: %g3 (g3) + 4: %g4 (g4) + 5: %g5 (g5) + 6: %g6 (g6) + 7: %g7 (g7) + 8: %o0 (o0) + 9: %o1 (o1) + 10: %o2 (o2) + 11: %o3 (o3) + 12: %o4 (o4) + 13: %o5 (o5) + 14: %o6 (o6) + 15: %o7 (o7) + 16: %l0 (l0) + 17: %l1 (l1) + 18: %l2 (l2) + 19: %l3 (l3) + 20: %l4 (l4) + 21: %l5 (l5) + 22: %l6 (l6) + 23: %l7 (l7) + 24: %i0 (i0) + 25: %i1 (i1) + 26: %i2 (i2) + 27: %i3 (i3) + 28: %i4 (i4) + 29: %i5 (i5) + 30: %i6 (i6) + 31: %i7 (i7) +FPU registers: + 32: %f0 (f0) + 33: %f1 (f1) + 34: %f2 (f2) + 35: %f3 (f3) + 36: %f4 (f4) + 37: %f5 (f5) + 38: %f6 (f6) + 39: %f7 (f7) + 40: %f8 (f8) + 41: %f9 (f9) + 42: %f10 (f10) + 43: %f11 (f11) + 44: %f12 (f12) + 45: %f13 (f13) + 46: %f14 (f14) + 47: %f15 (f15) + 48: %f16 (f16) + 49: %f17 (f17) + 50: %f18 (f18) + 51: %f19 (f19) + 52: %f20 (f20) + 53: %f21 (f21) + 54: %f22 (f22) + 55: %f23 (f23) + 56: %f24 (f24) + 57: %f25 (f25) + 58: %f26 (f26) + 59: %f27 (f27) + 60: %f28 (f28) + 61: %f29 (f29) + 62: %f30 (f30) + 63: %f31 (f31) +EOF + +regs_test testfile31 <<\EOF +integer registers: + 0: %g0 (g0) + 1: %g1 (g1) + 2: %g2 (g2) + 3: %g3 (g3) + 4: %g4 (g4) + 5: %g5 (g5) + 6: %g6 (g6) + 7: %g7 (g7) + 8: %o0 (o0) + 9: %o1 (o1) + 10: %o2 (o2) + 11: %o3 (o3) + 12: %o4 (o4) + 13: %o5 (o5) + 14: %o6 (o6) + 15: %o7 (o7) + 16: %l0 (l0) + 17: %l1 (l1) + 18: %l2 (l2) + 19: %l3 (l3) + 20: %l4 (l4) + 21: %l5 (l5) + 22: %l6 (l6) + 23: %l7 (l7) + 24: %i0 (i0) + 25: %i1 (i1) + 26: %i2 (i2) + 27: %i3 (i3) + 28: %i4 (i4) + 29: %i5 (i5) + 30: %i6 (i6) + 31: %i7 (i7) +FPU registers: + 32: %f0 (f0) + 33: %f1 (f1) + 34: %f2 (f2) + 35: %f3 (f3) + 36: %f4 (f4) + 37: %f5 (f5) + 38: %f6 (f6) + 39: %f7 (f7) + 40: %f8 (f8) + 41: %f9 (f9) + 42: %f10 (f10) + 43: %f11 (f11) + 44: %f12 (f12) + 45: %f13 (f13) + 46: %f14 (f14) + 47: %f15 (f15) + 48: %f16 (f16) + 49: %f17 (f17) + 50: %f18 (f18) + 51: %f19 (f19) + 52: %f20 (f20) + 53: %f21 (f21) + 54: %f22 (f22) + 55: %f23 (f23) + 56: %f24 (f24) + 57: %f25 (f25) + 58: %f26 (f26) + 59: %f27 (f27) + 60: %f28 (f28) + 61: %f29 (f29) + 62: %f30 (f30) + 63: %f31 (f31) + 64: %f32 (f32) + 65: %f33 (f33) + 66: %f34 (f34) + 67: %f35 (f35) + 68: %f36 (f36) + 69: %f37 (f37) + 70: %f38 (f38) + 71: %f39 (f39) + 72: %f40 (f40) + 73: %f41 (f41) + 74: %f42 (f42) + 75: %f43 (f43) + 76: %f44 (f44) + 77: %f45 (f45) + 78: %f46 (f46) + 79: %f47 (f47) + 80: %f48 (f48) + 81: %f49 (f49) + 82: %f50 (f50) + 83: %f51 (f51) + 84: %f52 (f52) + 85: %f53 (f53) + 86: %f54 (f54) + 87: %f55 (f55) + 88: %f56 (f56) + 89: %f57 (f57) + 90: %f58 (f58) + 91: %f59 (f59) + 92: %f60 (f60) + 93: %f61 (f61) + 94: %f62 (f62) + 95: %f63 (f63) +EOF + exit 0 |