1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
|
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __CCI_H__
#define __CCI_H__
/* Slave interface offsets from PERIPHBASE */
#define SLAVE_IFACE6_OFFSET 0x7000
#define SLAVE_IFACE5_OFFSET 0x6000
#define SLAVE_IFACE4_OFFSET 0x5000
#define SLAVE_IFACE3_OFFSET 0x4000
#define SLAVE_IFACE2_OFFSET 0x3000
#define SLAVE_IFACE1_OFFSET 0x2000
#define SLAVE_IFACE0_OFFSET 0x1000
#define SLAVE_IFACE_OFFSET(index) (SLAVE_IFACE0_OFFSET + \
(0x1000 * (index)))
/* Slave interface event and count register offsets from PERIPHBASE */
#define EVENT_SELECT7_OFFSET 0x80000
#define EVENT_SELECT6_OFFSET 0x70000
#define EVENT_SELECT5_OFFSET 0x60000
#define EVENT_SELECT4_OFFSET 0x50000
#define EVENT_SELECT3_OFFSET 0x40000
#define EVENT_SELECT2_OFFSET 0x30000
#define EVENT_SELECT1_OFFSET 0x20000
#define EVENT_SELECT0_OFFSET 0x10000
#define EVENT_OFFSET(index) (EVENT_SELECT0_OFFSET + \
(0x10000 * (index)))
/* Control and ID register offsets */
#define CTRL_OVERRIDE_REG 0x0
#define SECURE_ACCESS_REG 0x8
#define STATUS_REG 0xc
#define IMPRECISE_ERR_REG 0x10
#define PERFMON_CTRL_REG 0x100
#define IFACE_MON_CTRL_REG 0x104
/* Component and peripheral ID registers */
#define PERIPHERAL_ID0 0xFE0
#define PERIPHERAL_ID1 0xFE4
#define PERIPHERAL_ID2 0xFE8
#define PERIPHERAL_ID3 0xFEC
#define PERIPHERAL_ID4 0xFD0
#define PERIPHERAL_ID5 0xFD4
#define PERIPHERAL_ID6 0xFD8
#define PERIPHERAL_ID7 0xFDC
#define COMPONENT_ID0 0xFF0
#define COMPONENT_ID1 0xFF4
#define COMPONENT_ID2 0xFF8
#define COMPONENT_ID3 0xFFC
#define COMPONENT_ID4 0x1000
#define COMPONENT_ID5 0x1004
#define COMPONENT_ID6 0x1008
#define COMPONENT_ID7 0x100C
/* Slave interface register offsets */
#define SNOOP_CTRL_REG 0x0
#define SH_OVERRIDE_REG 0x4
#define READ_CHNL_QOS_VAL_OVERRIDE_REG 0x100
#define WRITE_CHNL_QOS_VAL_OVERRIDE_REG 0x104
#define MAX_OT_REG 0x110
/* Snoop Control register bit definitions */
#define DVM_EN_BIT (1 << 1)
#define SNOOP_EN_BIT (1 << 0)
#define SUPPORT_SNOOPS (1 << 30)
#define SUPPORT_DVM (1 << 31)
/* Status register bit definitions */
#define CHANGE_PENDING_BIT (1 << 0)
/* Event and count register offsets */
#define EVENT_SELECT_REG 0x0
#define EVENT_COUNT_REG 0x4
#define COUNT_CNTRL_REG 0x8
#define COUNT_OVERFLOW_REG 0xC
/* Slave interface monitor registers */
#define INT_MON_REG_SI0 0x90000
#define INT_MON_REG_SI1 0x90004
#define INT_MON_REG_SI2 0x90008
#define INT_MON_REG_SI3 0x9000C
#define INT_MON_REG_SI4 0x90010
#define INT_MON_REG_SI5 0x90014
#define INT_MON_REG_SI6 0x90018
/* Master interface monitor registers */
#define INT_MON_REG_MI0 0x90100
#define INT_MON_REG_MI1 0x90104
#define INT_MON_REG_MI2 0x90108
#define INT_MON_REG_MI3 0x9010c
#define INT_MON_REG_MI4 0x90110
#define INT_MON_REG_MI5 0x90114
#define SLAVE_IF_UNUSED -1
#if ARM_CCI_PRODUCT_ID == 400
#define CCI_SLAVE_INTERFACE_COUNT 5
#elif ARM_CCI_PRODUCT_ID == 500
#define CCI_SLAVE_INTERFACE_COUNT 7
#else
#error "Invalid CCI product or CCI not supported"
#endif
#ifndef __ASSEMBLY__
#include <stdint.h>
/* Function declarations */
/*
* The ARM CCI driver needs the following:
* 1. Base address of the CCI-500/CCI-400
* 2. An array of map between AMBA 4 master ids and ACE/ACE lite slave
* interfaces.
* 3. Size of the array.
*
* SLAVE_IF_UNUSED should be used in the map to represent no AMBA 4 master exists
* for that interface.
*/
void cci_init(unsigned long cci_base,
const int *map,
unsigned int num_cci_masters);
void cci_enable_snoop_dvm_reqs(unsigned int master_id);
void cci_disable_snoop_dvm_reqs(unsigned int master_id);
#endif /* __ASSEMBLY__ */
#endif /* __CCI_H__ */
|
