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* fix(spmd): fix build error with spmdGovindraj Raja2023-05-105-9/+9
| | | | | | | | | | | | | Currently when we build with 'SPD=spmd SPMD_SPM_AT_SEL2=0' options, this causes a build failure as 'plat_spmd_handle_group0_interrupt' is called irrespective of 'SPMD_SPM_AT_SEL2' usage in 'spmd_group0_interrupt_handler_nwd' So make 'plat_spmd_handle_group0_interrupt' dummy implementation available just when spmd is enabled and SPMC_AT_EL3 is disabled. Change-Id: Iaccd38faab81671c98f9165f318145187dca9bc2 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
* Merge changes I5bb43cb0,I6aebe2ca,Ib59df16a,I9d037ab2,I9df5a465, ... into ↵Manish V Badarkhe2023-05-097-28/+50
|\ | | | | | | | | | | | | | | | | | | | | | | | | integration * changes: fix(msm8916): add timeout for crash console TX flush style(msm8916): use size macros feat(msm8916): expose more timer frames fix(msm8916): drop unneeded initialization of CNTACR build(msm8916): disable unneeded workarounds fix(msm8916): flush dcache after writing msm8916_entry_point fix(msm8916): print \r before \n on UART console
| * fix(msm8916): add timeout for crash console TX flushStephan Gerhold2023-05-092-14/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Resetting the UART DM controller while there are still remaining characters in the FIFO often results in corruption on the UART receiver side. To avoid this the msm8916 crash console implementation tries to wait until the TX FIFO is empty. Unfortunately this might spin forever if the transmitter was disabled before it has fully finished transmitting. In this case the TXEMT bit console_uartdm_core_flush is waiting for will never get set. There seems to be no good way to detect if the transmitter is actually enabled via the status registers. However, the TX FIFO is fairly small and should not take too long to get flushed, so fix this by simply limiting the amount of iterations with a short timeout. Move the code to console_uartdm_core_init to ensure that this always happens before resetting the transmitter (also during initialization). Change-Id: I5bb43cb0b6c029bcd15e253d60d36c0b310e108b Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
| * style(msm8916): use size macrosStephan Gerhold2023-05-092-5/+5
| | | | | | | | | | | | | | | | Use the pre-defined size macros (SZ_*) for more clarity and to avoid having to add comments to each size represented by hexadecimal numbers. Change-Id: I6aebe2caf1365279670955b9b507dec7d7b04457 Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
| * feat(msm8916): expose more timer framesStephan Gerhold2023-05-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The memory-mapped generic timer on msm8916 has 7 timer frames, but currently only one is exposed for usage in the non-secure world. The platform port is currently only designed to be used as minimal PSCI implementation, without secure world that could make use of the other timer frames. Let's make all of them available to the normal world. If needed this could still be changed later by reserving some timer frames conditionally to a specific SPD being enabled in the build. Change-Id: Ib59df16aa1fd3dbc875ab6369c133737830c98c6 Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
| * fix(msm8916): drop unneeded initialization of CNTACRStephan Gerhold2023-05-091-5/+1
| | | | | | | | | | | | | | | | | | | | | | Normal world software is responsible to initialize CNTACR as needed. There is no existing software for msm8916 that depends on having this initialization in BL31 so drop it before anything starts to rely on it. Related issue: https://github.com/ARM-software/tf-issues/issues/170 Change-Id: I9d037ab218c0c1c8a5d5523722013eba531f4728 Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
| * build(msm8916): disable unneeded workaroundsStephan Gerhold2023-05-091-1/+5
| | | | | | | | | | | | | | | | | | The Cortex-A53 cores used in the msm8916 platform are not affected by CVE-2017-5715 and CVE-2022-23960, so disable the workarounds for them to drop the unused code from the compiled binary. Change-Id: I9df5a4657c4fd90702b4db4e82d4ee1a2f60303c Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
| * fix(msm8916): flush dcache after writing msm8916_entry_pointStephan Gerhold2023-05-091-1/+9
| | | | | | | | | | | | | | | | | | msm8916_entry_point is read with caches off (and even from two different physical addresses when read through the "boot remapper"), so it should be flushed to RAM after writing it. Change-Id: I5c8193954bb28043b0a46fb2038f629bd8796c74 Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
| * fix(msm8916): print \r before \n on UART consoleStephan Gerhold2023-05-091-1/+12
| | | | | | | | | | | | | | | | | | UART drivers in TF-A are expected to print \r before \n. Some terminal emulators expect \r\n as line endings by default so not doing this causes broken line breaks. Change-Id: I271a35a7c6907441bc71713b0b6a1da19da96878 Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
* | Merge changes I1bfa797e,I0ec7a70e into integrationManish Pandey2023-05-0959-65/+65
|\ \ | | | | | | | | | | | | | | | * changes: fix(tree): correct some typos fix(rockchip): use semicolon instead of comma
| * | fix(tree): correct some typosElyes Haouas2023-05-0958-64/+64
| | | | | | | | | | | | | | | | | | | | | found using codespell (https://github.com/codespell-project/codespell). Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373
| * | fix(rockchip): use semicolon instead of commaElyes Haouas2023-05-091-1/+1
| | | | | | | | | | | | | | | | | | | | | Use semicolon insted of comma at the end of line. Change-Id: I0ec7a70ec659333c98d586f7bebd5d91bd6c6cc1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
* | | Merge changes from topic "mp/feat_ras" into integrationManish Pandey2023-05-0915-19/+25
|\ \ \ | |_|/ |/| | | | | | | | | | | * changes: refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED refactor(ras): replace RAS_EXTENSION with FEAT_RAS
| * | refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKEDAndre Przywara2023-05-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_RAS to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (FEAT_RAS=2), by splitting is_armv8_2_feat_ras_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access RAS related registers. Also move the context saving code from assembly to C, and use the new is_feat_ras_supported() function to guard its execution. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I30498f72fd80b136850856244687400456a03d0e Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
| * | refactor(ras): replace RAS_EXTENSION with FEAT_RASManish Pandey2023-05-0915-19/+24
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current usage of RAS_EXTENSION in TF-A codebase is to cater for two things in TF-A : 1. Pull in necessary framework and platform hooks for Firmware first handling(FFH) of RAS errors. 2. Manage the FEAT_RAS extension when switching the worlds. FFH means that all the EAs from NS are trapped in EL3 first and signaled to NS world later after the first handling is done in firmware. There is an alternate way of handling RAS errors viz Kernel First handling(KFH). Tying FEAT_RAS to RAS_EXTENSION build flag was not correct as the feature is needed for proper handling KFH in as well. This patch breaks down the RAS_EXTENSION flag into a flag to denote the CPU architecture `ENABLE_FEAT_RAS` which is used in context management during world switch and another flag `RAS_FFH_SUPPORT` to pull in required framework and platform hooks for FFH. Proper support for KFH will be added in future patches. BREAKING CHANGE: The previous RAS_EXTENSION is now deprecated. The equivalent functionality can be achieved by the following 2 options: - ENABLE_FEAT_RAS - RAS_FFH_SUPPORT Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I1abb9ab6622b8f1b15712b12f17612804d48a6ec
* | Merge changes from topic "srm/Errata_ABI_El3" into integrationMadhukar Pappireddy2023-05-092-0/+65
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | * changes: docs(errata_abi): document the errata abi changes feat(fvp): enable errata management interface fix(cpus): workaround platforms non-arm interconnect refactor(errata_abi): factor in non-arm interconnect feat(errata_abi): errata management firmware interface
| * | feat(fvp): enable errata management interfaceSona Mathew2023-05-052-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Errata ABI feature specific build flag, flag to enable CPUs in the cpu list, flags to test non-arm interconnect based errata flags when enabled from a platform level. Added to the FVP platform makefile to test the errata abi feature implementation. The flags to enable CPUs in the cpu list will be removed once synchronized with the errata framework. Change-Id: I30877a22ac1348906a6ddfb26f9e8839912d3572 Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
* | | Merge "fix(qemu-sbsa): enable FGT" into integrationBipin Ravi2023-05-091-0/+3
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| * | | fix(qemu-sbsa): enable FGTMarcin Juszkiewicz2023-04-281-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QEMU 7.2+ has FEAT_FGT support added to 'max' cpu. So let's enable it to make Debian 'bookworm' kernel boot on sbsa-ref/max setup. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Change-Id: I49fb3e742b69ce7be5666e0144525dde21a68238
* | | | Merge "feat(mt8188): add MT8188 SPM debug logs" into integrationManish Pandey2023-05-098-11/+86
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| * | | feat(mt8188): add MT8188 SPM debug logsJason Chen2023-05-088-11/+86
| | |/ | |/| | | | | | | | | | | | | | | | Add debug logs for tracking the status of suspend and resume. Change-Id: Id2d2ab06fadb3118ab66f816937e0dd6e43dbdc3 Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com>
* | | Merge changes from topic "assert_boolean_set" into integrationManish Pandey2023-05-092-2/+6
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: build!: check boolean flags are not empty fix(build): add a default value for INVERTED_MEMMAP fix(a5ds): add default value for ARM_DISABLE_TRUSTED_WDOG fix(st-crypto): move flag control into source code fix(stm32mp1): always define PKA algos flags fix(stm32mp1): remove boolean check on PLAT_TBBR_IMG_DEF
| * | | fix(a5ds): add default value for ARM_DISABLE_TRUSTED_WDOGManish Pandey2023-05-031-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With introduction of check on boolean flags, it should be ensured that each boolean flag has default value provided by platform. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ia92c3dded842e14099b4a7667569605d7066a8f9
| * | | fix(stm32mp1): always define PKA algos flagsYann Gautier2023-05-031-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The flags to set PKA algo are set to 0 when TRUSTED_BOARD_BOOT is not set. Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: Ib70a2bc51451a2047d7a50a8307e9063d4a2a0ee
| * | | fix(stm32mp1): remove boolean check on PLAT_TBBR_IMG_DEFYann Gautier2023-05-031-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This flag just needs to be defined, and does not need to have a boolean value. Remove it from the assert_booleans check. Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: I4e4c9ae1e5003ca2cf7c0c0e31d1561d032937c8
* | | | Merge "feat(fvp): introduce PLATFORM_TEST_RAS_FFH config" into integrationManish Pandey2023-05-093-3/+72
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| * | | feat(fvp): introduce PLATFORM_TEST_RAS_FFH configManish Pandey2023-05-043-3/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While doing RAS related tests there were few patches related with fault injection and handling were applied through CI hooks. These patches were invisible as they were applied and removed after the build is done. This patch introduces build macro PLATFORM_TEST_RAS_FFH and moves the patches applied through CI under this. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Iddba52f3ebf21f575a473e50c607a944391156b9
* | | | feat(tc): allow secure watchdog timer to trigger periodicallyMadhukar Pappireddy2023-05-045-9/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch does the following: 1. Configures SBSA secure watchdog timer as Group0 interrupt for TC platform while keeping it as Group1 secure interrupt for other CSS based SoCs. 2. Programs the watchdog timer to trigger periodically 3. Provides a Group0 interrupt handler for TC platform port to deactivate the EL3 interrupt due to expiry of secure watchdog timer and refresh it explicitly. Change-Id: I3847d6eb7347c6ea0e527b97b096119ca1e6701b Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | | | Merge "feat(fvp): define ns memory in the SPMC manifest" into integrationMadhukar Pappireddy2023-05-042-9/+24
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| * | | | feat(fvp): define ns memory in the SPMC manifestJ-Alves2023-05-032-9/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPMC (Hafnium) looks for secure and non-secure ranges in its manifest. Those relate with ranges that can be used by SPs in their FF-A manifests. The NS memory that is not used by SPs will be assigned to the NWd, for it to share memory with SPs as needed. Thus, this limits the memory the NWd can share with SPs, to prevent NWD VMs from sharing memory that belongs to other critical components. Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: Iad03eb138a57068fbb18c53141bdf6bf9c171b28
* | | | | Merge changes from topic "allwinner_t507" into integrationMadhukar Pappireddy2023-05-0412-129/+185
|\ \ \ \ \ | |_|/ / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: feat(allwinner): add support for Allwinner T507 SoC feat(allwinner): add function to detect H616 die variant feat(allwinner): add extra CPU control registers refactor(allwinner): consolidate sunxi_cfg.h files
| * | | | feat(allwinner): add support for Allwinner T507 SoCMikhail Kalashnikov2023-04-262-30/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner T507 SoC is using the same die as the H616, but in a different package. On top of this, there is at least one different die revision out there, which uses a different CPU cluster control block. The same die revision has been spotted in some, but not all, H313 SoCs. Apart from that IP block, the rest of the SoC seems the same, so we can support them using the existing H616 port. The die revision can be auto-detected, so there is no extra build option or knowledge needed. Provide the deviating CPU power up/down sequence for the die variant. The new IP block uses per-core instead of per-cluster registers, but follows the same pattern otherwise. Since the CPU ops code is shared among all Allwinner SoCs, we need to dummy-define the new register names for the older SoCs. The actual new code is guarded by a predicate function, that is hard coded to return true on the other SoCs. Since this is a static inline function in a header file, the compiler will optimise away the unneeded branch there, so the generated code for the other SoCs stays the same. Change-Id: Ib5ade99d34b4ccb161ccde0e34f280ca6bd16ecd Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | | feat(allwinner): add function to detect H616 die variantAndre Przywara2023-04-266-1/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner provides a number of SoCs that use the same die as the H616. Some of those chips apparently use a slight variation of that die, that differs in the way the CPU cores' power and reset controls are handled. This die variation can be detected by reading the SRAM version register. Provide a predicate function that returns false if that die variant is used. Since the CPU power control code is shared for all supported SoCs, we provide an instance of this function for each SoC, as a static inline, and return true on all other SoCs. This allows to always use this function, and still let the compiler optimise away the unneeded branch for those older SoCs. This function is unused for now, but is needed in the next patch. Change-Id: I49e014b895b7e2f55b4e7dc2b3d8aa31cee711b5 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | | feat(allwinner): add extra CPU control registersMikhail Kalashnikov2023-04-263-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The die used in several variants of the Allwinner H616 SoC (H313, T507) seems to produced in at least two revisions. The newer one differs from the original by using a different CPU control register IP block. Add those newly used register offsets to the respective header file. The MMIO block itself is actually present in both variants, though the registers are different. The new registers tend to use one register per core, in contrast to one register per cluster in the older revisions. Change-Id: Ifbda1bdc67a6a16fbb901dbc83996e4a148b7602 Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | | refactor(allwinner): consolidate sunxi_cfg.h filesAndre Przywara2023-04-265-101/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The header files describing the CPU cluster configuration IP block for the H6 and H616 are actually identical, so merge them into one file and move that to a common location. There is an upcoming SoC which will similarly share a header file with the R329 SoC, so move that to the same location already. In Allwinner's BSP source those two SoC groups are typically called "NCAT" and "NCAT2", so use those names for the shared header files. No functional change. Change-Id: I98318373577344dbe228a81fa331ce660df32b5f Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | | | Merge "fix(tc): only suspend booting after running plat tests" into integrationSandrine Bailleux2023-05-041-1/+3
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| * | | | | fix(tc): only suspend booting after running plat testslaurenw-arm2023-05-041-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. When doing a normal boot, tc_bl31_common_platform_setup() should simply configure the platform and return. 2. When we are running the platform tests instead, tc_bl31_common_platform_setup() should run the tests then suspend booting (and thus never return). We were incorreclty suspending the boot in case 1 as well. Put that code under a preprocessor condition (PLATFORM_TEST_NV_COUNTERS or PLATFORM_TEST_TFM_TESTSUITE) to fix this. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I7d20800e3bcd85261e2cdad325586d184e12a3e3
* | | | | | Merge changes from topic "mp/group0_support" into integrationOlivier Deprez2023-05-037-2/+73
|\ \ \ \ \ \ | |/ / / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: docs(spm): support for handling Group0 interrupts feat(spmd): introduce platform handler for Group0 interrupt feat(spmd): add support for FFA_EL3_INTR_HANDLE_32 ABI feat(spmd): register handler for group0 interrupt from NWd
| * | | | | feat(spmd): introduce platform handler for Group0 interruptMadhukar Pappireddy2023-05-017-2/+73
| | |/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a handler for FVP platform to triage Group0 secure interrupts. Currently, it is empty but serves as a placeholder for future Group0 interrupt sources. Moreover, this patch also provides a dummy implementation of the above mentioned platform hook for QEMU, corstone100, n1sdp and hikey960 ports. Change-Id: I01d3451408f47ac313b0af74046cce89f89b85bb Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | | | | Merge changes I9d06e0ee,I6980e84f into integrationManish Pandey2023-05-037-7/+68
|\ \ \ \ \ | |_|_|/ / |/| | | | | | | | | | | | | | | | | | | * changes: feat(tegra): implement 'pwr_domain_off_early' handler feat(psci): introduce 'pwr_domain_off_early' hook
| * | | | feat(tegra): implement 'pwr_domain_off_early' handlerVarun Wadekar2023-04-267-7/+68
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements the pwr_domain_off_early handler for Tegra platforms. Powering off the boot core on some Tegra platforms is not allowed and the SOC specific helper functions for Tegra194, Tegra210 and Tegra186 implement this restriction. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I9d06e0eee12314764adb0422e023a5bec6ed9c1e
* | | | Merge "feat(xilinx): sync copyright format" into integrationJoanna Farley2023-05-0213-14/+14
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| * | | | feat(xilinx): sync copyright formatMichal Simek2023-04-2613-14/+14
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | Use the same format in all files 's/Copyright (C)/Copyright (c)/g'. Change-Id: I0e200eb135e7369d0e6b3b694acd406ec10ca9e7 Signed-off-by: Michal Simek <michal.simek@amd.com>
* | | | Merge "build: deprecate Arm rde1edge" into integrationManish V Badarkhe2023-05-021-1/+4
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| * | | | build: deprecate Arm rde1edgeManish V Badarkhe2023-04-201-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Arm has decided to deprecate the rde1edge platform. The development of software and fast model for this platform have been discontinued. Hence, updated the makefile to warn about the deprecation of this platform, and also reflected it in the documentation. Change-Id: I0d44de4590dd5dce02c7c4b433df25dc438e6c49 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
* | | | | Merge "fix(sme): disable SME for SPD=spmd" into integrationManish Pandey2023-05-021-1/+3
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| * | | | | fix(sme): disable SME for SPD=spmdJayanth Dodderi Chidanand2023-04-281-1/+3
| | |/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPMD is not compatible with ENABLE_SME_FOR_NS. Hence disable SME when SPD=spmd Change-Id: I8bcf2493819718732563f9db69f7186ac7437637 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* | | | | Merge changes Ia1142b31,I424f1cde into integrationSandrine Bailleux2023-05-025-10/+10
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: fix(tc): enable the execution of both platform tests fix(tc): update the name of mbedtls config header
| * | | | | fix(tc): enable the execution of both platform testsTamas Ban2023-04-274-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The C preprocessor cannot compare defines against strings. Such an expression is always evaluated to be true. Therefore, its usage in a conditional expression results that always the first branch is taken. Other branches cannot be reached by any configuration value. The fix removes this string comparison and instead it introduces distinct defines for all the cases. Signed-off-by: Tamas Ban <tamas.ban@arm.com> Change-Id: Ia1142b31b6778686c74e1e882fe4604fe3b6501d
| * | | | | fix(tc): update the name of mbedtls config headerTamas Ban2023-04-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recently mbedtls_cofig.h was renamed to: - mbedtls_config-2.h - mbedtls_config-3.h Modify the include order to resolve the static check failure in the CI. Signed-off-by: Tamas Ban <tamas.ban@arm.com> Change-Id: I424f1cde199397b8df780a9514f1042e601c6502
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