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* Merge changes from topic "mp/feat_ras" into integrationManish Pandey2023-05-092-2/+8
|\ | | | | | | | | | | * changes: refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED refactor(ras): replace RAS_EXTENSION with FEAT_RAS
| * refactor(ras): replace RAS_EXTENSION with FEAT_RASManish Pandey2023-05-092-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current usage of RAS_EXTENSION in TF-A codebase is to cater for two things in TF-A : 1. Pull in necessary framework and platform hooks for Firmware first handling(FFH) of RAS errors. 2. Manage the FEAT_RAS extension when switching the worlds. FFH means that all the EAs from NS are trapped in EL3 first and signaled to NS world later after the first handling is done in firmware. There is an alternate way of handling RAS errors viz Kernel First handling(KFH). Tying FEAT_RAS to RAS_EXTENSION build flag was not correct as the feature is needed for proper handling KFH in as well. This patch breaks down the RAS_EXTENSION flag into a flag to denote the CPU architecture `ENABLE_FEAT_RAS` which is used in context management during world switch and another flag `RAS_FFH_SUPPORT` to pull in required framework and platform hooks for FFH. Proper support for KFH will be added in future patches. BREAKING CHANGE: The previous RAS_EXTENSION is now deprecated. The equivalent functionality can be achieved by the following 2 options: - ENABLE_FEAT_RAS - RAS_FFH_SUPPORT Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I1abb9ab6622b8f1b15712b12f17612804d48a6ec
* | Merge changes from topic "srm/Errata_ABI_El3" into integrationMadhukar Pappireddy2023-05-091-0/+6
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | * changes: docs(errata_abi): document the errata abi changes feat(fvp): enable errata management interface fix(cpus): workaround platforms non-arm interconnect refactor(errata_abi): factor in non-arm interconnect feat(errata_abi): errata management firmware interface
| * | refactor(errata_abi): factor in non-arm interconnectSona Mathew2023-05-051-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Workaround to help enable the kernel to query errata status using the errata abi feature for platforms with a non-arm interconnect. Change-Id: I47b03eaee5a0a763056ae71883fa30dfacb9b3f7 Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
| * | feat(errata_abi): errata management firmware interfaceSona Mathew2023-05-051-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the errata management firmware interface for lower ELs to discover details about CPU erratum. Based on the CPU erratum identifier the interface enables the OS to find the mitigation of an erratum in EL3. The ABI can only be present in a system that is compliant with SMCCCv1.1 or higher. This implements v1.0 of the errata ABI spec. For details on all possible return values, refer the design documentation below: ABI design documentation: https://developer.arm.com/documentation/den0100/1-0?lang=en Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com> Change-Id: I70f0e2569cf92e6e02ad82e3e77874546232b89a
* | | Merge changes from topic "bk/context_refactor" into integrationManish V Badarkhe2023-05-091-8/+0
|\ \ \ | |_|/ |/| | | | | | | | | | | * changes: fix(gicv3): restore scr_el3 after changing it refactor(cm): make SVE and SME build dependencies logical
| * | refactor(cm): make SVE and SME build dependencies logicalBoyan Karatotev2023-05-051-8/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, enabling SME forces SVE off. However, the SME enablement requires SVE to be enabled, which is reflected in code. This is the opposite of what the build flags require. Further, the few platforms that enable SME also explicitly enable SVE. Their platform.mk runs after the defaults.mk file so this override never materializes. As a result, the override is only present on the commandline. Change it to something sensible where if SME is on then code can rely on SVE being on too. Do this with a check in the Makefile as it is the more widely used pattern. This maintains all valid use cases but subtly changes corner cases no one uses at the moment to require a slightly different combination of flags. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: If7ca3972ebc3c321e554533d7bc81af49c2472be
* | Merge changes from topic "assert_boolean_set" into integrationManish Pandey2023-05-091-0/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: build!: check boolean flags are not empty fix(build): add a default value for INVERTED_MEMMAP fix(a5ds): add default value for ARM_DISABLE_TRUSTED_WDOG fix(st-crypto): move flag control into source code fix(stm32mp1): always define PKA algos flags fix(stm32mp1): remove boolean check on PLAT_TBBR_IMG_DEF
| * | build!: check boolean flags are not emptyYann Gautier2023-05-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | For numeric flags, there is a check for the value to be set. Do the same for boolean flags. This avoids issues where a flag is defined but without a value, leading to potential unexpected behaviors. Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: Ib00da2784339471058887e93434d96ccba2aebb2
* | | fix(build): allow lower address access with gcc-12Govindraj Raja2023-05-091-0/+6
| |/ |/| | | | | | | | | | | | | | | | | | | | | With gcc-12 any lower address access can trigger a warning/error this would be useful in other parts of system but in TF-A there are various reasons to access to the lower address ranges, example using mmio_read_*/writes_* So setup to allow access to lower addresses while using gcc-12 Change-Id: Id1b4012b13bc6876d83b90a347fee12478a1921d Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
* | build: allow BL-specific includes/definitionsChris Kay2023-05-031-3/+12
|/ | | | | | | | | | This change introduces the `BLx_INCLUDE_DIRS` and `BLx_DEFINES` Makefile variables, which can be used to append include directories and preprocessor definitions to specific images created using the `MAKE_BL` Makefile macro. Change-Id: I9431f9d1cbde5b0b2624d9ce128a4f043c74c87f Signed-off-by: Chris Kay <chris.kay@arm.com>
* Merge "feat(el3-runtime): handle traps for IMPDEF registers accesses" into ↵Manish Pandey2023-05-021-0/+3
|\ | | | | | | integration
| * feat(el3-runtime): handle traps for IMPDEF registers accessesVarun Wadekar2023-04-301-0/+3
| | | | | | | | | | | | | | | | | | This patch introduces support to handle traps from lower ELs for IMPDEF system register accesses. The actual support is left to the platforms to implement. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I623d5c432b4ce4328b68f238c15b1c83df97c1e5
* | feat(sme): enable SME2 functionality for NS worldJayanth Dodderi Chidanand2023-04-271-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FEAT_SME2 is an extension of FEAT_SME and an optional feature from v9.2. Its an extension of SME, wherein it not only processes matrix operations efficiently, but also provides outer-product instructions to accelerate matrix operations. It affords instructions for multi-vector operations. Further, it adds an 512 bit architectural register ZT0. This patch implements all the changes introduced with FEAT_SME2 to ensure that the instructions are allowed to access ZT0 register from Non-secure lower exception levels. Additionally, it adds support to ensure FEAT_SME2 is aligned with the existing FEATURE DETECTION mechanism, and documented. Change-Id: Iee0f61943304a9cfc3db8f986047b1321d0a6463 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* | feat(gcs): support guarded control stackMark Brown2023-04-181-0/+3
|/ | | | | | | | | | | | | | Arm v9.4 introduces support for Guarded Control Stack, providing mitigations against some forms of RPO attacks and an efficient mechanism for obtaining the current call stack without requiring a full stack unwind. Enable access to this feature for EL2 and below, context switching the newly added EL2 registers as appropriate. Change the FVP platform to default to handling this as a dynamic option so the right decision can be made by the code at runtime. Signed-off-by: Mark Brown <broonie@kernel.org> Change-Id: I691aa7c22e3547bb3abe98d96993baf18c5f0e7b
* feat(pie/por): support permission indirection and overlayMark Brown2023-04-121-0/+12
| | | | | | | | | | | | | | | | | | | Arm v8.9 introduces a series of features providing a new way to set memory permissions. Instead of directly encoding the permissions in the page tables the PTEs contain indexes into an array of permissions stored in system registers, allowing greater flexibility and density of encoding. Enable access to these features for EL2 and below, context switching the newly added EL2 registers as appropriate. Since all of FEAT_S[12]P[IO]E are separately discoverable we have separate build time options for enabling them, but note that there is overlap in the registers that they implement and the enable bit required for lower EL access. Change the FVP platform to default to handling them as dynamic options so the right decision can be made by the code at runtime. Signed-off-by: Mark Brown <broonie@kernel.org> Change-Id: Icf89e444e39e1af768739668b505661df18fb234
* Merge changes from topic "mb/rst-to-bl31-update" into integrationManish V Badarkhe2023-04-111-3/+0
|\ | | | | | | | | | | | | | | * changes: docs: update RESET_TO_BL31 documentation fix(bl31): avoid clearing of argument registers in RESET_TO_BL31 case Revert "docs(bl31): aarch64: RESET_TO_BL31_WITH_PARAMS" Revert "feat(bl31): aarch64: RESET_TO_BL31_WITH_PARAMS"
| * Revert "feat(bl31): aarch64: RESET_TO_BL31_WITH_PARAMS"Manish V Badarkhe2023-03-091-3/+0
| | | | | | | | | | | | | | | | | | Adopted RESET_TO_BL31_WITH_PARAMS functionality in RESET_TO_BL31 in the subsequent patches hence reverted this patch. This reverts commit 25844ff728e4a0e5430ba2032457aba7b780a701. Change-Id: Ia0bfa22fc45754f15c82638662dde93f604992c3 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
* | feat(cpufeat): enable FEAT_SVE for FEAT_STATE_CHECKEDJayanth Dodderi Chidanand2023-03-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for runtime detection (ENABLE_SVE_FOR_NS=2), by splitting sve_supported() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we do SVE specific setup. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I1caaba2216e8e2a651452254944a003607503216 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* | feat(cpufeat): enable FEAT_SME for FEAT_STATE_CHECKEDJayanth Dodderi Chidanand2023-03-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for runtime detection (ENABLE_SME_FOR_NS=2), by splitting feat_sme_supported() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we do SME specific setup. Change the FVP platform default to the now supported dynamic option (=2),so the right decision can be made by the code at runtime. Change-Id: Ida9ccf737db5be20865b84f42b1f9587be0626ab Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* | Merge changes from topic "psci-osi" into integrationManish Pandey2023-03-281-0/+3
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: feat(sc7280): add support for PSCI_OS_INIT_MODE feat(fvp): enable support for PSCI OS-initiated mode feat(psci): update PSCI_FEATURES feat(psci): add support for OS-initiated mode feat(psci): add support for PSCI_SET_SUSPEND_MODE build(psci): add build option for OS-initiated mode docs(psci): add design proposal for OS-initiated mode
| * | build(psci): add build option for OS-initiated modeWing Li2023-03-201-0/+3
| | | | | | | | | | | | | | | Change-Id: Ie4f7b6a36926ab075ebb9c6507a3ff48ce5538fe Signed-off-by: Wing Li <wingers@google.com>
* | | refactor(amu): unify ENABLE_AMU and ENABLE_FEAT_AMUv1Andre Przywara2023-03-271-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far we have the ENABLE_AMU build option to include AMU register handling code for enabling and context switch. There is also an ENABLE_FEAT_AMUv1 option, solely to protect the HAFGRTR_EL2 system register handling. The latter needs some alignment with the new feature scheme, but it conceptually overlaps with the ENABLE_AMU option. Since there is no real need for two separate options, unify both into a new ENABLE_FEAT_AMU name in a first step. This is mostly just renaming at this point, a subsequent patch will make use of the new feature handling scheme. Change-Id: I97d8a55bdee2ed1e1509fa9f2b09fd0bdd82736e Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | Merge changes from topic "feat_state_part3" into integrationManish Pandey2023-03-201-2/+2
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: refactor(cpufeat): enable FEAT_VHE for FEAT_STATE_CHECKED refactor(mpam): enable FEAT_MPAM for FEAT_STATE_CHECKED feat(libc): add support for fallthrough statement refactor(spe): enable FEAT_SPE for FEAT_STATE_CHECKED refactor(cpufeat): rename ENABLE_SPE_FOR_LOWER_ELS to ENABLE_SPE_FOR_NS fix(spe): drop SPE EL2 context switch code
| * | | refactor(spe): enable FEAT_SPE for FEAT_STATE_CHECKEDAndre Przywara2023-03-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_SPE to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_SPE_FOR_NS=2), by splitting is_armv8_2_feat_spe_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access SPE related registers. Previously SPE was enabled unconditionally for all platforms, change this now to the runtime detection version. Change-Id: I830c094107ce6a398bf1f4aef7ffcb79d4f36552 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | refactor(cpufeat): rename ENABLE_SPE_FOR_LOWER_ELS to ENABLE_SPE_FOR_NSAndre Przywara2023-03-201-2/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we hardcode the SPE functionality to be available on the non-secure side only, by setting MDCR_EL2.E2PB accordingly. This should be reflected in the feature selection symbol, so rename that to ENABLE_SPE_FOR_NS, to make it clearer that SPE is not supported in the secure world. Change-Id: I3f9b48eab1a45d6ccfcbb9c90a11eeb66867ad9a Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | Merge changes from topic "bk/errata_refactor" into integrationManish Pandey2023-03-201-1/+12
|\ \ \ | |/ / |/| | | | | | | | | | | | | | * changes: chore(fvp): add the aarch32 cortex A57 to the build chore(cpus): remove redundant asserts refactor(cpus): shorten errata flag defines
| * | refactor(cpus): shorten errata flag definesBoyan Karatotev2023-03-161-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cpu-ops makefile has errata flag definition and flag processing done per flag in separate parts in the file. Rework this to make a list and do this in a much more concise way. To ensure no flags were missed, a bash script [1] was used to verify all errata flags made it across. Only the first few flags with different naming were checked manually. [1]: sed -n "s/CPU_FLAG_LIST += ERRATA_\(.*\)/\1/p" lib/cpus/cpu-ops.mk > \ /tmp/new git checkout origin/master sed -n "s/ERRATA_\([[:alnum:]_-]*\)\s*?=0/\1/p" lib/cpus/cpu-ops.mk > \ /tmp/old diff /tmp/old /tmp/new Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I3b88af46838cc26f42d2c66b31f96c0855fa406c
* | | Merge "feat(tcr2): support FEAT_TCR2" into integrationManish Pandey2023-03-171-0/+3
|\ \ \
| * | | feat(tcr2): support FEAT_TCR2Mark Brown2023-03-161-0/+3
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Arm v8.9 introduces FEAT_TCR2, adding extended translation control registers. Support this, context switching TCR2_EL2 and disabling traps so lower ELs can access the new registers. Change the FVP platform to default to handling this as a dynamic option so the right decision can be made by the code at runtime. Signed-off-by: Mark Brown <broonie@kernel.org> Change-Id: I297452acd8646d58bac64fc15e05b06a543e5148
* | | Merge "refactor(build): distinguish BL2 as TF-A entry point and BL2 running ↵Manish Pandey2023-03-152-5/+5
|\ \ \ | |/ / |/| | | | | at EL3" into integration
| * | refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3Arvind Ram Prakash2023-03-152-5/+5
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BL2_AT_EL3 is an overloaded macro which has two uses: 1. When BL2 is entry point into TF-A(no BL1) 2. When BL2 is running at EL3 exception level These two scenarios are not exactly same even though first implicitly means second to be true. To distinguish between these two use cases we introduce new macros. BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2. Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where BL2 runs at EL3 (including four world systems). BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the repository. Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72 Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
* | build(makefile): add helper to detect linker optionsMarco Felsch2023-03-131-0/+6
|/ | | | | | | | | | | | | This is a small helper to check for possible linker options. If the linker supports the requested option it is returned and if not nothing will be returned, e.g.: TF_LDFLAGS += $(call ld_option, --no-warn-rwx-segments) can be called unconditional. Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Change-Id: I236800852ece49948ff53a0b91fddba53c8f0f95
* feat(build): allow additional CFLAGS for library buildGovindraj Raja2023-02-211-1/+2
| | | | | | | | | | | | | | | | | Current CFLAGS if set for library builds could impact entire build, so allow to pass additional CFLAGs for library builds based on format <LIBNAME>_CFLAGS. This support is currently needed to avoid 'redundant declaration' error from latest mbedtls-3.3, the issue is reported to mbedtls[1] and is under consideration to remove any redundant declarations. But till then we have to disable that compiler option while building for mbedtls-3.3 [1]: https://github.com/Mbed-TLS/mbedtls/issues/6910 Change-Id: Ic99af22b229f8089c82110d6545f762c14a62f5c Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
* build: permit multiple linker scriptsChris Kay2023-02-101-5/+15
| | | | | | | | | | | | | | | | | | This change allows platforms to provide more than one linker script to any image utilizing the `MAKE_BL` build system macro. This is already done by some MediaTek platforms via the `EXTRA_LINKERFILE` build system variable, which has now been removed. In its place, additional linker scripts may be added to the `<IMAGE>_LINKER_SCRIPT_SOURCES` variable. BREAKING-CHANGE: The `EXTRA_LINKERFILE` build system variable has been replaced with the `<IMAGE>_LINKER_SCRIPT_SOURCES` variable. See the commit message for more information. Change-Id: I3f0b69200d6a4841fd158cd09344ce9e67047271 Signed-off-by: Chris Kay <chris.kay@arm.com>
* build: clarify linker script generationChris Kay2023-02-101-15/+21
| | | | | | | | | | | | | | | | | | | | | | | | | The following build system variables have been renamed: - `LINKERFILE` -> `DEFAULT_LINKER_SCRIPT` - `BL_LINKERFILE` -> `DEFAULT_LINKER_SCRIPT_SOURCE` - `<IMAGE>_LINKERFILE` -> `<IMAGE>_DEFAULT_LINKER_SCRIPT_SOURCE` These new names better reflect how each variable is used: 1. the default linker script is passed via `-dT` instead of `-T` 2. linker script source files are first preprocessed Additionally, linker scripts are now placed in the build directory relative to where they exist in the source directory. For example, the `bl32/sp_min/sp_min.ld.S` would now preprocess to `sp_min/sp_min.ld` instead of just `bl32.ld` BREAKING-CHANGE: The `LINKERFILE`, `BL_LINKERFILE` and `<IMAGE_LINKERFILE>` build system variables have been renamed. See the commit message for more information. Change-Id: If8cef65dcb8820e8993736702c8741e97a66e6cc Signed-off-by: Chris Kay <chris.kay@arm.com>
* build: restrict usage of CTX_INCLUDE_EL2_REGSGovindraj Raja2022-12-011-3/+4
| | | | | | | | | | | CTX_INCLUDE_EL2_REGS is used to save/restore EL2 registers and it should be only used when there is SPMD or RME enabled. Make CTX_INCLUDE_EL2_REGS an internal macro and remove from documentation. Signed-off-by: Govindraj Raja <govindraj.raja@arm.com> Change-Id: I6a70edfd88163423ff0482de094601cf794246d6
* Merge "refactor(security): add OpenSSL 1.x compatibility" into integrationManish V Badarkhe2022-11-112-2/+16
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| * refactor(security): add OpenSSL 1.x compatibilityJuan Pablo Conde2022-11-112-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When updated to work with OpenSSL 3.0, the host tools lost their compatibility with previous versions (1.x) of OpenSSL. This is mainly due to the fact that 1.x APIs became deprecated in 3.0 and therefore their use cause compiling errors. In addition, updating for a newer version of OpenSSL meant improving the stability against security threats. However, although version 1.1.1 is now deprecated, it still receives security updates, so it would not imply major security issues to keep compatibility with it too. This patch adds backwards compatibility with OpenSSL 1.x versions by adding back 1.x API code. It defines a macro USING_OPENSSL3, which will select the appropriate OpenSSL API version depending on the OpenSSL library path chosen (which is determined by the already-existing OPENSSL_DIR variable). In addition, cleanup items were packed in functions and moved to the proper modules in order to make the code more maintainable and legible. Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com> Change-Id: I8deceb5e419edc73277792861882404790ccd33c
* | Merge "feat(cpus): make cache ops conditional" into integrationBipin Ravi2022-11-111-0/+4
|\ \
| * | feat(cpus): make cache ops conditionalOkash Khawaja2022-11-101-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a core is in debug recovery mode its caches are not invalidated upon reset, so the L1 and L2 cache contents from before reset are observable after reset. Similarly, debug recovery mode of DynamIQ cluster ensures that contents of the shared L3 cache are also not invalidated upon transition to On mode. Booting cores in debug recovery mode means booting with caches disabled and preserving the caches until a point where software can dump the caches and retrieve their contents. TF-A however unconditionally cleans and invalidates caches at multiple points during boot. This can lead to memory corruption as well as loss of cache contents to be used for debugging. This patch fixes this by calling a platform hook before performing CMOs in helper routines in cache_helpers.S. The platform hook plat_can_cmo is an assembly routine which must not clobber x2 and x3, and avoid using stack. The whole checking is conditional upon `CONDITIONAL_CMO` which can be set at compile time. Signed-off-by: Okash Khawaja <okash@google.com> Change-Id: I172e999e4acd0f872c24056e647cc947ee54b193
* | | Merge changes from topic "mp/ras_refactoring" into integrationOlivier Deprez2022-11-101-2/+2
|\ \ \ | |/ / |/| | | | | | | | | | | * changes: docs: document do_panic() and panic() helper functions fix(ras): restrict RAS support for NS world
| * | fix(ras): restrict RAS support for NS worldManish Pandey2022-11-081-2/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current RAS framework in TF-A only supports handling errors originating from NS world but the HANDLE_EA_EL3_FIRST flag configures it for all lower Els. To make the current design of RAS explicit, rename this macro to HANDLE_EA_EL3_FIRST_NS and set EA bit in scr_el3 only when switching to NS world. Note: I am unaware of any platform which traps errors originating in Secure world to EL3, if there is any such platform then it need to be explicitly implemented in TF-A Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: If58eb201d8fa792c16325c85c26056e9b409b750
* | refactor(trng): cleanup the existing TRNG supportJayanth Dodderi Chidanand2022-11-081-1/+1
|/ | | | | | | | | | | | | This patch adds the following changes to complete the existing TRNG implementation: 1. Adds a feature specific scope for buildlog generation. 2. Updates the docs on the build flag "TRNG_SUPPORT" and its values. 3. Makefile update and improves the existing comments at few sections for better understanding of the underlying logic. Change-Id: I3f72f0ccd5c94005a2df87158cf23199d2160d37 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* fix(ras): trap "RAS error record" accesses only for NSManish Pandey2022-09-281-2/+2
| | | | | | | | | | | | | | | RAS_TRAP_LOWER_EL_ERR_ACCESS was used to prevent access to RAS error record registers (RAS ERR* & RAS ERX*) from lower EL's in any security state. To give more fine grain control per world basis re-purpose this macro to RAS_TRAP_NS_ERR_REC_ACCESS, which will enable the trap only if Error record registers are accessed from NS. This will also help in future scenarios when RAS handling(in Firmware first handling paradigm)can be offloaded to a secure partition. This is first patch in series to refactor RAS framework in TF-A. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ifa7f60bc8c82c9960adf029001bc36c443016d5d
* build: fix syntax error in semantic ver generationHarrison Mutai2022-08-231-1/+1
| | | | | Change-Id: I344aa5c779ec3f0a410d3b8bc42b6014a9b37314 Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
* Merge "build: fix semantic ver generation for windows" into integrationJoanna Farley2022-08-231-2/+2
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| * build: fix semantic ver generation for windowsHarrison Mutai2022-08-161-2/+2
| | | | | | | | | | | | | | Fix syntax error when generating semantic versions on windows hosts. Change-Id: Idba8827145b829a8ba07ff0540407dbfa1ca7984 Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
* | Merge "feat(rng-trap): add EL3 support for FEAT_RNG_TRAP" into integrationBipin Ravi2022-08-181-0/+4
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| * feat(rng-trap): add EL3 support for FEAT_RNG_TRAPJuan Pablo Conde2022-08-181-0/+4
| | | | | | | | | | | | | | | | | | | | | | FEAT_RNG_TRAP introduces support for EL3 trapping of reads of the RNDR and RNDRRS registers, which is enabled by setting the SCR_EL3.TRNDR bit. This patch adds a new build flag ENABLE_FEAT_RNG_TRAP that enables the feature. This feature is supported only in AArch64 state from Armv8.5 onwards. Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com> Change-Id: Ia9f17aef3444d3822bf03809036a1f668c9f2d89
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