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* Merge "fix(stm32mp15-fdts): use /omit-if-no-ref/ for spi and i2c" into ↵Madhukar Pappireddy2023-04-132-4/+6
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| * fix(stm32mp15-fdts): use /omit-if-no-ref/ for spi and i2cVyacheslav Yurkov2023-04-052-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use /omit-if-no-ref/ keyword in DT to remove extra device nodes only when they are not used / not referenced. If the board device tree only defines subnodes, dtc does not consider it as usage, you have to specifically mention device's phandle, e.g.: \ { i2c6-phandle = <&i2c6>; }; or in aliases section aliases { i2c6 = &i2c6; }; Signed-off-by: Vyacheslav Yurkov <uvv.mail@gmail.com> Change-Id: I431ecd93576f97fd021d82d23b93c659fc8f26b8
* | feat(ethos-n): add multiple asset allocatorsJoshua Pimm2023-04-041-6/+231
|/ | | | | | | | | | | Adds additional asset allocators to the device tree include file as the non-secure world kernel module for the Arm(R) Ethos(TM)-N NPU now fully supports having and using multiple asset allocators. Signed-off-by: Joshua Pimm <joshua.pimm@arm.com> Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: I82d53667ef64968ee814f611d0a90abd3b3cf3de
* Merge changes I6b4a4d22,I06bde289,I86e39481,I7ea9b75c into integrationMadhukar Pappireddy2023-04-035-87/+42
|\ | | | | | | | | | | | | | | * changes: feat(stm32mp1-fdts): use /omit-if-no-ref/ for pins nodes feat(st): mandate dtc version 1.4.7 refactor(st): move mbedtls config files refactor(st): add common mk files
| * feat(stm32mp1-fdts): use /omit-if-no-ref/ for pins nodesYann Gautier2023-03-155-87/+42
| | | | | | | | | | | | | | | | | | | | | | With the /omit-if-no-ref/ keyword in DT, the non-referenced nodes are just removed. This allows reducing the size of device tree blobs. Setting it before pins node allows a size reduction of more than 2kB. The corresponding nodes can also be removed from BL2 and BL32 DT overlays. Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I6b4a4d227d5592e1d253a1b35da2dafaac2ddcae
* | Merge "feat(stm32mp15-fdts): add support for prtt1x board family" into ↵Manish Pandey2023-03-283-0/+361
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| * feat(stm32mp15-fdts): add support for prtt1x board familyDavid Jander2023-03-063-0/+361
| | | | | | | | | | | | | | | | | | | | | | | | | | Add one device tree to support a family of boards (PRTT1C, PRTT1S, PRTT1A) based on STM32MP151AAD3, used as sensors and actuators for industrial, 10BaseT1L based networks. This change was tested with barebox 2022.12.0 bootloader and kernel v6.2.0-rc1. Signed-off-by: David Jander <david@protonic.nl> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Change-Id: Ibab9933eadd7aa379ae0a7c7ccbfc2fbb9a44ca8
* | fix(pmu): switch FVP PMUv3 SPIs to PPIAlexeiFedorov2023-03-071-4/+1
|/ | | | | | | | | | FVP PMUv3 SPIs legacy interrupts are only listed for cluster #0 and are missing for cluster #1. This patch changes FVP SPIs to PMUv3 PPI as in arm_fpga.dtsi, morello.dtsi and n1sdp.dtsi. Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com> Change-Id: Ic624cec09ba932666c746ae1a6a4b78b6decde96
* feat(morello): add GPU DT nodePatrik Berglund2023-02-201-1/+24
| | | | | Signed-off-by: Patrik Berglund <patrik.berglund@arm.com> Change-Id: Ie82158aeaaf9e4bc68bc4bb91e3a9cc572b40d23
* Merge "refactor(tc): update total compute gpu device node" into integrationManish V Badarkhe2023-02-031-2/+26
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| * refactor(tc): update total compute gpu device nodeRupinderjit Singh2023-02-031-3/+27
| | | | | | | | | | | | | | updated gpu clocks and added gpu simple power model node Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com> Change-Id: Ia475f136bec8a569f764255eb87c212a692626dc
* | feat(plat/tc): enable MPAM functionality of L3 DSU cacheDavidson K2023-01-271-1/+10
|/ | | | | | | | | | The L3 cache in the DSU supports the Memory System Resources Partitioning and Monitoring (MPAM). The MPAM specific registers in the DSU are accessed through utility bus of DSU that are memory mapped from 0x1_0000_1000. Signed-off-by: Davidson K <davidson.kumaresan@arm.com> Change-Id: I2798181d599228e96dd4c0043a2ccd94668c7e20
* Merge changes from topic "st_dt_update" into integrationManish Pandey2023-01-172-16/+5
|\ | | | | | | | | | | | | * changes: refactor(stm32mp15-fdts): remove unused PMIC nodes fix(stm32mp15-fdts): use interrupts-extended for i2c2 style(stm32mp15-fdts): remove extra spaces on vbus
| * refactor(stm32mp15-fdts): remove unused PMIC nodesYann Gautier2023-01-041-11/+0
| | | | | | | | | | | | | | | | The onkey and watchdog features of the PMIC are not used in TF-A for STM32MP15 boards. Remove the nodes from DT. Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I2933e0bdc5843fcb549a817742106d9c66097869
| * fix(stm32mp15-fdts): use interrupts-extended for i2c2Yann Gautier2023-01-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | Update SoC DT file STM32MP151 to use interrupts-extended instead of interrupts for i2c2. This correct a compilation warning: build/stm32mp1/debug/fdts/stm32mp157c-ev1-bl2.pre.dts:23.3-26: Warning (interrupts_property): /soc/i2c@40013000:#interrupt-cells: size is (28), expected multiple of 12 Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: If512807cd23c72f95e1e02b15f30d20a849d8412
| * style(stm32mp15-fdts): remove extra spaces on vbusYann Gautier2023-01-041-3/+3
| | | | | | | | | | | | | | | | | | | | Remove extra spaces before the closing brace of vbus_otg node in stm32mp157c-ed1 DT file, before the vbus_sw label, and before the closing brace of vbus_sw node. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I2e77e0a043594876551ed8d77ed3d13f6a098c81
* | fix(plat/tc): increase TC_TZC_DRAM1_SIZEArunachalam Ganapathy2023-01-041-2/+2
|/ | | | | | | | | Increase TC_TZC_DRAM1_SIZE for Trusty image and its memory size. Update OP-TEE reserved memory range in DTS Change-Id: Iad433c3c155f28860b15bde2398df653487189dd Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
* fix(tc): change the properties of optee reserved memoryDavidson K2022-12-201-1/+1
| | | | | | | | make it part of the restricted dma pool to ensure it is not used for general dma operations. Change-Id: Ia14738de70b4d7719d7460ed8d16e727aea8d8c4 Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
* feat(tc): use smmu 700Davidson K2022-12-201-6/+5
| | | | | | | Enable smmu for gpu and dpu Signed-off-by: Davidson K <davidson.kumaresan@arm.com> Change-Id: I6f4cffdc835dc542904b0a15b1db9a3382b78c08
* feat(rmm): add support for the 2nd DRAM bankAlexeiFedorov2022-12-061-1/+1
| | | | | | | | | | | | | | This patch adds support for RMM granules allocation in FVP 2nd DRAM 2GB bank at 0x880000000 base address. For ENABLE_RME = 1 case it also removes "mem=1G" Linux kernel command line option in fvp-base-psci-common.dsti to allow memory layout discovery from the FVP device tree. FVP parameter 'bp.dram_size' - size of main memory in gigabytes documented in docs/components/realm-management-extension.rst is changed from 2 to 4. Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com> Change-Id: I174da4416ad5a8d41bf0ac89f356dba7c0cd3fe7
* refactor(stm32mp1): remove STM32MP_USE_STM32IMAGEYann Gautier2022-11-141-2/+0
| | | | | | | | The code managing legacy boot (without FIP) that was under STM32MP_USE_STM32IMAGE flag is remove. Change-Id: I04452453ed84567b0de39e900594a81526562259 Signed-off-by: Yann Gautier <yann.gautier@st.com>
* fix(stm32mp13-fdts): remove secure statusLionel Debieve2022-11-141-2/+2
| | | | | | | | | Remove the secure status for PKA and SAES entries. The peripherals are used in BL2 at EL3, context will remain secure only. Change-Id: I79d95bc55a9afd27f295249936d7bc332c777f5e Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
* feat(stm32mp1-fdts): add CoT and fuse references for authenticationLionel Debieve2022-11-145-2/+212
| | | | | | | | | | Add the stm32mp1 CoT description file. Include the TRUSTED_BOARD_BOOT entry in the platform device tree file. Add the missing public root key reference for stm32mp15 and the encryption key reference for stm32mp13. Change-Id: I0ae2454979a3df6dd3e4361510317742e8fbc109 Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
* Merge "fix(stm32mp13-fdts): correct PLL nodes name" into integrationMadhukar Pappireddy2022-10-241-2/+2
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| * fix(stm32mp13-fdts): correct PLL nodes nameYann Gautier2022-10-051-2/+2
| | | | | | | | | | | | | | Align aliases and node names for PLL nodes. Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: I863995eb884fc61c10d512bed0fd404b75ead353
* | Merge "feat(ethos-n)!: add support for SMMU streams" into integrationJoanna Farley2022-10-201-11/+60
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| * | feat(ethos-n)!: add support for SMMU streamsMikael Olsson2022-10-041-11/+60
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Arm(R) Ethos(TM)-N NPU driver now supports configuring the SMMU streams that the NPU shall use and will therefore no longer delegate access to these registers to the non-secure world. In order for the driver to support this, the device tree parsing has been updated to support parsing the allocators used by the NPU and what SMMU stream that is associated with each allocator. To keep track of what NPU device each allocator is associated with, the resulting config from the device tree parsing will now group the NPU cores and allocators into their respective NPU device. The SMC API has been changed to allow the caller to specify what allocator the NPU shall be configured to use and the API version has been bumped to indicate this change. Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: I6ac43819133138614e3f55a014e93466fe3d5277
* | fix(fvp_ve): fdts: Fix vexpress,config-bus subnode namesAndre Przywara2022-10-111-6/+6
| | | | | | | | | | | | | | | | | | | | The arm,vexpress,config-bus DT binding restricts the possible (sub)node names. Adjust the current node names, to drop the unneeded address specifier, and make the node names binding compliant. Change-Id: Ic48c6969268c960ce92c8ec3a756ed1d89e61b08 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | fix(fvp): fdts: Fix idle-states entry methodAndre Przywara2022-10-111-1/+1
| | | | | | | | | | | | | | | | | | | | When firmware implements idle states via PSCI, the value of the DT entry-method property must be "psci", not "arm,psci". Fix this to make the CPU description binding compliant. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: Icd1bf704d177368af9b7aab545f47e580791b8cc
* | fix(fvp): fdts: fix memtimer subframe addressingAndre Przywara2022-10-111-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | The arm,armv7-timer-mem DT binding documentation demands that the #size-cells property should be <1> only. Adjust the value to be <1> and drop the now needless leading 0 in the frame's reg property. Convert to #address-cell = <1> on the way. Also adjust the interrupts property to use the proper GIC macros. Change-Id: Ia2224663b1e6aaa7cf94af777473641de6a840d2 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | feat(fvp): fdts: update rtsm_ve DT files from the Linux kernelAndre Przywara2022-10-114-304/+325
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing DT files for the base FVP model are having some issues, that lead to warnings reported by the device tree compiler. Those (and many other issues around (updated) DT binding compliance) were fixed in the Linux kernel tree, so let's sync those files back into TF-A. We cannot copy the files "as is" for now, since we rely on certain custom properties to be added (max-pwr-lvl in the PSCI node, SDEI nodes, etc). Merge in the changed parts of the Linux kernel DT (from Linux v6.0-rc1), and rework the base file to allow including the motherboard.dtsi unchanged. This should make any future update less painful. As this also affects the FVP VE boards (Cortex-A7 and Cortex-A5), since they share the motherboard include file, fix them up as well. Change-Id: I4f74d05e5583747f8849e32f246f74aeec7a9c60 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | refactor(fvp): fdts: consolidate GICv2 base FVP DT filesAndre Przywara2022-10-112-200/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GICv2 and GICv3 version of the FVP DT files are unnecessarily split, as the common part of the peripherals is the same: it's literally just the interrupt controller node that is different. Since the GICv3 versions now use a generic DT include file (without any GIC node), let's reuse that for the GICv2 versions of the FVP as well. We just add a separate fvp-base-gicv2.dtsi file which describes the GICv2 interrupt controller. Also shorten the compatible string, since the GICv2 binding documentation does not allow the current combination. This allows to remove the mostly redundant nodes from the GICv2 .dts file. Change-Id: I9018031bb611fb00ca7dbefc1bff7d40c3f05819 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | refactor(fvp): fdts: consolidate GICv3 base FVP DT filesAndre Przywara2022-10-116-37/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GICv2 and GICv3 version of the FVP DT files are unnecessarily split, as the common part of the peripherals is the same: it's literally just the interrupt controller node that is different. To facilitate a unification, refactor the DT include files to explicitly include a snippet with just the GICv3 description, and a generic base DT file for the rest. This generic file can then be reused by the GICv2 versions later. Since we can only have a /memreserve/ entry *before* any DT nodes, move that line to each file, to allow including the GIC DT file separately. Change-Id: I9ff357d3fe0ce46e280c30131aeae97a99631512 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | feat(fvp): dts: drop 32-bit .dts filesAndre Przywara2022-10-116-732/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conceptually the DT is a hardware description, as such it's independent from the instruction set that a DT client uses. So having separate DTs for aarch32 and aarch64 does not make sense and is not needed. Probably due to historic reasons (a Linux bug fixed in 2016 with Linux commit ba6dea4f7ced, in Linux v4.8) the CPU reg property was using a different size between aarch64 and aarch32, even though the size of it is solely governed by the parent's #address-cells property. Consolidate this to be always 2, and always use two cells to describe the CPU's MPIDR register. This removes the last difference of the -aarch32 versions of the FVP DT files, so just remove all of them. The respective versions without that suffix can now be used with AArch32 DT clients as well. Also remove the respective part in the documentation. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: I45d3a2cbba8e04595a741e1cf41900377952673e
* | refactor(fvp): fdts: merge motherboard .dtsi filesAndre Przywara2022-10-117-23/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For no real reason we were shipping two separate DT include files for the base FVP motherboard peripherals, one for aarch32, one for aarch64. There is no difference in the hardware description when using a different instruction set, and the diff between the two files was about a missing interrupt map for the 64-bit DT files. Consolidate the situation by just using a single motherboard .dtsi file, which relies on an interrupt map by the including files. Provide that map in the two files where it was missing before, and change the filenames to let all users include the same file now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: I19b77ecc8da9b4bfbd61d02f910b9ab05dbf92e9
* | refactor(fvp_ve): fdts: prepare Cortex-A5 and A7 model DTsAndre Przywara2022-10-112-37/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DT files for the Cortex-A5 and Cortex-A7 FVP models include the shared rtsm_ve-motherboard.dtsi file, which we need to sync with the upstream Linux version soon. To prepare for its changed structure there, adjust the top-level #address-cells and #size-cells properties to be compatible with the expectations of the Linux version. Also extend the interrupt map to cover all peripherals listed in the motherboard file, and use the proper GIC macros to make them more readable on the way. Change-Id: I7d1493f1a200e8350530f912833f9ffcc5f94b21 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | fix(fvp): fdts: unify and fix PSCI nodesAndre Przywara2022-10-114-24/+4
|/ | | | | | | | | | | | | | | | | | The PSCI DT nodes used for the various fvp-base model variants provide explicit function IDs, as required for the pre-v0.2 PSCI specification. This prevents them from being used from both AArch32 and AArch64 DT clients, and using this version of the PSCI spec is long deprecated anyway. Remove the old compatible string and the function properties, to force clients to use the standard function IDs as described in the PSCI spec. sys_poweroff and sys_reset were never standardised or used anyway. There should be no client software around that cannot deal with PSCI v0.2. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: Ie87deb9898eae79b7307c15bcefcd4b311d4dc22
* fix(tc): resolve the static-checks errorsJayanth Dodderi Chidanand2022-09-281-8/+8
| | | | | | | | Converted the space indentation to tabs to fix the errors listed under tf-static-checks CI job. Change-Id: Ie911a5befd0eeaa5a2019245cc3c43ad375cd068 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* Merge "feat(tc): add RTC PL031 device tree node" into integrationSandrine Bailleux2022-09-271-1/+10
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| * feat(tc): add RTC PL031 device tree nodeRupinderjit Singh2022-09-151-1/+10
| | | | | | | | | | | | | | It enables RTC PL031 driver in kernel. Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com> Change-Id: I6d7c1a5b6ce11b3d594f7575a747e72826c8d9b8
* | Merge changes from topic "morello-dt-fix" into integrationManish V Badarkhe2022-09-143-34/+28
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | * changes: fix(morello): dts: remove #a-c and #s-c from memory node fix(morello): dts: fix GICv3 compatible string fix(morello): dts: fix DT node naming fix(morello): dts: fix SCMI shmem/mboxes grouping fix(morello): dts: use documented DPU compatible string fix(morello): dts: fix DP SMMU IRQ ordering fix(morello): dts: fix SMMU IRQ ordering fix(morello): dts: add model names fix(morello): dts: fix stdout-path target
| * fix(morello): dts: remove #a-c and #s-c from memory nodeAndre Przywara2022-07-192-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The #address-cells and #size-cells properties affect the size of reg properties in *child* nodes only, they have no effect on the current node. The /memory node has no children, hence there is no need to specify those properties. dt-validate complains about this: ========== morello-soc.dtb: /: memory@80000000: '#address-cells', '#size-cells' do not match any of the regexes: 'pinctrl-[0-9]+' From schema: dt-schema.git/dtschema/schemas/memory.yaml ========== Remove the unneeded properties. Change-Id: I35058a00fa9bfa1007f31a4c21898dd45c586aa8 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * fix(morello): dts: fix GICv3 compatible stringAndre Przywara2022-07-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The official GICv3 DT bindings require only a limited number of compatible string, and disavowes the naming of an implementation. Linux' "make dtbs_check" reports: ============ .../morello-soc.dt.yaml: interrupt-controller@2c010000: compatible: 'oneOf' conditional failed, one must be fixed: ['arm,gic-600', 'arm,gic-v3'] is too long 'arm,gic-600' is not one of ['qcom,msm8996-gic-v3'] 'arm,gic-v3' was expected From schema: Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml ============ Drop the redundant (because runtime detectable) and undocumented implementation version, and just use the standard compatible string. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: I05b207df271d6aa5bf3f2163f99ac0c594204c75
| * fix(morello): dts: fix DT node namingAndre Przywara2022-07-192-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The various official DT bindings only allow certain node name patterns. Linux' "make dtbs_check" reports: =========== .../morello-soc.dt.yaml: sram@45200000: 'scp-shmem@0', 'scp-shmem@80' do not match any of the regexes: '^([a-z0-9]*-)?sram(-section)?@[a-f0-9]+$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/sram/sram.yaml .../morello-soc.dt.yaml: uart@2a400000: $nodename:0: 'uart@2a400000' does not match '^serial(@.*)?$' From schema: Documentation/devicetree/bindings/serial/pl011.yaml .../morello-soc.dt.yaml: interrupt-controller@2c010000: 'its@30040000', 'its@30060000', 'its@30080000', 'its@300a0000' do not match any of the regexes: '^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$', '^gic-its@', '^interrupt-controller@[0-9a-f]+$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml =========== Rename the node names to improve bindings compliance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: Ieff576512853eb2bf932c7a2b338c91e0c116b87
| * fix(morello): dts: fix SCMI shmem/mboxes groupingAndre Przywara2022-07-192-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The official Arm MHU DT binding suggests to group the shmem (and mboxes) values to signify the number of mailboxes supported. Linux' "make dtbs_check" reports: ============ .../morello-soc.dt.yaml: scmi: shmem:0: [17, 18] is too long From schema: dt-schema.git/dtschema/schemas/mbox/mbox-consumer.yaml ============ Add angle brackets at the right location to mark the boundaries between the two mailbox instances used. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: If585c98b5e8e55cd5c0b1261e03ce4b91a4c0413
| * fix(morello): dts: use documented DPU compatible stringAndre Przywara2022-07-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The official Arm Komeda DPU DT binding only mentions the "arm,mali-d71" string as a possible compatible string. The D32 version is just a variant of the D71, and the revision can and will be auto-detected at runtime. Add the usual fallback compatible string scheme to contain a documented compatible string. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: Ic1eade122b030dc983944b161eec175facf75357
| * fix(morello): dts: fix DP SMMU IRQ orderingAndre Przywara2022-07-191-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The official SMMUv3 DT bindings require a certain order of the interrupts, Linux' "make dtbs_check" reports: ============ .../morello-soc.dt.yaml: iommu@2ce00000: interrupt-names: 'oneOf' conditional failed, one must be fixed: ['eventq', 'cmdq-sync', 'gerror'] is too long 'combined' was expected 'gerror' was expected 'priq' was expected 'cmdq-sync' was expected From schema: Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml ============ Swap the order of the interrupts to improve bindings compliance. Actually in this case the binding needs to be extended, since PRI is not implemented in the SMMU in this case, so the PRI IRQ should be optional, but we still want to describe the CMDQ sync IRQ. A patch for the binding is pending. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: I3978f1c087136cd4c2e8f7fd4d1bba5b95f72726
| * fix(morello): dts: fix SMMU IRQ orderingAndre Przywara2022-07-191-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The official SMMUv3 DT bindings require a certain order of the interrupts, Linux' "make dtbs_check" reports: ============ .../morello-soc.dt.yaml: iommu@4f400000: interrupt-names: 'oneOf' conditional failed, one must be fixed: ['eventq', 'priq', 'cmdq-sync', 'gerror'] is too long 'combined' was expected 'gerror' was expected 'priq' was expected 'cmdq-sync' was expected From schema: Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml ============ Swap the order of the interrupt-names and their corresponding interrupts values to improve bindings compliance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: I2110b8509593a4f1aadff11bd518ec4a0f3f5d3c
| * fix(morello): dts: add model namesAndre Przywara2022-07-192-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The core root node DT bindings require every DT to have a "model" property. Linux' "make dtbs_check" reports: ============ .../morello-soc.dt.yaml: /: 'model' is a required property From schema: dt-schema.git/dtschema/schemas/root-node.yaml ============ Add a model name to both the SoC and FVP files to improve bindings compliance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: I64923edb947f8939dfa24c13a37996b1ba34ea54
| * fix(morello): dts: fix stdout-path targetAndre Przywara2022-03-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the DT spec, stdout-path must either start with the full path to a node, or with an alias. "soc_uart0" is neither of them, and consequently the Linux kernel complains that it cannot find the root console device when just given "earlycon" on the kernel command line: =========== [ 0.000000] OF: fdt: earlycon: stdout-path soc_uart0 not found =========== Use the already defined "serial0" alias to fix this and make "earlycon" work in Linux. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: Ie0ddb1909160c930af3831246f0140363bc0b5db
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