summaryrefslogtreecommitdiff
path: root/changelog.yaml
Commit message (Collapse)AuthorAgeFilesLines
* feat(sme): enable SME2 functionality for NS worldJayanth Dodderi Chidanand2023-04-271-1/+1
| | | | | | | | | | | | | | | | | | | FEAT_SME2 is an extension of FEAT_SME and an optional feature from v9.2. Its an extension of SME, wherein it not only processes matrix operations efficiently, but also provides outer-product instructions to accelerate matrix operations. It affords instructions for multi-vector operations. Further, it adds an 512 bit architectural register ZT0. This patch implements all the changes introduced with FEAT_SME2 to ensure that the instructions are allowed to access ZT0 register from Non-secure lower exception levels. Additionally, it adds support to ensure FEAT_SME2 is aligned with the existing FEATURE DETECTION mechanism, and documented. Change-Id: Iee0f61943304a9cfc3db8f986047b1321d0a6463 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* Merge "feat(tcr2): add FEAT_TCR2 to the changelog" into integrationManish Pandey2023-04-251-0/+3
|\
| * feat(tcr2): add FEAT_TCR2 to the changelogMark Brown2023-04-181-0/+3
| | | | | | | | | | | | | | This was omitted from the patch adding the feature. Signed-off-by: Mark Brown <broonie@kernel.org> Change-Id: Ie7f2b63434a70320178be74fc3f165618aca8392
* | Merge "feat(gcs): support guarded control stack" into integrationBipin Ravi2023-04-251-0/+3
|\ \ | |/
| * feat(gcs): support guarded control stackMark Brown2023-04-181-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Arm v9.4 introduces support for Guarded Control Stack, providing mitigations against some forms of RPO attacks and an efficient mechanism for obtaining the current call stack without requiring a full stack unwind. Enable access to this feature for EL2 and below, context switching the newly added EL2 registers as appropriate. Change the FVP platform to default to handling this as a dynamic option so the right decision can be made by the code at runtime. Signed-off-by: Mark Brown <broonie@kernel.org> Change-Id: I691aa7c22e3547bb3abe98d96993baf18c5f0e7b
* | fix(uuid): add missing `#include` directivesChris Kay2023-04-171-1/+3
|/ | | | | | | These include directives were missing from both `uuid.h` files. Change-Id: I875dfda3e0985728277b72f0e7597dde5cf9d304 Signed-off-by: Chris Kay <chris.kay@arm.com>
* docs(changelog): add 'porting' scopeSandrine Bailleux2023-04-111-0/+3
| | | | | Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: I22a81b3f69d90e0fcb88c7e98178e915253afb43
* refactor(cpufeat): move helpers into .c file, rename FEAT_STATE_Andre Przywara2023-01-111-0/+3
| | | | | | | | | | | | | | | | | | | | The FEATURE_DETECTION functionality had some definitions in a header file, although they were only used internally in the .c file. Move them over there, since there are of no interest to other users. Also use the opportuntiy to rename the less telling FEAT_STATE_[12] names, and let the "0" case join the game. We use DISABLED, ALWAYS, and CHECK now, so that the casual reader has some idea what those numbers are supposed to mean. feature_panic() becomes "static inline", since disabling all features makes it unused, so the compiler complains otherwise. Finally add a new category "cpufeat" to cover CPU feature related changes. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: If0c8ba91ad22440260ccff383c33bdd055eefbdc
* docs(changelog): add console scopeYann Gautier2023-01-061-1/+4
| | | | | Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: Ie9426509ee4f0a4c4f0fe0296d7a7378cc8828f5
* Merge "refactor(trng): cleanup the existing TRNG support" into integrationManish V Badarkhe2022-11-091-0/+3
|\
| * refactor(trng): cleanup the existing TRNG supportJayanth Dodderi Chidanand2022-11-081-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the following changes to complete the existing TRNG implementation: 1. Adds a feature specific scope for buildlog generation. 2. Updates the docs on the build flag "TRNG_SUPPORT" and its values. 3. Makefile update and improves the existing comments at few sections for better understanding of the underlying logic. Change-Id: I3f72f0ccd5c94005a2df87158cf23199d2160d37 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* | Merge "docs(changelog): add missing scopes for release" into integrationLauren Wehrmeister2022-11-081-21/+92
|\ \
| * | docs(changelog): add missing scopes for releaselaurenw-arm2022-11-071-21/+92
| |/ | | | | | | | | | | | | Add missing scopes from commits for the upcoming release. Change-Id: I22e38fb0658e42b45591c82aa30e063f7a7edc86 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
* | docs(changelog): fix invalid context management scopeChris Kay2022-11-041-1/+4
|/ | | | | Change-Id: Ia94b944a023568fc53a812cefffe97a7b3af4266 Signed-off-by: Chris Kay <chris.kay@arm.com>
* docs(changelog): add zlib and compiler-rt scopeDaniel Boulby2022-10-241-0/+7
| | | | | Change-Id: Id98ca7762fd17cb793b0ec9119d0b026195cf2c2 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
* Merge "build(changelog): add new scope for Performance Monitor Extensions" ↵Manish V Badarkhe2022-10-101-0/+3
|\ | | | | | | into integration
| * build(changelog): add new scope for Performance Monitor ExtensionsJayanth Dodderi Chidanand2022-09-291-0/+3
| | | | | | | | | | | | | | | | | | This patch adds a news scope for FEAT_PMUV3, alongside updating the existing comments related to the saving of PMCR_EL0 register routine for better understanding. Change-Id: Ib150244ce94cfcbbe5d12fdae56327c3d72bda0b Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* | Merge changes from topic "mb/drtm-preparatory-patches" into integrationManish Pandey2022-10-061-0/+9
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: docs(drtm): steps to run DRTM implementation docs(drtm): add platform APIs for DRTM feat(drtm): flush dcache before DLME launch feat(drtm): invalidate icache before DLME launch feat(drtm): ensure that passed region lies within Non-Secure region of DRAM feat(fvp): add plat API to validate that passed region is non-secure feat(drtm): ensure that no SDEI event registered during dynamic launch feat(drtm): prepare EL state during dynamic launch feat(drtm): prepare DLME data for DLME launch feat(drtm): take DRTM components measurements before DLME launch feat(drtm): add a few DRTM DMA protection APIs feat(drtm): add remediation driver support in DRTM feat(fvp): add plat API to set and get the DRTM error feat(drtm): add Event Log driver support for DRTM feat(drtm): check drtm arguments during dynamic launch feat(drtm): introduce drtm dynamic launch function refactor(measured-boot): split out a few Event Log driver functions feat(drtm): retrieve DRTM features feat(drtm): add platform functions for DRTM feat(sdei): add a function to return total number of events registered feat(drtm): add PCR entries for DRTM feat(drtm): update drtm setup function refactor(crypto): change CRYPTO_SUPPORT flag to numeric feat(mbedtls): update mbedTLS driver for DRTM support feat(fvp): add crypto support in BL31 feat(crypto): update crypto module for DRTM support build(changelog): add new scope for mbedTLS and Crypto module feat(drtm): add standard DRTM service build(changelog): add new scope for DRTM service feat(fvp): increase MAX_XLAT_TABLES entries for DRTM support feat(fvp): increase BL31's stack size for DRTM support feat(fvp): add platform hooks for DRTM DMA protection
| * | build(changelog): add new scope for mbedTLS and Crypto moduleManish V Badarkhe2022-10-051-0/+6
| | | | | | | | | | | | | | | | | | | | | Added new scope for mbedTLS and Crypto module. Change-Id: I127e7e32f103210e0a1c4c3072afa7249a24a7db Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
| * | build(changelog): add new scope for DRTM serviceManish V Badarkhe2022-10-051-0/+3
| | | | | | | | | | | | | | | | | | | | | Added new scope for DRTM service. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Idffb178026ef2910102b55e640d5f5bf904e6064
* | | Merge "fix(semihosting): fix seek call failure check" into integrationMadhukar Pappireddy2022-10-051-0/+3
|\ \ \ | |/ / |/| |
| * | fix(semihosting): fix seek call failure checkManish V Badarkhe2022-09-281-0/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code checks that the semihosting seek call return value is not zero instead of a negative value when there is an error condition. This defect has been fixed. In [1], possible return values for semihosting seek calls are mentioned. [1]: https://github.com/ARM-software/abi-aa/blob/main/semihosting/ semihosting.rst#sys-seek-0x0a Change-Id: I70f09e98323e9c5bf4eeda322ac065e855e256fc Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
* | docs(changelog): fix incorrect documentation titleChris Kay2022-09-291-1/+1
|/ | | | | Change-Id: Idb4b174f65891ba406f83c213c80ebb8a6ba0b81 Signed-off-by: Chris Kay <chris.kay@arm.com>
* Merge changes from topic "ffa_el3_spmc" into integrationOlivier Deprez2022-08-251-0/+7
|\ | | | | | | | | | | | | * changes: feat(tsp): enable test cases for EL3 SPMC feat(tsp): increase stack size for tsp feat(tsp): add ffa_helpers to enable more FF-A functionality
| * feat(tsp): increase stack size for tspShruti Gupta2022-08-251-0/+7
| | | | | | | | | | | | | | TSP testcases for EL3 SPMC have higher stack usage. Change-Id: Ib5bfdccc6d0f65174e257f3b0e8b41bcd3c704a6 Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
* | feat(rng-trap): add EL3 support for FEAT_RNG_TRAPJuan Pablo Conde2022-08-181-0/+3
|/ | | | | | | | | | | FEAT_RNG_TRAP introduces support for EL3 trapping of reads of the RNDR and RNDRRS registers, which is enabled by setting the SCR_EL3.TRNDR bit. This patch adds a new build flag ENABLE_FEAT_RNG_TRAP that enables the feature. This feature is supported only in AArch64 state from Armv8.5 onwards. Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com> Change-Id: Ia9f17aef3444d3822bf03809036a1f668c9f2d89
* build(changelog): add stm32mp13 and stm32mp15 fdts scopesYann Gautier2022-07-081-0/+7
| | | | | | | | Some fdts changes in STM32MP1 family can be dedicated to one SoC, STM32MP13 or STM32MP15. Add the dedicated scopes. Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I2d64244054251c1f89dfe1ebbf6ce9dac21d47b6
* feat(rmmd): add support for RMM Boot interfaceJavier Almansa Sobrino2022-07-041-0/+3
| | | | | | | | | | | | | | | | This patch adds the infrastructure needed to pass boot arguments from EL3 to RMM and allocates a shared buffer between both worlds that can be used, among others, to pass a boot manifest to RMM. The buffer is composed a single memory page be used by a later EL3 <-> RMM interface by all CPUs. The RMM boot manifest is not implemented by this patch. In addition to that, this patch also enables support for RMM when RESET_TO_BL31 is enabled. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I855cd4758ee3843eadd9fb482d70a6d18954d82a
* Merge changes from topic "lw/cca_cot" into integrationManish Pandey2022-06-241-0/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: feat(arm): retrieve the right ROTPK for cca feat(arm): add support for cca CoT feat(arm): provide some swd rotpk files build(tbbr): drive cert_create changes for cca CoT refactor(arm): add cca CoT certificates to fconf feat(fiptool): add cca, core_swd, plat cert in FIP feat(cert_create): define the cca chain of trust feat(cca): introduce new "cca" chain of trust build(changelog): add new scope for CCA refactor(fvp): increase bl2 size when bl31 in DRAM
| * build(changelog): add new scope for CCAlaurenw-arm2022-06-141-0/+3
| | | | | | | | | | Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Iccba57a292e6668e6a6d93f1cb0e1633592a4009
* | Merge "build(changelog): add stm32mp13 and stm32mp15 scopes" into integrationMadhukar Pappireddy2022-06-151-1/+8
|\ \
| * | build(changelog): add stm32mp13 and stm32mp15 scopesYann Gautier2022-06-021-1/+8
| |/ | | | | | | | | | | | | | | | | | | The STM32MP1 series includes STM32MP13 and STM32MP15. As some features may be dedicated to one SoC variant, add the 2 entries in the scopes list. While at it, correct the title for STM32MP1. Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I521d0e1dfdda0638ab9970c93821cf08efbd183a
* | refactor(context mgmt): refactor EL2 context save and restore functionsZelalem Aweke2022-06-081-0/+3
|/ | | | | | | | | | | | | | | | | | This patch splits the el2_sysregs_context_save/restore functions into multiple functions based on features. This will allow us to selectively save and restore EL2 context registers based on features enabled for a particular configuration. For now feature build flags are used to decide which registers to save and restore. The long term plan is to dynamically check for features that are enabled and then save/restore registers accordingly. Splitting el2_sysregs_context_save/restore functions into smaller assembly functions makes that task easier. For more information please take a look at: https://trustedfirmware-a.readthedocs.io/en/latest/design_documents/context_mgmt_rework.html Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com> Change-Id: I1819a9de8b70fa35c8f45568908025f790c4808c
* docs(changelog): changelog for v2.7 releaseJayanth Dodderi Chidanand2022-06-011-11/+121
| | | | | Change-Id: I573e5eb3c7fad097892292c8a967dc02d72d12e6 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* Merge changes from topic "mb/drtm-work-phase-1" into integrationManish Pandey2022-05-191-0/+3
|\ | | | | | | | | | | | | | | * changes: build(changelog): add new scope for Arm SMMU driver feat(smmu): add SMMU abort transaction function docs(build): add build option for DRTM support build(drtm): add DRTM support build option
| * build(changelog): add new scope for Arm SMMU driverManish V Badarkhe2022-05-181-0/+3
| | | | | | | | | | | | | | Added new scope for Arm SMMU driver. Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com> Change-Id: I62f5ed36657a071d125cdddacbff9fb23d2bc8e0
* | build(changelog): add new scope for the threat modelSandrine Bailleux2022-05-171-0/+3
|/ | | | | Change-Id: I884f31f7f4b5515c420839ff37d401faa69f5fff Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* Merge "build(changelog): add new scope for TI platform" into integrationManish Pandey2022-04-071-0/+7
|\
| * build(changelog): add new scope for TI platformDave Gerlach2022-03-221-0/+7
| | | | | | | | | | | | | | Add new scope for TI and K3 platforms. Change-Id: I3b666c73e3ee8bcf73fcd155b7a372f44b56b033 Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* | build(changelog): add new scopes for ls1088aJiafei Pan2022-03-271-0/+10
| | | | | | | | | | | | | | Add new scopes for ls1088a SoC, RDB and QDS boards. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I7c0018ecee3c590253cf258851a28c4dd7f9c1a1
* | build(changelog): add new scopes for NXP driverJiafei Pan2022-03-271-0/+6
|/ | | | | | | Add new scope for NXP DDR drivers and GIC drivers. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I8ff4d203c474593fe2cff846e0040fc8651b20b6
* Merge changes I75b3e3bf,I4cf9f1d9,I50d2ae74,Idbe62410,I84bbd06e, ... into ↵Madhukar Pappireddy2022-02-281-0/+7
|\ | | | | | | | | | | | | | | | | | | | | | | | | integration * changes: fix(intel): null pointer handling for resp_len fix(intel): define macros to handle buffer entries fix(intel): change SMC return arguments for INTEL_SIP_SMC_MBOX_SEND_CMD fix(intel): always set doorbell to SDM after sending command fix(intel): fix bit masking issue in intel_secure_reg_update fix(intel): fix ddr address range checker build(changelog): add new scope for Intel platform
| * build(changelog): add new scope for Intel platformSieu Mun Tang2022-02-231-0/+7
| | | | | | | | | | | | | | Add new scope for Intel platform. Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com> Change-Id: I1fa7f5e0e5567825615dd0275b204b82fe8c2337
* | build(changelog): add new scope for nxp cryptoJiafei Pan2022-02-181-0/+3
| | | | | | | | | | | | | | Add new scope for NXP Crypto CAAM drivers. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I4beb96d1dc655281cb2fc99b8b0b998f35499dba
* | Merge changes from topic "ls1046a" into integrationMadhukar Pappireddy2022-02-171-0/+19
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | * changes: docs(layerscape): add ls1046a soc and board support feat(ls1046aqds): add board ls1046aqds support feat(ls1046afrwy): add ls1046afrwy board support feat(ls1046ardb): add ls1046ardb board support feat(ls1046a): add new SoC platform ls1046a fix(nxp-tools): fix tool location path for byte_swape fix(nxp-qspi): fix include path for QSPI driver build(changelog): add new scopes for NXP layerscape platforms
| * build(changelog): add new scopes for NXP layerscape platformsJiafei Pan2022-02-151-0/+19
| | | | | | | | | | | | | | | | | | | | 1. Add scopes for ls1046a and related boards: ls1046ardb, ls1046aqds, ls1046afwry. 2. Add new scope for NXP QSPI driver. 3. Add new scope for NXP tools. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I68ef7dd25628b393dbfbb8dbf59d5185945ea61c
* | feat(spe): add support for FEAT_SPEv1p2Manish V Badarkhe2022-02-101-0/+3
| | | | | | | | | | | | | | | | Allow access to PMSNEVFR_EL1 register at NS-EL1 or NS-EL2 when FEAT_SPEv1p2 is implemented. Change-Id: I44b1de93526dbe9c11fd061d876371a6c0e6fa9c Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
* | docs(msm8916): new port for Qualcomm Snapdragon 410Stephan Gerhold2022-02-031-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Qualcomm Snapdragon 410 is Qualcomm's first 64-bit SoC, released in 2014 with four ARM Cortex-A53 cores. There are differents variants (MSM8916, APQ8016(E), ...) that are all very similar. A popular device based on APQ8016E is the DragonBoard 410c single-board computer, but the SoC is also used in various mid-range smartphones/tablets. This commit adds documentation for a minimal, community-maintained port of TF-A/BL31 for MSM8916. The actual platform port is added in the following four separate small commits to simplify the review process. The code is primarily based on the information from the public Snapdragon 410E Technical Reference Manual [1], combined with a lot of trial and error to actually make it work. Note that this port is a pure community effort without any commercial interests and is not related to Qualcomm in any way. The main motivation for this port is to have a minimal, updatable firmware since this old chip does not receive many updates anymore from Qualcomm. It works quite well for many use cases so I am willing to maintain it as a "code owner". I have also added Nikita Travkin as second code owner to help with reviews. The main limitation so far is the lack of memory protection for TF-A. This is similar to the ports for the Raspberry Pi but in this case not a lack of hardware support but rather a lack of documentation. However, this does not limit the usefulness of the port when used as a minimal PSCI implementation. [1]: https://developer.qualcomm.com/download/sd410/snapdragon-410e-technical-reference-manual.pdf Change-Id: I676adf86061638cfc2f3ae8615470d145e84f172 Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
* | Merge "docs(commit-style): change blessed scope of FF-A" into integrationMadhukar Pappireddy2022-02-011-3/+5
|\ \
| * | docs(commit-style): change blessed scope of FF-ADaniel Boulby2022-01-311-3/+5
| |/ | | | | | | | | | | | | Also split SPM MM into it's own scope. Change-Id: I9cfb1ddec7419ad0d7b539f65e7322bbd44a3913 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
View Lorry Controller Status