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| * | | Add support for Juno r1 in the platform reset handlerSandrine Bailleux2015-03-242-22/+80
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For Juno r0, the platform reset handler needs to: - Implement the workaround for defect #831273 - Increase the L2 Data and Tag RAM latencies for Cortex-A57. Defect #831273 does not affect Juno r1. Also, the default value for the L2 Tag RAM latency for Cortex-A57 is suitable on Juno r1. The L2 Data RAM latency for Cortex-A57 still needs to be increased, though. This patch modifies the Juno platform reset handler to detect the board revision and skip the unnecessary steps on Juno r1. The behaviour on Juno r0 is unchanged. Change-Id: I27542917223e680ef923ee860900806ffcd0357b
* | | Merge pull request #273 from achingupta/ag/genfw-389achingupta2015-03-261-6/+12
|\ \ \ | | | | | | | | Set group status of PPIs and SGIs correctly on GICv3 systems
| * | | Set group status of PPIs and SGIs correctly on GICv3 systemsAchin Gupta2015-03-201-6/+12
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On a GICv2 system, the group status of PPIs and SGIs is set in the GICD_IGROUPR0 register. On a GICv3 system, if affinity routing is enabled for the non-secure state, then the group status of PPIs and SGIs should be set in the GICR_IGROUPR0 register. ARM Trusted firmware sets the group status using the GICv2 sequence. On a GICv3 system, if the group status of an interrupt is set to Group 1 through a write to the GICD_IGROUPR0, then the GICR_IGROUPR0 is updated as well. The current sequence is incorrect since it first marks all PPIs and SGIs as Group 1. It then clears the bits in GICD_IGROUPR0 corresponding to secure interrupts to set their group status to Group 0. This operation is a no-op. It leaves the secure generic timer interrupt (#29) used by the TSP marked as Group 1. This causes the interrupt to interfere with the execution of non-secure software. Once an interrupt has been marked as Group 1, the GICR_IGROUPR0 should be programmed to change its group status. This patch rectifies this issue by setting the group status of only the non-secure PPI and SGIs to Group 1 in the first place. GICD_IGROUPR0 resets to 0. So secure interrupts are marked as Group 0 by default. Change-Id: I958b4b15f3e2b2444ce4c17764def36216498d00
* | | Merge pull request #270 from vikramkanigiri/vk/a72_cpu_supportdanh-arm2015-03-192-0/+301
|\ \ \ | |/ / |/| | Add support for ARM Cortex-A72 processor
| * | Add support for ARM Cortex-A72 processorVikram Kanigiri2015-03-182-0/+301
| |/ | | | | | | | | | | | | This patch adds support for ARM Cortex-A72 processor in the CPU specific framework. Change-Id: I5986855fc1b875aadf3eba8c36e989d8a05e5175
* | Merge pull request #263 from jcastillo-arm/jc/tbb_sha256_intdanh-arm2015-03-172-2/+0
|\ \ | | | | | | TBB: remove PolarSSL SHA1 functions from the binary
| * | TBB: remove PolarSSL SHA1 functions from the binaryJuan Castillo2015-03-112-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit ea4ec3aad5e1 ("TBB: use SHA256 to generate the certificate signatures") updated the cert_create tool to generate the signatures using SHA256 instead of SHA1. Therefore, SHA1 is no longer required. This patch removes the SHA1 option from the PolarSSL configuration file. The source file sha1.c is no longer needed and has been excluded from the build. The SHA1 functions are no longer included in the binary, reducing the memory footprint of BL1 and BL2 by approximately 6 KB. Change-Id: I72ea2cff03c0964c3eaadce148ec2ad2c6dde2e3
* | | Merge pull request #269 from vikramkanigiri/vk/common-ccidanh-arm2015-03-1723-46/+383
|\ \ \ | | | | | | | | Common driver for ARM cache coherent Interconnects
| * | | Use ARM CCI driver on FVP and Juno platformsVikram Kanigiri2015-03-1615-35/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the FVP and Juno platform ports to use the common driver for ARM Cache Coherent Interconnects. Change-Id: Ib142f456b9b673600592616a2ec99e9b230d6542
| * | | Common driver for ARM Cache Coherent InterconnectsVikram Kanigiri2015-03-165-0/+312
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even though both CCI-400 and CCI-500 IPs have different configurations with respect to the number and types of supported interfaces, their register offsets and programming sequences are similar. This patch creates a common driver for enabling and disabling snoop transactions and DVMs with both the IPs. New platform ports which implement one of these IPs should use this common driver. Existing platform ports which implement CCI-400 should migrate to the common driver as the standalone CCI-400 will be deprecated in the future. Change-Id: I3ccd0eb7b062922d2e4a374ff8c21e79fa357556
| * | | Add macro to calculate number of elements in an arrayVikram Kanigiri2015-03-165-12/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch defines the ARRAY_SIZE macro for calculating number of elements in an array and uses it where appropriate. Change-Id: I72746a9229f0b259323972b498b9a3999731bc9b
* | | | Merge pull request #268 from vikramkanigiri/vk/move_init_cpu_opsdanh-arm2015-03-175-25/+7
|\ \ \ \ | | | | | | | | | | Initialise cpu ops after enabling data cache
| * | | | Initialise cpu ops after enabling data cacheVikram Kanigiri2015-03-135-25/+7
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cpu-ops pointer was initialized before enabling the data cache in the cold and warm boot paths. This required a DCIVAC cache maintenance operation to invalidate any stale cache lines resident in other cpus. This patch moves this initialization to the bl31_arch_setup() function which is always called after the data cache and MMU has been enabled. This change removes the need: 1. for the DCIVAC cache maintenance operation. 2. to initialise the CPU ops upon resumption from a PSCI CPU_SUSPEND call since memory contents are always preserved in this case. Change-Id: Ibb2fa2f7460d1a1f1e721242025e382734c204c6
* | | | Merge pull request #267 from sandrine-bailleux/sb/doc-fixesdanh-arm2015-03-172-4/+14
|\ \ \ \ | | | | | | | | | | Documentation fixes in 'make help' message and User Guide
| * | | | User guide: Add dependency on libssl-dev for cert_create toolSandrine Bailleux2015-03-101-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'libssl-dev' package must be installed on the host to build the certificate generation tool. This patch adds it to the list of required tools in the User Guide. Change-Id: I018381fb14b7c2d2bd6f2b7929aaad0571f7eb2e
| * | | | Update help message printed by the MakefileSandrine Bailleux2015-03-101-4/+11
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The message printed by 'make help' is incomplete. It doesn't mention all relevant supported targets. This patch updates it. The format of the first line of the help message has been changed so that it no longer lists all supported targets. This eases the maintenance as we don't need to update the list in 2 places anymore whenever a new target is added. Also add a reference to the user guide to get the list of supported options. Change-Id: I79d8b815b0ffc0c43b4c05124378fce0e938365c
* | | | Merge pull request #266 from sandrine-bailleux/sb/juno-disable-errata-806969danh-arm2015-03-171-1/+1
|\ \ \ \ | | | | | | | | | | Juno: Disable workaround for Cortex-A57 erratum #806969
| * | | | Juno: Disable workaround for Cortex-A57 erratum #806969Sandrine Bailleux2015-03-111-1/+1
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cortex-A57 erratum #806969 applies to revision r0p0 of the CPU but does not manifest itself on Juno r0. It is not applicable to Juno r1 in any case. This patch modifies the Juno platform Makefile to no longer compile this erratum workaround in. Change-Id: I32b16835b2ac897e639e869ab2b78b62a51a0139
* | | | Merge pull request #264 from jcastillo-arm/jc/tbb_fip_depdanh-arm2015-03-171-1/+1
|\ \ \ \ | | | | | | | | | | TBB: fix build target 'all' dependency on certificates
| * | | | TBB: fix build target 'all' dependency on certificatesJuan Castillo2015-03-051-1/+1
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Build target 'all' fails when GENERATE_COT=1 and no BL3-3 or BL3-0 (if required) images are specified. The reason is that, when GENERATE_COT=1, a dependency on the certificates is added to the target 'all', and the certificates depend on the BL3-3 and BL3-0 images, causing the build process to fail if the images are not specified. This patch moves the dependency on the certificates from 'all' to 'fip'. Target 'all' may be used to build the individual images. The certificates will be created by calling the target 'fip', where BL3-3 and BL3-0 (if required) must be specified. Change-Id: I870beb4e8f9f1bfad1d35b09c850a7ce3c9f4ec6
* | | | Merge pull request #262 from sandrine-bailleux/sb/check-format-printfdanh-arm2015-03-175-24/+25
|\ \ \ \ | | | | | | | | | | Enable type-checking of arguments passed to printf() et al.
| * | | | Enable type-checking of arguments passed to printf() et al.Sandrine Bailleux2015-03-065-24/+25
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch modifies the declarations of the functions printf() et al. and adds the right GCC attribute to request the compiler to check the type of the arguments passed to these functions against the given format string. This will ensure that the compiler outputs warning messages like the following whenever it detects an inconsistency: file.c:42: warning: format ‘%d’ expects type ‘int’, but argument 3 has type ‘long int’ It also fixes the type mismatch inconsistencies that it revealed across the code base. NOTE: THIS PATCH MAY FORCE PLATFORM PORTS OR SP/SPDS THAT USE THE PRINTF FAMILY OF FUNCTIONS TO FIX ANY TYPE MISMATCH INCONSISTENCIES. Change-Id: If36bb54ec7d6dd2cb4791d89b02a24ac13fd2df6
* | | | Merge pull request #265 from jcastillo-arm/jc/git_commit_iddanh-arm2015-03-171-1/+3
|\ \ \ \ | |_|_|/ |/| | | checkpatch: ignore GIT_COMMIT_ID
| * | | checkpatch: ignore GIT_COMMIT_IDJuan Castillo2015-03-111-1/+3
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default, the checkpatch script requires that commit references included in commit messages follow a predefined format. Github merge commits do not follow this convention, causing the code style test to fail when a new pull request is created. This patch adds the ignore GIT_COMMIT_ID option to the checkpatch parameters. This flag indicates the tool to ignore the commit message format. Change-Id: I37133cc5cf803f664b8ff00f62d458b39f06918c
* | | Merge pull request #260 from jcastillo-arm/jc/tbb_sha256danh-arm2015-03-062-5/+4
|\ \ \ | |/ / |/| / | |/ TBB: use SHA256 to generate the certificate signatures
| * TBB: use SHA256 to generate the certificate signaturesJuan Castillo2015-03-052-5/+4
|/ | | | | | | | | | This patch replaces SHA1 by SHA256 in the 'cert_create' tool, so certificate signatures are generated according to the NSA Suite B cryptographic algorithm requirements. Documentation updated accordingly. Change-Id: I7be79e6b2b62dac8dc78a4f4f5006e37686bccf6
* Merge pull request #261 from sandrine-bailleux/sb/coding-styledanh-arm2015-03-057-10/+12
|\ | | | | | | Ignore C library files when checking coding style Fix violations to the coding style
| * Fix violations to the coding styleSandrine Bailleux2015-03-056-8/+8
| | | | | | | | | | | | | | | | | | | | All coding style violations have been fixed in a previous patch and since then, each individual patch has been checked in this regard. However, the latest version of the checkpatch.pl script from the Linux kernel is more advanced and it is able to flag new errors in the Trusted Firmware codebase. This patch fixes them. Change-Id: I1f332f2440984be85d36b231bb83260368987077
| * Ignore C library files when checking coding styleSandrine Bailleux2015-03-051-2/+4
|/ | | | | | | | | | | | | | The C library source files embedded into the Trusted Firmware tree are not required to comply to the Linux Coding Style. Unfortunately, 'make checkpatch' does take them into account. This patch modifies the Makefile so that the C library source and header files are now ignored by 'make checkpatch'. It also instructs the checkpatch.pl script to not treat the presence of a 'Change-Id' line in the commit message as an error. Change-Id: I38196202efe518bae3a57c2affe2ed7758c9f69c
* Merge pull request #259 from soby-mathew/sm/plat_max_afflvldanh-arm2015-02-2511-59/+29
|\ | | | | Export maximum affinity using PLATFORM_MAX_AFFLVL macro
| * Export maximum affinity using PLATFORM_MAX_AFFLVL macroSoby Mathew2015-02-1211-59/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the plat_get_max_afflvl() platform API and instead replaces it with a platform macro PLATFORM_MAX_AFFLVL. This is done because the maximum affinity level for a platform is a static value and it is more efficient for it to be defined as a platform macro. NOTE: PLATFORM PORTS NEED TO BE UPDATED ON MERGE OF THIS COMMIT Fixes ARM-Software/tf-issues#265 Change-Id: I31d89b30c2ccda30d28271154d869060d50df7bf
* | Merge pull request #258 from rmurphy-arm/rm/dma-smmudanh-arm2015-02-252-0/+22
|\ \ | | | | | | Juno: clear DMA-330 SMMU security state
| * | Juno: clear DMA-330 SMMU security stateRobin Murphy2015-02-162-0/+22
| |/ | | | | | | | | | | | | | | | | | | | | | | | | By default the SMMU for the DMA-330 is configured to mark some stream IDs as always belonging to the Secure world. As a result, if EL1 software turns the SMMU on, certain Non-Secure accesses get rewritten as Secure, making them bypass translation and access Secure physical addresses directly. Since the current Juno board firmware configures the DMA-330 hardware as Non-Secure, rewrite the SMMU's default SSD table as well to prevent any unexpected behaviour in EL1. Change-Id: Iaa81d883eecf28d80eb182b9ce475684bf9c718c
* | Merge pull request #257 from soby-mathew/sm/opt_mmap_regdanh-arm2015-02-196-2/+62
|\ \ | |/ |/| Minimize MAX_MMAP_REGIONS for each BL stage
| * Minimize MAX_MMAP_REGIONS for each BL stageSoby Mathew2015-02-126-2/+62
|/ | | | | | | | | | This patch defines MAX_MMAP_REGIONS separately for each BL stage as per its requirements. This minimizes the size of the mmap[] array. Fixes ARM-Software/tf-issues#201 Change-Id: I19b15e1a91a8365b2ecf24e2cd71937cb73916b2
* Merge pull request #256 from achingupta/ag/v1.1-rc2-fixv1.1-rc3v1.1achingupta2015-02-041-0/+1
|\ | | | | Fix model command line for legacy VE memory map
| * Fix model command line for legacy VE memory mapAchin Gupta2015-02-041-0/+1
|/ | | | | | | | | The command line options specified in the User Guide to run the AEMv8 Base FVP with the legacy VE memory map apply only when the model is configured to use GIC v2.0. This patch adds the 'gicv3.gicv2-only=1' to the command line to ensure that the right version of GIC is used. Change-Id: I34c44e19fd42c29818b734ac8f6aa9bf97b4e891
* Merge pull request #254 from achingupta/ag/v1.1-doc-updatesv1.1-rc2danh-arm2015-02-035-22/+192
|\ | | | | Documentation for version 1.1
| * Documentation for version 1.1Achin Gupta2015-02-035-22/+192
| | | | | | | | | | | | | | Final updates to readme.md and change-log.md for ARM Trusted Firmware version 1.1. Also increment the version in the Makefile. Change-Id: Ib001a6ec9a9c570985841d06f0ff80ed76c2996b
* | Merge pull request #255 from jcastillo-arm/jc/cert_create_gerritdanh-arm2015-02-033-0/+422
|\ \ | | | | | | TBB: Add documentation for Trusted Board Boot
| * | TBB: Add documentation for Trusted Board BootAchin Gupta2015-02-033-0/+422
|/ / | | | | | | | | | | | | | | | | This patch updates the user-guide.md with the various build options related to Trusted Board Boot and steps to build a FIP image which includes this support. It also adds a trusted-board-boot.md which describes the scope and design of this feature. Change-Id: Ifb421268ebf7e06a135684c8ebb04c94835ce061
* | Merge pull request #253 from danh-arm/dh/deps-for-v1.1danh-arm2015-02-021-100/+41
|\ \ | | | | | | Move up dependency versions in user guide
| * | Move up dependency versions in user guideSandrine Bailleux2015-02-021-100/+41
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move up the version numbers in the user guide of: * DS-5 (to v5.20) * EDK2 (to v2.1-rc0) * Linux Kernel (to 1.3-Juno) * Linaro file-system (to 14.12) * Juno SCP binary (to 1.5.0-rc0 within board recovery image 0.10.1). Also remove duplicate information that is available from the ARM Connected Community website. * Base FVP (to 6.2) * Foundation FVP (to 9.1). Also update the name of the Foundation FVP binary since it has changed since version 2.1. Co-Authored-By: Dan Handley <dan.handley@arm.com> Change-Id: I1cf2f2b1a3f1b997ac905a4ab440876d265698c0
* | Merge pull request #252 from sandrine-bailleux/v1.1-misc-doc-fixesdanh-arm2015-02-024-12/+9
|\ \ | |/ |/| Miscellaneous doc fixes for v1.1
| * Miscellaneous doc fixes for v1.1Sandrine Bailleux2015-02-024-12/+9
|/ | | | Change-Id: Iaf9d6305edc478d39cf1b37c8a70ccdf723e8ef9
* Merge pull request #251 from soby-mathew/sm/reset_handler_fix_v2v1.1-rc1danh-arm2015-01-305-9/+17
|\ | | | | Fix the Cortex-A57 reset handler register usage v2
| * Fix the Cortex-A57 reset handler register usageSoby Mathew2015-01-305-9/+17
|/ | | | | | | | | | | | | | The CPU specific reset handlers no longer have the freedom of using any general purpose register because it is being invoked by the BL3-1 entry point in addition to BL1. The Cortex-A57 CPU specific reset handler was overwriting x20 register which was being used by the BL3-1 entry point to save the entry point information. This patch fixes this bug by reworking the register allocation in the Cortex-A57 reset handler to avoid using x20. The patch also explicitly mentions the register clobber list for each of the callee functions invoked by the reset handler Change-Id: I28fcff8e742aeed883eaec8f6c4ee2bd3fce30df
* Merge pull request #249 from danh-arm/jc/tbb_prototypev1.1-rc0danh-arm2015-01-2861-21/+5312
|\ | | | | Trusted Board Boot Prototype
| * TBB: authenticate BL3-x images and certificatesJuan Castillo2015-01-286-2/+428
| | | | | | | | | | | | | | This patch adds support to authenticate the Trusted Key certificate and the BL3-x certificates and images at BL2. Change-Id: I69a8c13a14c8da8b75f93097d3a4576aed71c5dd
| * FVP: initialize IO framework in bl2_early_platform_setup()Juan Castillo2015-01-281-3/+3
| | | | | | | | | | | | | | This patch moves fvp_io_setup() to bl2_early_platform_setup() in order to allow BL2 to use the IO framework before bl2_platform_setup(). Change-Id: I75e1a772ab5f9b4727f6727822a2527c30f3c63d
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