diff options
Diffstat (limited to 'plat/rockchip')
-rw-r--r-- | plat/rockchip/common/bl31_plat_setup.c | 2 | ||||
-rw-r--r-- | plat/rockchip/common/drivers/pmu/pmu_com.h | 2 | ||||
-rw-r--r-- | plat/rockchip/common/sp_min_plat_setup.c | 2 | ||||
-rw-r--r-- | plat/rockchip/rk3288/drivers/pmu/pmu.c | 2 | ||||
-rw-r--r-- | plat/rockchip/rk3288/drivers/soc/soc.c | 2 | ||||
-rw-r--r-- | plat/rockchip/rk3328/drivers/pmu/pmu.c | 6 | ||||
-rw-r--r-- | plat/rockchip/rk3328/drivers/soc/soc.h | 2 | ||||
-rw-r--r-- | plat/rockchip/rk3368/drivers/soc/soc.c | 2 | ||||
-rw-r--r-- | plat/rockchip/rk3399/drivers/dram/dfs.c | 2 | ||||
-rw-r--r-- | plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h | 2 | ||||
-rw-r--r-- | plat/rockchip/rk3399/drivers/dram/suspend.c | 2 | ||||
-rw-r--r-- | plat/rockchip/rk3399/drivers/m0/src/suspend.c | 2 | ||||
-rw-r--r-- | plat/rockchip/rk3399/drivers/secure/secure.h | 2 | ||||
-rw-r--r-- | plat/rockchip/rk3399/drivers/soc/soc.c | 2 |
14 files changed, 16 insertions, 16 deletions
diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c index 98ef415c9..59db3d85c 100644 --- a/plat/rockchip/common/bl31_plat_setup.c +++ b/plat/rockchip/common/bl31_plat_setup.c @@ -87,7 +87,7 @@ void bl31_platform_setup(void) /******************************************************************************* * Perform the very early platform specific architectural setup here. At the - * moment this is only intializes the mmu in a quick and dirty way. + * moment this is only initializes the mmu in a quick and dirty way. ******************************************************************************/ void bl31_plat_arch_setup(void) { diff --git a/plat/rockchip/common/drivers/pmu/pmu_com.h b/plat/rockchip/common/drivers/pmu/pmu_com.h index 5359f73b4..022bb024a 100644 --- a/plat/rockchip/common/drivers/pmu/pmu_com.h +++ b/plat/rockchip/common/drivers/pmu/pmu_com.h @@ -90,7 +90,7 @@ static int check_cpu_wfie(uint32_t cpu_id, uint32_t wfie_msk) /* * wfe/wfi tracking not possible, hopefully the host - * was sucessful in enabling wfe/wfi. + * was successful in enabling wfe/wfi. * We'll give a bit of additional time, like the kernel does. */ if ((cluster_id && clstb_cpu_wfe < 0) || diff --git a/plat/rockchip/common/sp_min_plat_setup.c b/plat/rockchip/common/sp_min_plat_setup.c index 0237b167f..8fb3f8ef1 100644 --- a/plat/rockchip/common/sp_min_plat_setup.c +++ b/plat/rockchip/common/sp_min_plat_setup.c @@ -82,7 +82,7 @@ void sp_min_platform_setup(void) /******************************************************************************* * Perform the very early platform specific architectural setup here. At the - * moment this is only intializes the mmu in a quick and dirty way. + * moment this is only initializes the mmu in a quick and dirty way. ******************************************************************************/ void sp_min_plat_arch_setup(void) { diff --git a/plat/rockchip/rk3288/drivers/pmu/pmu.c b/plat/rockchip/rk3288/drivers/pmu/pmu.c index d6d709887..085976c16 100644 --- a/plat/rockchip/rk3288/drivers/pmu/pmu.c +++ b/plat/rockchip/rk3288/drivers/pmu/pmu.c @@ -288,7 +288,7 @@ int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint) /* * We communicate with the bootrom to active the cpus other * than cpu0, after a blob of initialize code, they will - * stay at wfe state, once they are actived, they will check + * stay at wfe state, once they are activated, they will check * the mailbox: * sram_base_addr + 4: 0xdeadbeaf * sram_base_addr + 8: start address for pc diff --git a/plat/rockchip/rk3288/drivers/soc/soc.c b/plat/rockchip/rk3288/drivers/soc/soc.c index 36f410b1a..2316fbebe 100644 --- a/plat/rockchip/rk3288/drivers/soc/soc.c +++ b/plat/rockchip/rk3288/drivers/soc/soc.c @@ -216,7 +216,7 @@ void __dead2 rockchip_soc_soft_reset(void) /* * Maybe the HW needs some times to reset the system, - * so we do not hope the core to excute valid codes. + * so we do not hope the core to execute valid codes. */ while (1) ; diff --git a/plat/rockchip/rk3328/drivers/pmu/pmu.c b/plat/rockchip/rk3328/drivers/pmu/pmu.c index a17fef9e1..597db978f 100644 --- a/plat/rockchip/rk3328/drivers/pmu/pmu.c +++ b/plat/rockchip/rk3328/drivers/pmu/pmu.c @@ -202,7 +202,7 @@ void __dead2 rockchip_soc_soft_reset(void) dsb(); /* * Maybe the HW needs some times to reset the system, - * so we do not hope the core to excute valid codes. + * so we do not hope the core to execute valid codes. */ while (1) ; @@ -210,7 +210,7 @@ void __dead2 rockchip_soc_soft_reset(void) /* * For PMIC RK805, its sleep pin is connect with gpio2_d2 from rk3328. - * If the PMIC is configed for responding the sleep pin to power off it, + * If the PMIC is configured for responding the sleep pin to power off it, * once the pin is output high, it will get the pmic power off. */ void __dead2 rockchip_soc_system_off(void) @@ -462,7 +462,7 @@ static __sramfunc void sram_udelay(uint32_t us) /* * For PMIC RK805, its sleep pin is connect with gpio2_d2 from rk3328. - * If the PMIC is configed for responding the sleep pin + * If the PMIC is configured for responding the sleep pin * to get it into sleep mode, * once the pin is output high, it will get the pmic into sleep mode. */ diff --git a/plat/rockchip/rk3328/drivers/soc/soc.h b/plat/rockchip/rk3328/drivers/soc/soc.h index e8cbc09f6..e081f7171 100644 --- a/plat/rockchip/rk3328/drivers/soc/soc.h +++ b/plat/rockchip/rk3328/drivers/soc/soc.h @@ -27,7 +27,7 @@ enum plls_id { DPLL_ID, CPLL_ID, GPLL_ID, - REVERVE, + RESERVE, NPLL_ID, MAX_PLL, }; diff --git a/plat/rockchip/rk3368/drivers/soc/soc.c b/plat/rockchip/rk3368/drivers/soc/soc.c index 7d51bb8e8..9bb237f80 100644 --- a/plat/rockchip/rk3368/drivers/soc/soc.c +++ b/plat/rockchip/rk3368/drivers/soc/soc.c @@ -202,7 +202,7 @@ void __dead2 rockchip_soc_soft_reset(void) /* * Maybe the HW needs some times to reset the system, - * so we do not hope the core to excute valid codes. + * so we do not hope the core to execute valid codes. */ while (1) ; diff --git a/plat/rockchip/rk3399/drivers/dram/dfs.c b/plat/rockchip/rk3399/drivers/dram/dfs.c index 816372bfc..11b0373a7 100644 --- a/plat/rockchip/rk3399/drivers/dram/dfs.c +++ b/plat/rockchip/rk3399/drivers/dram/dfs.c @@ -1696,7 +1696,7 @@ static int to_get_clk_index(unsigned int mhz) pll_cnt = ARRAY_SIZE(dpll_rates_table); - /* Assumming rate_table is in descending order */ + /* Assuming rate_table is in descending order */ for (i = 0; i < pll_cnt; i++) { if (mhz >= dpll_rates_table[i].mhz) break; diff --git a/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h b/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h index 9cda22ca9..102ba789f 100644 --- a/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h +++ b/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h @@ -103,7 +103,7 @@ struct dram_timing_t { uint32_t tcksre; uint32_t tcksrx; uint32_t tdpd; - /* mode regiter timing */ + /* mode register timing */ uint32_t tmod; uint32_t tmrd; uint32_t tmrr; diff --git a/plat/rockchip/rk3399/drivers/dram/suspend.c b/plat/rockchip/rk3399/drivers/dram/suspend.c index a8b1c32d5..caa784c79 100644 --- a/plat/rockchip/rk3399/drivers/dram/suspend.c +++ b/plat/rockchip/rk3399/drivers/dram/suspend.c @@ -561,7 +561,7 @@ static __pmusramfunc int dram_switch_to_next_index( ch_count = sdram_params->num_channels; - /* LPDDR4 f2 cann't do training, all training will fail */ + /* LPDDR4 f2 can't do training, all training will fail */ for (ch = 0; ch < ch_count; ch++) { /* * Without this disabled for LPDDR4 we end up writing 0's diff --git a/plat/rockchip/rk3399/drivers/m0/src/suspend.c b/plat/rockchip/rk3399/drivers/m0/src/suspend.c index 9ad2fa26a..8a0ea32ab 100644 --- a/plat/rockchip/rk3399/drivers/m0/src/suspend.c +++ b/plat/rockchip/rk3399/drivers/m0/src/suspend.c @@ -30,7 +30,7 @@ __attribute__((noreturn)) void m0_main(void) } /* - * FSM power secquence is .. -> ST_INPUT_CLAMP(step.17) -> .. -> + * FSM power sequence is .. -> ST_INPUT_CLAMP(step.17) -> .. -> * ST_WAKEUP_RESET -> ST_EXT_PWRUP-> ST_RELEASE_CLAMP -> * ST_24M_OSC_EN -> .. -> ST_WAKEUP_RESET_CLR(step.26) -> .., * INPUT_CLAMP and WAKEUP_RESET will hold the SOC not affect by diff --git a/plat/rockchip/rk3399/drivers/secure/secure.h b/plat/rockchip/rk3399/drivers/secure/secure.h index e31c999b7..79997b2f6 100644 --- a/plat/rockchip/rk3399/drivers/secure/secure.h +++ b/plat/rockchip/rk3399/drivers/secure/secure.h @@ -32,7 +32,7 @@ /* security config pmu slave ip */ /* All of slaves is ns */ #define SGRF_PMU_SLV_S_NS BIT_WITH_WMSK(0) -/* slaves secure attr is configed */ +/* slaves secure attr is configured */ #define SGRF_PMU_SLV_S_CFGED WMSK_BIT(0) #define SGRF_PMU_SLV_CRYPTO1_NS WMSK_BIT(1) diff --git a/plat/rockchip/rk3399/drivers/soc/soc.c b/plat/rockchip/rk3399/drivers/soc/soc.c index 98b5ad646..e2b2934b0 100644 --- a/plat/rockchip/rk3399/drivers/soc/soc.c +++ b/plat/rockchip/rk3399/drivers/soc/soc.c @@ -343,7 +343,7 @@ void __dead2 soc_global_soft_reset(void) /* * Maybe the HW needs some times to reset the system, - * so we do not hope the core to excute valid codes. + * so we do not hope the core to execute valid codes. */ while (1) ; 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