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-rw-r--r--plat/rockchip/rk3288/drivers/pmu/pmu.c2
-rw-r--r--plat/rockchip/rk3288/drivers/soc/soc.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/plat/rockchip/rk3288/drivers/pmu/pmu.c b/plat/rockchip/rk3288/drivers/pmu/pmu.c
index d6d709887..085976c16 100644
--- a/plat/rockchip/rk3288/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3288/drivers/pmu/pmu.c
@@ -288,7 +288,7 @@ int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint)
/*
* We communicate with the bootrom to active the cpus other
* than cpu0, after a blob of initialize code, they will
- * stay at wfe state, once they are actived, they will check
+ * stay at wfe state, once they are activated, they will check
* the mailbox:
* sram_base_addr + 4: 0xdeadbeaf
* sram_base_addr + 8: start address for pc
diff --git a/plat/rockchip/rk3288/drivers/soc/soc.c b/plat/rockchip/rk3288/drivers/soc/soc.c
index 36f410b1a..2316fbebe 100644
--- a/plat/rockchip/rk3288/drivers/soc/soc.c
+++ b/plat/rockchip/rk3288/drivers/soc/soc.c
@@ -216,7 +216,7 @@ void __dead2 rockchip_soc_soft_reset(void)
/*
* Maybe the HW needs some times to reset the system,
- * so we do not hope the core to excute valid codes.
+ * so we do not hope the core to execute valid codes.
*/
while (1)
;