diff options
Diffstat (limited to 'plat/nvidia')
18 files changed, 90 insertions, 33 deletions
diff --git a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S index 6c8c4f018..72ecd54e9 100644 --- a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S +++ b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S @@ -125,15 +125,18 @@ .endm /* ----------------------------------------------------- - * unsigned int plat_is_my_cpu_primary(void); + * bool plat_is_my_cpu_primary(void); * * This function checks if this is the Primary CPU + * + * Registers clobbered: x0, x1 * ----------------------------------------------------- */ func plat_is_my_cpu_primary mrs x0, mpidr_el1 - and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) - cmp x0, #TEGRA_PRIMARY_CPU + adr x1, tegra_primary_cpu_mpid + ldr x1, [x1] + cmp x0, x1 cset x0, eq ret endfunc plat_is_my_cpu_primary @@ -251,6 +254,14 @@ _end: mov x0, x20 adr x18, bl31_entrypoint str x18, [x17] + /* ----------------------------------- + * save the boot CPU MPID value + * ----------------------------------- + */ + mrs x0, mpidr_el1 + adr x1, tegra_primary_cpu_mpid + str x0, [x1] + 1: cpu_init_common ret @@ -426,3 +437,10 @@ tegra_bl31_phys_base: */ tegra_console_base: .quad 0 + + /* -------------------------------------------------- + * MPID value for the boot CPU + * -------------------------------------------------- + */ +tegra_primary_cpu_mpid: + .quad 0 diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c index 6a3eae0dd..e3068b699 100644 --- a/plat/nvidia/tegra/common/tegra_bl31_setup.c +++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. + * Copyright (c) 2020-2023, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -92,21 +92,16 @@ plat_params_from_bl2_t *bl31_get_plat_params(void) void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { - struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0; - plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1; + struct tegra_bl31_params *arg_from_bl2 = plat_get_bl31_params(); + plat_params_from_bl2_t *plat_params = plat_get_bl31_plat_params(); int32_t ret; /* - * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so - * there's no argument to relay from a previous bootloader. Platforms - * might use custom ways to get arguments. + * Tegra platforms will receive boot parameters through custom + * mechanisms. So, we ignore the input parameters. */ - if (arg_from_bl2 == NULL) { - arg_from_bl2 = plat_get_bl31_params(); - } - if (plat_params == NULL) { - plat_params = plat_get_bl31_plat_params(); - } + (void)arg0; + (void)arg1; /* * Copy BL3-3, BL3-2 entry point information. @@ -267,7 +262,7 @@ void bl31_plat_runtime_setup(void) /******************************************************************************* * Perform the very early platform specific architectural setup here. At the - * moment this only intializes the mmu in a quick and dirty way. + * moment this only initializes the mmu in a quick and dirty way. ******************************************************************************/ void bl31_plat_arch_setup(void) { diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c index ec34a850d..8edb0247e 100644 --- a/plat/nvidia/tegra/common/tegra_pm.c +++ b/plat/nvidia/tegra/common/tegra_pm.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. + * Copyright (c) 2020-2023, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -92,6 +92,16 @@ static int32_t tegra_pwr_domain_on(u_register_t mpidr) /******************************************************************************* * Handler called when a power domain is about to be turned off. The * target_state encodes the power state that each level should transition to. + * Return error if CPU off sequence is not allowed for the current core. + ******************************************************************************/ +static int tegra_pwr_domain_off_early(const psci_power_state_t *target_state) +{ + return tegra_soc_pwr_domain_off_early(target_state); +} + +/******************************************************************************* + * Handler called when a power domain is about to be turned off. The + * target_state encodes the power state that each level should transition to. ******************************************************************************/ static void tegra_pwr_domain_off(const psci_power_state_t *target_state) { @@ -268,6 +278,7 @@ static int32_t tegra_validate_ns_entrypoint(uintptr_t entrypoint) static plat_psci_ops_t tegra_plat_psci_ops = { .cpu_standby = tegra_cpu_standby, .pwr_domain_on = tegra_pwr_domain_on, + .pwr_domain_off_early = tegra_pwr_domain_off_early, .pwr_domain_off = tegra_pwr_domain_off, .pwr_domain_suspend_pwrdown_early = tegra_pwr_domain_suspend_pwrdown_early, .pwr_domain_suspend = tegra_pwr_domain_suspend, diff --git a/plat/nvidia/tegra/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/drivers/memctrl/memctrl_v2.c index 92120b527..0644fd203 100644 --- a/plat/nvidia/tegra/drivers/memctrl/memctrl_v2.c +++ b/plat/nvidia/tegra/drivers/memctrl/memctrl_v2.c @@ -301,7 +301,7 @@ void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes) if (video_mem_base != 0U) { /* * Lock the non overlapping memory being cleared so that - * other masters do not accidently write to it. The memory + * other masters do not accidentally write to it. The memory * would be unlocked once the non overlapping region is * cleared and the new memory settings take effect. */ diff --git a/plat/nvidia/tegra/include/drivers/tegra_gic.h b/plat/nvidia/tegra/include/drivers/tegra_gic.h index 6661dff76..9f9477c0f 100644 --- a/plat/nvidia/tegra/include/drivers/tegra_gic.h +++ b/plat/nvidia/tegra/include/drivers/tegra_gic.h @@ -19,7 +19,7 @@ typedef struct pcpu_fiq_state { } pcpu_fiq_state_t; /******************************************************************************* - * Fucntion declarations + * Function declarations ******************************************************************************/ void tegra_gic_cpuif_deactivate(void); void tegra_gic_init(void); diff --git a/plat/nvidia/tegra/include/platform_def.h b/plat/nvidia/tegra/include/platform_def.h index 84b3297e0..958a3f972 100644 --- a/plat/nvidia/tegra/include/platform_def.h +++ b/plat/nvidia/tegra/include/platform_def.h @@ -41,8 +41,6 @@ #define PLATFORM_STACK_SIZE U(0x400) #endif -#define TEGRA_PRIMARY_CPU U(0x0) - #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ PLATFORM_MAX_CPUS_PER_CLUSTER) diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h index a971cec93..cf8778b26 100644 --- a/plat/nvidia/tegra/include/t186/tegra_def.h +++ b/plat/nvidia/tegra/include/t186/tegra_def.h @@ -84,7 +84,7 @@ #define TEGRA_CLK_SE TEGRA186_CLK_SE /******************************************************************************* - * Tegra Miscellanous register constants + * Tegra Miscellaneous register constants ******************************************************************************/ #define TEGRA_MISC_BASE U(0x00100000) #define HARDWARE_REVISION_OFFSET U(0x4) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index abe193fcd..2158913be 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -60,7 +60,7 @@ #define TEGRA_CLK_SE TEGRA194_CLK_SE /******************************************************************************* - * Tegra Miscellanous register constants + * Tegra Miscellaneous register constants ******************************************************************************/ #define TEGRA_MISC_BASE U(0x00100000) diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h index cc2ad869c..f93585d9d 100644 --- a/plat/nvidia/tegra/include/tegra_private.h +++ b/plat/nvidia/tegra/include/tegra_private.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. + * Copyright (c) 2020-2023, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -98,6 +98,9 @@ void tegra_fiq_handler_setup(void); int32_t tegra_fiq_get_intr_context(void); void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint); +/* Declarations for tegra_helpers.S */ +bool plat_is_my_cpu_primary(void); + /* Declarations for tegra_security.c */ void tegra_security_setup(void); void tegra_security_setup_videomem(uintptr_t base, uint64_t size); @@ -109,6 +112,7 @@ int32_t tegra_system_suspended(void); int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state); int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state); int32_t tegra_soc_pwr_domain_on(u_register_t mpidr); +int32_t tegra_soc_pwr_domain_off_early(const psci_power_state_t *target_state); int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state); int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state); int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state); @@ -150,7 +154,7 @@ int plat_sip_handler(uint32_t smc_fid, void *handle, uint64_t flags); -#if RAS_EXTENSION +#if RAS_FFH_SUPPORT void tegra194_ras_enable(void); void tegra194_ras_corrected_err_clear(uint64_t *cookie); #endif diff --git a/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h b/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h index ecfb3f4b3..45302da1b 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h +++ b/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h @@ -40,7 +40,7 @@ typedef enum { /* index 83 is deprecated */ TEGRA_ARI_PERFMON = 84U, TEGRA_ARI_UPDATE_CCPLEX_GSC = 85U, - /* index 86 is depracated */ + /* index 86 is deprecated */ /* index 87 is deprecated */ TEGRA_ARI_ROC_FLUSH_CACHE_ONLY = 88U, TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS = 89U, diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c index af4182e24..8f88e2887 100644 --- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c @@ -433,6 +433,16 @@ int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) return PSCI_E_SUCCESS; } +int32_t tegra_soc_pwr_domain_off_early(const psci_power_state_t *target_state) +{ + /* Do not power off the boot CPU */ + if (plat_is_my_cpu_primary()) { + return PSCI_E_DENIED; + } + + return PSCI_E_SUCCESS; +} + int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) { uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK; diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h index 7a68a4303..ca74d2cf9 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h @@ -17,7 +17,7 @@ /** * Current version - Major version increments may break backwards - * compatiblity and binary compatibility. Minor version increments + * compatibility and binary compatibility. Minor version increments * occur when there is only new functionality. */ enum { diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index 41a85ee7c..83d815afc 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -463,6 +463,16 @@ int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) return PSCI_E_SUCCESS; } +int32_t tegra_soc_pwr_domain_off_early(const psci_power_state_t *target_state) +{ + /* Do not power off the boot CPU */ + if (plat_is_my_cpu_primary()) { + return PSCI_E_DENIED; + } + + return PSCI_E_SUCCESS; +} + int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) { uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; diff --git a/plat/nvidia/tegra/soc/t194/plat_ras.c b/plat/nvidia/tegra/soc/t194/plat_ras.c index a9fed0ac7..2f438c3c0 100644 --- a/plat/nvidia/tegra/soc/t194/plat_ras.c +++ b/plat/nvidia/tegra/soc/t194/plat_ras.c @@ -284,7 +284,7 @@ static int32_t tegra194_ras_node_handler(uint32_t errselr, const char *name, ERROR("RAS Error in %s, ERRSELR_EL1=0x%x:\n", name, errselr); ERROR("\tStatus = 0x%" PRIx64 "\n", status); - /* Print uncorrectable errror information. */ + /* Print uncorrectable error information. */ if (ERR_STATUS_GET_FIELD(status, UE) != 0U) { ERR_STATUS_SET_FIELD(val, UE, 1); @@ -484,7 +484,7 @@ REGISTER_RAS_INTERRUPTS(carmel_ras_interrupts); void plat_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie, void *handle, uint64_t flags) { -#if RAS_EXTENSION +#if RAS_FFH_SUPPORT tegra194_ea_handler(ea_reason, syndrome, cookie, handle, flags); #else plat_default_ea_handler(ea_reason, syndrome, cookie, handle, flags); diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index 8f7d1e9a1..d3d09d3dc 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -254,7 +254,7 @@ void plat_early_platform_setup(void) /* sanity check MCE firmware compatibility */ mce_verify_firmware_version(); -#if RAS_EXTENSION +#if RAS_FFH_SUPPORT /* Enable Uncorrectable RAS error */ tegra194_ras_enable(); #endif diff --git a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c index 1eef55912..f0704edb1 100644 --- a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c +++ b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c @@ -71,7 +71,7 @@ int32_t plat_sip_handler(uint32_t smc_fid, break; -#if RAS_EXTENSION +#if RAS_FFH_SUPPORT case TEGRA_SIP_CLEAR_RAS_CORRECTED_ERRORS: { /* diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk index 631c92691..a183d0e9d 100644 --- a/plat/nvidia/tegra/soc/t194/platform_t194.mk +++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk @@ -34,7 +34,8 @@ $(eval $(call add_define,MAX_MMAP_REGIONS)) # enable RAS handling HANDLE_EA_EL3_FIRST_NS := 1 -RAS_EXTENSION := 1 +ENABLE_FEAT_RAS := 1 +RAS_FFH_SUPPORT := 1 # platform files PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t194 \ @@ -68,7 +69,7 @@ BL31_SOURCES += ${TEGRA_DRIVERS}/spe/shared_console.S endif # RAS sources -ifeq (${RAS_EXTENSION},1) +ifeq (${RAS_FFH_SUPPORT},1) BL31_SOURCES += lib/extensions/ras/std_err_record.c \ lib/extensions/ras/ras_common.c \ ${SOC_DIR}/plat_ras.c diff --git a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c index 7f73ea506..2ec044c40 100644 --- a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c @@ -575,6 +575,16 @@ int tegra_soc_pwr_domain_on(u_register_t mpidr) return PSCI_E_SUCCESS; } +int32_t tegra_soc_pwr_domain_off_early(const psci_power_state_t *target_state) +{ + /* Do not power off the boot CPU */ + if (plat_is_my_cpu_primary()) { + return PSCI_E_DENIED; + } + + return PSCI_E_SUCCESS; +} + int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) { tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK); |