diff options
Diffstat (limited to 'plat/imx')
-rw-r--r-- | plat/imx/common/include/sci/sci_rpc.h | 2 | ||||
-rw-r--r-- | plat/imx/common/include/sci/svc/pad/sci_pad_api.h | 4 | ||||
-rw-r--r-- | plat/imx/common/include/sci/svc/pm/sci_pm_api.h | 2 | ||||
-rw-r--r-- | plat/imx/imx8m/gpc_common.c | 2 | ||||
-rw-r--r-- | plat/imx/imx8m/imx8mm/gpc.c | 2 | ||||
-rw-r--r-- | plat/imx/imx8m/imx8mn/gpc.c | 2 | ||||
-rw-r--r-- | plat/imx/imx8m/imx8mp/gpc.c | 2 | ||||
-rw-r--r-- | plat/imx/imx8m/imx8mq/gpc.c | 2 |
8 files changed, 9 insertions, 9 deletions
diff --git a/plat/imx/common/include/sci/sci_rpc.h b/plat/imx/common/include/sci/sci_rpc.h index 60dbc27b6..b6adf3308 100644 --- a/plat/imx/common/include/sci/sci_rpc.h +++ b/plat/imx/common/include/sci/sci_rpc.h @@ -100,7 +100,7 @@ typedef struct sc_rpc_async_msg_s { void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, bool no_resp); /*! - * This is an internal function to dispath an RPC call that has + * This is an internal function to dispatch an RPC call that has * arrived via IPC over an MU. It is called by server-side SCFW. * * @param[in] mu MU message arrived on diff --git a/plat/imx/common/include/sci/svc/pad/sci_pad_api.h b/plat/imx/common/include/sci/svc/pad/sci_pad_api.h index dc23eedb3..ac93aae3f 100644 --- a/plat/imx/common/include/sci/svc/pad/sci_pad_api.h +++ b/plat/imx/common/include/sci/svc/pad/sci_pad_api.h @@ -42,7 +42,7 @@ * * Pads are managed as a resource by the Resource Manager (RM). They have * assigned owners and only the owners can configure the pads. Some of the - * pads are reserved for use by the SCFW itself and this can be overriden + * pads are reserved for use by the SCFW itself and this can be overridden * with the implementation of board_config_sc(). Additionally, pads may * be assigned to various other partitions via the implementation of * board_system_config(). @@ -156,7 +156,7 @@ typedef uint8_t sc_pad_config_t; * This type is used to declare a pad low-power isolation config. * ISO_LATE is the most common setting. ISO_EARLY is only used when * an output pad is directly determined by another input pad. The - * other two are only used when SW wants to directly contol isolation. + * other two are only used when SW wants to directly control isolation. */ typedef uint8_t sc_pad_iso_t; diff --git a/plat/imx/common/include/sci/svc/pm/sci_pm_api.h b/plat/imx/common/include/sci/svc/pm/sci_pm_api.h index 76ca5c4ea..13647956a 100644 --- a/plat/imx/common/include/sci/svc/pm/sci_pm_api.h +++ b/plat/imx/common/include/sci/svc/pm/sci_pm_api.h @@ -294,7 +294,7 @@ sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt, * Note some resources are still not accessible even when powered up if bus * transactions go through a fabric not powered up. Examples of this are * resources in display and capture subsystems which require the display - * controller or the imaging subsytem to be powered up first. + * controller or the imaging subsystem to be powered up first. * * Not that resources are grouped into power domains by the underlying * hardware. If any resource in the domain is on, the entire power domain diff --git a/plat/imx/imx8m/gpc_common.c b/plat/imx/imx8m/gpc_common.c index 32a35ef0b..71e0af1fd 100644 --- a/plat/imx/imx8m/gpc_common.c +++ b/plat/imx/imx8m/gpc_common.c @@ -98,7 +98,7 @@ void imx_set_cpu_lpm(unsigned int core_id, bool pdn) /* assert the pcg pcr bit of the core */ mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); } else { - /* disbale CORE WFI PDN & IRQ PUP */ + /* disable CORE WFI PDN & IRQ PUP */ mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | COREx_IRQ_WUP(core_id)); /* deassert the pcg pcr bit of the core */ diff --git a/plat/imx/imx8m/imx8mm/gpc.c b/plat/imx/imx8m/imx8mm/gpc.c index cc1cb1066..e0e38a9ae 100644 --- a/plat/imx/imx8m/imx8mm/gpc.c +++ b/plat/imx/imx8m/imx8mm/gpc.c @@ -376,7 +376,7 @@ void imx_gpc_init(void) /* * Set the CORE & SCU power up timing: * SW = 0x1, SW2ISO = 0x1; - * the CPU CORE and SCU power up timming counter + * the CPU CORE and SCU power up timing counter * is drived by 32K OSC, each domain's power up * latency is (SW + SW2ISO) / 32768 */ diff --git a/plat/imx/imx8m/imx8mn/gpc.c b/plat/imx/imx8m/imx8mn/gpc.c index 4e052972c..20c9a5561 100644 --- a/plat/imx/imx8m/imx8mn/gpc.c +++ b/plat/imx/imx8m/imx8mn/gpc.c @@ -170,7 +170,7 @@ void imx_gpc_init(void) /* * Set the CORE & SCU power up timing: * SW = 0x1, SW2ISO = 0x1; - * the CPU CORE and SCU power up timming counter + * the CPU CORE and SCU power up timing counter * is drived by 32K OSC, each domain's power up * latency is (SW + SW2ISO) / 32768 */ diff --git a/plat/imx/imx8m/imx8mp/gpc.c b/plat/imx/imx8m/imx8mp/gpc.c index 452e7883c..956b50817 100644 --- a/plat/imx/imx8m/imx8mp/gpc.c +++ b/plat/imx/imx8m/imx8mp/gpc.c @@ -337,7 +337,7 @@ void imx_gpc_init(void) /* * Set the CORE & SCU power up timing: * SW = 0x1, SW2ISO = 0x1; - * the CPU CORE and SCU power up timming counter + * the CPU CORE and SCU power up timing counter * is drived by 32K OSC, each domain's power up * latency is (SW + SW2ISO) / 32768 */ diff --git a/plat/imx/imx8m/imx8mq/gpc.c b/plat/imx/imx8m/imx8mq/gpc.c index 0a029d66c..ebf92f724 100644 --- a/plat/imx/imx8m/imx8mq/gpc.c +++ b/plat/imx/imx8m/imx8mq/gpc.c @@ -417,7 +417,7 @@ void imx_gpc_init(void) /* set all mix/PU in A53 domain */ mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xfffd); - /* set SCU timming */ + /* set SCU timing */ mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING, (0x59 << 10) | 0x5B | (0x2 << 20)); |