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-rw-r--r--plat/arm/board/a5ds/platform.mk2
-rw-r--r--plat/arm/board/fvp/aarch64/fvp_ras.c51
-rw-r--r--plat/arm/board/fvp/fvp_cpu_errata.mk61
-rw-r--r--plat/arm/board/fvp/include/platform_def.h12
-rw-r--r--plat/arm/board/fvp/platform.mk19
-rw-r--r--plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c2
-rw-r--r--plat/arm/board/tc/include/platform_def.h13
-rw-r--r--plat/arm/board/tc/platform.mk7
-rw-r--r--plat/arm/board/tc/tc_bl31_setup.c35
-rw-r--r--plat/arm/board/tc/tc_plat.c11
-rw-r--r--plat/arm/common/arm_bl31_setup.c5
-rw-r--r--plat/arm/common/arm_common.mk2
-rw-r--r--plat/arm/common/tsp/arm_tsp_setup.c2
-rw-r--r--plat/arm/css/sgi/include/sgi_base_platform_def.h4
-rw-r--r--plat/arm/css/sgi/sgi-common.mk6
-rw-r--r--plat/arm/css/sgi/sgi_bl31_setup.c2
-rw-r--r--plat/arm/css/sgi/sgi_plat.c2
17 files changed, 212 insertions, 24 deletions
diff --git a/plat/arm/board/a5ds/platform.mk b/plat/arm/board/a5ds/platform.mk
index 4f873069a..6fcf080a1 100644
--- a/plat/arm/board/a5ds/platform.mk
+++ b/plat/arm/board/a5ds/platform.mk
@@ -100,6 +100,8 @@ NEED_BL32 := yes
MULTI_CONSOLE_API := 1
+ARM_DISABLE_TRUSTED_WDOG := 1
+
PLAT_BL_COMMON_SOURCES += lib/xlat_tables/aarch32/nonlpae_tables.c
# Use translation tables library v1 when using Cortex-A5
diff --git a/plat/arm/board/fvp/aarch64/fvp_ras.c b/plat/arm/board/fvp/aarch64/fvp_ras.c
index 759f6d0d8..f9b96341a 100644
--- a/plat/arm/board/fvp/aarch64/fvp_ras.c
+++ b/plat/arm/board/fvp/aarch64/fvp_ras.c
@@ -4,12 +4,63 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <inttypes.h>
+#include <stdint.h>
+
#include <lib/extensions/ras.h>
+#include <services/sdei.h>
+
+#ifdef PLATFORM_TEST_RAS_FFH
+static int injected_fault_handler(const struct err_record_info *info,
+ int probe_data, const struct err_handler_data *const data)
+{
+ uint64_t status;
+ int ret;
+
+ /*
+ * The faulting error record is already selected by the SER probe
+ * function.
+ */
+ status = read_erxstatus_el1();
+
+ ERROR("Fault reported by system error record %d on 0x%lx: status=0x%" PRIx64 "\n",
+ probe_data, read_mpidr_el1(), status);
+ ERROR(" exception reason=%u syndrome=0x%" PRIx64 "\n", data->ea_reason,
+ data->flags);
+
+ /* Clear error */
+ write_erxstatus_el1(status);
+
+ ret = sdei_dispatch_event(5000);
+ if (ret < 0) {
+ ERROR("Can't dispatch event to SDEI\n");
+ panic();
+ } else {
+ INFO("SDEI event dispatched\n");
+ }
+
+ return 0;
+}
+
+void plat_handle_uncontainable_ea(void)
+{
+ /* Do not change the string, CI expects it. Wait forever */
+ INFO("Injected Uncontainable Error\n");
+ while (true) {
+ wfe();
+ }
+}
+#endif
struct ras_interrupt fvp_ras_interrupts[] = {
};
struct err_record_info fvp_err_records[] = {
+#ifdef PLATFORM_TEST_RAS_FFH
+ /* Record for injected fault */
+ ERR_RECORD_SYSREG_V1(0, 2, ras_err_ser_probe_sysreg,
+ injected_fault_handler, NULL),
+#endif
};
REGISTER_ERR_RECORD_INFO(fvp_err_records);
diff --git a/plat/arm/board/fvp/fvp_cpu_errata.mk b/plat/arm/board/fvp/fvp_cpu_errata.mk
new file mode 100644
index 000000000..944571dd5
--- /dev/null
+++ b/plat/arm/board/fvp/fvp_cpu_errata.mk
@@ -0,0 +1,61 @@
+#
+# Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+
+#/*
+# * TODO: below lines of code to be removed
+# * after abi and framework are synchronized
+# */
+
+ifeq (${ERRATA_ABI_SUPPORT}, 1)
+# enable the cpu macros for errata abi interface
+ifeq (${ARCH}, aarch64)
+ifeq (${HW_ASSISTED_COHERENCY}, 0)
+CORTEX_A35_H_INC := 1
+CORTEX_A53_H_INC := 1
+CORTEX_A57_H_INC := 1
+CORTEX_A72_H_INC := 1
+CORTEX_A73_H_INC := 1
+$(eval $(call add_define, CORTEX_A35_H_INC))
+$(eval $(call add_define, CORTEX_A53_H_INC))
+$(eval $(call add_define, CORTEX_A57_H_INC))
+$(eval $(call add_define, CORTEX_A72_H_INC))
+$(eval $(call add_define, CORTEX_A73_H_INC))
+else
+ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0)
+CORTEX_A76_H_INC := 1
+CORTEX_A77_H_INC := 1
+CORTEX_A78_H_INC := 1
+NEOVERSE_N1_H_INC := 1
+NEOVERSE_V1_H_INC := 1
+CORTEX_A78_AE_H_INC := 1
+CORTEX_A510_H_INC := 1
+CORTEX_A710_H_INC := 1
+CORTEX_A715_H_INC := 1
+CORTEX_A78C_H_INC := 1
+CORTEX_X2_H_INC := 1
+$(eval $(call add_define, CORTEX_A76_H_INC))
+$(eval $(call add_define, CORTEX_A77_H_INC))
+$(eval $(call add_define, CORTEX_A78_H_INC))
+$(eval $(call add_define, NEOVERSE_N1_H_INC))
+$(eval $(call add_define, NEOVERSE_V1_H_INC))
+$(eval $(call add_define, CORTEX_A78_AE_H_INC))
+$(eval $(call add_define, CORTEX_A510_H_INC))
+$(eval $(call add_define, CORTEX_A710_H_INC))
+$(eval $(call add_define, CORTEX_A715_H_INC))
+$(eval $(call add_define, CORTEX_A78C_H_INC))
+$(eval $(call add_define, CORTEX_X2_H_INC))
+endif
+CORTEX_A55_H_INC := 1
+CORTEX_A75_H_INC := 1
+$(eval $(call add_define, CORTEX_A55_H_INC))
+$(eval $(call add_define, CORTEX_A75_H_INC))
+endif
+else
+CORTEX_A32_H_INC := 1
+$(eval $(call add_define, CORTEX_A32_H_INC))
+endif
+endif
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index 79d7451ef..9e72ba08c 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -397,7 +397,17 @@ defined(IMAGE_BL2) && MEASURED_BOOT
#define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT
#define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT
#else
-#define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS
+ #if PLATFORM_TEST_RAS_FFH
+ #define PLAT_ARM_PRIVATE_SDEI_EVENTS \
+ ARM_SDEI_PRIVATE_EVENTS, \
+ SDEI_EXPLICIT_EVENT(5000, SDEI_MAPF_NORMAL), \
+ SDEI_EXPLICIT_EVENT(5001, SDEI_MAPF_NORMAL), \
+ SDEI_EXPLICIT_EVENT(5002, SDEI_MAPF_NORMAL), \
+ SDEI_EXPLICIT_EVENT(5003, SDEI_MAPF_CRITICAL), \
+ SDEI_EXPLICIT_EVENT(5004, SDEI_MAPF_CRITICAL)
+ #else
+ #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS
+ #endif
#define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS
#endif
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index ea3f95486..0433b61d5 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -50,6 +50,7 @@ ifneq (${SPD}, tspd)
ENABLE_FEAT_RNG := 2
ENABLE_FEAT_TWED := 2
ENABLE_FEAT_GCS := 2
+ ENABLE_FEAT_RAS := 2
ifeq (${ARCH}, aarch64)
ifneq (${SPD}, spmd)
ifeq (${SPM_MM}, 0)
@@ -387,7 +388,7 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \
endif
endif
-ifeq (${RAS_EXTENSION},1)
+ifeq (${RAS_FFH_SUPPORT},1)
BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c
endif
@@ -505,6 +506,11 @@ endif
PSCI_OS_INIT_MODE := 1
+ifeq (${SPD},spmd)
+BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c
+endif
+
+# Test specific macros, keep them at bottom of this file
$(eval $(call add_define,PLATFORM_TEST_EA_FFH))
ifeq (${PLATFORM_TEST_EA_FFH}, 1)
ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0)
@@ -513,6 +519,13 @@ ifeq (${PLATFORM_TEST_EA_FFH}, 1)
BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c
endif
-ifeq (${SPD},spmd)
-BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c
+$(eval $(call add_define,PLATFORM_TEST_RAS_FFH))
+ifeq (${PLATFORM_TEST_RAS_FFH}, 1)
+ ifeq (${RAS_EXTENSION}, 0)
+ $(error "PLATFORM_TEST_RAS_FFH expects RAS_EXTENSION to be 1")
+ endif
+endif
+
+ifeq (${ERRATA_ABI_SUPPORT}, 1)
+include plat/arm/board/fvp/fvp_cpu_errata.mk
endif
diff --git a/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c b/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c
index b961da939..705ec384c 100644
--- a/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c
+++ b/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c
@@ -84,7 +84,7 @@ void sp_min_plat_arch_setup(void)
(void *)hw_config_info->config_addr);
/*
- * Preferrably we expect this address and size are page aligned,
+ * Preferably we expect this address and size are page aligned,
* but if they are not then align it.
*/
hw_config_base_align = page_align(hw_config_info->config_addr, DOWN);
diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h
index eea1be6ba..59fff6e2a 100644
--- a/plat/arm/board/tc/include/platform_def.h
+++ b/plat/arm/board/tc/include/platform_def.h
@@ -212,8 +212,11 @@
#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
#define PLAT_ARM_DRAM2_END (PLAT_ARM_DRAM2_BASE + PLAT_ARM_DRAM2_SIZE - 1ULL)
-#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp)
-#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
+#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_INT_PROPS(grp)
+#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp), \
+ INTR_PROP_DESC(SBSA_SECURE_WDOG_INTID, \
+ GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_LEVEL)
#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
PLAT_SP_IMAGE_NS_BUF_SIZE)
@@ -229,9 +232,11 @@
#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
-/*Secure Watchdog Constants */
-#define SBSA_SECURE_WDOG_BASE UL(0x2A480000)
+/* Secure Watchdog Constants */
+#define SBSA_SECURE_WDOG_CONTROL_BASE UL(0x2A480000)
+#define SBSA_SECURE_WDOG_REFRESH_BASE UL(0x2A490000)
#define SBSA_SECURE_WDOG_TIMEOUT UL(100)
+#define SBSA_SECURE_WDOG_INTID 86
#define PLAT_ARM_SCMI_CHANNEL_COUNT 1
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index 63a923795..98c2e0ed6 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk
@@ -20,7 +20,9 @@ CSS_LOAD_SCP_IMAGES := 1
CSS_USE_SCMI_SDS_DRIVER := 1
-RAS_EXTENSION := 0
+ENABLE_FEAT_RAS := 1
+
+RAS_FFH_SUPPORT := 0
SDEI_SUPPORT := 0
@@ -118,7 +120,8 @@ BL31_SOURCES += ${INTERCONNECT_SOURCES} \
lib/fconf/fconf_dyn_cfg_getter.c \
drivers/cfi/v2m/v2m_flash.c \
lib/utils/mem_region.c \
- plat/arm/common/arm_nor_psci_mem_protect.c
+ plat/arm/common/arm_nor_psci_mem_protect.c \
+ drivers/arm/sbsa/sbsa.c
BL31_SOURCES += ${FDT_WRAPPERS_SOURCES}
diff --git a/plat/arm/board/tc/tc_bl31_setup.c b/plat/arm/board/tc/tc_bl31_setup.c
index 8ad1d3056..630324fb3 100644
--- a/plat/arm/board/tc/tc_bl31_setup.c
+++ b/plat/arm/board/tc/tc_bl31_setup.c
@@ -13,6 +13,7 @@
#include <common/debug.h>
#include <drivers/arm/css/css_mhu_doorbell.h>
#include <drivers/arm/css/scmi.h>
+#include <drivers/arm/sbsa.h>
#include <lib/fconf/fconf.h>
#include <lib/fconf/fconf_dyn_cfg_getter.h>
#include <plat/arm/common/plat_arm.h>
@@ -81,3 +82,37 @@ void __init bl31_plat_arch_setup(void)
fconf_populate("HW_CONFIG", hw_config_info->config_addr);
}
+
+#if defined(SPD_spmd) && (SPMD_SPM_AT_SEL2 == 1)
+void tc_bl31_plat_runtime_setup(void)
+{
+ arm_bl31_plat_runtime_setup();
+
+ /* Start secure watchdog timer. */
+ plat_arm_secure_wdt_start();
+}
+
+void bl31_plat_runtime_setup(void)
+{
+ tc_bl31_plat_runtime_setup();
+}
+
+/*
+ * Platform handler for Group0 secure interrupt.
+ */
+int plat_spmd_handle_group0_interrupt(uint32_t intid)
+{
+ /* Trusted Watchdog timer is the only source of Group0 interrupt now. */
+ if (intid == SBSA_SECURE_WDOG_INTID) {
+ INFO("Watchdog restarted\n");
+ /* Refresh the timer. */
+ plat_arm_secure_wdt_refresh();
+
+ /* Deactivate the corresponding interrupt. */
+ plat_ic_end_of_interrupt(intid);
+ return 0;
+ }
+
+ return -1;
+}
+#endif /*defined(SPD_spmd) && (SPMD_SPM_AT_SEL2 == 1)*/
diff --git a/plat/arm/board/tc/tc_plat.c b/plat/arm/board/tc/tc_plat.c
index 228f2fab3..766bfb570 100644
--- a/plat/arm/board/tc/tc_plat.c
+++ b/plat/arm/board/tc/tc_plat.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -147,10 +147,15 @@ int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
void plat_arm_secure_wdt_start(void)
{
- sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
+ sbsa_wdog_start(SBSA_SECURE_WDOG_CONTROL_BASE, SBSA_SECURE_WDOG_TIMEOUT);
}
void plat_arm_secure_wdt_stop(void)
{
- sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
+ sbsa_wdog_stop(SBSA_SECURE_WDOG_CONTROL_BASE);
+}
+
+void plat_arm_secure_wdt_refresh(void)
+{
+ sbsa_wdog_refresh(SBSA_SECURE_WDOG_REFRESH_BASE);
}
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index 19efdd32e..cfd1aac08 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -43,6 +43,7 @@ CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows);
#pragma weak bl31_platform_setup
#pragma weak bl31_plat_arch_setup
#pragma weak bl31_plat_get_next_image_ep_info
+#pragma weak bl31_plat_runtime_setup
#define MAP_BL31_TOTAL MAP_REGION_FLAT( \
BL31_START, \
@@ -294,7 +295,7 @@ void arm_bl31_platform_setup(void)
/* Initialize power controller before setting up topology */
plat_arm_pwrc_setup();
-#if RAS_EXTENSION
+#if RAS_FFH_SUPPORT
ras_init();
#endif
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index fca6f4f95..647a9d932 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -386,7 +386,7 @@ endif
endif
# RAS sources
-ifeq (${RAS_EXTENSION},1)
+ifeq (${RAS_FFH_SUPPORT},1)
BL31_SOURCES += lib/extensions/ras/std_err_record.c \
lib/extensions/ras/ras_common.c
endif
diff --git a/plat/arm/common/tsp/arm_tsp_setup.c b/plat/arm/common/tsp/arm_tsp_setup.c
index a4da8c35e..df3488bf5 100644
--- a/plat/arm/common/tsp/arm_tsp_setup.c
+++ b/plat/arm/common/tsp/arm_tsp_setup.c
@@ -62,7 +62,7 @@ void tsp_platform_setup(void)
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the MMU
+ * moment this is only initializes the MMU
******************************************************************************/
void tsp_plat_arch_setup(void)
{
diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h
index c1fadc654..c6cf0e616 100644
--- a/plat/arm/css/sgi/include/sgi_base_platform_def.h
+++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h
@@ -206,7 +206,7 @@
#define PLAT_SP_PRI PLAT_RAS_PRI
-#if SPM_MM && RAS_EXTENSION
+#if SPM_MM && RAS_FFH_SUPPORT
/*
* CPER buffer memory of 128KB is reserved and it is placed adjacent to the
* memory shared between EL3 and S-EL0.
@@ -235,7 +235,7 @@
*/
#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
PLAT_SP_IMAGE_NS_BUF_SIZE)
-#endif /* SPM_MM && RAS_EXTENSION */
+#endif /* SPM_MM && RAS_FFH_SUPPORT */
/* Platform ID address */
#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)
diff --git a/plat/arm/css/sgi/sgi-common.mk b/plat/arm/css/sgi/sgi-common.mk
index 282a5f080..6d17bc22f 100644
--- a/plat/arm/css/sgi/sgi-common.mk
+++ b/plat/arm/css/sgi/sgi-common.mk
@@ -8,7 +8,9 @@ CSS_USE_SCMI_SDS_DRIVER := 1
CSS_ENT_BASE := plat/arm/css/sgi
-RAS_EXTENSION := 0
+ENABLE_FEAT_RAS := 1
+
+RAS_FFH_SUPPORT := 0
SDEI_SUPPORT := 0
@@ -52,7 +54,7 @@ BL31_SOURCES += ${INTERCONNECT_SOURCES} \
${CSS_ENT_BASE}/sgi_bl31_setup.c \
${CSS_ENT_BASE}/sgi_topology.c
-ifeq (${RAS_EXTENSION},1)
+ifeq (${RAS_FFH_SUPPORT},1)
BL31_SOURCES += ${CSS_ENT_BASE}/sgi_ras.c
endif
diff --git a/plat/arm/css/sgi/sgi_bl31_setup.c b/plat/arm/css/sgi/sgi_bl31_setup.c
index df2ce387a..9c8d16341 100644
--- a/plat/arm/css/sgi/sgi_bl31_setup.c
+++ b/plat/arm/css/sgi/sgi_bl31_setup.c
@@ -106,7 +106,7 @@ void sgi_bl31_common_platform_setup(void)
{
arm_bl31_platform_setup();
-#if RAS_EXTENSION
+#if RAS_FFH_SUPPORT
sgi_ras_intr_handler_setup();
#endif
diff --git a/plat/arm/css/sgi/sgi_plat.c b/plat/arm/css/sgi/sgi_plat.c
index b8ba49f7e..7f79d5409 100644
--- a/plat/arm/css/sgi/sgi_plat.c
+++ b/plat/arm/css/sgi/sgi_plat.c
@@ -93,7 +93,7 @@ const mmap_region_t plat_arm_secure_partition_mmap[] = {
PLAT_ARM_SECURE_MAP_DEVICE,
ARM_SP_IMAGE_MMAP,
ARM_SP_IMAGE_NS_BUF_MMAP,
-#if RAS_EXTENSION
+#if RAS_FFH_SUPPORT
CSS_SGI_SP_CPER_BUF_MMAP,
#endif
ARM_SP_IMAGE_RW_MMAP,
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