diff options
Diffstat (limited to 'plat/arm')
30 files changed, 318 insertions, 158 deletions
diff --git a/plat/arm/board/a5ds/platform.mk b/plat/arm/board/a5ds/platform.mk index 4f873069a..6fcf080a1 100644 --- a/plat/arm/board/a5ds/platform.mk +++ b/plat/arm/board/a5ds/platform.mk @@ -100,6 +100,8 @@ NEED_BL32 := yes MULTI_CONSOLE_API := 1 +ARM_DISABLE_TRUSTED_WDOG := 1 + PLAT_BL_COMMON_SOURCES += lib/xlat_tables/aarch32/nonlpae_tables.c # Use translation tables library v1 when using Cortex-A5 diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk index 109bfbec9..f88eaa852 100644 --- a/plat/arm/board/arm_fpga/platform.mk +++ b/plat/arm/board/arm_fpga/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2021-2022, Arm Limited. All rights reserved. +# Copyright (c) 2021-2023, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -58,23 +58,19 @@ ifeq (${HW_ASSISTED_COHERENCY}, 0) lib/cpus/aarch64/cortex_a73.S else # AArch64-only cores - FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \ - lib/cpus/aarch64/cortex_a76ae.S \ - lib/cpus/aarch64/cortex_a77.S \ - lib/cpus/aarch64/cortex_a78.S \ - lib/cpus/aarch64/neoverse_n_common.S \ - lib/cpus/aarch64/neoverse_n1.S \ - lib/cpus/aarch64/neoverse_n2.S \ - lib/cpus/aarch64/neoverse_e1.S \ - lib/cpus/aarch64/neoverse_v1.S \ - lib/cpus/aarch64/cortex_a78_ae.S \ - lib/cpus/aarch64/cortex_a65.S \ - lib/cpus/aarch64/cortex_a65ae.S \ - lib/cpus/aarch64/cortex_a510.S \ - lib/cpus/aarch64/cortex_a710.S \ - lib/cpus/aarch64/cortex_a715.S \ - lib/cpus/aarch64/cortex_x3.S \ - lib/cpus/aarch64/cortex_a78c.S + FPGA_CPU_LIBS +=lib/cpus/aarch64/cortex_a510.S \ + lib/cpus/aarch64/cortex_a710.S \ + lib/cpus/aarch64/cortex_a715.S \ + lib/cpus/aarch64/cortex_x3.S \ + lib/cpus/aarch64/neoverse_n_common.S \ + lib/cpus/aarch64/neoverse_n1.S \ + lib/cpus/aarch64/neoverse_n2.S \ + lib/cpus/aarch64/neoverse_v1.S \ + lib/cpus/aarch64/cortex_hayes.S \ + lib/cpus/aarch64/cortex_hunter.S \ + lib/cpus/aarch64/cortex_hunter_elp_arm.S \ + lib/cpus/aarch64/cortex_chaberton.S \ + lib/cpus/aarch64/cortex_blackhawk.S # AArch64/AArch32 cores FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ diff --git a/plat/arm/board/corstone1000/common/corstone1000_bl31_setup.c b/plat/arm/board/corstone1000/common/corstone1000_bl31_setup.c new file mode 100644 index 000000000..b6765a60e --- /dev/null +++ b/plat/arm/board/corstone1000/common/corstone1000_bl31_setup.c @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdint.h> + +#if defined(SPD_spmd) +/* + * A dummy implementation of the platform handler for Group0 secure interrupt. + */ +int plat_spmd_handle_group0_interrupt(uint32_t intid) +{ + (void)intid; + return -1; +} +#endif /*defined(SPD_spmd)*/ diff --git a/plat/arm/board/corstone1000/platform.mk b/plat/arm/board/corstone1000/platform.mk index d89169142..3edffe087 100644 --- a/plat/arm/board/corstone1000/platform.mk +++ b/plat/arm/board/corstone1000/platform.mk @@ -56,6 +56,7 @@ BL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \ plat/arm/board/corstone1000/common/corstone1000_security.c \ plat/arm/board/corstone1000/common/corstone1000_plat.c \ plat/arm/board/corstone1000/common/corstone1000_pm.c \ + plat/arm/board/corstone1000/common/corstone1000_bl31_setup.c \ ${CORSTONE1000_CPU_LIBS} \ ${CORSTONE1000_GIC_SOURCES} diff --git a/plat/arm/board/fvp/aarch64/fvp_ras.c b/plat/arm/board/fvp/aarch64/fvp_ras.c index 759f6d0d8..f9b96341a 100644 --- a/plat/arm/board/fvp/aarch64/fvp_ras.c +++ b/plat/arm/board/fvp/aarch64/fvp_ras.c @@ -4,12 +4,63 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include <inttypes.h> +#include <stdint.h> + #include <lib/extensions/ras.h> +#include <services/sdei.h> + +#ifdef PLATFORM_TEST_RAS_FFH +static int injected_fault_handler(const struct err_record_info *info, + int probe_data, const struct err_handler_data *const data) +{ + uint64_t status; + int ret; + + /* + * The faulting error record is already selected by the SER probe + * function. + */ + status = read_erxstatus_el1(); + + ERROR("Fault reported by system error record %d on 0x%lx: status=0x%" PRIx64 "\n", + probe_data, read_mpidr_el1(), status); + ERROR(" exception reason=%u syndrome=0x%" PRIx64 "\n", data->ea_reason, + data->flags); + + /* Clear error */ + write_erxstatus_el1(status); + + ret = sdei_dispatch_event(5000); + if (ret < 0) { + ERROR("Can't dispatch event to SDEI\n"); + panic(); + } else { + INFO("SDEI event dispatched\n"); + } + + return 0; +} + +void plat_handle_uncontainable_ea(void) +{ + /* Do not change the string, CI expects it. Wait forever */ + INFO("Injected Uncontainable Error\n"); + while (true) { + wfe(); + } +} +#endif struct ras_interrupt fvp_ras_interrupts[] = { }; struct err_record_info fvp_err_records[] = { +#ifdef PLATFORM_TEST_RAS_FFH + /* Record for injected fault */ + ERR_RECORD_SYSREG_V1(0, 2, ras_err_ser_probe_sysreg, + injected_fault_handler, NULL), +#endif }; REGISTER_ERR_RECORD_INFO(fvp_err_records); diff --git a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts index 4543671a9..4f97339f7 100644 --- a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts +++ b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2022, Arm Limited. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,7 +15,7 @@ / { compatible = "arm,ffa-core-manifest-1.0"; #address-cells = <2>; - #size-cells = <1>; + #size-cells = <2>; attribute { spmc_id = <0x8000>; @@ -78,9 +78,17 @@ CPU_1 }; - memory@6000000 { + memory@0 { device_type = "memory"; - reg = <0x0 0x6000000 0x2000000>; /* Trusted DRAM */ + reg = <0x0 0xfd000000 0x0 0x2000000>, + <0x0 0x7000000 0x0 0x1000000>, + <0x0 0xff000000 0x0 0x1000000>; + }; + + memory@1 { + device_type = "ns-memory"; + reg = <0x00008800 0x80000000 0x0 0x7f000000>, + <0x0 0x88000000 0x0 0x10000000>; }; #if MEASURED_BOOT diff --git a/plat/arm/board/fvp/fvp_cpu_errata.mk b/plat/arm/board/fvp/fvp_cpu_errata.mk new file mode 100644 index 000000000..944571dd5 --- /dev/null +++ b/plat/arm/board/fvp/fvp_cpu_errata.mk @@ -0,0 +1,61 @@ +# +# Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + + +#/* +# * TODO: below lines of code to be removed +# * after abi and framework are synchronized +# */ + +ifeq (${ERRATA_ABI_SUPPORT}, 1) +# enable the cpu macros for errata abi interface +ifeq (${ARCH}, aarch64) +ifeq (${HW_ASSISTED_COHERENCY}, 0) +CORTEX_A35_H_INC := 1 +CORTEX_A53_H_INC := 1 +CORTEX_A57_H_INC := 1 +CORTEX_A72_H_INC := 1 +CORTEX_A73_H_INC := 1 +$(eval $(call add_define, CORTEX_A35_H_INC)) +$(eval $(call add_define, CORTEX_A53_H_INC)) +$(eval $(call add_define, CORTEX_A57_H_INC)) +$(eval $(call add_define, CORTEX_A72_H_INC)) +$(eval $(call add_define, CORTEX_A73_H_INC)) +else +ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) +CORTEX_A76_H_INC := 1 +CORTEX_A77_H_INC := 1 +CORTEX_A78_H_INC := 1 +NEOVERSE_N1_H_INC := 1 +NEOVERSE_V1_H_INC := 1 +CORTEX_A78_AE_H_INC := 1 +CORTEX_A510_H_INC := 1 +CORTEX_A710_H_INC := 1 +CORTEX_A715_H_INC := 1 +CORTEX_A78C_H_INC := 1 +CORTEX_X2_H_INC := 1 +$(eval $(call add_define, CORTEX_A76_H_INC)) +$(eval $(call add_define, CORTEX_A77_H_INC)) +$(eval $(call add_define, CORTEX_A78_H_INC)) +$(eval $(call add_define, NEOVERSE_N1_H_INC)) +$(eval $(call add_define, NEOVERSE_V1_H_INC)) +$(eval $(call add_define, CORTEX_A78_AE_H_INC)) +$(eval $(call add_define, CORTEX_A510_H_INC)) +$(eval $(call add_define, CORTEX_A710_H_INC)) +$(eval $(call add_define, CORTEX_A715_H_INC)) +$(eval $(call add_define, CORTEX_A78C_H_INC)) +$(eval $(call add_define, CORTEX_X2_H_INC)) +endif +CORTEX_A55_H_INC := 1 +CORTEX_A75_H_INC := 1 +$(eval $(call add_define, CORTEX_A55_H_INC)) +$(eval $(call add_define, CORTEX_A75_H_INC)) +endif +else +CORTEX_A32_H_INC := 1 +$(eval $(call add_define, CORTEX_A32_H_INC)) +endif +endif diff --git a/plat/arm/board/fvp/fvp_spmd.c b/plat/arm/board/fvp/fvp_spmd.c new file mode 100644 index 000000000..8213e5ea4 --- /dev/null +++ b/plat/arm/board/fvp/fvp_spmd.c @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdint.h> + +int plat_spmd_handle_group0_interrupt(uint32_t intid) +{ + /* + * As of now, there are no sources of Group0 secure interrupt enabled + * for FVP. + */ + (void)intid; + return -1; +} diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index 79d7451ef..9e72ba08c 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -397,7 +397,17 @@ defined(IMAGE_BL2) && MEASURED_BOOT #define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT #define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT #else -#define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS + #if PLATFORM_TEST_RAS_FFH + #define PLAT_ARM_PRIVATE_SDEI_EVENTS \ + ARM_SDEI_PRIVATE_EVENTS, \ + SDEI_EXPLICIT_EVENT(5000, SDEI_MAPF_NORMAL), \ + SDEI_EXPLICIT_EVENT(5001, SDEI_MAPF_NORMAL), \ + SDEI_EXPLICIT_EVENT(5002, SDEI_MAPF_NORMAL), \ + SDEI_EXPLICIT_EVENT(5003, SDEI_MAPF_CRITICAL), \ + SDEI_EXPLICIT_EVENT(5004, SDEI_MAPF_CRITICAL) + #else + #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS + #endif #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS #endif diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index af082ba0c..0433b61d5 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -50,7 +50,9 @@ ifneq (${SPD}, tspd) ENABLE_FEAT_RNG := 2 ENABLE_FEAT_TWED := 2 ENABLE_FEAT_GCS := 2 -ifeq (${ARCH},aarch64) + ENABLE_FEAT_RAS := 2 +ifeq (${ARCH}, aarch64) +ifneq (${SPD}, spmd) ifeq (${SPM_MM}, 0) ifeq (${ENABLE_RME}, 0) ifeq (${CTX_INCLUDE_FPREGS}, 0) @@ -61,6 +63,7 @@ endif endif endif endif +endif # enable unconditionally for all builds ifeq (${ARCH}, aarch64) @@ -385,7 +388,7 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ endif endif -ifeq (${RAS_EXTENSION},1) +ifeq (${RAS_FFH_SUPPORT},1) BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c endif @@ -503,6 +506,11 @@ endif PSCI_OS_INIT_MODE := 1 +ifeq (${SPD},spmd) +BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c +endif + +# Test specific macros, keep them at bottom of this file $(eval $(call add_define,PLATFORM_TEST_EA_FFH)) ifeq (${PLATFORM_TEST_EA_FFH}, 1) ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) @@ -510,3 +518,14 @@ ifeq (${PLATFORM_TEST_EA_FFH}, 1) endif BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c endif + +$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) +ifeq (${PLATFORM_TEST_RAS_FFH}, 1) + ifeq (${RAS_EXTENSION}, 0) + $(error "PLATFORM_TEST_RAS_FFH expects RAS_EXTENSION to be 1") + endif +endif + +ifeq (${ERRATA_ABI_SUPPORT}, 1) +include plat/arm/board/fvp/fvp_cpu_errata.mk +endif diff --git a/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c b/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c index b961da939..705ec384c 100644 --- a/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c +++ b/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c @@ -84,7 +84,7 @@ void sp_min_plat_arch_setup(void) (void *)hw_config_info->config_addr); /* - * Preferrably we expect this address and size are page aligned, + * Preferably we expect this address and size are page aligned, * but if they are not then align it. */ hw_config_base_align = page_align(hw_config_info->config_addr, DOWN); diff --git a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c index 4941a4bd4..6809541a6 100644 --- a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c +++ b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c @@ -159,3 +159,14 @@ void bl31_platform_setup(void) if ((plat_info.multichip_mode) && (plat_info.remote_ddr_size != 0)) remote_dmc_ecc_setup(plat_info.remote_ddr_size); } + +#if defined(SPD_spmd) +/* + * A dummy implementation of the platform handler for Group0 secure interrupt. + */ +int plat_spmd_handle_group0_interrupt(uint32_t intid) +{ + (void)intid; + return -1; +} +#endif /*defined(SPD_spmd)*/ diff --git a/plat/arm/board/rde1edge/platform.mk b/plat/arm/board/rde1edge/platform.mk index 0f9dd496a..4a9a467b2 100644 --- a/plat/arm/board/rde1edge/platform.mk +++ b/plat/arm/board/rde1edge/platform.mk @@ -1,9 +1,12 @@ # -# Copyright (c) 2018-2020, Arm Limited. All rights reserved. +# Copyright (c) 2018-2023, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # +$(warning Platform ${PLAT} is deprecated. \ + Some of the features might not work as expected) + include plat/arm/css/sgi/sgi-common.mk RDE1EDGE_BASE = plat/arm/board/rde1edge diff --git a/plat/arm/board/tc/fdts/tc_spmc_manifest.dts b/plat/arm/board/tc/fdts/tc_spmc_manifest.dts index d3a5e1a77..b64e0762e 100644 --- a/plat/arm/board/tc/fdts/tc_spmc_manifest.dts +++ b/plat/arm/board/tc/fdts/tc_spmc_manifest.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, Arm Limited. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,7 +8,7 @@ / { compatible = "arm,ffa-core-manifest-1.0"; #address-cells = <2>; - #size-cells = <1>; + #size-cells = <2>; attribute { spmc_id = <0x8000>; @@ -117,9 +117,16 @@ }; }; - /* 32MB of TC_TZC_DRAM1_BASE */ - memory@fd000000 { + memory@0 { device_type = "memory"; - reg = <0x0 0xfd000000 0x2000000>; + reg = <0x0 0xfd000000 0x0 0x2000000>, + <0x0 0x7000000 0x0 0x1000000>, + <0x0 0xff000000 0x0 0x1000000>; + }; + + memory@1 { + device_type = "ns-memory"; + reg = <0x00008800 0x80000000 0x0 0x7f000000>, + <0x0 0x88000000 0x1 0x00000000>; }; }; diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h index eea1be6ba..59fff6e2a 100644 --- a/plat/arm/board/tc/include/platform_def.h +++ b/plat/arm/board/tc/include/platform_def.h @@ -212,8 +212,11 @@ #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) #define PLAT_ARM_DRAM2_END (PLAT_ARM_DRAM2_BASE + PLAT_ARM_DRAM2_SIZE - 1ULL) -#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) -#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) +#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_INT_PROPS(grp) +#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp), \ + INTR_PROP_DESC(SBSA_SECURE_WDOG_INTID, \ + GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL) #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ PLAT_SP_IMAGE_NS_BUF_SIZE) @@ -229,9 +232,11 @@ #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) -/*Secure Watchdog Constants */ -#define SBSA_SECURE_WDOG_BASE UL(0x2A480000) +/* Secure Watchdog Constants */ +#define SBSA_SECURE_WDOG_CONTROL_BASE UL(0x2A480000) +#define SBSA_SECURE_WDOG_REFRESH_BASE UL(0x2A490000) #define SBSA_SECURE_WDOG_TIMEOUT UL(100) +#define SBSA_SECURE_WDOG_INTID 86 #define PLAT_ARM_SCMI_CHANNEL_COUNT 1 diff --git a/plat/arm/board/tc/include/tc_plat.h b/plat/arm/board/tc/include/tc_plat.h index ba1831fb3..195366e48 100644 --- a/plat/arm/board/tc/include/tc_plat.h +++ b/plat/arm/board/tc/include/tc_plat.h @@ -9,8 +9,10 @@ void tc_bl31_common_platform_setup(void); -#ifdef PLATFORM_TEST +#ifdef PLATFORM_TEST_TFM_TESTSUITE void run_platform_tests(void); +#endif +#ifdef PLATFORM_TEST_NV_COUNTERS void nv_counter_test(void); #endif diff --git a/plat/arm/board/tc/plat_def_uuid_config.c b/plat/arm/board/tc/plat_def_uuid_config.c deleted file mode 100644 index 903310b21..000000000 --- a/plat/arm/board/tc/plat_def_uuid_config.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2022, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include <stddef.h> - -#include <firmware_image_package.h> - -#include "tbbr_config.h" - -toc_entry_t plat_def_toc_entries[] = { - { - .name = "RSS Firmware BL1_2 image", - .uuid = UUID_RSS_FIRMWARE_BL1_2, - .cmdline_name = "rss-bl1_2" - }, - { - .name = "RSS Firmware BL2 image", - .uuid = UUID_RSS_FIRMWARE_BL2, - .cmdline_name = "rss-bl2" - }, - { - .name = "RSS Firmware SCP BL1 image", - .uuid = UUID_RSS_FIRMWARE_SCP_BL1, - .cmdline_name = "rss-scp-bl1" - }, - { - .name = "RSS Firmware AP BL1 image", - .uuid = UUID_RSS_FIRMWARE_AP_BL1, - .cmdline_name = "rss-ap-bl1" - }, - { - .name = "RSS Firmware non-secure image", - .uuid = UUID_RSS_FIRMWARE_NS, - .cmdline_name = "rss-ns" - }, - { - .name = "RSS Firmware secure image", - .uuid = UUID_RSS_FIRMWARE_S, - .cmdline_name = "rss-s" - }, - { - .name = "RSS Firmware non-secure SIC tables", - .uuid = UUID_RSS_SIC_TABLES_NS, - .cmdline_name = "rss-sic-tables-ns" - }, - { - .name = "RSS Firmware secure SIC tables", - .uuid = UUID_RSS_SIC_TABLES_S, - .cmdline_name = "rss-sic-tables-s" - }, - - { - .name = NULL, - .uuid = { {0} }, - .cmdline_name = NULL, - } -}; diff --git a/plat/arm/board/tc/plat_fiptool.mk b/plat/arm/board/tc/plat_fiptool.mk deleted file mode 100644 index 0e1355689..000000000 --- a/plat/arm/board/tc/plat_fiptool.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# Copyright (c) 2021, NXP. All rights reserved. -# Copyright (c) 2022, Arm Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -# Name of the platform defined source file name, -# which contains platform defined UUID entries populated -# in the plat_def_toc_entries[]. -PLAT_DEF_UUID_CONFIG_FILE_NAME := plat_def_uuid_config - -PLAT_DEF_UUID_CONFIG_FILE_PATH := ../../plat/arm/board/tc - -PLAT_DEF_UUID := yes -PLAT_DEF_UUID_OID_CONFIG_PATH := ../../plat/arm/board/tc - - -INCLUDE_PATHS += -I${PLAT_DEF_UUID_OID_CONFIG_PATH} \ - -I./ -# Clean the stale object file. -$(shell rm ${PLAT_DEF_UUID_CONFIG_FILE_PATH}/${PLAT_DEF_UUID_CONFIG_FILE_NAME}.o) - -ifeq (${PLAT_DEF_OID},yes) -HOSTCCFLAGS += -DPLAT_DEF_OID -endif - -ifeq (${PLAT_DEF_UUID},yes) -HOSTCCFLAGS += -DPLAT_DEF_FIP_UUID -PLAT_OBJECTS += ${PLAT_DEF_UUID_CONFIG_FILE_PATH}/${PLAT_DEF_UUID_CONFIG_FILE_NAME}.o -endif - -OBJECTS += ${PLAT_OBJECTS} diff --git a/plat/arm/board/tc/plat_tc_mbedtls_config.h b/plat/arm/board/tc/plat_tc_mbedtls_config.h index d776b638a..f0aa60b52 100644 --- a/plat/arm/board/tc/plat_tc_mbedtls_config.h +++ b/plat/arm/board/tc/plat_tc_mbedtls_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, Arm Ltd. All rights reserved. + * Copyright (c) 2022-2023, Arm Ltd. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,8 +7,8 @@ #ifndef PLAT_TC_MBEDTLS_CONFIG_H #define PLAT_TC_MBEDTLS_CONFIG_H -#include <mbedtls_config.h> #include <export/lib/utils_def_exp.h> +#include <mbedtls_config-3.h> #ifndef TF_MBEDTLS_HEAP_SIZE #error TF_MBEDTLS_HEAP_SIZE is not defined diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk index 7fdc4fd84..98c2e0ed6 100644 --- a/plat/arm/board/tc/platform.mk +++ b/plat/arm/board/tc/platform.mk @@ -20,7 +20,9 @@ CSS_LOAD_SCP_IMAGES := 1 CSS_USE_SCMI_SDS_DRIVER := 1 -RAS_EXTENSION := 0 +ENABLE_FEAT_RAS := 1 + +RAS_FFH_SUPPORT := 0 SDEI_SUPPORT := 0 @@ -53,9 +55,6 @@ ENABLE_SYS_REG_TRACE_FOR_NS := 1 # enable trace filter control registers access to NS by default ENABLE_TRF_FOR_NS := 1 -# Enable RSS-required FIP UUIDs -$(shell cp plat/arm/board/tc/plat_fiptool.mk ${PLAT_DIR}) - # Include GICv3 driver files include drivers/arm/gic/v3/gicv3.mk @@ -121,7 +120,8 @@ BL31_SOURCES += ${INTERCONNECT_SOURCES} \ lib/fconf/fconf_dyn_cfg_getter.c \ drivers/cfi/v2m/v2m_flash.c \ lib/utils/mem_region.c \ - plat/arm/common/arm_nor_psci_mem_protect.c + plat/arm/common/arm_nor_psci_mem_protect.c \ + drivers/arm/sbsa/sbsa.c BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} @@ -209,7 +209,7 @@ ifeq (${PLATFORM_TEST},rss-nv-counters) PLAT_INCLUDES += -Iinclude/lib/psa - $(eval $(call add_define,PLATFORM_TEST)) + $(eval $(call add_define,PLATFORM_TEST_NV_COUNTERS)) else ifeq (${PLATFORM_TEST},tfm-testsuite) # Add this include as first, before arm_common.mk. This is necessary # because arm_common.mk builds Mbed TLS, and platform_test.mk can diff --git a/plat/arm/board/tc/platform_test.mk b/plat/arm/board/tc/platform_test.mk index 5cdbb86be..e974855ad 100644 --- a/plat/arm/board/tc/platform_test.mk +++ b/plat/arm/board/tc/platform_test.mk @@ -76,5 +76,5 @@ ifeq (${PLATFORM_TEST},tfm-testsuite) $(eval $(call add_define,MEASURED_BOOT_HASH_ALG)) $(eval $(call add_define,DELEG_ATTEST_DUMP_TOKEN_AND_KEY)) - $(eval $(call add_define,PLATFORM_TEST)) + $(eval $(call add_define,PLATFORM_TEST_TFM_TESTSUITE)) endif diff --git a/plat/arm/board/tc/tc_bl31_setup.c b/plat/arm/board/tc/tc_bl31_setup.c index 1c1e2fb2a..630324fb3 100644 --- a/plat/arm/board/tc/tc_bl31_setup.c +++ b/plat/arm/board/tc/tc_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2023, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,6 +13,7 @@ #include <common/debug.h> #include <drivers/arm/css/css_mhu_doorbell.h> #include <drivers/arm/css/scmi.h> +#include <drivers/arm/sbsa.h> #include <lib/fconf/fconf.h> #include <lib/fconf/fconf_dyn_cfg_getter.h> #include <plat/arm/common/plat_arm.h> @@ -53,11 +54,11 @@ void tc_bl31_common_platform_setup(void) { arm_bl31_platform_setup(); -#ifdef PLATFORM_TEST -#if PLATFORM_TEST == rss-nv-counters +#if defined(PLATFORM_TEST_NV_COUNTERS) || defined(PLATFORM_TEST_TFM_TESTSUITE) +#ifdef PLATFORM_TEST_NV_COUNTERS nv_counter_test(); -#elif PLATFORM_TEST == tfm-testsuite - run_platform_tests() +#elif PLATFORM_TEST_TFM_TESTSUITE + run_platform_tests(); #endif /* Suspend booting */ plat_error_handler(-1); @@ -81,3 +82,37 @@ void __init bl31_plat_arch_setup(void) fconf_populate("HW_CONFIG", hw_config_info->config_addr); } + +#if defined(SPD_spmd) && (SPMD_SPM_AT_SEL2 == 1) +void tc_bl31_plat_runtime_setup(void) +{ + arm_bl31_plat_runtime_setup(); + + /* Start secure watchdog timer. */ + plat_arm_secure_wdt_start(); +} + +void bl31_plat_runtime_setup(void) +{ + tc_bl31_plat_runtime_setup(); +} + +/* + * Platform handler for Group0 secure interrupt. + */ +int plat_spmd_handle_group0_interrupt(uint32_t intid) +{ + /* Trusted Watchdog timer is the only source of Group0 interrupt now. */ + if (intid == SBSA_SECURE_WDOG_INTID) { + INFO("Watchdog restarted\n"); + /* Refresh the timer. */ + plat_arm_secure_wdt_refresh(); + + /* Deactivate the corresponding interrupt. */ + plat_ic_end_of_interrupt(intid); + return 0; + } + + return -1; +} +#endif /*defined(SPD_spmd) && (SPMD_SPM_AT_SEL2 == 1)*/ diff --git a/plat/arm/board/tc/tc_plat.c b/plat/arm/board/tc/tc_plat.c index 228f2fab3..766bfb570 100644 --- a/plat/arm/board/tc/tc_plat.c +++ b/plat/arm/board/tc/tc_plat.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2023, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -147,10 +147,15 @@ int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) void plat_arm_secure_wdt_start(void) { - sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT); + sbsa_wdog_start(SBSA_SECURE_WDOG_CONTROL_BASE, SBSA_SECURE_WDOG_TIMEOUT); } void plat_arm_secure_wdt_stop(void) { - sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE); + sbsa_wdog_stop(SBSA_SECURE_WDOG_CONTROL_BASE); +} + +void plat_arm_secure_wdt_refresh(void) +{ + sbsa_wdog_refresh(SBSA_SECURE_WDOG_REFRESH_BASE); } diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c index 19efdd32e..cfd1aac08 100644 --- a/plat/arm/common/arm_bl31_setup.c +++ b/plat/arm/common/arm_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -43,6 +43,7 @@ CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows); #pragma weak bl31_platform_setup #pragma weak bl31_plat_arch_setup #pragma weak bl31_plat_get_next_image_ep_info +#pragma weak bl31_plat_runtime_setup #define MAP_BL31_TOTAL MAP_REGION_FLAT( \ BL31_START, \ @@ -294,7 +295,7 @@ void arm_bl31_platform_setup(void) /* Initialize power controller before setting up topology */ plat_arm_pwrc_setup(); -#if RAS_EXTENSION +#if RAS_FFH_SUPPORT ras_init(); #endif diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index fca6f4f95..647a9d932 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk @@ -386,7 +386,7 @@ endif endif # RAS sources -ifeq (${RAS_EXTENSION},1) +ifeq (${RAS_FFH_SUPPORT},1) BL31_SOURCES += lib/extensions/ras/std_err_record.c \ lib/extensions/ras/ras_common.c endif diff --git a/plat/arm/common/tsp/arm_tsp_setup.c b/plat/arm/common/tsp/arm_tsp_setup.c index a4da8c35e..df3488bf5 100644 --- a/plat/arm/common/tsp/arm_tsp_setup.c +++ b/plat/arm/common/tsp/arm_tsp_setup.c @@ -62,7 +62,7 @@ void tsp_platform_setup(void) /******************************************************************************* * Perform the very early platform specific architectural setup here. At the - * moment this is only intializes the MMU + * moment this is only initializes the MMU ******************************************************************************/ void tsp_plat_arch_setup(void) { diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h index c1fadc654..c6cf0e616 100644 --- a/plat/arm/css/sgi/include/sgi_base_platform_def.h +++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h @@ -206,7 +206,7 @@ #define PLAT_SP_PRI PLAT_RAS_PRI -#if SPM_MM && RAS_EXTENSION +#if SPM_MM && RAS_FFH_SUPPORT /* * CPER buffer memory of 128KB is reserved and it is placed adjacent to the * memory shared between EL3 and S-EL0. @@ -235,7 +235,7 @@ */ #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ PLAT_SP_IMAGE_NS_BUF_SIZE) -#endif /* SPM_MM && RAS_EXTENSION */ +#endif /* SPM_MM && RAS_FFH_SUPPORT */ /* Platform ID address */ #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) diff --git a/plat/arm/css/sgi/sgi-common.mk b/plat/arm/css/sgi/sgi-common.mk index 282a5f080..6d17bc22f 100644 --- a/plat/arm/css/sgi/sgi-common.mk +++ b/plat/arm/css/sgi/sgi-common.mk @@ -8,7 +8,9 @@ CSS_USE_SCMI_SDS_DRIVER := 1 CSS_ENT_BASE := plat/arm/css/sgi -RAS_EXTENSION := 0 +ENABLE_FEAT_RAS := 1 + +RAS_FFH_SUPPORT := 0 SDEI_SUPPORT := 0 @@ -52,7 +54,7 @@ BL31_SOURCES += ${INTERCONNECT_SOURCES} \ ${CSS_ENT_BASE}/sgi_bl31_setup.c \ ${CSS_ENT_BASE}/sgi_topology.c -ifeq (${RAS_EXTENSION},1) +ifeq (${RAS_FFH_SUPPORT},1) BL31_SOURCES += ${CSS_ENT_BASE}/sgi_ras.c endif diff --git a/plat/arm/css/sgi/sgi_bl31_setup.c b/plat/arm/css/sgi/sgi_bl31_setup.c index df2ce387a..9c8d16341 100644 --- a/plat/arm/css/sgi/sgi_bl31_setup.c +++ b/plat/arm/css/sgi/sgi_bl31_setup.c @@ -106,7 +106,7 @@ void sgi_bl31_common_platform_setup(void) { arm_bl31_platform_setup(); -#if RAS_EXTENSION +#if RAS_FFH_SUPPORT sgi_ras_intr_handler_setup(); #endif diff --git a/plat/arm/css/sgi/sgi_plat.c b/plat/arm/css/sgi/sgi_plat.c index b8ba49f7e..7f79d5409 100644 --- a/plat/arm/css/sgi/sgi_plat.c +++ b/plat/arm/css/sgi/sgi_plat.c @@ -93,7 +93,7 @@ const mmap_region_t plat_arm_secure_partition_mmap[] = { PLAT_ARM_SECURE_MAP_DEVICE, ARM_SP_IMAGE_MMAP, ARM_SP_IMAGE_NS_BUF_MMAP, -#if RAS_EXTENSION +#if RAS_FFH_SUPPORT CSS_SGI_SP_CPER_BUF_MMAP, #endif ARM_SP_IMAGE_RW_MMAP, |