diff options
Diffstat (limited to 'include')
25 files changed, 112 insertions, 65 deletions
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h index 8678bf3d8..227f05862 100644 --- a/include/arch/aarch32/arch.h +++ b/include/arch/aarch32/arch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,8 +16,10 @@ #define MIDR_IMPL_SHIFT U(24) #define MIDR_VAR_SHIFT U(20) #define MIDR_VAR_BITS U(4) +#define MIDR_VAR_MASK U(0xf) #define MIDR_REV_SHIFT U(0) #define MIDR_REV_BITS U(4) +#define MIDR_REV_MASK U(0xf) #define MIDR_PN_MASK U(0xfff) #define MIDR_PN_SHIFT U(4) @@ -264,7 +266,7 @@ #define TCP10_BIT (U(1) << 10) #define HCPTR_RESET_VAL HCPTR_RES1 -/* VTTBR defintions */ +/* VTTBR definitions */ #define VTTBR_RESET_VAL ULL(0x0) #define VTTBR_VMID_MASK ULL(0xff) #define VTTBR_VMID_SHIFT U(48) diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index ac5eae249..003889346 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -393,6 +393,9 @@ #define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1) #define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0) +#define VDISR_EL2 S3_4_C12_C1_1 +#define VSESR_EL2 S3_4_C5_C2_3 + /* Memory Tagging Extension is not implemented */ #define MTE_UNIMPLEMENTED U(0) /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ @@ -752,7 +755,7 @@ #define HI_VECTOR_BASE U(0xFFFF0000) /* - * TCR defintions + * TCR definitions */ #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h index a0141defa..d6f12f3f2 100644 --- a/include/arch/aarch64/arch_features.h +++ b/include/arch/aarch64/arch_features.h @@ -499,14 +499,22 @@ static inline bool is_feat_sve_supported(void) return read_feat_sve_id_field() >= ID_AA64PFR0_SVE_SUPPORTED; } -/******************************************************************************* - * Function to identify the presence of FEAT_RAS (Reliability,Availability, - * and Serviceability Extension) - ******************************************************************************/ -static inline bool is_armv8_2_feat_ras_present(void) +static unsigned int read_feat_ras_id_field(void) +{ + return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_RAS); +} + +static inline bool is_feat_ras_supported(void) { - return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_RAS_SHIFT) & - ID_AA64PFR0_RAS_MASK) != ID_AA64PFR0_RAS_NOT_SUPPORTED); + if (ENABLE_FEAT_RAS == FEAT_STATE_DISABLED) { + return false; + } + + if (ENABLE_FEAT_RAS == FEAT_STATE_ALWAYS) { + return true; + } + + return read_feat_ras_id_field() != 0U; } static unsigned int read_feat_dit_id_field(void) diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h index 1b4bc1113..5b3d4c26f 100644 --- a/include/arch/aarch64/arch_helpers.h +++ b/include/arch/aarch64/arch_helpers.h @@ -549,6 +549,10 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(ttbr1_el2, TTBR1_EL2) /* Armv8.2 ID Registers */ DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1) +/* Armv8.2 RAS Registers */ +DEFINE_RENAME_SYSREG_RW_FUNCS(vdisr_el2, VDISR_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(vsesr_el2, VSESR_EL2) + /* Armv8.2 MPAM Registers */ DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3) diff --git a/include/bl31/ehf.h b/include/bl31/ehf.h index c13d28c35..63943a926 100644 --- a/include/bl31/ehf.h +++ b/include/bl31/ehf.h @@ -30,7 +30,7 @@ .ehf_handler = EHF_NO_HANDLER_, \ } -/* Macro for platforms to regiter its exception priorities */ +/* Macro for platforms to register its exception priorities */ #define EHF_REGISTER_PRIORITIES(priorities, num, bits) \ const ehf_priorities_t exception_data = { \ .num_priorities = (num), \ diff --git a/include/drivers/arm/cryptocell/712/cc_pal_types_plat.h b/include/drivers/arm/cryptocell/712/cc_pal_types_plat.h index 84100245b..f6d41d786 100644 --- a/include/drivers/arm/cryptocell/712/cc_pal_types_plat.h +++ b/include/drivers/arm/cryptocell/712/cc_pal_types_plat.h @@ -9,7 +9,7 @@ */ #ifndef _CC_PAL_TYPES_PLAT_H #define _CC_PAL_TYPES_PLAT_H -/* Host specific types for standard (ISO-C99) compilant platforms */ +/* Host specific types for standard (ISO-C99) compliant platforms */ #include <stddef.h> #include <stdint.h> diff --git a/include/drivers/arm/cryptocell/713/cc_pal_types_plat.h b/include/drivers/arm/cryptocell/713/cc_pal_types_plat.h index 984847217..0c102a092 100644 --- a/include/drivers/arm/cryptocell/713/cc_pal_types_plat.h +++ b/include/drivers/arm/cryptocell/713/cc_pal_types_plat.h @@ -9,7 +9,7 @@ */ #ifndef _CC_PAL_TYPES_PLAT_H #define _CC_PAL_TYPES_PLAT_H -/* Host specific types for standard (ISO-C99) compilant platforms */ +/* Host specific types for standard (ISO-C99) compliant platforms */ #include <stddef.h> #include <stdint.h> diff --git a/include/drivers/arm/gic600ae_fmu.h b/include/drivers/arm/gic600ae_fmu.h index 88b87b920..d2a92ddfd 100644 --- a/include/drivers/arm/gic600ae_fmu.h +++ b/include/drivers/arm/gic600ae_fmu.h @@ -85,7 +85,7 @@ #define FMU_BLK_PPI31 U(43) #define FMU_BLK_PRESENT_MASK U(0xFFFFFFFFFFF) -/* Safety Mechamism limit */ +/* Safety Mechanism limit */ #define FMU_SMID_GICD_MAX U(33) #define FMU_SMID_PPI_MAX U(12) #define FMU_SMID_ITS_MAX U(14) diff --git a/include/drivers/arm/sbsa.h b/include/drivers/arm/sbsa.h index 9403634f7..4ca71942e 100644 --- a/include/drivers/arm/sbsa.h +++ b/include/drivers/arm/sbsa.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,7 +9,12 @@ #include <stdint.h> -/* Register Offsets */ +/* SBSA Secure Watchdog Register Offsets */ +/* Refresh frame */ +#define SBSA_WDOG_WRR_OFFSET UL(0x000) +#define SBSA_WDOG_WRR_REFRESH UL(0x1) + +/* Control and status frame */ #define SBSA_WDOG_WCS_OFFSET UL(0x000) #define SBSA_WDOG_WOR_LOW_OFFSET UL(0x008) #define SBSA_WDOG_WOR_HIGH_OFFSET UL(0x00C) @@ -20,5 +25,6 @@ void sbsa_wdog_start(uintptr_t base, uint64_t ms); void sbsa_wdog_stop(uintptr_t base); +void sbsa_wdog_refresh(uintptr_t refresh_base); #endif /* SBSA_H */ diff --git a/include/drivers/auth/crypto_mod.h b/include/drivers/auth/crypto_mod.h index 00ea8c620..bec19da2c 100644 --- a/include/drivers/auth/crypto_mod.h +++ b/include/drivers/auth/crypto_mod.h @@ -46,7 +46,7 @@ typedef struct crypto_lib_desc_s { const char *name; /* Initialize library. This function is not expected to fail. All errors - * must be handled inside the function, asserting or panicing in case of + * must be handled inside the function, asserting or panicking in case of * a non-recoverable error */ void (*init)(void); diff --git a/include/drivers/brcm/emmc/emmc_csl_sdprot.h b/include/drivers/brcm/emmc/emmc_csl_sdprot.h index 597e1e087..580194034 100644 --- a/include/drivers/brcm/emmc/emmc_csl_sdprot.h +++ b/include/drivers/brcm/emmc/emmc_csl_sdprot.h @@ -139,7 +139,7 @@ * The Common I/O area shall be implemented on all SDIO cards and * is accessed the the host via I/O reads and writes to function 0, * the registers within the CIA are provided to enable/disable - * the operationo fthe i/o funciton. + * the operationo fthe i/o function. */ /* cccr_sdio_rev */ @@ -303,7 +303,7 @@ #define SBSDIO_CIS_BASE_COMMON 0x1000 /* function 0(common) cis size in bytes */ #define SBSDIO_CIS_FUNC0_LIMIT 0x020 -/* funciton 1 cis size in bytes */ +/* function 1 cis size in bytes */ #define SBSDIO_CIS_SIZE_LIMIT 0x200 /* cis offset addr is < 17 bits */ #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF @@ -313,7 +313,7 @@ /* indirect cis access (in sprom) */ /* 8 control bytes first, CIS starts from 8th uint8_t */ #define SBSDIO_SPROM_CIS_OFFSET 0x8 -/* sdio uint8_t mode: maximum length of one data comamnd */ +/* sdio uint8_t mode: maximum length of one data command */ #define SBSDIO_BYTEMODE_DATALEN_MAX 64 /* 4317 supports less */ #define SBSDIO_BYTEMODE_DATALEN_MAX_4317 52 diff --git a/include/drivers/brcm/i2c/i2c.h b/include/drivers/brcm/i2c/i2c.h index 24d42e208..2cc81d5b3 100644 --- a/include/drivers/brcm/i2c/i2c.h +++ b/include/drivers/brcm/i2c/i2c.h @@ -78,7 +78,7 @@ uint32_t i2c_get_bus_speed(uint32_t bus_id); * * Description: * This function reads I2C data from a device without specifying - * a command regsiter. + * a command register. * * Parameters: * bus_id - I2C bus ID @@ -95,7 +95,7 @@ int i2c_recv_byte(uint32_t bus_id, uint8_t devaddr, uint8_t *value); * * Description: * This function send I2C data to a device without specifying - * a command regsiter. + * a command register. * * Parameters: * bus_id - I2C bus ID diff --git a/include/drivers/io/io_dummy.h b/include/drivers/io/io_dummy.h deleted file mode 100644 index edfc6993e..000000000 --- a/include/drivers/io/io_dummy.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef IO_DUMMY_H -#define IO_DUMMY_H - -int register_io_dev_dummy(const struct io_dev_connector **dev_con); - -#endif /* IO_DUMMY_H */ diff --git a/include/drivers/io/io_storage.h b/include/drivers/io/io_storage.h index 8f30ed050..31793832d 100644 --- a/include/drivers/io/io_storage.h +++ b/include/drivers/io/io_storage.h @@ -19,7 +19,6 @@ typedef enum { IO_TYPE_INVALID, IO_TYPE_SEMIHOSTING, IO_TYPE_MEMMAP, - IO_TYPE_DUMMY, IO_TYPE_FIRMWARE_IMAGE_PACKAGE, IO_TYPE_BLOCK, IO_TYPE_MTD, diff --git a/include/drivers/nxp/crypto/caam/sec_hw_specific.h b/include/drivers/nxp/crypto/caam/sec_hw_specific.h index 98007938e..bc11aca1e 100644 --- a/include/drivers/nxp/crypto/caam/sec_hw_specific.h +++ b/include/drivers/nxp/crypto/caam/sec_hw_specific.h @@ -221,7 +221,7 @@ typedef struct { /* Lists the possible states for a job ring. */ typedef enum sec_job_ring_state_e { SEC_JOB_RING_STATE_STARTED, /* Job ring is initialized */ - SEC_JOB_RING_STATE_RESET, /* Job ring reset is in progres */ + SEC_JOB_RING_STATE_RESET, /* Job ring reset is in progress */ } sec_job_ring_state_t; struct sec_job_ring_t { diff --git a/include/drivers/nxp/crypto/caam/sec_jr_driver.h b/include/drivers/nxp/crypto/caam/sec_jr_driver.h index 57e0fa0ee..a6570d8bf 100644 --- a/include/drivers/nxp/crypto/caam/sec_jr_driver.h +++ b/include/drivers/nxp/crypto/caam/sec_jr_driver.h @@ -57,7 +57,7 @@ typedef void (*user_callback) (uint32_t *desc, uint32_t status, /* * Structure encompassing a job descriptor which is to be processed * by SEC. User should also initialise this structure with the callback - * function pointer which will be called by driver after recieving proccessed + * function pointer which will be called by driver after receiving proccessed * descriptor from SEC. User data is also passed in this data structure which * will be sent as an argument to the user callback function. */ diff --git a/include/drivers/nxp/dcfg/dcfg_lsch2.h b/include/drivers/nxp/dcfg/dcfg_lsch2.h index 882ba5a33..bdef6deba 100644 --- a/include/drivers/nxp/dcfg/dcfg_lsch2.h +++ b/include/drivers/nxp/dcfg/dcfg_lsch2.h @@ -55,7 +55,7 @@ #define DISR5_DDRC1_MASK 0x1 #define DISR5_OCRAM_MASK 0x40 -/* DCFG regsiters bit masks */ +/* DCFG registers bit masks */ #define RCWSR0_SYS_PLL_RAT_SHIFT 25 #define RCWSR0_SYS_PLL_RAT_MASK 0x1f #define RCWSR0_MEM_PLL_RAT_SHIFT 16 diff --git a/include/drivers/st/stm32_pka.h b/include/drivers/st/stm32_pka.h index ad4690ae5..34b3f6b5f 100644 --- a/include/drivers/st/stm32_pka.h +++ b/include/drivers/st/stm32_pka.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + * Copyright (c) 2022-2023, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,24 +9,11 @@ #include <stdint.h> -#if !PKA_USE_NIST_P256 && !PKA_USE_BRAINPOOL_P256R1 && !PKA_USE_BRAINPOOL_P256T1 && \ - !PKA_USE_NIST_P521 -#error "At least one ECDSA curve needs to be selected" -#endif - enum stm32_pka_ecdsa_curve_id { -#if PKA_USE_NIST_P256 PKA_NIST_P256, -#endif -#if PKA_USE_BRAINPOOL_P256R1 PKA_BRAINPOOL_P256R1, -#endif -#if PKA_USE_BRAINPOOL_P256T1 PKA_BRAINPOOL_P256T1, -#endif -#if PKA_USE_NIST_P521 PKA_NIST_P521, -#endif }; struct stm32_pka_platdata { diff --git a/include/lib/cpus/aarch64/generic.h b/include/lib/cpus/aarch64/generic.h index 53df58761..dd71554d0 100644 --- a/include/lib/cpus/aarch64/generic.h +++ b/include/lib/cpus/aarch64/generic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserverd. + * Copyright (c) 2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h index dd2b83681..e6af43e58 100644 --- a/include/lib/el3_runtime/aarch64/context.h +++ b/include/lib/el3_runtime/aarch64/context.h @@ -523,10 +523,6 @@ void el2_sysregs_context_restore_common(el2_sysregs_t *regs); void el2_sysregs_context_save_mte(el2_sysregs_t *regs); void el2_sysregs_context_restore_mte(el2_sysregs_t *regs); #endif /* CTX_INCLUDE_MTE_REGS */ -#if RAS_EXTENSION -void el2_sysregs_context_save_ras(el2_sysregs_t *regs); -void el2_sysregs_context_restore_ras(el2_sysregs_t *regs); -#endif /* RAS_EXTENSION */ #endif /* CTX_INCLUDE_EL2_REGS */ #if CTX_INCLUDE_FPREGS diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index 925ff2115..16be97116 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -731,7 +731,7 @@ MEASURED_BOOT # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ - + (UL(1) << 21)) + + SZ_4M) # elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h index ffbd4ca13..e8461f5a2 100644 --- a/include/plat/arm/common/plat_arm.h +++ b/include/plat/arm/common/plat_arm.h @@ -364,6 +364,7 @@ extern const unsigned int arm_pm_idle_states[]; /* secure watchdog */ void plat_arm_secure_wdt_start(void); void plat_arm_secure_wdt_stop(void); +void plat_arm_secure_wdt_refresh(void); /* Get SOC-ID of ARM platform */ uint32_t plat_arm_get_soc_id(void); diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h index dde174c37..f87f857c5 100644 --- a/include/plat/arm/css/common/css_def.h +++ b/include/plat/arm/css/common/css_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -52,18 +52,21 @@ * terminology. On a GICv2 system or mode, the interrupts will be treated as * Group 0 interrupts. */ -#define CSS_G1S_IRQ_PROPS(grp) \ +#define CSS_G1S_INT_PROPS(grp) \ INTR_PROP_DESC(CSS_IRQ_MHU, GIC_HIGHEST_SEC_PRIORITY, grp, \ GIC_INTR_CFG_LEVEL), \ INTR_PROP_DESC(CSS_IRQ_GPU_SMMU_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ GIC_INTR_CFG_LEVEL), \ INTR_PROP_DESC(CSS_IRQ_TZC, GIC_HIGHEST_SEC_PRIORITY, grp, \ GIC_INTR_CFG_LEVEL), \ - INTR_PROP_DESC(CSS_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_LEVEL), \ INTR_PROP_DESC(CSS_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ GIC_INTR_CFG_LEVEL) +#define CSS_G1S_IRQ_PROPS(grp) \ + CSS_G1S_INT_PROPS(grp), \ + INTR_PROP_DESC(CSS_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL) + #if CSS_USE_SCMI_SDS_DRIVER /* Memory region for shared data storage */ #define PLAT_ARM_SDS_MEM_BASE ARM_SHARED_RAM_BASE diff --git a/include/services/errata_abi_svc.h b/include/services/errata_abi_svc.h new file mode 100644 index 000000000..12500661b --- /dev/null +++ b/include/services/errata_abi_svc.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef ERRATA_ABI_SVC_H +#define ERRATA_ABI_SVC_H + +#include <lib/smccc.h> + +#define ARM_EM_VERSION U(0x840000F0) +#define ARM_EM_FEATURES U(0x840000F1) +#define ARM_EM_CPU_ERRATUM_FEATURES U(0x840000F2) + +/* EM version numbers */ +#define EM_VERSION_MAJOR (0x1) +#define EM_VERSION_MINOR (0x0) + +/* EM CPU_ERRATUM_FEATURES return codes */ +#define EM_HIGHER_EL_MITIGATION (3) +#define EM_NOT_AFFECTED (2) +#define EM_AFFECTED (1) +#define EM_SUCCESS (0) +#define EM_NOT_SUPPORTED (-1) +#define EM_INVALID_PARAMETERS (-2) +#define EM_UNKNOWN_ERRATUM (-3) + +#if ERRATA_ABI_SUPPORT +bool is_errata_fid(uint32_t smc_fid); +#else +static inline bool is_errata_fid(uint32_t smc_fid) +{ + return false; +} +#endif /* ERRATA_ABI_SUPPORT */ +uintptr_t errata_abi_smc_handler( + uint32_t smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags +); +#endif /* ERRATA_ABI_SVC_H */ + diff --git a/include/services/ffa_svc.h b/include/services/ffa_svc.h index 8bc911a68..64af437bb 100644 --- a/include/services/ffa_svc.h +++ b/include/services/ffa_svc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2022, Arm Limited. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,7 +24,7 @@ /* The macros below are used to identify FFA calls from the SMC function ID */ #define FFA_FNUM_MIN_VALUE U(0x60) -#define FFA_FNUM_MAX_VALUE U(0x8B) +#define FFA_FNUM_MAX_VALUE U(0x8C) #define is_ffa_fid(fid) __extension__ ({ \ __typeof__(fid) _fid = (fid); \ ((GET_SMC_NUM(_fid) >= FFA_FNUM_MIN_VALUE) && \ @@ -118,6 +118,7 @@ #define FFA_FNUM_MSG_SEND2 U(0x86) #define FFA_FNUM_SECONDARY_EP_REGISTER U(0x87) #define FFA_FNUM_PARTITION_INFO_GET_REGS U(0x8B) +#define FFA_FNUM_EL3_INTR_HANDLE U(0x8C) /* FFA SMC32 FIDs */ #define FFA_ERROR FFA_FID(SMC_32, FFA_FNUM_ERROR) @@ -163,6 +164,7 @@ #define FFA_MEM_FRAG_TX FFA_FID(SMC_32, FFA_FNUM_MEM_FRAG_TX) #define FFA_SPM_ID_GET FFA_FID(SMC_32, FFA_FNUM_SPM_ID_GET) #define FFA_NORMAL_WORLD_RESUME FFA_FID(SMC_32, FFA_FNUM_NORMAL_WORLD_RESUME) +#define FFA_EL3_INTR_HANDLE FFA_FID(SMC_32, FFA_FNUM_EL3_INTR_HANDLE) /* FFA SMC64 FIDs */ #define FFA_ERROR_SMC64 FFA_FID(SMC_64, FFA_FNUM_ERROR) |