diff options
183 files changed, 1559 insertions, 527 deletions
@@ -414,6 +414,10 @@ ifeq ($(findstring clang,$(notdir $(CC))),) WARNINGS += -Wunused-but-set-variable -Wmaybe-uninitialized \ -Wpacked-bitfield-compat -Wshift-overflow=2 \ -Wlogical-op + +# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105523 +TF_CFLAGS += $(call cc_option, --param=min-pagesize=0) + else # using clang WARNINGS += -Wshift-overflow -Wshift-sign-overflow \ @@ -790,17 +794,23 @@ ifeq ($(RESET_TO_BL2)-$(BL2_IN_XIP_MEM),0-1) $(error "BL2_IN_XIP_MEM is only supported when RESET_TO_BL2 is enabled") endif -# For RAS_EXTENSION, require that EAs are handled in EL3 first +# RAS_EXTENSION is deprecated, provide alternate build options ifeq ($(RAS_EXTENSION),1) + $(error "RAS_EXTENSION is now deprecated, please use ENABLE_FEAT_RAS and RAS_FFH_SUPPORT instead") +endif +# RAS firmware first handling requires that EAs are handled in EL3 first +ifeq ($(RAS_FFH_SUPPORT),1) + ifneq ($(ENABLE_FEAT_RAS),1) + $(error For RAS_FFH_SUPPORT, ENABLE_FEAT_RAS must also be 1) + endif ifneq ($(HANDLE_EA_EL3_FIRST_NS),1) - $(error For RAS_EXTENSION, HANDLE_EA_EL3_FIRST_NS must also be 1) + $(error For RAS_FFH_SUPPORT, HANDLE_EA_EL3_FIRST_NS must also be 1) endif endif - -# When FAULT_INJECTION_SUPPORT is used, require that RAS_EXTENSION is enabled +# When FAULT_INJECTION_SUPPORT is used, require that FEAT_RAS is enabled ifeq ($(FAULT_INJECTION_SUPPORT),1) - ifneq ($(RAS_EXTENSION),1) - $(error For FAULT_INJECTION_SUPPORT, RAS_EXTENSION must also be 1) + ifeq ($(ENABLE_FEAT_RAS),0) + $(error For FAULT_INJECTION_SUPPORT, ENABLE_FEAT_RAS must not be 0) endif endif @@ -1067,6 +1077,7 @@ PYTHON ?= python3 # Variables for use with PRINT_MEMORY_MAP PRINT_MEMORY_MAP_PATH ?= tools/memory PRINT_MEMORY_MAP ?= ${PRINT_MEMORY_MAP_PATH}/print_memory_map.py +INVERTED_MEMMAP ?= 0 # Variables for use with documentation build using Sphinx tool DOCS_PATH ?= docs @@ -1172,7 +1183,10 @@ $(eval $(call assert_booleans,\ SIMICS_BUILD \ FEATURE_DETECTION \ TRNG_SUPPORT \ + ERRATA_ABI_SUPPORT \ + ERRATA_NON_ARM_INTERCONNECT \ CONDITIONAL_CMO \ + RAS_FFH_SUPPORT \ ))) $(eval $(call assert_numerics,\ @@ -1191,6 +1205,7 @@ $(eval $(call assert_numerics,\ ENABLE_FEAT_AMU \ ENABLE_FEAT_AMUv1p1 \ ENABLE_FEAT_CSV2_2 \ + ENABLE_FEAT_RAS \ ENABLE_FEAT_DIT \ ENABLE_FEAT_ECV \ ENABLE_FEAT_FGT \ @@ -1217,7 +1232,6 @@ $(eval $(call assert_numerics,\ FW_ENC_STATUS \ NR_OF_FW_BANKS \ NR_OF_IMAGES_IN_FW_BANK \ - RAS_EXTENSION \ TWED_DELAY \ ENABLE_FEAT_TWED \ SVE_VECTOR_LEN \ @@ -1290,7 +1304,8 @@ $(eval $(call add_defines,\ PROGRAMMABLE_RESET_ADDRESS \ PSCI_EXTENDED_STATE_ID \ PSCI_OS_INIT_MODE \ - RAS_EXTENSION \ + ENABLE_FEAT_RAS \ + RAS_FFH_SUPPORT \ RESET_TO_BL31 \ SEPARATE_CODE_AND_RODATA \ SEPARATE_BL2_NOLOAD_REGION \ @@ -1304,6 +1319,8 @@ $(eval $(call add_defines,\ TRUSTED_BOARD_BOOT \ CRYPTO_SUPPORT \ TRNG_SUPPORT \ + ERRATA_ABI_SUPPORT \ + ERRATA_NON_ARM_INTERCONNECT \ USE_COHERENT_MEM \ USE_DEBUGFS \ ARM_IO_IN_DTB \ diff --git a/bl31/aarch64/ea_delegate.S b/bl31/aarch64/ea_delegate.S index 92df653b1..dd6b4dc9c 100644 --- a/bl31/aarch64/ea_delegate.S +++ b/bl31/aarch64/ea_delegate.S @@ -149,7 +149,7 @@ endfunc handle_lower_el_async_ea * x1: EA syndrome */ func delegate_sync_ea -#if RAS_EXTENSION +#if RAS_FFH_SUPPORT /* * Check for Uncontainable error type. If so, route to the platform * fatal error handler rather than the generic EA one. @@ -179,7 +179,7 @@ endfunc delegate_sync_ea * x1: EA syndrome */ func delegate_async_ea -#if RAS_EXTENSION +#if RAS_FFH_SUPPORT /* Check Exception Class to ensure SError, as this function should * only be invoked for SError. If that is not the case, which implies * either an HW error or programming error, panic. diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S index b02e8bb21..8bcf94e21 100644 --- a/bl31/aarch64/runtime_exceptions.S +++ b/bl31/aarch64/runtime_exceptions.S @@ -50,16 +50,16 @@ /* * Macro that prepares entry to EL3 upon taking an exception. * - * With RAS_EXTENSION, this macro synchronizes pending errors with an ESB - * instruction. When an error is thus synchronized, the handling is + * With RAS_FFH_SUPPORT, this macro synchronizes pending errors with an + * ESB instruction. When an error is thus synchronized, the handling is * delegated to platform EA handler. * - * Without RAS_EXTENSION, this macro synchronizes pending errors using + * Without RAS_FFH_SUPPORT, this macro synchronizes pending errors using * a DSB, unmasks Asynchronous External Aborts and saves X30 before * setting the flag CTX_IS_IN_EL3. */ .macro check_and_unmask_ea -#if RAS_EXTENSION +#if RAS_FFH_SUPPORT /* Synchronize pending External Aborts */ esb @@ -303,7 +303,7 @@ vector_entry fiq_sp_elx end_vector_entry fiq_sp_elx vector_entry serror_sp_elx -#if !RAS_EXTENSION +#if !RAS_FFH_SUPPORT /* * This will trigger if the exception was taken due to SError in EL3 or * because of pending asynchronous external aborts from lower EL that got @@ -355,7 +355,7 @@ end_vector_entry fiq_aarch64 vector_entry serror_aarch64 save_x30 apply_at_speculative_wa -#if RAS_EXTENSION +#if RAS_FFH_SUPPORT msr daifclr, #DAIF_ABT_BIT #else check_and_unmask_ea @@ -398,7 +398,7 @@ end_vector_entry fiq_aarch32 vector_entry serror_aarch32 save_x30 apply_at_speculative_wa -#if RAS_EXTENSION +#if RAS_FFH_SUPPORT msr daifclr, #DAIF_ABT_BIT #else check_and_unmask_ea diff --git a/bl31/bl31.mk b/bl31/bl31.mk index b16b4e79b..d7c9a521d 100644 --- a/bl31/bl31.mk +++ b/bl31/bl31.mk @@ -91,6 +91,10 @@ ifneq (${ENABLE_SPE_FOR_NS},0) BL31_SOURCES += lib/extensions/spe/spe.c endif +ifeq (${ERRATA_ABI_SUPPORT},1) +BL31_SOURCES += services/std_svc/errata_abi/errata_abi_main.c +endif + ifneq (${ENABLE_FEAT_AMU},0) BL31_SOURCES += ${AMU_SOURCES} endif diff --git a/bl32/sp_min/sp_min.mk b/bl32/sp_min/sp_min.mk index fb0161c28..ec75d88ac 100644 --- a/bl32/sp_min/sp_min.mk +++ b/bl32/sp_min/sp_min.mk @@ -46,6 +46,10 @@ BL32_SOURCES += services/std_svc/trng/trng_main.c \ services/std_svc/trng/trng_entropy_pool.c endif +ifeq (${ERRATA_ABI_SUPPORT}, 1) +BL32_SOURCES += services/std_svc/errata_abi/errata_abi_main.c +endif + ifneq (${ENABLE_SYS_REG_TRACE_FOR_NS},0) BL32_SOURCES += lib/extensions/sys_reg_trace/aarch32/sys_reg_trace.c endif diff --git a/changelog.yaml b/changelog.yaml index 6dbb9b20d..9114dadb5 100644 --- a/changelog.yaml +++ b/changelog.yaml @@ -662,6 +662,9 @@ subsections: - title: TRNG scope: trng + - title: ERRATA_ABI + scope: errata_abi + - title: Libraries subsections: @@ -877,6 +880,9 @@ subsections: deprecated: - drivers/tzc380 + - title: SBSA + scope: sbsa + - title: Marvell scope: marvell-drivers diff --git a/common/feat_detect.c b/common/feat_detect.c index eb4db95a0..50b74d0c8 100644 --- a/common/feat_detect.c +++ b/common/feat_detect.c @@ -60,16 +60,6 @@ check_feature(int state, unsigned long field, const char *feat_name, } } -/******************************************************************************* - * Feature : FEAT_RAS (Reliability, Availability, and Serviceability Extension) - ******************************************************************************/ -static void read_feat_ras(void) -{ -#if (RAS_EXTENSION == FEAT_STATE_ALWAYS) - feat_detect_panic(is_armv8_2_feat_ras_present(), "RAS"); -#endif -} - /************************************************ * Feature : FEAT_PAUTH (Pointer Authentication) ***********************************************/ @@ -160,9 +150,9 @@ void detect_arch_features(void) check_feature(ENABLE_FEAT_VHE, read_feat_vhe_id_field(), "VHE", 1, 1); /* v8.2 features */ - read_feat_ras(); check_feature(ENABLE_SVE_FOR_NS, read_feat_sve_id_field(), "SVE", 1, 1); + check_feature(ENABLE_FEAT_RAS, read_feat_ras_id_field(), "RAS", 1, 2); /* v8.3 features */ read_feat_pauth(); diff --git a/docs/about/release-information.rst b/docs/about/release-information.rst index cd52460b9..0ba0a7aa0 100644 --- a/docs/about/release-information.rst +++ b/docs/about/release-information.rst @@ -67,7 +67,7 @@ after which it will be removed. | | Date | after | | | | | Release | | +================================+=============+=========+=========================================================+ -| plat_convert_pk() function | Nov'22 | 2.9 | Platform conversion to manage specific PK hash | +| None at this time | | | | +--------------------------------+-------------+---------+---------------------------------------------------------+ Removal of Deprecated Drivers @@ -82,8 +82,6 @@ after which it will be removed. | | Date | after | | | | | Release | | +================================+=============+=========+=========================================================+ -| io_dummy driver | Nov'22 | 2.9 | No more used by any upstream platform | -+--------------------------------+-------------+---------+---------------------------------------------------------+ | CryptoCell-712 | 2.9 | 3.0 | No longer maintained. | +--------------------------------+-------------+---------+---------------------------------------------------------+ | CryptoCell-713 | 2.9 | 3.0 | No longer maintained. | diff --git a/docs/components/ras.rst b/docs/components/ras.rst index 871be2d76..8d003452c 100644 --- a/docs/components/ras.rst +++ b/docs/components/ras.rst @@ -1,45 +1,89 @@ Reliability, Availability, and Serviceability (RAS) Extensions -============================================================== +************************************************************** This document describes |TF-A| support for Arm Reliability, Availability, and Serviceability (RAS) extensions. RAS is a mandatory extension for Armv8.2 and later CPUs, and also an optional extension to the base Armv8.0 architecture. -In conjunction with the |EHF|, support for RAS extension enables firmware-first -paradigm for handling platform errors: exceptions resulting from errors in -Non-secure world are routed to and handled in EL3. -Said errors are Synchronous External Abort (SEA), Asynchronous External Abort -(signalled as SErrors), Fault Handling and Error Recovery interrupts. -The |EHF| document mentions various :ref:`error handling -use-cases <delegation-use-cases>` . - For the description of Arm RAS extensions, Standard Error Records, and the precise definition of RAS terminology, please refer to the Arm Architecture -Reference Manual. The rest of this document assumes familiarity with -architecture and terminology. +Reference Manual and `RAS Supplement`_. The rest of this document assumes +familiarity with architecture and terminology. + +There are two philosophies for handling RAS errors from Non-secure world point +of view. + +- :ref:`Firmware First Handling (FFH)` +- :ref:`Kernel First Handling (KFH)` + +.. _Firmware First Handling (FFH): + +Firmware First Handling (FFH) +============================= + +Introduction +------------ + +EA’s and Error interrupts corresponding to NS nodes are handled first in firmware + +- Errors signaled back to NS world via suitable mechanism +- Kernel is prohibited from accessing the RAS error records directly +- Firmware creates CPER records for kernel to navigate and process +- Firmware signals error back to Kernel via SDEI Overview -------- -As mentioned above, the RAS support in |TF-A| enables routing to and handling of -exceptions resulting from platform errors in EL3. It allows the platform to -define an External Abort handler, and to register RAS nodes and interrupts. RAS -framework also provides `helpers`__ for accessing Standard Error Records as -introduced by the RAS extensions. +FFH works in conjunction with `Exception Handling Framework`. Exceptions resulting from +errors in Non-secure world are routed to and handled in EL3. Said errors are Synchronous +External Abort (SEA), Asynchronous External Abort (signalled as SErrors), Fault Handling +and Error Recovery interrupts. +RAS Framework in TF-A allows the platform to define an external abort handler and to +register RAS nodes and interrupts. It also provides `helpers`__ for accessing Standard +Error Records as introduced by the RAS extensions + .. __: `Standard Error Record helpers`_ -The build option ``RAS_EXTENSION`` when set to ``1`` includes the RAS in run -time firmware; ``EL3_EXCEPTION_HANDLING`` and ``HANDLE_EA_EL3_FIRST_NS`` must also -be set ``1``. ``RAS_TRAP_NS_ERR_REC_ACCESS`` controls the access to the RAS -error record registers from Non-secure. +.. _Kernel First Handling (KFH): + +Kernel First Handling (KFH) +=========================== + +Introduction +------------ + +EA's originating/attributed to NS world are handled first in NS and Kernel navigates +the std error records directly. + +**KFH can be supported in a platform without TF-A being aware of it but there are few +corner cases where TF-A needs to have special handling, which is currently missing and +will be added in future** + +TF-A build options +================== + +- **ENABLE_FEAT_RAS**: Manage FEAT_RAS extension when switching the world. +- **RAS_FFH_SUPPORT**: Pull in necessary framework and platform hooks for Firmware first + handling(FFH) of RAS errors. +- **RAS_TRAP_NS_ERR_REC_ACCESS**: Trap Non-secure access of RAS error record registers. +- **RAS_EXTENSION**: Deprecated macro, equivalent to ENABLE_FEAT_RAS and RAS_FFH_SUPPORT + put together. + +RAS feature has dependency on some other TF-A build flags + +- **EL3_EXCEPTION_HANDLING**: Required for FFH +- **HANDLE_EA_EL3_FIRST_NS**: Required for FFH +- **FAULT_INJECTION_SUPPORT**: Required for testing RAS feature on fvp platform + +RAS Framework +============= + .. _ras-figure: .. image:: ../resources/diagrams/draw.io/ras.svg -See more on `Engaging the RAS framework`_. - Platform APIs ------------- @@ -191,19 +235,10 @@ doesn't return. Engaging the RAS framework -------------------------- -Enabling RAS support is a platform choice constructed from three distinct, but -related, build options: - -- ``RAS_EXTENSION=1`` includes the RAS framework in the run time firmware; - -- ``EL3_EXCEPTION_HANDLING=1`` enables handling of exceptions at EL3. See - `Interaction with Exception Handling Framework`_; - -- ``HANDLE_EA_EL3_FIRST_NS=1`` enables routing of External Aborts and SErrors, - resulting from errors in NS world, to EL3. +Enabling RAS support is a platform choice The RAS support in |TF-A| introduces a default implementation of -``plat_ea_handler``, the External Abort handler in EL3. When ``RAS_EXTENSION`` +``plat_ea_handler``, the External Abort handler in EL3. When ``RAS_FFH_SUPPORT`` is set to ``1``, it'll first call ``ras_ea_handler()`` function, which is the top-level RAS exception handler. ``ras_ea_handler`` is responsible for iterating to through platform-supplied error records, probe them, and when an error is @@ -239,4 +274,6 @@ for non-interrupt exceptions, they're explicit using :ref:`EHF APIs -------------- -*Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.* + +.. _RAS Supplement: https://developer.arm.com/documentation/ddi0587/latest diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 0f1f92aea..758d62be9 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -317,6 +317,11 @@ For Cortex-A78, the following errata build flags are defined : CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and it is still open. +- ``ERRATA_A78_2712571``: This applies erratum 2712571 workaround to Cortex-A78 + CPU, this erratum affects system configurations that do not use an ARM + interconnect IP. This needs to be enabled for revisions r0p0, r1p0, r1p1 + and r1p2 and it is still open. + - ``ERRATA_A78_2742426``: This applies erratum 2742426 workaround to Cortex-A78 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and it is still open. @@ -347,6 +352,11 @@ For Cortex-A78 AE, the following errata build flags are defined : Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is still open. +- ``ERRATA_A78_AE_2712574`` : This applies erratum 2712574 workaround to + Cortex-A78 AE CPU. This erratum affects system configurations that do not use + an ARM interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and + r0p2. This erratum is still open. + For Cortex-A78C, the following errata build flags are defined : - ``ERRATA_A78C_1827430`` : This applies errata 1827430 workaround to @@ -373,6 +383,11 @@ For Cortex-A78C, the following errata build flags are defined : Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This erratum is still open. +- ``ERRATA_A78C_2712575`` : This applies erratum 2712575 workaround to + Cortex-A78C CPU, this erratum affects system configurations that do not use + an ARM interconnect IP. This needs to be enabled for revisions r0p1 and r0p2 + and is still open. + - ``ERRATA_A78C_2772121`` : This applies errata 2772121 workaround to Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. This erratum is still open. @@ -488,6 +503,11 @@ For Neoverse V1, the following errata build flags are defined : CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. It is still open. +- ``ERRATA_V1_2701953``: This applies erratum 2701953 workaround to Neoverse-V1 + CPU, this erratum affects system configurations that do not use an ARM + interconnect IP. This needs to be enabled for revisions r0p0, r1p0 and r1p1. + It has been fixed in r1p2. + - ``ERRATA_V1_2743093``: This applies errata 2743093 workaround to Neoverse-V1 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 of the CPU. It is still open. @@ -500,6 +520,13 @@ For Neoverse V1, the following errata build flags are defined : CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, r1p2 of the CPU. It is still open. +For Neoverse V2, the following errata build flags are defined : + +- ``ERRATA_V2_2719103``: This applies errata 2719103 workaround to Neoverse-V2 + CPU, this affects system configurations that do not use and ARM interconnect + IP. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed + in r0p2. + For Cortex-A710, the following errata build flags are defined : - ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to @@ -558,6 +585,11 @@ For Cortex-A710, the following errata build flags are defined : Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU and is fixed in r2p1. +- ``ERRATA_A710_2701952``: This applies erratum 2701952 workaround to Cortex-A710 + CPU, and applies to system configurations that do not use and ARM + interconnect IP. This needs to be enabled for r0p0, r1p0, r2p0 and r2p1 and + is still open. + - ``ERRATA_A710_2768515``: This applies errata 2768515 workaround to Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the CPU and is still open. @@ -610,6 +642,11 @@ For Neoverse N2, the following errata build flags are defined : CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed in r0p3. +- ``ERRATA_N2_2728475``: This applies erratum 2728475 workaround to Neoverse-N2 + CPU, this erratum affects system configurations that do not use and ARM + interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and r0p2. + It is fixed in r0p3. + For Cortex-X2, the following errata build flags are defined : - ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2 @@ -647,6 +684,11 @@ For Cortex-X2, the following errata build flags are defined : CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU and is fixed in r2p1. +- ``ERRATA_X2_2701952``: This applies erratum 2701952 workaround to Cortex-X2 + CPU and affects system configurations that do not use an ARM interconnect IP. + This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 and is + still open. + - ``ERRATA_X2_2768515``: This applies errata 2768515 workaround to Cortex-X2 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the CPU and is still open. @@ -709,6 +751,13 @@ For Cortex-A510, the following errata build flags are defined : Cortex-A510 CPU. This needs to be applied to revision r0p0, r0p1, r0p2, r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3. +For Cortex-A715, the following errata build flags are defined : + +- ``ERRATA_A715_2701951``: This applies erratum 2701951 workaround to Cortex-A715 + CPU and affects system configurations that do not use an ARM interconnect + IP. This needs to be applied to revisions r0p0, r1p0 and r1p1. It is fixed + in r1p2. + DSU Errata Workarounds ---------------------- diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst index 97f355045..2c9b76a01 100644 --- a/docs/design/firmware-design.rst +++ b/docs/design/firmware-design.rst @@ -1759,6 +1759,10 @@ BL image during boot. DRAM 0xffffffff +----------+ + | EL3 TZC | + 0xffe00000 |----------| (secure) + | AP TZC | + 0xff000000 +----------+ : : 0x82100000 |----------| |HW_CONFIG | @@ -1800,6 +1804,10 @@ BL image during boot. DRAM 0xffffffff +--------------+ + | EL3 TZC | + 0xffe00000 |--------------| (secure) + | AP TZC | + 0xff000000 +--------------+ : : 0x82100000 |--------------| | HW_CONFIG | @@ -1840,7 +1848,10 @@ BL image during boot. DRAM 0xffffffff +----------+ - | BL32 | (secure) + | EL3 TZC | + 0xffe00000 |----------| (secure) + | AP TZC | + | (BL32) | 0xff000000 +----------+ | | 0x82100000 |----------| @@ -1880,6 +1891,20 @@ BL image during boot. :: + DRAM + 0xFFFFFFFF +----------+ + | SCP TZC | + 0xFFE00000 |----------| + | EL3 TZC | + 0xFFC00000 |----------| (secure) + | AP TZC | + 0xFF000000 +----------+ + | | + : : (non-secure) + | | + 0x80000000 +----------+ + + Flash0 0x0C000000 +----------+ : : @@ -1909,9 +1934,14 @@ BL image during boot. :: DRAM - 0xFFE00000 +----------+ - | BL32 | (secure) - 0xFF000000 |----------| + 0xFFFFFFFF +----------+ + | SCP TZC | + 0xFFE00000 |----------| + | EL3 TZC | + 0xFFC00000 |----------| (secure) + | AP TZC | + | (BL32) | + 0xFF000000 +----------+ | | : : (non-secure) | | diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst index ffde0a409..4eafb392b 100644 --- a/docs/getting_started/build-options.rst +++ b/docs/getting_started/build-options.rst @@ -775,15 +775,14 @@ Common build options - ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI OS-initiated mode. This option defaults to 0. -- ``RAS_EXTENSION``: Numeric value to enable Armv8.2 RAS features. RAS features +- ``ENABLE_FEAT_RAS``: Numeric value to enable Armv8.2 RAS features. RAS features are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 or later CPUs. This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. - When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST_NS`` must also be - set to ``1``. - - This option is disabled by default. +- ``RAS_FFH_SUPPORT``: Support to enable Firmware first handling of RAS errors + originating from NS world. When ``RAS_FFH_SUPPORT`` is set to ``1``, + ``HANDLE_EA_EL3_FIRST_NS`` and ``ENABLE_FEAT_RAS`` must also be set to ``1``. - ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 @@ -1130,6 +1129,13 @@ Common build options means platform hook won't be checked and CMOs will always be performed when related functions are called. +- ``ERRATA_ABI_SUPPORT``: Boolean option to enable support for Errata management + firmware interface for the BL31 image. By default its disabled (``0``). + +- ``ERRATA_NON_ARM_INTERCONNECT``: Boolean option to enable support for the + errata mitigation for platforms with a non-arm interconnect using the errata + ABI. By default its disabled (``0``). + GICv3 driver options -------------------- diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst index bf10ecffb..a3f8cc850 100644 --- a/docs/getting_started/prerequisites.rst +++ b/docs/getting_started/prerequisites.rst @@ -26,7 +26,7 @@ Toolchain |TF-A| can be built with any of the following *cross-compiler* toolchains that target the Armv7-A or Armv8-A architectures: -- GCC >= 11.3.Rel1 (from the `Arm Developer website`_) +- GCC >= 12.2.Rel1 (from the `Arm Developer website`_) You will need the targets ``arm-none-eabi`` and ``aarch64-none-elf`` for AArch32 and AArch64 builds respectively. diff --git a/docs/global_substitutions.txt b/docs/global_substitutions.txt index 9428fe97d..80012e7b8 100644 --- a/docs/global_substitutions.txt +++ b/docs/global_substitutions.txt @@ -69,3 +69,4 @@ .. |UEFI| replace:: :term:`UEFI` .. |WDOG| replace:: :term:`WDOG` .. |XLAT| replace:: :term:`XLAT` +.. |ERRATA_ABI| replace:: :term:`ERRATA_ABI` diff --git a/docs/glossary.rst b/docs/glossary.rst index 12c6ab756..58b7d999b 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -70,6 +70,9 @@ You can find additional definitions in the `Arm Glossary`_. EHF Exception Handling Framework + ERRATA_ABI + Errata management firmware interface + FCONF Firmware Configuration Framework diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst index 1225a9f79..1250071ef 100644 --- a/docs/porting-guide.rst +++ b/docs/porting-guide.rst @@ -3418,11 +3418,11 @@ The third parameter (``void *cookie``) is unused for now. The fourth parameter (``uint64_t flags``) indicates the preempted security state. These parameters are received from the top-level exception handler. -If ``RAS_EXTENSION`` is set to ``1``, the default implementation of this +If ``RAS_FFH_SUPPORT`` is set to ``1``, the default implementation of this function iterates through RAS handlers registered by the platform. If any of the RAS handlers resolve the External Abort, no further action is taken. -If ``RAS_EXTENSION`` is set to ``0``, or if none of the platform RAS handlers +If ``RAS_FFH_SUPPORT`` is set to ``0``, or if none of the platform RAS handlers could resolve the External Abort, the default implementation prints an error message, and panics. diff --git a/drivers/arm/css/scmi/vendor/scmi_sq.c b/drivers/arm/css/scmi/vendor/scmi_sq.c index f18542487..103763360 100644 --- a/drivers/arm/css/scmi/vendor/scmi_sq.c +++ b/drivers/arm/css/scmi/vendor/scmi_sq.c @@ -15,7 +15,7 @@ #include <sq_common.h> -/* SCMI messge ID to get the available DRAM region */ +/* SCMI message ID to get the available DRAM region */ #define SCMI_VENDOR_EXT_MEMINFO_GET_MSG 0x3 #define SCMI_VENDOR_EXT_MEMINFO_GET_MSG_LEN 4 diff --git a/drivers/arm/gic/v2/gicv2_main.c b/drivers/arm/gic/v2/gicv2_main.c index 1925a13ac..ca2a0389a 100644 --- a/drivers/arm/gic/v2/gicv2_main.c +++ b/drivers/arm/gic/v2/gicv2_main.c @@ -252,7 +252,7 @@ void gicv2_end_of_interrupt(unsigned int id) * Ensure the write to peripheral registers are *complete* before the write * to GIC_EOIR. * - * Note: The completion gurantee depends on various factors of system design + * Note: The completion guarantee depends on various factors of system design * and the barrier is the best core can do by which execution of further * instructions waits till the barrier is alive. */ diff --git a/drivers/arm/gic/v3/gic600_multichip.c b/drivers/arm/gic/v3/gic600_multichip.c index f26e056c9..7f0735d42 100644 --- a/drivers/arm/gic/v3/gic600_multichip.c +++ b/drivers/arm/gic/v3/gic600_multichip.c @@ -322,7 +322,7 @@ static void gic700_multichip_validate_data( } /******************************************************************************* - * Intialize GIC-600 and GIC-700 Multichip operation. + * Initialize GIC-600 and GIC-700 Multichip operation. ******************************************************************************/ void gic600_multichip_init(struct gic600_multichip_data *multichip_data) { diff --git a/drivers/arm/sbsa/sbsa.c b/drivers/arm/sbsa/sbsa.c index 79c6f2620..a88e20c04 100644 --- a/drivers/arm/sbsa/sbsa.c +++ b/drivers/arm/sbsa/sbsa.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -40,3 +40,9 @@ void sbsa_wdog_stop(uintptr_t base) { mmio_write_32(base + SBSA_WDOG_WCS_OFFSET, (0x0)); } + +/* Refresh the secure watchdog timer explicitly */ +void sbsa_wdog_refresh(uintptr_t refresh_base) +{ + mmio_write_32(refresh_base + SBSA_WDOG_WRR_OFFSET, SBSA_WDOG_WRR_REFRESH); +} diff --git a/drivers/brcm/emmc/emmc_chal_sd.c b/drivers/brcm/emmc/emmc_chal_sd.c index 34d761c73..5379ec1a7 100644 --- a/drivers/brcm/emmc/emmc_chal_sd.c +++ b/drivers/brcm/emmc/emmc_chal_sd.c @@ -119,7 +119,7 @@ static int32_t chal_sd_set_power(struct sd_dev *handle, mmio_setbits_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL_OFFSET, SD4_EMMC_TOP_CTRL_SDPWR_MASK); - /* dummy write & ack to verify if the sdio is ready to send commads */ + /* dummy write & ack to verify if the sdio is ready to send commands */ mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_ARG_OFFSET, 0); mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CMD_OFFSET, 0); @@ -600,7 +600,7 @@ uint32_t chal_sd_freq_2_div_ctrl_setting(uint32_t desired_freq) if (actual_freq > desired_freq) { /* - * Division does not result in exact freqency match. + * Division does not result in exact frequency match. * Make sure resulting frequency does not exceed requested freq. */ div_ctrl_setting++; diff --git a/drivers/brcm/emmc/emmc_csl_sdcard.c b/drivers/brcm/emmc/emmc_csl_sdcard.c index 40bc4a058..789ed9c82 100644 --- a/drivers/brcm/emmc/emmc_csl_sdcard.c +++ b/drivers/brcm/emmc/emmc_csl_sdcard.c @@ -244,7 +244,7 @@ static int abort_err(struct sd_handle *handle) * The function handles real data transmission on both DMA and * none DMA mode, In None DMA mode the data transfer starts * when the command is sent to the card, data has to be written - * into the host contollers buffer at this time one block + * into the host controllers buffer at this time one block * at a time. * In DMA mode, the real data transfer is done by the DMA engine * and this functions just waits for the data transfer to complete. @@ -318,7 +318,7 @@ int select_blk_sz(struct sd_handle *handle, uint16_t size) /* - * The function initalizes the SD/SDIO/MMC/CEATA and detects + * The function initializes the SD/SDIO/MMC/CEATA and detects * the card according to the flag of detection. * Once this function is called, the card is put into ready state * so application can do data transfer to and from the card. @@ -393,7 +393,7 @@ int init_card(struct sd_handle *handle, int detection) /* - * The function handles MMC/CEATA card initalization. + * The function handles MMC/CEATA card initialization. */ int init_mmc_card(struct sd_handle *handle) { diff --git a/drivers/brcm/i2c/i2c.c b/drivers/brcm/i2c/i2c.c index 2096a8259..b45c0e771 100644 --- a/drivers/brcm/i2c/i2c.c +++ b/drivers/brcm/i2c/i2c.c @@ -612,7 +612,7 @@ int i2c_probe(uint32_t bus_id, uint8_t devaddr) * * Description: * This function reads I2C data from a device without specifying - * a command regsiter. + * a command register. * * Parameters: * bus_id - I2C bus ID @@ -647,7 +647,7 @@ int i2c_recv_byte(uint32_t bus_id, uint8_t devaddr, uint8_t *value) * * Description: * This function send I2C data to a device without specifying - * a command regsiter. + * a command register. * * Parameters: * bus_id - I2C bus ID diff --git a/drivers/brcm/sotp.c b/drivers/brcm/sotp.c index 63c482066..20c644129 100644 --- a/drivers/brcm/sotp.c +++ b/drivers/brcm/sotp.c @@ -168,7 +168,7 @@ void sotp_mem_write(uint32_t addr, uint32_t sotp_add_ecc, uint64_t wdata) BIT(SOTP_STATUS__FDONE)) ; - /* Enable OTP acces by CPU */ + /* Enable OTP access by CPU */ mmio_setbits_32(SOTP_PROG_CONTROL, BIT(SOTP_PROG_CONTROL__OTP_CPU_MODE_EN)); @@ -244,7 +244,7 @@ void sotp_mem_write(uint32_t addr, uint32_t sotp_add_ecc, uint64_t wdata) /* Command done is cleared w1c */ mmio_setbits_32(SOTP_STATUS_1, BIT(SOTP_STATUS_1__CMD_DONE)); - /* disable OTP acces by CPU */ + /* disable OTP access by CPU */ mmio_clrbits_32(SOTP_PROG_CONTROL, BIT(SOTP_PROG_CONTROL__OTP_CPU_MODE_EN)); diff --git a/drivers/io/io_dummy.c b/drivers/io/io_dummy.c deleted file mode 100644 index 4f0cda6da..000000000 --- a/drivers/io/io_dummy.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <assert.h> -#include <string.h> - -#include <common/debug.h> -#include <drivers/io/io_driver.h> -#include <drivers/io/io_dummy.h> -#include <drivers/io/io_storage.h> - -struct file_state { - int in_use; - size_t size; -}; - -static struct file_state current_file = {0}; - -/* Identify the device type as dummy */ -static io_type_t device_type_dummy(void) -{ - return IO_TYPE_DUMMY; -} - -/* Dummy device functions */ -static int dummy_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info); -static int dummy_block_open(io_dev_info_t *dev_info, const uintptr_t spec, - io_entity_t *entity); -static int dummy_block_len(io_entity_t *entity, size_t *length); -static int dummy_block_read(io_entity_t *entity, uintptr_t buffer, - size_t length, size_t *length_read); -static int dummy_block_close(io_entity_t *entity); -static int dummy_dev_close(io_dev_info_t *dev_info); - - -static const io_dev_connector_t dummy_dev_connector = { - .dev_open = dummy_dev_open -}; - - -static const io_dev_funcs_t dummy_dev_funcs = { - .type = device_type_dummy, - .open = dummy_block_open, - .seek = NULL, - .size = dummy_block_len, - .read = dummy_block_read, - .write = NULL, - .close = dummy_block_close, - .dev_init = NULL, - .dev_close = dummy_dev_close, -}; - - -static const io_dev_info_t dummy_dev_info = { - .funcs = &dummy_dev_funcs, - .info = (uintptr_t)NULL -}; - - -/* Open a connection to the dummy device */ -static int dummy_dev_open(const uintptr_t dev_spec __attribute__((unused)), - io_dev_info_t **dev_info) -{ - assert(dev_info != NULL); - *dev_info = (io_dev_info_t *)&dummy_dev_info; - - return 0; -} - - -/* Close a connection to the dummy device */ -static int dummy_dev_close(io_dev_info_t *dev_info) -{ - return 0; -} - - -/* Open a file on the dummy device */ -static int dummy_block_open(io_dev_info_t *dev_info, const uintptr_t spec, - io_entity_t *entity) -{ - int result; - const io_block_spec_t *block_spec = (io_block_spec_t *)spec; - - if (current_file.in_use == 0) { - assert(block_spec != NULL); - assert(entity != NULL); - - current_file.in_use = 1; - current_file.size = block_spec->length; - entity->info = (uintptr_t)¤t_file; - result = 0; - } else { - WARN("A Dummy device is already active. Close first.\n"); - result = -ENOMEM; - } - - return result; -} - - -/* Return the size of a file on the dummy device */ -static int dummy_block_len(io_entity_t *entity, size_t *length) -{ - assert(entity != NULL); - assert(length != NULL); - - *length = ((struct file_state *)entity->info)->size; - - return 0; -} - - -/* Read data from a file on the dummy device */ -static int dummy_block_read(io_entity_t *entity, uintptr_t buffer, - size_t length, size_t *length_read) -{ - assert(length_read != NULL); - - *length_read = length; - - return 0; -} - - -/* Close a file on the dummy device */ -static int dummy_block_close(io_entity_t *entity) -{ - assert(entity != NULL); - - entity->info = 0; - current_file.in_use = 0; - - return 0; -} - - -/* Exported functions */ - -/* Register the dummy driver with the IO abstraction */ -int register_io_dev_dummy(const io_dev_connector_t **dev_con) -{ - int result; - - assert(dev_con != NULL); - - result = io_register_device(&dummy_dev_info); - if (result == 0) - *dev_con = &dummy_dev_connector; - - return result; -} diff --git a/drivers/marvell/comphy/phy-comphy-cp110.c b/drivers/marvell/comphy/phy-comphy-cp110.c index fa9fe4100..e256fa7f4 100644 --- a/drivers/marvell/comphy/phy-comphy-cp110.c +++ b/drivers/marvell/comphy/phy-comphy-cp110.c @@ -2053,7 +2053,7 @@ static int mvebu_cp110_comphy_usb3_power_on(uint64_t comphy_base, mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK; data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET; reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); - /* Confifure SSC amplitude */ + /* Configure SSC amplitude */ mask = HPIPE_G2_TX_SSC_AMP_MASK; data = 0x1f << HPIPE_G2_TX_SSC_AMP_OFFSET; reg_set(hpipe_addr + HPIPE_G2_SET_2_REG, data, mask); diff --git a/drivers/marvell/gwin.c b/drivers/marvell/gwin.c index fa59cb033..40f8c9310 100644 --- a/drivers/marvell/gwin.c +++ b/drivers/marvell/gwin.c @@ -213,7 +213,7 @@ int init_gwin(int ap_index) * remote AP should be accompanied with proper configuration to * GWIN registers group and therefore the GWIN Miss feature * should be set into Bypass mode, need to make sure all GWIN regions - * are defined correctly that will assure no GWIN miss occurrance + * are defined correctly that will assure no GWIN miss occurrence * JIRA-AURORA2-1630 */ INFO("Update GWIN miss bypass\n"); diff --git a/drivers/marvell/mg_conf_cm3/mg_conf_cm3.c b/drivers/marvell/mg_conf_cm3/mg_conf_cm3.c index 98e189687..935243777 100644 --- a/drivers/marvell/mg_conf_cm3/mg_conf_cm3.c +++ b/drivers/marvell/mg_conf_cm3/mg_conf_cm3.c @@ -55,7 +55,7 @@ int mg_image_load(uintptr_t src_addr, uint32_t size, int cp_index) /* Don't release MG CM3 from reset - it will be done by next step * bootloader (e.g. U-Boot), when appriopriate device-tree setup (which - * has enabeld 802.3. auto-neg) will be choosen. + * has enabeld 802.3. auto-neg) will be chosen. */ return 0; diff --git a/drivers/nxp/crypto/caam/src/auth/hash.c b/drivers/nxp/crypto/caam/src/auth/hash.c index 1665df1a8..0f3cf9552 100644 --- a/drivers/nxp/crypto/caam/src/auth/hash.c +++ b/drivers/nxp/crypto/caam/src/auth/hash.c @@ -106,7 +106,7 @@ int hash_update(enum hash_algo algo, void *context, void *data_ptr, * Function : hash_final * Arguments : ctx - SHA context * Return : SUCCESS or FAILURE - * Description : This function sets the final bit and enqueues the decriptor + * Description : This function sets the final bit and enqueues the descriptor ***************************************************************************/ int hash_final(enum hash_algo algo, void *context, void *hash_ptr, unsigned int hash_len) diff --git a/drivers/nxp/crypto/caam/src/hw_key_blob.c b/drivers/nxp/crypto/caam/src/hw_key_blob.c index 0720695d3..6bcb6ba7f 100644 --- a/drivers/nxp/crypto/caam/src/hw_key_blob.c +++ b/drivers/nxp/crypto/caam/src/hw_key_blob.c @@ -18,7 +18,7 @@ #include "sec_hw_specific.h" -/* Callback function after Instantiation decsriptor is submitted to SEC +/* Callback function after Instantiation descriptor is submitted to SEC */ static void blob_done(uint32_t *desc, uint32_t status, void *arg, void *job_ring) diff --git a/drivers/nxp/crypto/caam/src/rng.c b/drivers/nxp/crypto/caam/src/rng.c index 0b9d87de4..58430dbfd 100644 --- a/drivers/nxp/crypto/caam/src/rng.c +++ b/drivers/nxp/crypto/caam/src/rng.c @@ -17,7 +17,7 @@ #include "sec_hw_specific.h" -/* Callback function after Instantiation decsriptor is submitted to SEC */ +/* Callback function after Instantiation descriptor is submitted to SEC */ static void rng_done(uint32_t *desc, uint32_t status, void *arg, void *job_ring) { @@ -183,7 +183,7 @@ int hw_rng_instantiate(void) /*if instantiate_rng(...) fails, the loop will rerun *and the kick_trng(...) function will modify the *upper and lower limits of the entropy sampling - *interval, leading to a sucessful initialization of + *interval, leading to a successful initialization of */ ret = instantiate_rng(); } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); diff --git a/drivers/nxp/ddr/nxp-ddr/ddr.c b/drivers/nxp/ddr/nxp-ddr/ddr.c index faf20e963..17c2bbb2a 100644 --- a/drivers/nxp/ddr/nxp-ddr/ddr.c +++ b/drivers/nxp/ddr/nxp-ddr/ddr.c @@ -293,7 +293,7 @@ static int cal_odt(const unsigned int clk, } if (pdodt == NULL) { - ERROR("Error determing ODT.\n"); + ERROR("Error determining ODT.\n"); return -EINVAL; } @@ -916,7 +916,7 @@ long long dram_init(struct ddr_info *priv debug("Program controller registers\n"); ret = write_ddrc_regs(priv); if (ret != 0) { - ERROR("Programing DDRC error\n"); + ERROR("Programming DDRC error\n"); return ret; } diff --git a/drivers/nxp/ddr/nxp-ddr/ddrc.c b/drivers/nxp/ddr/nxp-ddr/ddrc.c index 17a2b6a47..4133fac1a 100644 --- a/drivers/nxp/ddr/nxp-ddr/ddrc.c +++ b/drivers/nxp/ddr/nxp-ddr/ddrc.c @@ -346,7 +346,7 @@ int ddrc_set_regs(const unsigned long clk, #ifdef ERRATA_DDR_A008511 /* Part 1 of 2 */ - /* This erraum only applies to verion 5.2.1 */ + /* This erraum only applies to version 5.2.1 */ if (get_ddrc_version(ddr) == 0x50200) { ERROR("Unsupported SoC.\n"); } else if (get_ddrc_version(ddr) == 0x50201) { diff --git a/drivers/nxp/ddr/phy-gen2/messages.h b/drivers/nxp/ddr/phy-gen2/messages.h index a2310f23b..bf2d45910 100644 --- a/drivers/nxp/ddr/phy-gen2/messages.h +++ b/drivers/nxp/ddr/phy-gen2/messages.h @@ -144,7 +144,7 @@ static const struct phy_msg messages_1d[] = { "PMU3: Precharge all open banks\n" }, {0x002b0002, - "PMU: Error: Dbyte %d nibble %d found mutliple working coarse delay setting for MRD/MWD\n" + "PMU: Error: Dbyte %d nibble %d found multiple working coarse delay setting for MRD/MWD\n" }, {0x002c0000, "PMU4: MRD Passing Regions (coarseVal, fineLeft fineRight -> fineCenter)\n" @@ -536,7 +536,7 @@ static const struct phy_msg messages_1d[] = { "PMU3: Resetting DRAM\n" }, {0x00b10000, - "PMU3: setup for RCD initalization\n" + "PMU3: setup for RCD initialization\n" }, {0x00b20000, "PMU3: pmu_exit_SR from dev_init()\n" @@ -974,10 +974,10 @@ static const struct phy_msg messages_1d[] = { "PMU0: PHY VREF @ (%d/1000) VDDQ\n" }, {0x01430002, - "PMU0: initalizing phy vrefDacs to %d ExtVrefRange %x\n" + "PMU0: initializing phy vrefDacs to %d ExtVrefRange %x\n" }, {0x01440002, - "PMU0: initalizing global vref to %d range %d\n" + "PMU0: initializing global vref to %d range %d\n" }, {0x01450002, "PMU4: Setting initial device vrefDQ for CS%d to MR6 = 0x%04x\n" @@ -1811,7 +1811,7 @@ static const struct phy_msg messages_2d[] = { "PMU3: Precharge all open banks\n" }, {0x00be0002, - "PMU: Error: Dbyte %d nibble %d found mutliple working coarse delay setting for MRD/MWD\n" + "PMU: Error: Dbyte %d nibble %d found multiple working coarse delay setting for MRD/MWD\n" }, {0x00bf0000, "PMU4: MRD Passing Regions (coarseVal, fineLeft fineRight -> fineCenter)\n" @@ -2203,7 +2203,7 @@ static const struct phy_msg messages_2d[] = { "PMU3: Resetting DRAM\n" }, {0x01440000, - "PMU3: setup for RCD initalization\n" + "PMU3: setup for RCD initialization\n" }, {0x01450000, "PMU3: pmu_exit_SR from dev_init()\n" @@ -2641,10 +2641,10 @@ static const struct phy_msg messages_2d[] = { "PMU0: PHY VREF @ (%d/1000) VDDQ\n" }, {0x01d60002, - "PMU0: initalizing phy vrefDacs to %d ExtVrefRange %x\n" + "PMU0: initializing phy vrefDacs to %d ExtVrefRange %x\n" }, {0x01d70002, - "PMU0: initalizing global vref to %d range %d\n" + "PMU0: initializing global vref to %d range %d\n" }, {0x01d80002, "PMU4: Setting initial device vrefDQ for CS%d to MR6 = 0x%04x\n" diff --git a/drivers/nxp/ifc/nand/ifc_nand.c b/drivers/nxp/ifc/nand/ifc_nand.c index 1f7092a78..df7ec8579 100644 --- a/drivers/nxp/ifc/nand/ifc_nand.c +++ b/drivers/nxp/ifc/nand/ifc_nand.c @@ -531,7 +531,7 @@ static int update_bbt(uint32_t idx, uint32_t blk, return 0; /* special case for lgb == 0 */ - /* if blk <= lgb retrun */ + /* if blk <= lgb return */ if (nand->lgb != 0 && blk <= nand->lgb) return 0; diff --git a/drivers/nxp/sd/sd_mmc.c b/drivers/nxp/sd/sd_mmc.c index f7f48e723..48b27c164 100644 --- a/drivers/nxp/sd/sd_mmc.c +++ b/drivers/nxp/sd/sd_mmc.c @@ -344,7 +344,7 @@ static int esdhc_wait_response(struct mmc *mmc, uint32_t *response) * Function : mmc_switch_to_high_frquency * Arguments : mmc - Pointer to mmc struct * Return : SUCCESS or Error Code - * Description : mmc card bellow ver 4.0 does not support high speed + * Description : mmc card below ver 4.0 does not support high speed * freq = 20 MHz * Send CMD6 (CMD_SWITCH_FUNC) With args 0x03B90100 * Send CMD13 (CMD_SEND_STATUS) @@ -358,7 +358,7 @@ static int mmc_switch_to_high_frquency(struct mmc *mmc) uint64_t start_time; mmc->card.bus_freq = MMC_SS_20MHZ; - /* mmc card bellow ver 4.0 does not support high speed */ + /* mmc card below ver 4.0 does not support high speed */ if (mmc->card.version < MMC_CARD_VERSION_4_X) { return 0; } @@ -463,7 +463,7 @@ static int esdhc_set_data_attributes(struct mmc *mmc, uint32_t *dest_ptr, /*************************************************************************** * Function : esdhc_read_data_nodma * Arguments : mmc - Pointer to mmc struct - * dest_ptr - Bufffer where read data is to be copied + * dest_ptr - Buffer where read data is to be copied * len - Length of Data to be read * Return : SUCCESS or Error Code * Description : Read data from the sdhc buffer without using DMA @@ -698,7 +698,7 @@ static int esdhc_write_data_dma(struct mmc *mmc, uint32_t len) /*************************************************************************** * Function : esdhc_read_data * Arguments : mmc - Pointer to mmc struct - * dest_ptr - Bufffer where read data is to be copied + * dest_ptr - Buffer where read data is to be copied * len - Length of Data to be read * Return : SUCCESS or Error Code * Description : Calls esdhc_read_data_nodma and clear interrupt status diff --git a/drivers/renesas/common/console/rcar_printf.c b/drivers/renesas/common/console/rcar_printf.c index ad074fe05..6af10eeca 100644 --- a/drivers/renesas/common/console/rcar_printf.c +++ b/drivers/renesas/common/console/rcar_printf.c @@ -24,7 +24,7 @@ /* * The log is initialized and used before BL31 xlat tables are initialized, * therefore the log memory is a device memory at that point. Make sure the - * memory is correclty aligned and accessed only with up-to 32bit, aligned, + * memory is correctly aligned and accessed only with up-to 32bit, aligned, * writes. */ CASSERT((RCAR_BL31_LOG_BASE & 0x7) == 0, assert_bl31_log_base_unaligned); diff --git a/drivers/renesas/common/emmc/emmc_hal.h b/drivers/renesas/common/emmc/emmc_hal.h index 0a8551719..4e6942faf 100644 --- a/drivers/renesas/common/emmc/emmc_hal.h +++ b/drivers/renesas/common/emmc/emmc_hal.h @@ -512,7 +512,7 @@ typedef struct { /* maximum block count which can be transferred at once */ uint32_t max_block_count; - /* maximum clock frequence in Hz supported by HW */ + /* maximum clock frequency in Hz supported by HW */ uint32_t max_clock_freq; /* maximum data bus width supported by HW */ diff --git a/drivers/renesas/common/pfc_regs.h b/drivers/renesas/common/pfc_regs.h index 418773366..36084f550 100644 --- a/drivers/renesas/common/pfc_regs.h +++ b/drivers/renesas/common/pfc_regs.h @@ -146,10 +146,10 @@ #define GPIO_OUTDTL7 (GPIO_BASE + 0x5848U) #define GPIO_BOTHEDGE7 (GPIO_BASE + 0x584CU) -/* Pin functon base address */ +/* Pin function base address */ #define PFC_BASE (0xE6060000U) -/* Pin functon registers */ +/* Pin function registers */ #define PFC_PMMR (PFC_BASE + 0x0000U) #define PFC_GPSR0 (PFC_BASE + 0x0100U) #define PFC_GPSR1 (PFC_BASE + 0x0104U) diff --git a/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c b/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c index 606375807..5de4f1f65 100644 --- a/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c +++ b/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c @@ -12,7 +12,7 @@ #include "rcar_private.h" #include "../pfc_regs.h" -/* Pin functon bit */ +/* Pin function bit */ #define GPSR0_DU_EXODDF_DU_ODDF_DISP_CDE BIT(21) #define GPSR0_DU_EXVSYNC_DU_VSYNC BIT(20) #define GPSR0_DU_EXHSYNC_DU_HSYNC BIT(19) diff --git a/drivers/scmi-msg/clock.c b/drivers/scmi-msg/clock.c index 85bf7d24c..98fdc6a15 100644 --- a/drivers/scmi-msg/clock.c +++ b/drivers/scmi-msg/clock.c @@ -344,7 +344,7 @@ static void scmi_clock_describe_rates(struct scmi_msg *msg) scmi_status_response(msg, status); } else { /* - * Message payload is already writen to msg->out, and + * Message payload is already written to msg->out, and * msg->out_size_out updated. */ } diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c index aa5db6fc2..c9c3c5f9b 100644 --- a/drivers/st/clk/stm32mp1_clk.c +++ b/drivers/st/clk/stm32mp1_clk.c @@ -2049,7 +2049,7 @@ int stm32mp1_clk_init(void) stm32mp1_pll_start(i); } - /* Wait and start PLLs ouptut when ready */ + /* Wait and start PLLs output when ready */ for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { if (!pllcfg_valid[i]) { continue; diff --git a/drivers/st/crypto/stm32_pka.c b/drivers/st/crypto/stm32_pka.c index 2bbb31dc5..1e7c42c95 100644 --- a/drivers/st/crypto/stm32_pka.c +++ b/drivers/st/crypto/stm32_pka.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + * Copyright (c) 2022-2023, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,6 +19,11 @@ #include <platform_def.h> +#if !PKA_USE_NIST_P256 && !PKA_USE_BRAINPOOL_P256R1 && !PKA_USE_BRAINPOOL_P256T1 && \ + !PKA_USE_NIST_P521 +#error "At least one ECDSA curve needs to be selected" +#endif + /* * For our comprehension in this file * _len are in BITs @@ -690,7 +695,7 @@ int stm32_pka_ecdsa_verif(void *hash, unsigned int hash_size, mmio_setbits_32(base + _PKA_CLRFR, _PKA_IT_PROCEND); out: - /* Disable PKA (will stop all pending proccess and reset RAM) */ + /* Disable PKA (will stop all pending process and reset RAM) */ pka_disable(base); return ret; diff --git a/drivers/st/ddr/stm32mp1_ddr.c b/drivers/st/ddr/stm32mp1_ddr.c index 4719e1e68..27d8b2c00 100644 --- a/drivers/st/ddr/stm32mp1_ddr.c +++ b/drivers/st/ddr/stm32mp1_ddr.c @@ -755,7 +755,7 @@ void stm32mp1_ddr_init(struct stm32mp_ddr_priv *priv, stm32mp1_ddrphy_idone_wait(priv->phy); /* - * 12. set back registers in step 8 to the orginal values if desidered + * 12. set back registers in step 8 to the original values if desidered */ stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3, config->c_reg.pwrctl); diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h index 8678bf3d8..227f05862 100644 --- a/include/arch/aarch32/arch.h +++ b/include/arch/aarch32/arch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,8 +16,10 @@ #define MIDR_IMPL_SHIFT U(24) #define MIDR_VAR_SHIFT U(20) #define MIDR_VAR_BITS U(4) +#define MIDR_VAR_MASK U(0xf) #define MIDR_REV_SHIFT U(0) #define MIDR_REV_BITS U(4) +#define MIDR_REV_MASK U(0xf) #define MIDR_PN_MASK U(0xfff) #define MIDR_PN_SHIFT U(4) @@ -264,7 +266,7 @@ #define TCP10_BIT (U(1) << 10) #define HCPTR_RESET_VAL HCPTR_RES1 -/* VTTBR defintions */ +/* VTTBR definitions */ #define VTTBR_RESET_VAL ULL(0x0) #define VTTBR_VMID_MASK ULL(0xff) #define VTTBR_VMID_SHIFT U(48) diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index ac5eae249..003889346 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -393,6 +393,9 @@ #define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1) #define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0) +#define VDISR_EL2 S3_4_C12_C1_1 +#define VSESR_EL2 S3_4_C5_C2_3 + /* Memory Tagging Extension is not implemented */ #define MTE_UNIMPLEMENTED U(0) /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ @@ -752,7 +755,7 @@ #define HI_VECTOR_BASE U(0xFFFF0000) /* - * TCR defintions + * TCR definitions */ #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h index a0141defa..d6f12f3f2 100644 --- a/include/arch/aarch64/arch_features.h +++ b/include/arch/aarch64/arch_features.h @@ -499,14 +499,22 @@ static inline bool is_feat_sve_supported(void) return read_feat_sve_id_field() >= ID_AA64PFR0_SVE_SUPPORTED; } -/******************************************************************************* - * Function to identify the presence of FEAT_RAS (Reliability,Availability, - * and Serviceability Extension) - ******************************************************************************/ -static inline bool is_armv8_2_feat_ras_present(void) +static unsigned int read_feat_ras_id_field(void) +{ + return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_RAS); +} + +static inline bool is_feat_ras_supported(void) { - return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_RAS_SHIFT) & - ID_AA64PFR0_RAS_MASK) != ID_AA64PFR0_RAS_NOT_SUPPORTED); + if (ENABLE_FEAT_RAS == FEAT_STATE_DISABLED) { + return false; + } + + if (ENABLE_FEAT_RAS == FEAT_STATE_ALWAYS) { + return true; + } + + return read_feat_ras_id_field() != 0U; } static unsigned int read_feat_dit_id_field(void) diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h index 1b4bc1113..5b3d4c26f 100644 --- a/include/arch/aarch64/arch_helpers.h +++ b/include/arch/aarch64/arch_helpers.h @@ -549,6 +549,10 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(ttbr1_el2, TTBR1_EL2) /* Armv8.2 ID Registers */ DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1) +/* Armv8.2 RAS Registers */ +DEFINE_RENAME_SYSREG_RW_FUNCS(vdisr_el2, VDISR_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(vsesr_el2, VSESR_EL2) + /* Armv8.2 MPAM Registers */ DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3) diff --git a/include/bl31/ehf.h b/include/bl31/ehf.h index c13d28c35..63943a926 100644 --- a/include/bl31/ehf.h +++ b/include/bl31/ehf.h @@ -30,7 +30,7 @@ .ehf_handler = EHF_NO_HANDLER_, \ } -/* Macro for platforms to regiter its exception priorities */ +/* Macro for platforms to register its exception priorities */ #define EHF_REGISTER_PRIORITIES(priorities, num, bits) \ const ehf_priorities_t exception_data = { \ .num_priorities = (num), \ diff --git a/include/drivers/arm/cryptocell/712/cc_pal_types_plat.h b/include/drivers/arm/cryptocell/712/cc_pal_types_plat.h index 84100245b..f6d41d786 100644 --- a/include/drivers/arm/cryptocell/712/cc_pal_types_plat.h +++ b/include/drivers/arm/cryptocell/712/cc_pal_types_plat.h @@ -9,7 +9,7 @@ */ #ifndef _CC_PAL_TYPES_PLAT_H #define _CC_PAL_TYPES_PLAT_H -/* Host specific types for standard (ISO-C99) compilant platforms */ +/* Host specific types for standard (ISO-C99) compliant platforms */ #include <stddef.h> #include <stdint.h> diff --git a/include/drivers/arm/cryptocell/713/cc_pal_types_plat.h b/include/drivers/arm/cryptocell/713/cc_pal_types_plat.h index 984847217..0c102a092 100644 --- a/include/drivers/arm/cryptocell/713/cc_pal_types_plat.h +++ b/include/drivers/arm/cryptocell/713/cc_pal_types_plat.h @@ -9,7 +9,7 @@ */ #ifndef _CC_PAL_TYPES_PLAT_H #define _CC_PAL_TYPES_PLAT_H -/* Host specific types for standard (ISO-C99) compilant platforms */ +/* Host specific types for standard (ISO-C99) compliant platforms */ #include <stddef.h> #include <stdint.h> diff --git a/include/drivers/arm/gic600ae_fmu.h b/include/drivers/arm/gic600ae_fmu.h index 88b87b920..d2a92ddfd 100644 --- a/include/drivers/arm/gic600ae_fmu.h +++ b/include/drivers/arm/gic600ae_fmu.h @@ -85,7 +85,7 @@ #define FMU_BLK_PPI31 U(43) #define FMU_BLK_PRESENT_MASK U(0xFFFFFFFFFFF) -/* Safety Mechamism limit */ +/* Safety Mechanism limit */ #define FMU_SMID_GICD_MAX U(33) #define FMU_SMID_PPI_MAX U(12) #define FMU_SMID_ITS_MAX U(14) diff --git a/include/drivers/arm/sbsa.h b/include/drivers/arm/sbsa.h index 9403634f7..4ca71942e 100644 --- a/include/drivers/arm/sbsa.h +++ b/include/drivers/arm/sbsa.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,7 +9,12 @@ #include <stdint.h> -/* Register Offsets */ +/* SBSA Secure Watchdog Register Offsets */ +/* Refresh frame */ +#define SBSA_WDOG_WRR_OFFSET UL(0x000) +#define SBSA_WDOG_WRR_REFRESH UL(0x1) + +/* Control and status frame */ #define SBSA_WDOG_WCS_OFFSET UL(0x000) #define SBSA_WDOG_WOR_LOW_OFFSET UL(0x008) #define SBSA_WDOG_WOR_HIGH_OFFSET UL(0x00C) @@ -20,5 +25,6 @@ void sbsa_wdog_start(uintptr_t base, uint64_t ms); void sbsa_wdog_stop(uintptr_t base); +void sbsa_wdog_refresh(uintptr_t refresh_base); #endif /* SBSA_H */ diff --git a/include/drivers/auth/crypto_mod.h b/include/drivers/auth/crypto_mod.h index 00ea8c620..bec19da2c 100644 --- a/include/drivers/auth/crypto_mod.h +++ b/include/drivers/auth/crypto_mod.h @@ -46,7 +46,7 @@ typedef struct crypto_lib_desc_s { const char *name; /* Initialize library. This function is not expected to fail. All errors - * must be handled inside the function, asserting or panicing in case of + * must be handled inside the function, asserting or panicking in case of * a non-recoverable error */ void (*init)(void); diff --git a/include/drivers/brcm/emmc/emmc_csl_sdprot.h b/include/drivers/brcm/emmc/emmc_csl_sdprot.h index 597e1e087..580194034 100644 --- a/include/drivers/brcm/emmc/emmc_csl_sdprot.h +++ b/include/drivers/brcm/emmc/emmc_csl_sdprot.h @@ -139,7 +139,7 @@ * The Common I/O area shall be implemented on all SDIO cards and * is accessed the the host via I/O reads and writes to function 0, * the registers within the CIA are provided to enable/disable - * the operationo fthe i/o funciton. + * the operationo fthe i/o function. */ /* cccr_sdio_rev */ @@ -303,7 +303,7 @@ #define SBSDIO_CIS_BASE_COMMON 0x1000 /* function 0(common) cis size in bytes */ #define SBSDIO_CIS_FUNC0_LIMIT 0x020 -/* funciton 1 cis size in bytes */ +/* function 1 cis size in bytes */ #define SBSDIO_CIS_SIZE_LIMIT 0x200 /* cis offset addr is < 17 bits */ #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF @@ -313,7 +313,7 @@ /* indirect cis access (in sprom) */ /* 8 control bytes first, CIS starts from 8th uint8_t */ #define SBSDIO_SPROM_CIS_OFFSET 0x8 -/* sdio uint8_t mode: maximum length of one data comamnd */ +/* sdio uint8_t mode: maximum length of one data command */ #define SBSDIO_BYTEMODE_DATALEN_MAX 64 /* 4317 supports less */ #define SBSDIO_BYTEMODE_DATALEN_MAX_4317 52 diff --git a/include/drivers/brcm/i2c/i2c.h b/include/drivers/brcm/i2c/i2c.h index 24d42e208..2cc81d5b3 100644 --- a/include/drivers/brcm/i2c/i2c.h +++ b/include/drivers/brcm/i2c/i2c.h @@ -78,7 +78,7 @@ uint32_t i2c_get_bus_speed(uint32_t bus_id); * * Description: * This function reads I2C data from a device without specifying - * a command regsiter. + * a command register. * * Parameters: * bus_id - I2C bus ID @@ -95,7 +95,7 @@ int i2c_recv_byte(uint32_t bus_id, uint8_t devaddr, uint8_t *value); * * Description: * This function send I2C data to a device without specifying - * a command regsiter. + * a command register. * * Parameters: * bus_id - I2C bus ID diff --git a/include/drivers/io/io_dummy.h b/include/drivers/io/io_dummy.h deleted file mode 100644 index edfc6993e..000000000 --- a/include/drivers/io/io_dummy.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef IO_DUMMY_H -#define IO_DUMMY_H - -int register_io_dev_dummy(const struct io_dev_connector **dev_con); - -#endif /* IO_DUMMY_H */ diff --git a/include/drivers/io/io_storage.h b/include/drivers/io/io_storage.h index 8f30ed050..31793832d 100644 --- a/include/drivers/io/io_storage.h +++ b/include/drivers/io/io_storage.h @@ -19,7 +19,6 @@ typedef enum { IO_TYPE_INVALID, IO_TYPE_SEMIHOSTING, IO_TYPE_MEMMAP, - IO_TYPE_DUMMY, IO_TYPE_FIRMWARE_IMAGE_PACKAGE, IO_TYPE_BLOCK, IO_TYPE_MTD, diff --git a/include/drivers/nxp/crypto/caam/sec_hw_specific.h b/include/drivers/nxp/crypto/caam/sec_hw_specific.h index 98007938e..bc11aca1e 100644 --- a/include/drivers/nxp/crypto/caam/sec_hw_specific.h +++ b/include/drivers/nxp/crypto/caam/sec_hw_specific.h @@ -221,7 +221,7 @@ typedef struct { /* Lists the possible states for a job ring. */ typedef enum sec_job_ring_state_e { SEC_JOB_RING_STATE_STARTED, /* Job ring is initialized */ - SEC_JOB_RING_STATE_RESET, /* Job ring reset is in progres */ + SEC_JOB_RING_STATE_RESET, /* Job ring reset is in progress */ } sec_job_ring_state_t; struct sec_job_ring_t { diff --git a/include/drivers/nxp/crypto/caam/sec_jr_driver.h b/include/drivers/nxp/crypto/caam/sec_jr_driver.h index 57e0fa0ee..a6570d8bf 100644 --- a/include/drivers/nxp/crypto/caam/sec_jr_driver.h +++ b/include/drivers/nxp/crypto/caam/sec_jr_driver.h @@ -57,7 +57,7 @@ typedef void (*user_callback) (uint32_t *desc, uint32_t status, /* * Structure encompassing a job descriptor which is to be processed * by SEC. User should also initialise this structure with the callback - * function pointer which will be called by driver after recieving proccessed + * function pointer which will be called by driver after receiving proccessed * descriptor from SEC. User data is also passed in this data structure which * will be sent as an argument to the user callback function. */ diff --git a/include/drivers/nxp/dcfg/dcfg_lsch2.h b/include/drivers/nxp/dcfg/dcfg_lsch2.h index 882ba5a33..bdef6deba 100644 --- a/include/drivers/nxp/dcfg/dcfg_lsch2.h +++ b/include/drivers/nxp/dcfg/dcfg_lsch2.h @@ -55,7 +55,7 @@ #define DISR5_DDRC1_MASK 0x1 #define DISR5_OCRAM_MASK 0x40 -/* DCFG regsiters bit masks */ +/* DCFG registers bit masks */ #define RCWSR0_SYS_PLL_RAT_SHIFT 25 #define RCWSR0_SYS_PLL_RAT_MASK 0x1f #define RCWSR0_MEM_PLL_RAT_SHIFT 16 diff --git a/include/drivers/st/stm32_pka.h b/include/drivers/st/stm32_pka.h index ad4690ae5..34b3f6b5f 100644 --- a/include/drivers/st/stm32_pka.h +++ b/include/drivers/st/stm32_pka.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + * Copyright (c) 2022-2023, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,24 +9,11 @@ #include <stdint.h> -#if !PKA_USE_NIST_P256 && !PKA_USE_BRAINPOOL_P256R1 && !PKA_USE_BRAINPOOL_P256T1 && \ - !PKA_USE_NIST_P521 -#error "At least one ECDSA curve needs to be selected" -#endif - enum stm32_pka_ecdsa_curve_id { -#if PKA_USE_NIST_P256 PKA_NIST_P256, -#endif -#if PKA_USE_BRAINPOOL_P256R1 PKA_BRAINPOOL_P256R1, -#endif -#if PKA_USE_BRAINPOOL_P256T1 PKA_BRAINPOOL_P256T1, -#endif -#if PKA_USE_NIST_P521 PKA_NIST_P521, -#endif }; struct stm32_pka_platdata { diff --git a/include/lib/cpus/aarch64/generic.h b/include/lib/cpus/aarch64/generic.h index 53df58761..dd71554d0 100644 --- a/include/lib/cpus/aarch64/generic.h +++ b/include/lib/cpus/aarch64/generic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserverd. + * Copyright (c) 2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h index dd2b83681..e6af43e58 100644 --- a/include/lib/el3_runtime/aarch64/context.h +++ b/include/lib/el3_runtime/aarch64/context.h @@ -523,10 +523,6 @@ void el2_sysregs_context_restore_common(el2_sysregs_t *regs); void el2_sysregs_context_save_mte(el2_sysregs_t *regs); void el2_sysregs_context_restore_mte(el2_sysregs_t *regs); #endif /* CTX_INCLUDE_MTE_REGS */ -#if RAS_EXTENSION -void el2_sysregs_context_save_ras(el2_sysregs_t *regs); -void el2_sysregs_context_restore_ras(el2_sysregs_t *regs); -#endif /* RAS_EXTENSION */ #endif /* CTX_INCLUDE_EL2_REGS */ #if CTX_INCLUDE_FPREGS diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h index ffbd4ca13..e8461f5a2 100644 --- a/include/plat/arm/common/plat_arm.h +++ b/include/plat/arm/common/plat_arm.h @@ -364,6 +364,7 @@ extern const unsigned int arm_pm_idle_states[]; /* secure watchdog */ void plat_arm_secure_wdt_start(void); void plat_arm_secure_wdt_stop(void); +void plat_arm_secure_wdt_refresh(void); /* Get SOC-ID of ARM platform */ uint32_t plat_arm_get_soc_id(void); diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h index dde174c37..f87f857c5 100644 --- a/include/plat/arm/css/common/css_def.h +++ b/include/plat/arm/css/common/css_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -52,18 +52,21 @@ * terminology. On a GICv2 system or mode, the interrupts will be treated as * Group 0 interrupts. */ -#define CSS_G1S_IRQ_PROPS(grp) \ +#define CSS_G1S_INT_PROPS(grp) \ INTR_PROP_DESC(CSS_IRQ_MHU, GIC_HIGHEST_SEC_PRIORITY, grp, \ GIC_INTR_CFG_LEVEL), \ INTR_PROP_DESC(CSS_IRQ_GPU_SMMU_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ GIC_INTR_CFG_LEVEL), \ INTR_PROP_DESC(CSS_IRQ_TZC, GIC_HIGHEST_SEC_PRIORITY, grp, \ GIC_INTR_CFG_LEVEL), \ - INTR_PROP_DESC(CSS_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_LEVEL), \ INTR_PROP_DESC(CSS_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ GIC_INTR_CFG_LEVEL) +#define CSS_G1S_IRQ_PROPS(grp) \ + CSS_G1S_INT_PROPS(grp), \ + INTR_PROP_DESC(CSS_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL) + #if CSS_USE_SCMI_SDS_DRIVER /* Memory region for shared data storage */ #define PLAT_ARM_SDS_MEM_BASE ARM_SHARED_RAM_BASE diff --git a/include/services/errata_abi_svc.h b/include/services/errata_abi_svc.h new file mode 100644 index 000000000..12500661b --- /dev/null +++ b/include/services/errata_abi_svc.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef ERRATA_ABI_SVC_H +#define ERRATA_ABI_SVC_H + +#include <lib/smccc.h> + +#define ARM_EM_VERSION U(0x840000F0) +#define ARM_EM_FEATURES U(0x840000F1) +#define ARM_EM_CPU_ERRATUM_FEATURES U(0x840000F2) + +/* EM version numbers */ +#define EM_VERSION_MAJOR (0x1) +#define EM_VERSION_MINOR (0x0) + +/* EM CPU_ERRATUM_FEATURES return codes */ +#define EM_HIGHER_EL_MITIGATION (3) +#define EM_NOT_AFFECTED (2) +#define EM_AFFECTED (1) +#define EM_SUCCESS (0) +#define EM_NOT_SUPPORTED (-1) +#define EM_INVALID_PARAMETERS (-2) +#define EM_UNKNOWN_ERRATUM (-3) + +#if ERRATA_ABI_SUPPORT +bool is_errata_fid(uint32_t smc_fid); +#else +static inline bool is_errata_fid(uint32_t smc_fid) +{ + return false; +} +#endif /* ERRATA_ABI_SUPPORT */ +uintptr_t errata_abi_smc_handler( + uint32_t smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags +); +#endif /* ERRATA_ABI_SVC_H */ + diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 82a4890cf..e16c8e495 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -324,6 +324,11 @@ CPU_FLAG_LIST += ERRATA_A78_2376745 # to revisions r0p0, r1p0, r1p1, and r1p2 of the A78 cpu. It is still open. CPU_FLAG_LIST += ERRATA_A78_2395406 +# Flag to apply erratum 2712571 workaround for non-arm interconnect ip. This +# erratum applies to revisions r0p0, r1p0, r1p1, and r1p2 of the A78 cpu. +# It is fixed in r1p2. +CPU_FLAG_LIST += ERRATA_A78_2712571 + # Flag to apply erratum 2742426 workaround during reset. This erratum # applies to revisions r0p0, r1p0, r1p1 and r1p2 of the A78 cpu. It is still # open. @@ -362,6 +367,11 @@ CPU_FLAG_LIST += ERRATA_A78C_1827430 # to revision r0p0 of the A78C cpu. It is fixed in r0p1. CPU_FLAG_LIST += ERRATA_A78C_1827440 +# Flag to apply erratum 2712574 workaround for non-arm interconnect ip. This +# erratum applies to revisions r0p0, r0p1 and r0p2 of the A78 AE cpu. +# It is still open. +CPU_FLAG_LIST += ERRATA_A78_AE_2712574 + # Flag to apply erratum 2132064 workaround during reset. This erratum applies # to revisions r0p1 and r0p2 of the A78C cpu. It is still open. CPU_FLAG_LIST += ERRATA_A78C_2132064 @@ -378,6 +388,11 @@ CPU_FLAG_LIST += ERRATA_A78C_2376749 # to revisions r0p1 and r0p2 of the A78C cpu. It is still open. CPU_FLAG_LIST += ERRATA_A78C_2395411 +# Flag to apply erratum 2712575 workaround for non-arm interconnect ip. This +# erratum applies to revisions r0p1 and r0p2 of the A78C cpu. +# It is still open. +CPU_FLAG_LIST += ERRATA_A78C_2712575 + # Flag to apply erratum 2772121 workaround during powerdown. This erratum # applies to revisions r0p0, r0p1 and r0p2 of the A78C cpu. It is still open. CPU_FLAG_LIST += ERRATA_A78C_2772121 @@ -509,6 +524,11 @@ CPU_FLAG_LIST += ERRATA_V1_2294912 # to revisions r0p0, r1p0 and r1p1 of the Neoverse V1 cpu and is still open. CPU_FLAG_LIST += ERRATA_V1_2372203 +# Flag to apply erratum 2701953 workaround to non-arm interconnect ip. This +# erratum applies to revisions r0p0, r1p0, r1p1 of the Neoverse V1 cpu, +# it is fixed in r1p2. +CPU_FLAG_LIST += ERRATA_V1_2701953 + # Flag to apply erratum 2743093 workaround during powerdown. This erratum # applies to revisions r0p0, r1p0, r1p1 and r1p2 of the Neoverse V1 cpu and is # still open. @@ -581,6 +601,11 @@ CPU_FLAG_LIST += ERRATA_A710_2008768 # to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1. CPU_FLAG_LIST += ERRATA_A710_2371105 +# Flag to apply erratum 2701952 workaround for non-arm interconnect ip. This +# erratum applies to revision r0p0, r1p0, r2p0, r2p1 of the Cortex-A710 cpu +# and is still open. +CPU_FLAG_LIST += ERRATA_A710_2701952 + # Flag to apply erratum 2768515 workaround during power down. This erratum # applies to revision r0p0, r1p0, r2p0 and r2p1 of the Cortex-A710 cpu and is # still open. @@ -638,6 +663,11 @@ CPU_FLAG_LIST += ERRATA_N2_2376738 # to revision r0p0 of the Neoverse N2 cpu, it is fixed in r0p1. CPU_FLAG_LIST += ERRATA_N2_2388450 +# Flag to apply erratum 2728475 workaround for non-arm interconnect ip. This +# erratum applies to r0p0, r0p1, r0p2 of the Neoverse N2 cpu, it is fixed in +# r0p3. +CPU_FLAG_LIST += ERRATA_N2_2728475 + # Flag to apply erratum 2743089 workaround during during powerdown. This erratum # applies to all revisions <= r0p2 of the Neoverse N2 cpu, it is fixed in r0p3. CPU_FLAG_LIST += ERRATA_N2_2743089 @@ -682,6 +712,11 @@ CPU_FLAG_LIST += ERRATA_X2_2282622 # to revision r0p0, r1p0 and r2p0 of the Cortex-X2 cpu and is fixed in r2p1. CPU_FLAG_LIST += ERRATA_X2_2371105 +# Flag to apply erratum 2701952 workaround for non-arm interconnect ip. This +# erratum applies to revisions r0p0, r1p0, r2p0, r2p1 of the Cortex-x2 cpu +# and is still open. +CPU_FLAG_LIST += ERRATA_X2_2701952 + # Flag to apply erratum 2768515 workaround during power down. This erratum # applies to revision r0p0, r1p0, r2p0 and r2p1 of the Cortex-X2 cpu and is # still open. @@ -743,6 +778,14 @@ CPU_FLAG_LIST += ERRATA_A510_2666669 # Cortex-A510 cpu and is fixed in r1p3. CPU_FLAG_LIST += ERRATA_A510_2684597 +# Flag to apply erratum 2719103 workaround for non-arm interconnect ip. This +# erratum applies to revisions r0p0, rop1. Fixed in r0p2. +CPU_FLAG_LIST += ERRATA_V2_2719103 + +# Flag to apply erratum 2701951 workaround for non-arm interconnect ip. +# This erratum applies to revisions r0p0, r1p0, and r1p1. Its is fixed in r1p2. +CPU_FLAG_LIST += ERRATA_A715_2701951 + # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0. # Applying the workaround results in higher DSU power consumption on idle. CPU_FLAG_LIST += ERRATA_DSU_798953 diff --git a/lib/debugfs/debugfs_smc.c b/lib/debugfs/debugfs_smc.c index 400c166d7..13ced3db1 100644 --- a/lib/debugfs/debugfs_smc.c +++ b/lib/debugfs/debugfs_smc.c @@ -54,7 +54,7 @@ static union debugfs_parms { } parms; /* debugfs_access_lock protects shared buffer and internal */ -/* FS functions from concurrent acccesses. */ +/* FS functions from concurrent accesses. */ static spinlock_t debugfs_access_lock; static bool debugfs_initialized; diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S index 456ed5113..9922fb147 100644 --- a/lib/el3_runtime/aarch64/context.S +++ b/lib/el3_runtime/aarch64/context.S @@ -17,10 +17,6 @@ .global el2_sysregs_context_save_mte .global el2_sysregs_context_restore_mte #endif /* CTX_INCLUDE_MTE_REGS */ -#if RAS_EXTENSION - .global el2_sysregs_context_save_ras - .global el2_sysregs_context_restore_ras -#endif /* RAS_EXTENSION */ #endif /* CTX_INCLUDE_EL2_REGS */ .global el1_sysregs_context_save @@ -210,30 +206,6 @@ func el2_sysregs_context_restore_mte endfunc el2_sysregs_context_restore_mte #endif /* CTX_INCLUDE_MTE_REGS */ -#if RAS_EXTENSION -func el2_sysregs_context_save_ras - /* - * VDISR_EL2 and VSESR_EL2 registers are saved only when - * FEAT_RAS is supported. - */ - mrs x11, vdisr_el2 - mrs x12, vsesr_el2 - stp x11, x12, [x0, #CTX_VDISR_EL2] - ret -endfunc el2_sysregs_context_save_ras - -func el2_sysregs_context_restore_ras - /* - * VDISR_EL2 and VSESR_EL2 registers are restored only when FEAT_RAS - * is supported. - */ - ldp x11, x12, [x0, #CTX_VDISR_EL2] - msr vdisr_el2, x11 - msr vsesr_el2, x12 - ret -endfunc el2_sysregs_context_restore_ras -#endif /* RAS_EXTENSION */ - #endif /* CTX_INCLUDE_EL2_REGS */ /* ------------------------------------------------------------------ @@ -796,7 +768,12 @@ sve_not_enabled: 1: #endif /* IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 */ -#if IMAGE_BL31 && RAS_EXTENSION +/* + * This is a hot path, so we don't want to do some actual FEAT_RAS runtime + * detection here. The "esb" is a cheaper variant, so using "dsb" in the + * ENABLE_FEAT_RAS==2 case is not ideal, but won't hurt. + */ +#if IMAGE_BL31 && ENABLE_FEAT_RAS == 1 /* ---------------------------------------------------------- * Issue Error Synchronization Barrier to synchronize SErrors * before exiting EL3. We're running with EAs unmasked, so @@ -807,7 +784,7 @@ sve_not_enabled: esb #else dsb sy -#endif /* IMAGE_BL31 && RAS_EXTENSION */ +#endif /* IMAGE_BL31 && ENABLE_FEAT_RAS */ /* ---------------------------------------------------------- * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index 744e4f910..3760b8f13 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -457,7 +457,7 @@ static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *e void __init cm_init(void) { /* - * The context management library has only global data to intialize, but + * The context management library has only global data to initialize, but * that will be done when the BSS is zeroed out. */ } @@ -1013,9 +1013,13 @@ void cm_el2_sysregs_context_save(uint32_t security_state) write_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2, read_ttbr1_el2()); } -#if RAS_EXTENSION - el2_sysregs_context_save_ras(el2_sysregs_ctx); -#endif + + if (is_feat_ras_supported()) { + write_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2, + read_vdisr_el2()); + write_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2, + read_vsesr_el2()); + } if (is_feat_nv2_supported()) { write_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2, @@ -1096,9 +1100,11 @@ void cm_el2_sysregs_context_restore(uint32_t security_state) write_contextidr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2)); write_ttbr1_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2)); } -#if RAS_EXTENSION - el2_sysregs_context_restore_ras(el2_sysregs_ctx); -#endif + + if (is_feat_ras_supported()) { + write_vdisr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2)); + write_vsesr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2)); + } if (is_feat_nv2_supported()) { write_vncr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2)); diff --git a/lib/optee/optee_utils.c b/lib/optee/optee_utils.c index 25272fc94..6641db9af 100644 --- a/lib/optee/optee_utils.c +++ b/lib/optee/optee_utils.c @@ -180,7 +180,7 @@ int parse_optee_header(entry_point_info_t *header_ep, /* * Update "pc" value which should comes from pager image. After the - * header image is parsed, it will be unuseful, and the actual + * header image is parsed, it will be useless, and the actual * execution image after BL31 is pager image. */ header_ep->pc = pager_image_info->image_base; diff --git a/lib/xlat_tables/aarch32/nonlpae_tables.c b/lib/xlat_tables/aarch32/nonlpae_tables.c index 5646f347c..f58240470 100644 --- a/lib/xlat_tables/aarch32/nonlpae_tables.c +++ b/lib/xlat_tables/aarch32/nonlpae_tables.c @@ -272,7 +272,7 @@ void mmap_add_region(unsigned long long base_pa, uintptr_t base_va, /* Make room for new region by moving other regions up by one place */ (void)memmove(mm + 1, mm, (uintptr_t)mm_last - (uintptr_t)mm); - /* Check we haven't lost the empty sentinal from the end of the array */ + /* Check we haven't lost the empty sentinel from the end of the array */ assert(mm_last->size == 0U); mm->base_pa = base_pa; diff --git a/lib/xlat_tables/xlat_tables_common.c b/lib/xlat_tables/xlat_tables_common.c index 71273cb97..e2c8370e2 100644 --- a/lib/xlat_tables/xlat_tables_common.c +++ b/lib/xlat_tables/xlat_tables_common.c @@ -161,7 +161,7 @@ void mmap_add_region(unsigned long long base_pa, uintptr_t base_va, /* Make room for new region by moving other regions up by one place */ (void)memmove(mm + 1, mm, (uintptr_t)mm_last - (uintptr_t)mm); - /* Check we haven't lost the empty sentinal from the end of the array */ + /* Check we haven't lost the empty sentinel from the end of the array */ assert(mm_last->size == 0U); mm->base_pa = base_pa; diff --git a/lib/xlat_tables_v2/xlat_tables_core.c b/lib/xlat_tables_v2/xlat_tables_core.c index de5718454..3a9c0588d 100644 --- a/lib/xlat_tables_v2/xlat_tables_core.c +++ b/lib/xlat_tables_v2/xlat_tables_core.c @@ -988,7 +988,7 @@ int mmap_add_dynamic_region_ctx(xlat_ctx_t *ctx, mmap_region_t *mm) (uintptr_t)mm_last - (uintptr_t)mm_cursor); /* - * Check we haven't lost the empty sentinal from the end of the array. + * Check we haven't lost the empty sentinel from the end of the array. * This shouldn't happen as we have checked in mmap_add_region_check * that there is free space. */ diff --git a/lib/xlat_tables_v2/xlat_tables_utils.c b/lib/xlat_tables_v2/xlat_tables_utils.c index 38a375edf..f3a53ccd3 100644 --- a/lib/xlat_tables_v2/xlat_tables_utils.c +++ b/lib/xlat_tables_v2/xlat_tables_utils.c @@ -585,7 +585,7 @@ int xlat_change_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va, base_va += PAGE_SIZE; } - /* Ensure that the last descriptor writen is seen by the system. */ + /* Ensure that the last descriptor written is seen by the system. */ dsbish(); return 0; diff --git a/make_helpers/arch_features.mk b/make_helpers/arch_features.mk index 01e3e096d..b799697fb 100644 --- a/make_helpers/arch_features.mk +++ b/make_helpers/arch_features.mk @@ -13,6 +13,11 @@ ENABLE_FEAT_PAN = 1 ENABLE_FEAT_VHE = 1 endif +# Enable the features which are mandatory from ARCH version 8.2 and upwards. +ifeq "8.2" "$(word 1, $(sort 8.2 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))" +ENABLE_FEAT_RAS = 1 +endif + # Enable the features which are mandatory from ARCH version 8.4 and upwards. ifeq "8.4" "$(word 1, $(sort 8.4 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))" ENABLE_FEAT_DIT = 1 diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk index 0c82a715a..3bce3a5c8 100644 --- a/make_helpers/build_macros.mk +++ b/make_helpers/build_macros.mk @@ -73,6 +73,7 @@ endef # Convenience function for verifying option has a boolean value # $(eval $(call assert_boolean,FOO)) will assert FOO is 0 or 1 define assert_boolean + $(if $($(1)),,$(error $(1) must not be empty)) $(if $(filter-out 0 1,$($1)),$(error $1 must be boolean)) endef @@ -104,6 +105,12 @@ define ld_option $(shell if $(LD) $(1) -v >/dev/null 2>&1; then echo $(1); fi ) endef +# Convenience function to check for a given compiler option. A call to +# $(call cc_option, --no-XYZ) will return --no-XYZ if supported by the compiler +define cc_option + $(shell if $(CC) $(1) -c -x c /dev/null -o /dev/null >/dev/null 2>&1; then echo $(1); fi ) +endef + # CREATE_SEQ is a recursive function to create sequence of numbers from 1 to # $(2) and assign the sequence to $(1) define CREATE_SEQ diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index e2a67f7ac..f9077eb9b 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk @@ -276,8 +276,9 @@ PSCI_EXTENDED_STATE_ID := 0 # Enable PSCI OS-initiated mode support PSCI_OS_INIT_MODE := 0 -# Enable RAS support -RAS_EXTENSION := 0 +# Enable RAS Support +ENABLE_FEAT_RAS := 0 +RAS_FFH_SUPPORT := 0 # By default, BL1 acts as the reset handler, not BL31 RESET_TO_BL31 := 0 @@ -291,6 +292,12 @@ SDEI_SUPPORT := 0 # True Random Number firmware Interface support TRNG_SUPPORT := 0 +# Check to see if Errata ABI is supported +ERRATA_ABI_SUPPORT := 0 + +# Check to enable Errata ABI for platforms with non-arm interconnect +ERRATA_NON_ARM_INTERCONNECT := 0 + # SMCCC PCI support SMC_PCI_SUPPORT := 0 diff --git a/plat/arm/board/a5ds/platform.mk b/plat/arm/board/a5ds/platform.mk index 4f873069a..6fcf080a1 100644 --- a/plat/arm/board/a5ds/platform.mk +++ b/plat/arm/board/a5ds/platform.mk @@ -100,6 +100,8 @@ NEED_BL32 := yes MULTI_CONSOLE_API := 1 +ARM_DISABLE_TRUSTED_WDOG := 1 + PLAT_BL_COMMON_SOURCES += lib/xlat_tables/aarch32/nonlpae_tables.c # Use translation tables library v1 when using Cortex-A5 diff --git a/plat/arm/board/fvp/aarch64/fvp_ras.c b/plat/arm/board/fvp/aarch64/fvp_ras.c index 759f6d0d8..f9b96341a 100644 --- a/plat/arm/board/fvp/aarch64/fvp_ras.c +++ b/plat/arm/board/fvp/aarch64/fvp_ras.c @@ -4,12 +4,63 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include <inttypes.h> +#include <stdint.h> + #include <lib/extensions/ras.h> +#include <services/sdei.h> + +#ifdef PLATFORM_TEST_RAS_FFH +static int injected_fault_handler(const struct err_record_info *info, + int probe_data, const struct err_handler_data *const data) +{ + uint64_t status; + int ret; + + /* + * The faulting error record is already selected by the SER probe + * function. + */ + status = read_erxstatus_el1(); + + ERROR("Fault reported by system error record %d on 0x%lx: status=0x%" PRIx64 "\n", + probe_data, read_mpidr_el1(), status); + ERROR(" exception reason=%u syndrome=0x%" PRIx64 "\n", data->ea_reason, + data->flags); + + /* Clear error */ + write_erxstatus_el1(status); + + ret = sdei_dispatch_event(5000); + if (ret < 0) { + ERROR("Can't dispatch event to SDEI\n"); + panic(); + } else { + INFO("SDEI event dispatched\n"); + } + + return 0; +} + +void plat_handle_uncontainable_ea(void) +{ + /* Do not change the string, CI expects it. Wait forever */ + INFO("Injected Uncontainable Error\n"); + while (true) { + wfe(); + } +} +#endif struct ras_interrupt fvp_ras_interrupts[] = { }; struct err_record_info fvp_err_records[] = { +#ifdef PLATFORM_TEST_RAS_FFH + /* Record for injected fault */ + ERR_RECORD_SYSREG_V1(0, 2, ras_err_ser_probe_sysreg, + injected_fault_handler, NULL), +#endif }; REGISTER_ERR_RECORD_INFO(fvp_err_records); diff --git a/plat/arm/board/fvp/fvp_cpu_errata.mk b/plat/arm/board/fvp/fvp_cpu_errata.mk new file mode 100644 index 000000000..944571dd5 --- /dev/null +++ b/plat/arm/board/fvp/fvp_cpu_errata.mk @@ -0,0 +1,61 @@ +# +# Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + + +#/* +# * TODO: below lines of code to be removed +# * after abi and framework are synchronized +# */ + +ifeq (${ERRATA_ABI_SUPPORT}, 1) +# enable the cpu macros for errata abi interface +ifeq (${ARCH}, aarch64) +ifeq (${HW_ASSISTED_COHERENCY}, 0) +CORTEX_A35_H_INC := 1 +CORTEX_A53_H_INC := 1 +CORTEX_A57_H_INC := 1 +CORTEX_A72_H_INC := 1 +CORTEX_A73_H_INC := 1 +$(eval $(call add_define, CORTEX_A35_H_INC)) +$(eval $(call add_define, CORTEX_A53_H_INC)) +$(eval $(call add_define, CORTEX_A57_H_INC)) +$(eval $(call add_define, CORTEX_A72_H_INC)) +$(eval $(call add_define, CORTEX_A73_H_INC)) +else +ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) +CORTEX_A76_H_INC := 1 +CORTEX_A77_H_INC := 1 +CORTEX_A78_H_INC := 1 +NEOVERSE_N1_H_INC := 1 +NEOVERSE_V1_H_INC := 1 +CORTEX_A78_AE_H_INC := 1 +CORTEX_A510_H_INC := 1 +CORTEX_A710_H_INC := 1 +CORTEX_A715_H_INC := 1 +CORTEX_A78C_H_INC := 1 +CORTEX_X2_H_INC := 1 +$(eval $(call add_define, CORTEX_A76_H_INC)) +$(eval $(call add_define, CORTEX_A77_H_INC)) +$(eval $(call add_define, CORTEX_A78_H_INC)) +$(eval $(call add_define, NEOVERSE_N1_H_INC)) +$(eval $(call add_define, NEOVERSE_V1_H_INC)) +$(eval $(call add_define, CORTEX_A78_AE_H_INC)) +$(eval $(call add_define, CORTEX_A510_H_INC)) +$(eval $(call add_define, CORTEX_A710_H_INC)) +$(eval $(call add_define, CORTEX_A715_H_INC)) +$(eval $(call add_define, CORTEX_A78C_H_INC)) +$(eval $(call add_define, CORTEX_X2_H_INC)) +endif +CORTEX_A55_H_INC := 1 +CORTEX_A75_H_INC := 1 +$(eval $(call add_define, CORTEX_A55_H_INC)) +$(eval $(call add_define, CORTEX_A75_H_INC)) +endif +else +CORTEX_A32_H_INC := 1 +$(eval $(call add_define, CORTEX_A32_H_INC)) +endif +endif diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index 79d7451ef..9e72ba08c 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -397,7 +397,17 @@ defined(IMAGE_BL2) && MEASURED_BOOT #define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT #define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT #else -#define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS + #if PLATFORM_TEST_RAS_FFH + #define PLAT_ARM_PRIVATE_SDEI_EVENTS \ + ARM_SDEI_PRIVATE_EVENTS, \ + SDEI_EXPLICIT_EVENT(5000, SDEI_MAPF_NORMAL), \ + SDEI_EXPLICIT_EVENT(5001, SDEI_MAPF_NORMAL), \ + SDEI_EXPLICIT_EVENT(5002, SDEI_MAPF_NORMAL), \ + SDEI_EXPLICIT_EVENT(5003, SDEI_MAPF_CRITICAL), \ + SDEI_EXPLICIT_EVENT(5004, SDEI_MAPF_CRITICAL) + #else + #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS + #endif #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS #endif diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index ea3f95486..0433b61d5 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -50,6 +50,7 @@ ifneq (${SPD}, tspd) ENABLE_FEAT_RNG := 2 ENABLE_FEAT_TWED := 2 ENABLE_FEAT_GCS := 2 + ENABLE_FEAT_RAS := 2 ifeq (${ARCH}, aarch64) ifneq (${SPD}, spmd) ifeq (${SPM_MM}, 0) @@ -387,7 +388,7 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ endif endif -ifeq (${RAS_EXTENSION},1) +ifeq (${RAS_FFH_SUPPORT},1) BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c endif @@ -505,6 +506,11 @@ endif PSCI_OS_INIT_MODE := 1 +ifeq (${SPD},spmd) +BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c +endif + +# Test specific macros, keep them at bottom of this file $(eval $(call add_define,PLATFORM_TEST_EA_FFH)) ifeq (${PLATFORM_TEST_EA_FFH}, 1) ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) @@ -513,6 +519,13 @@ ifeq (${PLATFORM_TEST_EA_FFH}, 1) BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c endif -ifeq (${SPD},spmd) -BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c +$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) +ifeq (${PLATFORM_TEST_RAS_FFH}, 1) + ifeq (${RAS_EXTENSION}, 0) + $(error "PLATFORM_TEST_RAS_FFH expects RAS_EXTENSION to be 1") + endif +endif + +ifeq (${ERRATA_ABI_SUPPORT}, 1) +include plat/arm/board/fvp/fvp_cpu_errata.mk endif diff --git a/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c b/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c index b961da939..705ec384c 100644 --- a/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c +++ b/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c @@ -84,7 +84,7 @@ void sp_min_plat_arch_setup(void) (void *)hw_config_info->config_addr); /* - * Preferrably we expect this address and size are page aligned, + * Preferably we expect this address and size are page aligned, * but if they are not then align it. */ hw_config_base_align = page_align(hw_config_info->config_addr, DOWN); diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h index eea1be6ba..59fff6e2a 100644 --- a/plat/arm/board/tc/include/platform_def.h +++ b/plat/arm/board/tc/include/platform_def.h @@ -212,8 +212,11 @@ #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) #define PLAT_ARM_DRAM2_END (PLAT_ARM_DRAM2_BASE + PLAT_ARM_DRAM2_SIZE - 1ULL) -#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) -#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) +#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_INT_PROPS(grp) +#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp), \ + INTR_PROP_DESC(SBSA_SECURE_WDOG_INTID, \ + GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL) #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ PLAT_SP_IMAGE_NS_BUF_SIZE) @@ -229,9 +232,11 @@ #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) -/*Secure Watchdog Constants */ -#define SBSA_SECURE_WDOG_BASE UL(0x2A480000) +/* Secure Watchdog Constants */ +#define SBSA_SECURE_WDOG_CONTROL_BASE UL(0x2A480000) +#define SBSA_SECURE_WDOG_REFRESH_BASE UL(0x2A490000) #define SBSA_SECURE_WDOG_TIMEOUT UL(100) +#define SBSA_SECURE_WDOG_INTID 86 #define PLAT_ARM_SCMI_CHANNEL_COUNT 1 diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk index 63a923795..98c2e0ed6 100644 --- a/plat/arm/board/tc/platform.mk +++ b/plat/arm/board/tc/platform.mk @@ -20,7 +20,9 @@ CSS_LOAD_SCP_IMAGES := 1 CSS_USE_SCMI_SDS_DRIVER := 1 -RAS_EXTENSION := 0 +ENABLE_FEAT_RAS := 1 + +RAS_FFH_SUPPORT := 0 SDEI_SUPPORT := 0 @@ -118,7 +120,8 @@ BL31_SOURCES += ${INTERCONNECT_SOURCES} \ lib/fconf/fconf_dyn_cfg_getter.c \ drivers/cfi/v2m/v2m_flash.c \ lib/utils/mem_region.c \ - plat/arm/common/arm_nor_psci_mem_protect.c + plat/arm/common/arm_nor_psci_mem_protect.c \ + drivers/arm/sbsa/sbsa.c BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} diff --git a/plat/arm/board/tc/tc_bl31_setup.c b/plat/arm/board/tc/tc_bl31_setup.c index 8ad1d3056..630324fb3 100644 --- a/plat/arm/board/tc/tc_bl31_setup.c +++ b/plat/arm/board/tc/tc_bl31_setup.c @@ -13,6 +13,7 @@ #include <common/debug.h> #include <drivers/arm/css/css_mhu_doorbell.h> #include <drivers/arm/css/scmi.h> +#include <drivers/arm/sbsa.h> #include <lib/fconf/fconf.h> #include <lib/fconf/fconf_dyn_cfg_getter.h> #include <plat/arm/common/plat_arm.h> @@ -81,3 +82,37 @@ void __init bl31_plat_arch_setup(void) fconf_populate("HW_CONFIG", hw_config_info->config_addr); } + +#if defined(SPD_spmd) && (SPMD_SPM_AT_SEL2 == 1) +void tc_bl31_plat_runtime_setup(void) +{ + arm_bl31_plat_runtime_setup(); + + /* Start secure watchdog timer. */ + plat_arm_secure_wdt_start(); +} + +void bl31_plat_runtime_setup(void) +{ + tc_bl31_plat_runtime_setup(); +} + +/* + * Platform handler for Group0 secure interrupt. + */ +int plat_spmd_handle_group0_interrupt(uint32_t intid) +{ + /* Trusted Watchdog timer is the only source of Group0 interrupt now. */ + if (intid == SBSA_SECURE_WDOG_INTID) { + INFO("Watchdog restarted\n"); + /* Refresh the timer. */ + plat_arm_secure_wdt_refresh(); + + /* Deactivate the corresponding interrupt. */ + plat_ic_end_of_interrupt(intid); + return 0; + } + + return -1; +} +#endif /*defined(SPD_spmd) && (SPMD_SPM_AT_SEL2 == 1)*/ diff --git a/plat/arm/board/tc/tc_plat.c b/plat/arm/board/tc/tc_plat.c index 228f2fab3..766bfb570 100644 --- a/plat/arm/board/tc/tc_plat.c +++ b/plat/arm/board/tc/tc_plat.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2023, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -147,10 +147,15 @@ int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) void plat_arm_secure_wdt_start(void) { - sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT); + sbsa_wdog_start(SBSA_SECURE_WDOG_CONTROL_BASE, SBSA_SECURE_WDOG_TIMEOUT); } void plat_arm_secure_wdt_stop(void) { - sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE); + sbsa_wdog_stop(SBSA_SECURE_WDOG_CONTROL_BASE); +} + +void plat_arm_secure_wdt_refresh(void) +{ + sbsa_wdog_refresh(SBSA_SECURE_WDOG_REFRESH_BASE); } diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c index 19efdd32e..cfd1aac08 100644 --- a/plat/arm/common/arm_bl31_setup.c +++ b/plat/arm/common/arm_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -43,6 +43,7 @@ CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows); #pragma weak bl31_platform_setup #pragma weak bl31_plat_arch_setup #pragma weak bl31_plat_get_next_image_ep_info +#pragma weak bl31_plat_runtime_setup #define MAP_BL31_TOTAL MAP_REGION_FLAT( \ BL31_START, \ @@ -294,7 +295,7 @@ void arm_bl31_platform_setup(void) /* Initialize power controller before setting up topology */ plat_arm_pwrc_setup(); -#if RAS_EXTENSION +#if RAS_FFH_SUPPORT ras_init(); #endif diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index fca6f4f95..647a9d932 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk @@ -386,7 +386,7 @@ endif endif # RAS sources -ifeq (${RAS_EXTENSION},1) +ifeq (${RAS_FFH_SUPPORT},1) BL31_SOURCES += lib/extensions/ras/std_err_record.c \ lib/extensions/ras/ras_common.c endif diff --git a/plat/arm/common/tsp/arm_tsp_setup.c b/plat/arm/common/tsp/arm_tsp_setup.c index a4da8c35e..df3488bf5 100644 --- a/plat/arm/common/tsp/arm_tsp_setup.c +++ b/plat/arm/common/tsp/arm_tsp_setup.c @@ -62,7 +62,7 @@ void tsp_platform_setup(void) /******************************************************************************* * Perform the very early platform specific architectural setup here. At the - * moment this is only intializes the MMU + * moment this is only initializes the MMU ******************************************************************************/ void tsp_plat_arch_setup(void) { diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h index c1fadc654..c6cf0e616 100644 --- a/plat/arm/css/sgi/include/sgi_base_platform_def.h +++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h @@ -206,7 +206,7 @@ #define PLAT_SP_PRI PLAT_RAS_PRI -#if SPM_MM && RAS_EXTENSION +#if SPM_MM && RAS_FFH_SUPPORT /* * CPER buffer memory of 128KB is reserved and it is placed adjacent to the * memory shared between EL3 and S-EL0. @@ -235,7 +235,7 @@ */ #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ PLAT_SP_IMAGE_NS_BUF_SIZE) -#endif /* SPM_MM && RAS_EXTENSION */ +#endif /* SPM_MM && RAS_FFH_SUPPORT */ /* Platform ID address */ #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) diff --git a/plat/arm/css/sgi/sgi-common.mk b/plat/arm/css/sgi/sgi-common.mk index 282a5f080..6d17bc22f 100644 --- a/plat/arm/css/sgi/sgi-common.mk +++ b/plat/arm/css/sgi/sgi-common.mk @@ -8,7 +8,9 @@ CSS_USE_SCMI_SDS_DRIVER := 1 CSS_ENT_BASE := plat/arm/css/sgi -RAS_EXTENSION := 0 +ENABLE_FEAT_RAS := 1 + +RAS_FFH_SUPPORT := 0 SDEI_SUPPORT := 0 @@ -52,7 +54,7 @@ BL31_SOURCES += ${INTERCONNECT_SOURCES} \ ${CSS_ENT_BASE}/sgi_bl31_setup.c \ ${CSS_ENT_BASE}/sgi_topology.c -ifeq (${RAS_EXTENSION},1) +ifeq (${RAS_FFH_SUPPORT},1) BL31_SOURCES += ${CSS_ENT_BASE}/sgi_ras.c endif diff --git a/plat/arm/css/sgi/sgi_bl31_setup.c b/plat/arm/css/sgi/sgi_bl31_setup.c index df2ce387a..9c8d16341 100644 --- a/plat/arm/css/sgi/sgi_bl31_setup.c +++ b/plat/arm/css/sgi/sgi_bl31_setup.c @@ -106,7 +106,7 @@ void sgi_bl31_common_platform_setup(void) { arm_bl31_platform_setup(); -#if RAS_EXTENSION +#if RAS_FFH_SUPPORT sgi_ras_intr_handler_setup(); #endif diff --git a/plat/arm/css/sgi/sgi_plat.c b/plat/arm/css/sgi/sgi_plat.c index b8ba49f7e..7f79d5409 100644 --- a/plat/arm/css/sgi/sgi_plat.c +++ b/plat/arm/css/sgi/sgi_plat.c @@ -93,7 +93,7 @@ const mmap_region_t plat_arm_secure_partition_mmap[] = { PLAT_ARM_SECURE_MAP_DEVICE, ARM_SP_IMAGE_MMAP, ARM_SP_IMAGE_NS_BUF_MMAP, -#if RAS_EXTENSION +#if RAS_FFH_SUPPORT CSS_SGI_SP_CPER_BUF_MMAP, #endif ARM_SP_IMAGE_RW_MMAP, diff --git a/plat/brcm/board/stingray/driver/swreg.c b/plat/brcm/board/stingray/driver/swreg.c index 2b7c53b53..a5b5b9f3a 100644 --- a/plat/brcm/board/stingray/driver/swreg.c +++ b/plat/brcm/board/stingray/driver/swreg.c @@ -296,7 +296,7 @@ failed: return ret; } -/* Update SWREG firmware for all power doman for A2 chip */ +/* Update SWREG firmware for all power domain for A2 chip */ int swreg_firmware_update(void) { enum sw_reg reg_id; diff --git a/plat/common/aarch64/plat_common.c b/plat/common/aarch64/plat_common.c index 042916a7d..eca81b11f 100644 --- a/plat/common/aarch64/plat_common.c +++ b/plat/common/aarch64/plat_common.c @@ -11,7 +11,7 @@ #include <arch_helpers.h> #include <common/debug.h> #include <drivers/console.h> -#if RAS_EXTENSION +#if RAS_FFH_SUPPORT #include <lib/extensions/ras.h> #endif #include <lib/xlat_tables/xlat_mmu_helpers.h> @@ -81,7 +81,7 @@ const char *get_el_str(unsigned int el) void plat_default_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie, void *handle, uint64_t flags) { -#if RAS_EXTENSION +#if RAS_FFH_SUPPORT /* Call RAS EA handler */ int handled = ras_ea_handler(ea_reason, syndrome, cookie, handle, flags); if (handled != 0) diff --git a/plat/common/aarch64/plat_ehf.c b/plat/common/aarch64/plat_ehf.c index da768843e..4ec69b1b0 100644 --- a/plat/common/aarch64/plat_ehf.c +++ b/plat/common/aarch64/plat_ehf.c @@ -12,7 +12,7 @@ * Enumeration of priority levels on ARM platforms. */ ehf_pri_desc_t plat_exceptions[] = { -#if RAS_EXTENSION +#if RAS_FFH_SUPPORT /* RAS Priority */ EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_RAS_PRI), #endif @@ -27,7 +27,7 @@ ehf_pri_desc_t plat_exceptions[] = { #if SPM_MM EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SP_PRI), #endif - /* Plaform specific exceptions description */ + /* Platform specific exceptions description */ #ifdef PLAT_EHF_DESC PLAT_EHF_DESC, #endif diff --git a/plat/imx/common/include/sci/sci_rpc.h b/plat/imx/common/include/sci/sci_rpc.h index 60dbc27b6..b6adf3308 100644 --- a/plat/imx/common/include/sci/sci_rpc.h +++ b/plat/imx/common/include/sci/sci_rpc.h @@ -100,7 +100,7 @@ typedef struct sc_rpc_async_msg_s { void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, bool no_resp); /*! - * This is an internal function to dispath an RPC call that has + * This is an internal function to dispatch an RPC call that has * arrived via IPC over an MU. It is called by server-side SCFW. * * @param[in] mu MU message arrived on diff --git a/plat/imx/common/include/sci/svc/pad/sci_pad_api.h b/plat/imx/common/include/sci/svc/pad/sci_pad_api.h index dc23eedb3..ac93aae3f 100644 --- a/plat/imx/common/include/sci/svc/pad/sci_pad_api.h +++ b/plat/imx/common/include/sci/svc/pad/sci_pad_api.h @@ -42,7 +42,7 @@ * * Pads are managed as a resource by the Resource Manager (RM). They have * assigned owners and only the owners can configure the pads. Some of the - * pads are reserved for use by the SCFW itself and this can be overriden + * pads are reserved for use by the SCFW itself and this can be overridden * with the implementation of board_config_sc(). Additionally, pads may * be assigned to various other partitions via the implementation of * board_system_config(). @@ -156,7 +156,7 @@ typedef uint8_t sc_pad_config_t; * This type is used to declare a pad low-power isolation config. * ISO_LATE is the most common setting. ISO_EARLY is only used when * an output pad is directly determined by another input pad. The - * other two are only used when SW wants to directly contol isolation. + * other two are only used when SW wants to directly control isolation. */ typedef uint8_t sc_pad_iso_t; diff --git a/plat/imx/common/include/sci/svc/pm/sci_pm_api.h b/plat/imx/common/include/sci/svc/pm/sci_pm_api.h index 76ca5c4ea..13647956a 100644 --- a/plat/imx/common/include/sci/svc/pm/sci_pm_api.h +++ b/plat/imx/common/include/sci/svc/pm/sci_pm_api.h @@ -294,7 +294,7 @@ sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt, * Note some resources are still not accessible even when powered up if bus * transactions go through a fabric not powered up. Examples of this are * resources in display and capture subsystems which require the display - * controller or the imaging subsytem to be powered up first. + * controller or the imaging subsystem to be powered up first. * * Not that resources are grouped into power domains by the underlying * hardware. If any resource in the domain is on, the entire power domain diff --git a/plat/imx/imx8m/gpc_common.c b/plat/imx/imx8m/gpc_common.c index 32a35ef0b..71e0af1fd 100644 --- a/plat/imx/imx8m/gpc_common.c +++ b/plat/imx/imx8m/gpc_common.c @@ -98,7 +98,7 @@ void imx_set_cpu_lpm(unsigned int core_id, bool pdn) /* assert the pcg pcr bit of the core */ mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); } else { - /* disbale CORE WFI PDN & IRQ PUP */ + /* disable CORE WFI PDN & IRQ PUP */ mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | COREx_IRQ_WUP(core_id)); /* deassert the pcg pcr bit of the core */ diff --git a/plat/imx/imx8m/imx8mm/gpc.c b/plat/imx/imx8m/imx8mm/gpc.c index cc1cb1066..e0e38a9ae 100644 --- a/plat/imx/imx8m/imx8mm/gpc.c +++ b/plat/imx/imx8m/imx8mm/gpc.c @@ -376,7 +376,7 @@ void imx_gpc_init(void) /* * Set the CORE & SCU power up timing: * SW = 0x1, SW2ISO = 0x1; - * the CPU CORE and SCU power up timming counter + * the CPU CORE and SCU power up timing counter * is drived by 32K OSC, each domain's power up * latency is (SW + SW2ISO) / 32768 */ diff --git a/plat/imx/imx8m/imx8mn/gpc.c b/plat/imx/imx8m/imx8mn/gpc.c index 4e052972c..20c9a5561 100644 --- a/plat/imx/imx8m/imx8mn/gpc.c +++ b/plat/imx/imx8m/imx8mn/gpc.c @@ -170,7 +170,7 @@ void imx_gpc_init(void) /* * Set the CORE & SCU power up timing: * SW = 0x1, SW2ISO = 0x1; - * the CPU CORE and SCU power up timming counter + * the CPU CORE and SCU power up timing counter * is drived by 32K OSC, each domain's power up * latency is (SW + SW2ISO) / 32768 */ diff --git a/plat/imx/imx8m/imx8mp/gpc.c b/plat/imx/imx8m/imx8mp/gpc.c index 452e7883c..956b50817 100644 --- a/plat/imx/imx8m/imx8mp/gpc.c +++ b/plat/imx/imx8m/imx8mp/gpc.c @@ -337,7 +337,7 @@ void imx_gpc_init(void) /* * Set the CORE & SCU power up timing: * SW = 0x1, SW2ISO = 0x1; - * the CPU CORE and SCU power up timming counter + * the CPU CORE and SCU power up timing counter * is drived by 32K OSC, each domain's power up * latency is (SW + SW2ISO) / 32768 */ diff --git a/plat/imx/imx8m/imx8mq/gpc.c b/plat/imx/imx8m/imx8mq/gpc.c index 0a029d66c..ebf92f724 100644 --- a/plat/imx/imx8m/imx8mq/gpc.c +++ b/plat/imx/imx8m/imx8mq/gpc.c @@ -417,7 +417,7 @@ void imx_gpc_init(void) /* set all mix/PU in A53 domain */ mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xfffd); - /* set SCU timming */ + /* set SCU timing */ mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING, (0x59 << 10) | 0x5B | (0x2 << 20)); diff --git a/plat/intel/soc/agilex/bl31_plat_setup.c b/plat/intel/soc/agilex/bl31_plat_setup.c index 26ed7efc8..b4e19def9 100644 --- a/plat/intel/soc/agilex/bl31_plat_setup.c +++ b/plat/intel/soc/agilex/bl31_plat_setup.c @@ -155,7 +155,7 @@ const mmap_region_t plat_agilex_mmap[] = { /******************************************************************************* * Perform the very early platform specific architectural setup here. At the - * moment this is only intializes the mmu in a quick and dirty way. + * moment this is only initializes the mmu in a quick and dirty way. ******************************************************************************/ void bl31_plat_arch_setup(void) { diff --git a/plat/intel/soc/common/sip/socfpga_sip_fcs.c b/plat/intel/soc/common/sip/socfpga_sip_fcs.c index 508043ff7..d99026bcc 100644 --- a/plat/intel/soc/common/sip/socfpga_sip_fcs.c +++ b/plat/intel/soc/common/sip/socfpga_sip_fcs.c @@ -1804,7 +1804,7 @@ int intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize(uint32_t session_i /* * Source data must be 4 bytes aligned - * Source addrress must be 8 bytes aligned + * Source address must be 8 bytes aligned * User data must be 8 bytes aligned */ if ((dst_size == NULL) || (mbox_error == NULL) || diff --git a/plat/intel/soc/n5x/bl31_plat_setup.c b/plat/intel/soc/n5x/bl31_plat_setup.c index 5ca1a716e..a5337ceec 100644 --- a/plat/intel/soc/n5x/bl31_plat_setup.c +++ b/plat/intel/soc/n5x/bl31_plat_setup.c @@ -140,7 +140,7 @@ const mmap_region_t plat_dm_mmap[] = { /******************************************************************************* * Perform the very early platform specific architectural setup here. At the - * moment this is only intializes the mmu in a quick and dirty way. + * moment this is only initializes the mmu in a quick and dirty way. ******************************************************************************/ void bl31_plat_arch_setup(void) { diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c index be0fae563..ba00e8202 100644 --- a/plat/intel/soc/stratix10/bl31_plat_setup.c +++ b/plat/intel/soc/stratix10/bl31_plat_setup.c @@ -147,7 +147,7 @@ const mmap_region_t plat_stratix10_mmap[] = { /******************************************************************************* * Perform the very early platform specific architectural setup here. At the - * moment this is only intializes the mmu in a quick and dirty way. + * moment this is only initializes the mmu in a quick and dirty way. ******************************************************************************/ void bl31_plat_arch_setup(void) { diff --git a/plat/marvell/armada/a8k/common/plat_pm.c b/plat/marvell/armada/a8k/common/plat_pm.c index 9ea927608..f08f08a35 100644 --- a/plat/marvell/armada/a8k/common/plat_pm.c +++ b/plat/marvell/armada/a8k/common/plat_pm.c @@ -423,7 +423,7 @@ static int a8k_pwr_domain_on(u_register_t mpidr) } else #endif { - /* proprietary CPU ON exection flow */ + /* proprietary CPU ON execution flow */ plat_marvell_cpu_on(mpidr); } return 0; diff --git a/plat/marvell/armada/common/marvell_ddr_info.c b/plat/marvell/armada/common/marvell_ddr_info.c index 734099652..1ae0254b4 100644 --- a/plat/marvell/armada/common/marvell_ddr_info.c +++ b/plat/marvell/armada/common/marvell_ddr_info.c @@ -34,7 +34,7 @@ DRAM_AREA_LENGTH_MASK) >> DRAM_AREA_LENGTH_OFFS /* Mapping between DDR area length and real DDR size is specific and looks like - * bellow: + * below: * 0 => 384 MB * 1 => 768 MB * 2 => 1536 MB diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_bus26m.c b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_bus26m.c index 0b792ab1b..c8a2d4c37 100644 --- a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_bus26m.c +++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_bus26m.c @@ -53,6 +53,7 @@ static unsigned int bus26m_ext_opand2; static struct mt_irqremain *refer2remain_irq; static struct mt_spm_cond_tables cond_bus26m = { + .name = "bus26m", .table_cg = { 0xFF5DD002, /* MTCMOS1 */ 0x0000003C, /* MTCMOS2 */ @@ -175,7 +176,7 @@ bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id) (IS_PLAT_SUSPEND_ID(state_id) || (state_id == MT_PLAT_PWR_STATE_SYSTEM_BUS))); } -static int update_rc_condition(const void *val) +static int update_rc_condition(int state_id, const void *val) { const struct mt_spm_cond_tables *tlb = (const struct mt_spm_cond_tables *)val; const struct mt_spm_cond_tables *tlb_check = @@ -185,7 +186,7 @@ static int update_rc_condition(const void *val) return MT_RM_STATUS_BAD; } - status.is_cond_block = mt_spm_cond_check(tlb, tlb_check, + status.is_cond_block = mt_spm_cond_check(state_id, tlb, tlb_check, (status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ? &cond_bus26m_res : NULL); status.all_pll_dump = mt_spm_dump_all_pll(tlb, tlb_check, @@ -279,7 +280,7 @@ int spm_update_rc_bus26m(int state_id, int type, const void *val) switch (type) { case PLAT_RC_UPDATE_CONDITION: - res = update_rc_condition(val); + res = update_rc_condition(state_id, val); break; case PLAT_RC_UPDATE_REMAIN_IRQS: update_rc_remain_irqs(val); diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_dram.c b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_dram.c index d1a2435f6..82b38ade4 100644 --- a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_dram.c +++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_dram.c @@ -37,6 +37,7 @@ #define CONSTRAINT_DRAM_RESOURCE_REQ (MT_SPM_SYSPLL | MT_SPM_INFRA | MT_SPM_26M) static struct mt_spm_cond_tables cond_dram = { + .name = "dram", .table_cg = { 0xFF5DD002, /* MTCMOS1 */ 0x0000003C, /* MTCMOS2 */ @@ -104,7 +105,7 @@ bool spm_is_valid_rc_dram(unsigned int cpu, int state_id) (state_id == MT_PLAT_PWR_STATE_SYSTEM_BUS))); } -static int update_rc_condition(const void *val) +static int update_rc_condition(int state_id, const void *val) { const struct mt_spm_cond_tables *tlb = (const struct mt_spm_cond_tables *)val; const struct mt_spm_cond_tables *tlb_check = (const struct mt_spm_cond_tables *)&cond_dram; @@ -113,7 +114,7 @@ static int update_rc_condition(const void *val) return MT_RM_STATUS_BAD; } - status.is_cond_block = mt_spm_cond_check(tlb, tlb_check, + status.is_cond_block = mt_spm_cond_check(state_id, tlb, tlb_check, (status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ? &cond_dram_res : NULL); return MT_RM_STATUS_OK; @@ -185,7 +186,7 @@ int spm_update_rc_dram(int state_id, int type, const void *val) switch (type) { case PLAT_RC_UPDATE_CONDITION: - res = update_rc_condition(val); + res = update_rc_condition(state_id, val); break; case PLAT_RC_CLKBUF_STATUS: update_rc_clkbuf_status(val); diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_syspll.c b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_syspll.c index 700f50018..5359c7c1b 100644 --- a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_syspll.c +++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_syspll.c @@ -49,6 +49,7 @@ static unsigned int syspll_ext_opand2; static unsigned short ext_status_syspll; static struct mt_spm_cond_tables cond_syspll = { + .name = "syspll", .table_cg = { 0xFF5DD002, /* MTCMOS1 */ 0x0000003C, /* MTCMOS2 */ @@ -113,7 +114,7 @@ bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id) (state_id == MT_PLAT_PWR_STATE_SYSTEM_BUS))); } -static int update_rc_condition(const void *val) +static int update_rc_condition(int state_id, const void *val) { int res = MT_RM_STATUS_OK; @@ -126,7 +127,7 @@ static int update_rc_condition(const void *val) return MT_RM_STATUS_BAD; } - status.is_cond_block = mt_spm_cond_check(tlb, tlb_check, + status.is_cond_block = mt_spm_cond_check(state_id, tlb, tlb_check, (status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ? &cond_syspll_res : NULL); return res; @@ -228,7 +229,7 @@ int spm_update_rc_syspll(int state_id, int type, const void *val) switch (type) { case PLAT_RC_UPDATE_CONDITION: - res = update_rc_condition(val); + res = update_rc_condition(state_id, val); break; case PLAT_RC_CLKBUF_STATUS: update_rc_clkbuf_status(val); diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.c b/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.c index fe6e59828..bed55c906 100644 --- a/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.c +++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.c @@ -126,12 +126,14 @@ static struct idle_cond_info idle_cg_info[PLAT_SPM_COND_MAX] = { #define PLL_APLL4 MT_LP_TZ_APMIXEDSYS(0x404) #define PLL_APLL5 MT_LP_TZ_APMIXEDSYS(0x418) -unsigned int mt_spm_cond_check(const struct mt_spm_cond_tables *src, +unsigned int mt_spm_cond_check(int state_id, + const struct mt_spm_cond_tables *src, const struct mt_spm_cond_tables *dest, struct mt_spm_cond_tables *res) { unsigned int b_res = 0U; unsigned int i; + bool is_system_suspend = IS_PLAT_SUSPEND_ID(state_id); if ((src == NULL) || (dest == NULL)) { return SPM_COND_CHECK_FAIL; @@ -140,6 +142,11 @@ unsigned int mt_spm_cond_check(const struct mt_spm_cond_tables *src, for (i = 0; i < PLAT_SPM_COND_MAX; i++) { if (res != NULL) { res->table_cg[i] = (src->table_cg[i] & dest->table_cg[i]); + if (is_system_suspend && ((res->table_cg[i]) != 0U)) { + INFO("suspend: %s block[%u](0x%lx) = 0x%08x\n", + dest->name, i, idle_cg_info[i].addr, + res->table_cg[i]); + } if ((res->table_cg[i]) != 0U) { b_res |= BIT(i); @@ -161,6 +168,10 @@ unsigned int mt_spm_cond_check(const struct mt_spm_cond_tables *src, b_res |= SPM_COND_CHECK_BLOCKED_PLL; } + if (is_system_suspend && ((b_res) != 0U)) { + INFO("suspend: %s total blocked = 0x%08x\n", dest->name, b_res); + } + return b_res; } diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.h b/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.h index 793d5e81c..d93df57eb 100644 --- a/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.h +++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.h @@ -75,13 +75,15 @@ enum plat_spm_cond_pll { #define SPM_COND_CHECK_FAIL BIT(31) struct mt_spm_cond_tables { + char *name; unsigned int table_cg[PLAT_SPM_COND_MAX]; unsigned int table_pll; unsigned int table_all_pll; void *priv; }; -unsigned int mt_spm_cond_check(const struct mt_spm_cond_tables *src, +unsigned int mt_spm_cond_check(int state_id, + const struct mt_spm_cond_tables *src, const struct mt_spm_cond_tables *dest, struct mt_spm_cond_tables *res); unsigned int mt_spm_dump_all_pll(const struct mt_spm_cond_tables *src, diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_conservation.c b/plat/mediatek/drivers/spm/mt8188/mt_spm_conservation.c index bcb2df64b..395448a9f 100644 --- a/plat/mediatek/drivers/spm/mt8188/mt_spm_conservation.c +++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_conservation.c @@ -61,6 +61,14 @@ static int go_to_spm_before_wfi(int state_id, unsigned int ext_opand, __spm_send_cpu_wakeup_event(); + INFO("cpu%d: wakesrc = 0x%x, settle = 0x%x, sec = %u\n", + cpu, pwrctrl->wake_src, mmio_read_32(SPM_CLK_SETTLE), + (mmio_read_32(PCM_TIMER_VAL) / 32768)); + INFO("sw_flag = 0x%x 0x%x, req = 0x%x, pwr = 0x%x 0x%x\n", + pwrctrl->pcm_flags, pwrctrl->pcm_flags1, + mmio_read_32(SPM_SRC_REQ), mmio_read_32(PWR_STATUS), + mmio_read_32(PWR_STATUS_2ND)); + return ret; } diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.c b/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.c index b38a6d0a7..5eb16b35a 100644 --- a/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.c +++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.c @@ -24,6 +24,7 @@ wake_reason_t __spm_output_wake_reason(const struct wake_status *wakesta) { + uint32_t bk_vtcxo_dur, spm_26m_off_pct; wake_reason_t wr = WR_UNKNOWN; if (wakesta == NULL) { @@ -46,6 +47,33 @@ wake_reason_t __spm_output_wake_reason(const struct wake_status *wakesta) } } + INFO("r12 = 0x%x, r12_ext = 0x%x, r13 = 0x%x, debug_flag = 0x%x 0x%x\n", + wakesta->tr.comm.r12, wakesta->r12_ext, wakesta->tr.comm.r13, wakesta->tr.comm.debug_flag, + wakesta->tr.comm.debug_flag1); + INFO("raw_sta = 0x%x 0x%x 0x%x, idle_sta = 0x%x, cg_check_sta = 0x%x\n", + wakesta->tr.comm.raw_sta, wakesta->md32pcm_wakeup_sta, + wakesta->md32pcm_event_sta, wakesta->idle_sta, + wakesta->cg_check_sta); + INFO("req_sta = 0x%x 0x%x 0x%x 0x%x 0x%x, isr = 0x%x\n", + wakesta->tr.comm.req_sta0, wakesta->tr.comm.req_sta1, wakesta->tr.comm.req_sta2, + wakesta->tr.comm.req_sta3, wakesta->tr.comm.req_sta4, wakesta->isr); + INFO("rt_req_sta0 = 0x%x, rt_req_sta1 = 0x%x, rt_req_sta2 = 0x%x\n", + wakesta->rt_req_sta0, wakesta->rt_req_sta1, wakesta->rt_req_sta2); + INFO("rt_req_sta3 = 0x%x, dram_sw_con_3 = 0x%x, raw_ext_sta = 0x%x\n", + wakesta->rt_req_sta3, wakesta->rt_req_sta4, wakesta->raw_ext_sta); + INFO("wake_misc = 0x%x, pcm_flag = 0x%x 0x%x 0x%x 0x%x, req = 0x%x\n", + wakesta->wake_misc, wakesta->sw_flag0, wakesta->sw_flag1, + wakesta->tr.comm.b_sw_flag0, wakesta->tr.comm.b_sw_flag1, wakesta->src_req); + INFO("clk_settle = 0x%x, wlk_cntcv_l = 0x%x, wlk_cntcv_h = 0x%x\n", + wakesta->clk_settle, mmio_read_32(SYS_TIMER_VALUE_L), + mmio_read_32(SYS_TIMER_VALUE_H)); + + if (wakesta->tr.comm.timer_out != 0U) { + bk_vtcxo_dur = mmio_read_32(SPM_BK_VTCXO_DUR); + spm_26m_off_pct = (100 * bk_vtcxo_dur) / wakesta->tr.comm.timer_out; + INFO("spm_26m_off_pct = %u\n", spm_26m_off_pct); + } + return wr; } @@ -331,6 +359,18 @@ void __spm_get_wakeup_status(struct wake_status *wakesta, unsigned int ext_statu wakesta->tr.comm.b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7); /* SPM_SW_RSV_7 */ wakesta->tr.comm.b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8); /* SPM_SW_RSV_8 */ + /* record below spm info for debug */ + wakesta->src_req = mmio_read_32(SPM_SRC_REQ); + + /* get HW CG check status */ + wakesta->cg_check_sta = mmio_read_32(SPM_CG_CHECK_STA); + + wakesta->rt_req_sta0 = mmio_read_32(SPM_SW_RSV_2); + wakesta->rt_req_sta1 = mmio_read_32(SPM_SW_RSV_3); + wakesta->rt_req_sta2 = mmio_read_32(SPM_SW_RSV_4); + wakesta->rt_req_sta3 = mmio_read_32(SPM_SW_RSV_5); + wakesta->rt_req_sta4 = mmio_read_32(SPM_SW_RSV_6); + /* get ISR status */ wakesta->isr = mmio_read_32(SPM_IRQ_STA); @@ -338,6 +378,9 @@ void __spm_get_wakeup_status(struct wake_status *wakesta, unsigned int ext_statu wakesta->sw_flag0 = mmio_read_32(SPM_SW_FLAG_0); wakesta->sw_flag1 = mmio_read_32(SPM_SW_FLAG_1); + /* get CLK SETTLE */ + wakesta->clk_settle = mmio_read_32(SPM_CLK_SETTLE); + /* check abort */ wakesta->is_abort = wakesta->tr.comm.debug_flag & DEBUG_ABORT_MASK; wakesta->is_abort |= wakesta->tr.comm.debug_flag1 & DEBUG_ABORT_MASK_1; diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.h b/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.h index c719cafcb..5e3390f29 100644 --- a/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.h +++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.h @@ -628,11 +628,19 @@ struct wake_status { uint32_t md32pcm_event_sta; /* MD32PCM_EVENT_STA */ uint32_t wake_misc; /* SPM_SW_RSV_5 */ uint32_t idle_sta; /* SUBSYS_IDLE_STA */ + uint32_t cg_check_sta; /* SPM_CG_CHECK_STA */ uint32_t sw_flag0; /* SPM_SW_FLAG_0 */ uint32_t sw_flag1; /* SPM_SW_FLAG_1 */ uint32_t isr; /* SPM_IRQ_STA */ + uint32_t clk_settle; /* SPM_CLK_SETTLE */ + uint32_t src_req; /* SPM_SRC_REQ */ uint32_t log_index; uint32_t is_abort; + uint32_t rt_req_sta0; /* SPM_SW_RSV_2 */ + uint32_t rt_req_sta1; /* SPM_SW_RSV_3 */ + uint32_t rt_req_sta2; /* SPM_SW_RSV_4 */ + uint32_t rt_req_sta3; /* SPM_SW_RSV_5 */ + uint32_t rt_req_sta4; /* SPM_SW_RSV_6 */ }; struct spm_lp_scen { diff --git a/plat/mediatek/include/mtk_sip_svc.h b/plat/mediatek/include/mtk_sip_svc.h index f67791572..684f95108 100644 --- a/plat/mediatek/include/mtk_sip_svc.h +++ b/plat/mediatek/include/mtk_sip_svc.h @@ -97,7 +97,7 @@ struct smc_descriptor { }; /* - * This function should be implemented in MediaTek SOC directory. It fullfills + * This function should be implemented in MediaTek SOC directory. It fulfills * MTK_SIP_SET_AUTHORIZED_SECURE_REG SiP call by checking the sreg with the * predefined secure register list, if a match was found, set val to sreg. * diff --git a/plat/mediatek/mt8173/bl31_plat_setup.c b/plat/mediatek/mt8173/bl31_plat_setup.c index bd7d0b0ee..fd7874fd0 100644 --- a/plat/mediatek/mt8173/bl31_plat_setup.c +++ b/plat/mediatek/mt8173/bl31_plat_setup.c @@ -129,7 +129,7 @@ void bl31_platform_setup(void) /******************************************************************************* * Perform the very early platform specific architectural setup here. At the - * moment this is only intializes the mmu in a quick and dirty way. + * moment this is only initializes the mmu in a quick and dirty way. ******************************************************************************/ void bl31_plat_arch_setup(void) { diff --git a/plat/mediatek/mt8173/drivers/spm/spm.c b/plat/mediatek/mt8173/drivers/spm/spm.c index 8980e075e..0d3acb268 100644 --- a/plat/mediatek/mt8173/drivers/spm/spm.c +++ b/plat/mediatek/mt8173/drivers/spm/spm.c @@ -20,7 +20,7 @@ * - spm_suspend.c for system power control in system suspend scenario. * * This file provide utility functions common to hotplug, mcdi(idle), suspend - * power scenarios. A bakery lock (software lock) is incoporated to protect + * power scenarios. A bakery lock (software lock) is incorporated to protect * certain critical sections to avoid kicking different SPM firmware * concurrently. */ diff --git a/plat/mediatek/mt8183/bl31_plat_setup.c b/plat/mediatek/mt8183/bl31_plat_setup.c index 7dac8a49b..f608da3cf 100644 --- a/plat/mediatek/mt8183/bl31_plat_setup.c +++ b/plat/mediatek/mt8183/bl31_plat_setup.c @@ -163,7 +163,7 @@ void bl31_platform_setup(void) /******************************************************************************* * Perform the very early platform specific architectural setup here. At the - * moment this is only intializes the mmu in a quick and dirty way. + * moment this is only initializes the mmu in a quick and dirty way. ******************************************************************************/ void bl31_plat_arch_setup(void) { diff --git a/plat/mediatek/mt8186/bl31_plat_setup.c b/plat/mediatek/mt8186/bl31_plat_setup.c index 5fc6b6ea9..fb826befe 100644 --- a/plat/mediatek/mt8186/bl31_plat_setup.c +++ b/plat/mediatek/mt8186/bl31_plat_setup.c @@ -102,7 +102,7 @@ void bl31_platform_setup(void) /******************************************************************************* * Perform the very early platform specific architectural setup here. At the - * moment this is only intializes the mmu in a quick and dirty way. + * moment this is only initializes the mmu in a quick and dirty way. ******************************************************************************/ void bl31_plat_arch_setup(void) { diff --git a/plat/mediatek/mt8192/bl31_plat_setup.c b/plat/mediatek/mt8192/bl31_plat_setup.c index c3cb9a555..3b2302763 100644 --- a/plat/mediatek/mt8192/bl31_plat_setup.c +++ b/plat/mediatek/mt8192/bl31_plat_setup.c @@ -110,7 +110,7 @@ void bl31_platform_setup(void) /******************************************************************************* * Perform the very early platform specific architectural setup here. At the - * moment this is only intializes the mmu in a quick and dirty way. + * moment this is only initializes the mmu in a quick and dirty way. ******************************************************************************/ void bl31_plat_arch_setup(void) { diff --git a/plat/mediatek/mt8195/bl31_plat_setup.c b/plat/mediatek/mt8195/bl31_plat_setup.c index dff66709e..0f5674fd8 100644 --- a/plat/mediatek/mt8195/bl31_plat_setup.c +++ b/plat/mediatek/mt8195/bl31_plat_setup.c @@ -106,7 +106,7 @@ void bl31_platform_setup(void) /******************************************************************************* * Perform the very early platform specific architectural setup here. At the - * moment this is only intializes the mmu in a quick and dirty way. + * moment this is only initializes the mmu in a quick and dirty way. ******************************************************************************/ void bl31_plat_arch_setup(void) { diff --git a/plat/mediatek/mt8195/drivers/apusys/apupll.c b/plat/mediatek/mt8195/drivers/apusys/apupll.c index 0eb8d4a5c..3c18798c7 100644 --- a/plat/mediatek/mt8195/drivers/apusys/apupll.c +++ b/plat/mediatek/mt8195/drivers/apusys/apupll.c @@ -268,7 +268,7 @@ static int32_t _cal_pll_data(uint32_t *pd, uint32_t *dds, uint32_t freq) * @pll_idx: Which PLL to enable/disable * @on: 1 -> enable, 0 -> disable. * - * This funciton will only change RG_PLL_EN of CON1 for pll[pll_idx]. + * This function will only change RG_PLL_EN of CON1 for pll[pll_idx]. * * Context: Any context. */ @@ -286,7 +286,7 @@ static void _pll_en(uint32_t pll_idx, bool on) * @pll_idx: Which PLL to enable/disable * @on: 1 -> enable, 0 -> disable. * - * This funciton will only change PLL_SDM_PWR_ON of CON3 for pll[pll_idx]. + * This function will only change PLL_SDM_PWR_ON of CON3 for pll[pll_idx]. * * Context: Any context. */ @@ -304,7 +304,7 @@ static void _pll_pwr(uint32_t pll_idx, bool on) * @pll_idx: Which PLL to enable/disable * @enable: 1 -> turn on isolation, 0 -> turn off isolation. * - * This funciton will turn on/off pll isolation by + * This function will turn on/off pll isolation by * changing PLL_SDM_PWR_ON of CON3 for pll[pll_idx]. * * Context: Any context. @@ -324,7 +324,7 @@ static void _pll_iso(uint32_t pll_idx, bool enable) * @on: 1 -> enable, 0 -> disable. * @fhctl_en: enable or disable fhctl function * - * This is the entry poing for controlling pll and fhctl funciton on/off. + * This is the entry poing for controlling pll and fhctl function on/off. * Caller can chose only enable pll instead of fhctl function. * * Context: Any context. diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c index 050ef52d9..e3068b699 100644 --- a/plat/nvidia/tegra/common/tegra_bl31_setup.c +++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c @@ -262,7 +262,7 @@ void bl31_plat_runtime_setup(void) /******************************************************************************* * Perform the very early platform specific architectural setup here. At the - * moment this only intializes the mmu in a quick and dirty way. + * moment this only initializes the mmu in a quick and dirty way. ******************************************************************************/ void bl31_plat_arch_setup(void) { diff --git a/plat/nvidia/tegra/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/drivers/memctrl/memctrl_v2.c index 92120b527..0644fd203 100644 --- a/plat/nvidia/tegra/drivers/memctrl/memctrl_v2.c +++ b/plat/nvidia/tegra/drivers/memctrl/memctrl_v2.c @@ -301,7 +301,7 @@ void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes) if (video_mem_base != 0U) { /* * Lock the non overlapping memory being cleared so that - * other masters do not accidently write to it. The memory + * other masters do not accidentally write to it. The memory * would be unlocked once the non overlapping region is * cleared and the new memory settings take effect. */ diff --git a/plat/nvidia/tegra/include/drivers/tegra_gic.h b/plat/nvidia/tegra/include/drivers/tegra_gic.h index 6661dff76..9f9477c0f 100644 --- a/plat/nvidia/tegra/include/drivers/tegra_gic.h +++ b/plat/nvidia/tegra/include/drivers/tegra_gic.h @@ -19,7 +19,7 @@ typedef struct pcpu_fiq_state { } pcpu_fiq_state_t; /******************************************************************************* - * Fucntion declarations + * Function declarations ******************************************************************************/ void tegra_gic_cpuif_deactivate(void); void tegra_gic_init(void); diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h index a971cec93..cf8778b26 100644 --- a/plat/nvidia/tegra/include/t186/tegra_def.h +++ b/plat/nvidia/tegra/include/t186/tegra_def.h @@ -84,7 +84,7 @@ #define TEGRA_CLK_SE TEGRA186_CLK_SE /******************************************************************************* - * Tegra Miscellanous register constants + * Tegra Miscellaneous register constants ******************************************************************************/ #define TEGRA_MISC_BASE U(0x00100000) #define HARDWARE_REVISION_OFFSET U(0x4) diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index abe193fcd..2158913be 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -60,7 +60,7 @@ #define TEGRA_CLK_SE TEGRA194_CLK_SE /******************************************************************************* - * Tegra Miscellanous register constants + * Tegra Miscellaneous register constants ******************************************************************************/ #define TEGRA_MISC_BASE U(0x00100000) diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h index 71bea0845..f93585d9d 100644 --- a/plat/nvidia/tegra/include/tegra_private.h +++ b/plat/nvidia/tegra/include/tegra_private.h @@ -154,7 +154,7 @@ int plat_sip_handler(uint32_t smc_fid, void *handle, uint64_t flags); -#if RAS_EXTENSION +#if RAS_FFH_SUPPORT void tegra194_ras_enable(void); void tegra194_ras_corrected_err_clear(uint64_t *cookie); #endif diff --git a/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h b/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h index ecfb3f4b3..45302da1b 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h +++ b/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h @@ -40,7 +40,7 @@ typedef enum { /* index 83 is deprecated */ TEGRA_ARI_PERFMON = 84U, TEGRA_ARI_UPDATE_CCPLEX_GSC = 85U, - /* index 86 is depracated */ + /* index 86 is deprecated */ /* index 87 is deprecated */ TEGRA_ARI_ROC_FLUSH_CACHE_ONLY = 88U, TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS = 89U, diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h index 7a68a4303..ca74d2cf9 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h @@ -17,7 +17,7 @@ /** * Current version - Major version increments may break backwards - * compatiblity and binary compatibility. Minor version increments + * compatibility and binary compatibility. Minor version increments * occur when there is only new functionality. */ enum { diff --git a/plat/nvidia/tegra/soc/t194/plat_ras.c b/plat/nvidia/tegra/soc/t194/plat_ras.c index a9fed0ac7..2f438c3c0 100644 --- a/plat/nvidia/tegra/soc/t194/plat_ras.c +++ b/plat/nvidia/tegra/soc/t194/plat_ras.c @@ -284,7 +284,7 @@ static int32_t tegra194_ras_node_handler(uint32_t errselr, const char *name, ERROR("RAS Error in %s, ERRSELR_EL1=0x%x:\n", name, errselr); ERROR("\tStatus = 0x%" PRIx64 "\n", status); - /* Print uncorrectable errror information. */ + /* Print uncorrectable error information. */ if (ERR_STATUS_GET_FIELD(status, UE) != 0U) { ERR_STATUS_SET_FIELD(val, UE, 1); @@ -484,7 +484,7 @@ REGISTER_RAS_INTERRUPTS(carmel_ras_interrupts); void plat_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie, void *handle, uint64_t flags) { -#if RAS_EXTENSION +#if RAS_FFH_SUPPORT tegra194_ea_handler(ea_reason, syndrome, cookie, handle, flags); #else plat_default_ea_handler(ea_reason, syndrome, cookie, handle, flags); diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index 8f7d1e9a1..d3d09d3dc 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -254,7 +254,7 @@ void plat_early_platform_setup(void) /* sanity check MCE firmware compatibility */ mce_verify_firmware_version(); -#if RAS_EXTENSION +#if RAS_FFH_SUPPORT /* Enable Uncorrectable RAS error */ tegra194_ras_enable(); #endif diff --git a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c index 1eef55912..f0704edb1 100644 --- a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c +++ b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c @@ -71,7 +71,7 @@ int32_t plat_sip_handler(uint32_t smc_fid, break; -#if RAS_EXTENSION +#if RAS_FFH_SUPPORT case TEGRA_SIP_CLEAR_RAS_CORRECTED_ERRORS: { /* diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk index 631c92691..a183d0e9d 100644 --- a/plat/nvidia/tegra/soc/t194/platform_t194.mk +++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk @@ -34,7 +34,8 @@ $(eval $(call add_define,MAX_MMAP_REGIONS)) # enable RAS handling HANDLE_EA_EL3_FIRST_NS := 1 -RAS_EXTENSION := 1 +ENABLE_FEAT_RAS := 1 +RAS_FFH_SUPPORT := 1 # platform files PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t194 \ @@ -68,7 +69,7 @@ BL31_SOURCES += ${TEGRA_DRIVERS}/spe/shared_console.S endif # RAS sources -ifeq (${RAS_EXTENSION},1) +ifeq (${RAS_FFH_SUPPORT},1) BL31_SOURCES += lib/extensions/ras/std_err_record.c \ lib/extensions/ras/ras_common.c \ ${SOC_DIR}/plat_ras.c diff --git a/plat/nxp/common/setup/ls_bl31_setup.c b/plat/nxp/common/setup/ls_bl31_setup.c index bd0ab4fb7..3d0d804c7 100644 --- a/plat/nxp/common/setup/ls_bl31_setup.c +++ b/plat/nxp/common/setup/ls_bl31_setup.c @@ -174,7 +174,7 @@ void bl31_platform_setup(void) soc_platform_setup(); /* Console logs gone missing as part going to - * EL1 for initilizing Bl32 if present. + * EL1 for initializing Bl32 if present. * console flush is necessary to avoid it. */ (void)console_flush(); diff --git a/plat/nxp/soc-ls1088a/include/soc.h b/plat/nxp/soc-ls1088a/include/soc.h index eb36c2e13..793feee5d 100644 --- a/plat/nxp/soc-ls1088a/include/soc.h +++ b/plat/nxp/soc-ls1088a/include/soc.h @@ -112,7 +112,7 @@ #define IPSTPCR1_VALUE 0x000003FF #define IPSTPCR2_VALUE 0x00013006 -/* Dont' stop UART */ +/* Don't stop UART */ #define IPSTPCR3_VALUE 0x0000033A #define IPSTPCR4_VALUE 0x00103300 diff --git a/plat/qemu/qemu_sbsa/platform.mk b/plat/qemu/qemu_sbsa/platform.mk index 7b3129c3b..8b8d76be8 100644 --- a/plat/qemu/qemu_sbsa/platform.mk +++ b/plat/qemu/qemu_sbsa/platform.mk @@ -139,3 +139,6 @@ $(eval $(call add_define,ARM_PRELOADED_DTB_BASE)) # Later QEMU versions support SME and SVE. ENABLE_SVE_FOR_NS := 2 ENABLE_SME_FOR_NS := 2 + +# QEMU 7.2+ has support for FGT and Linux needs it enabled to boot on max +ENABLE_FEAT_FGT := 2 diff --git a/plat/qti/common/src/qti_bl31_setup.c b/plat/qti/common/src/qti_bl31_setup.c index dac025356..a5f58584d 100644 --- a/plat/qti/common/src/qti_bl31_setup.c +++ b/plat/qti/common/src/qti_bl31_setup.c @@ -81,7 +81,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, /******************************************************************************* * Perform the very early platform specific architectural setup here. At the - * moment this only intializes the mmu in a quick and dirty way. + * moment this only initializes the mmu in a quick and dirty way. ******************************************************************************/ void bl31_plat_arch_setup(void) { diff --git a/plat/qti/msm8916/aarch64/msm8916_helpers.S b/plat/qti/msm8916/aarch64/msm8916_helpers.S index dad9968ad..528c5a42e 100644 --- a/plat/qti/msm8916/aarch64/msm8916_helpers.S +++ b/plat/qti/msm8916/aarch64/msm8916_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net> + * Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net> * * SPDX-License-Identifier: BSD-3-Clause */ @@ -31,17 +31,6 @@ */ func plat_crash_console_init mov x1, #BLSP_UART2_BASE - - /* - * If the non-secure world has been actively using the UART there might - * be still some characters left to be sent in the FIFO. In that case, - * resetting the transmitter too early might cause all output to become - * corrupted. To avoid that, try to flush (wait until FIFO empty) first. - */ - mov x4, lr - bl console_uartdm_core_flush - mov lr, x4 - mov x0, #1 b console_uartdm_core_init endfunc plat_crash_console_init diff --git a/plat/qti/msm8916/aarch64/uartdm_console.S b/plat/qti/msm8916/aarch64/uartdm_console.S index c69c1932a..6c65daf04 100644 --- a/plat/qti/msm8916/aarch64/uartdm_console.S +++ b/plat/qti/msm8916/aarch64/uartdm_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net> + * Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net> * * Based on aarch64/skeleton_console.S: * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. @@ -65,7 +65,21 @@ endfunc console_uartdm_register * ----------------------------------------------------------- */ func console_uartdm_core_init - /* Reset receiver */ + /* + * Try to flush remaining characters from the TX FIFO before resetting + * the transmitter. Unfortunately there is no good way to check if + * the transmitter is actually enabled (and will finish eventually), + * so use a timeout to avoid looping forever. + */ + mov w2, #65536 +1: + ldr w3, [x1, #UART_DM_SR] + tbnz w3, #UART_DM_SR_TXEMT_BIT, 2f + subs w2, w2, #1 + b.ne 1b + /* Timeout */ + +2: /* Reset receiver */ mov w3, #UART_DM_CR_RESET_RX str w3, [x1, #UART_DM_CR] @@ -113,10 +127,21 @@ endfunc console_uartdm_putc * ----------------------------------------------------------- */ func console_uartdm_core_putc + cmp w0, #'\n' + b.ne 2f + 1: /* Loop until TX FIFO has space */ ldr w2, [x1, #UART_DM_SR] tbz w2, #UART_DM_SR_TXRDY_BIT, 1b + /* Prepend '\r' to '\n' */ + mov w2, #'\r' + str w2, [x1, #UART_DM_TF] + +2: /* Loop until TX FIFO has space */ + ldr w2, [x1, #UART_DM_SR] + tbz w2, #UART_DM_SR_TXRDY_BIT, 2b + /* Write character to FIFO */ str w0, [x1, #UART_DM_TF] ret diff --git a/plat/qti/msm8916/include/msm8916_mmap.h b/plat/qti/msm8916/include/msm8916_mmap.h index 406ae6b4e..d20153682 100644 --- a/plat/qti/msm8916/include/msm8916_mmap.h +++ b/plat/qti/msm8916/include/msm8916_mmap.h @@ -8,9 +8,9 @@ #define MSM8916_MMAP_H #define PCNOC_BASE 0x00000000 -#define PCNOC_SIZE 0x8000000 /* 128 MiB */ +#define PCNOC_SIZE SZ_128M #define APCS_BASE 0x0b000000 -#define APCS_SIZE 0x800000 /* 8 MiB */ +#define APCS_SIZE SZ_8M #define MPM_BASE (PCNOC_BASE + 0x04a0000) #define MPM_PS_HOLD (MPM_BASE + 0xb000) diff --git a/plat/qti/msm8916/include/platform_def.h b/plat/qti/msm8916/include/platform_def.h index bfade70a3..6d5ff2b33 100644 --- a/plat/qti/msm8916/include/platform_def.h +++ b/plat/qti/msm8916/include/platform_def.h @@ -16,11 +16,11 @@ * the overall limit to 128 KiB. This could be increased if needed by placing * the "msm8916_entry_point" variable explicitly in the first 64 KiB of BL31. */ -#define BL31_LIMIT (BL31_BASE + 0x20000) /* 128 KiB */ -#define BL31_PROGBITS_LIMIT (BL31_BASE + 0x10000) /* 64 KiB */ +#define BL31_LIMIT (BL31_BASE + SZ_128K) +#define BL31_PROGBITS_LIMIT (BL31_BASE + SZ_64K) #define CACHE_WRITEBACK_GRANULE U(64) -#define PLATFORM_STACK_SIZE U(0x1000) +#define PLATFORM_STACK_SIZE SZ_4K /* CPU topology: single cluster with 4 cores */ #define PLATFORM_CLUSTER_COUNT U(1) diff --git a/plat/qti/msm8916/msm8916_bl31_setup.c b/plat/qti/msm8916/msm8916_bl31_setup.c index 638cd09d0..8cba5c521 100644 --- a/plat/qti/msm8916/msm8916_bl31_setup.c +++ b/plat/qti/msm8916/msm8916_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net> + * Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net> * * SPDX-License-Identifier: BSD-3-Clause */ @@ -119,12 +119,8 @@ static void msm8916_configure_timer(void) /* Set timer frequency */ mmio_write_32(APCS_QTMR + CNTCTLBASE_CNTFRQ, plat_get_syscnt_freq2()); - /* Make frame 0 available to non-secure world */ - mmio_write_32(APCS_QTMR + CNTNSAR, BIT_32(CNTNSAR_NS_SHIFT(0))); - mmio_write_32(APCS_QTMR + CNTACR_BASE(0), - BIT_32(CNTACR_RPCT_SHIFT) | BIT_32(CNTACR_RVCT_SHIFT) | - BIT_32(CNTACR_RFRQ_SHIFT) | BIT_32(CNTACR_RVOFF_SHIFT) | - BIT_32(CNTACR_RWVT_SHIFT) | BIT_32(CNTACR_RWPT_SHIFT)); + /* Make all timer frames available to non-secure world */ + mmio_write_32(APCS_QTMR + CNTNSAR, GENMASK_32(7, 0)); } /* diff --git a/plat/qti/msm8916/msm8916_pm.c b/plat/qti/msm8916/msm8916_pm.c index 6891e3800..792a09688 100644 --- a/plat/qti/msm8916/msm8916_pm.c +++ b/plat/qti/msm8916/msm8916_pm.c @@ -1,10 +1,11 @@ /* - * Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net> + * Copyright (c) 2021-2022, Stephan Gerhold <stephan@gerhold.net> * * SPDX-License-Identifier: BSD-3-Clause */ #include <arch.h> +#include <arch_helpers.h> #include <common/debug.h> #include <drivers/arm/gicv2.h> #include <drivers/delay_timer.h> @@ -53,7 +54,14 @@ extern uintptr_t msm8916_entry_point; int plat_setup_psci_ops(uintptr_t sec_entrypoint, const plat_psci_ops_t **psci_ops) { + /* + * The entry point is read with caches off (and even from two different + * physical addresses when read through the "boot remapper"), so make + * sure it is flushed to memory. + */ msm8916_entry_point = sec_entrypoint; + flush_dcache_range((uintptr_t)&msm8916_entry_point, sizeof(uintptr_t)); + *psci_ops = &msm8916_psci_ops; return 0; } diff --git a/plat/qti/msm8916/platform.mk b/plat/qti/msm8916/platform.mk index 2baf2032a..107296b0a 100644 --- a/plat/qti/msm8916/platform.mk +++ b/plat/qti/msm8916/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net> +# Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net> # # SPDX-License-Identifier: BSD-3-Clause # @@ -46,6 +46,10 @@ WARMBOOT_ENABLE_DCACHE_EARLY := 1 ENABLE_SPE_FOR_NS := 0 ENABLE_SVE_FOR_NS := 0 +# Disable workarounds unnecessary for Cortex-A53 +WORKAROUND_CVE_2017_5715 := 0 +WORKAROUND_CVE_2022_23960 := 0 + # MSM8916 uses ARM Cortex-A53 r0p0 so likely all the errata apply ERRATA_A53_819472 := 1 ERRATA_A53_824069 := 1 diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c index f85db8d65..9ec4bcdf0 100644 --- a/plat/renesas/rcar/bl2_plat_setup.c +++ b/plat/renesas/rcar/bl2_plat_setup.c @@ -1190,7 +1190,7 @@ static void bl2_init_generic_timer(void) break; } #endif /* RCAR_LSI == RCAR_E3 */ - /* Update memory mapped and register based freqency */ + /* Update memory mapped and register based frequency */ write_cntfrq_el0((u_register_t )reg_cntfid); mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); /* Enable counter */ diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c index 98ef415c9..59db3d85c 100644 --- a/plat/rockchip/common/bl31_plat_setup.c +++ b/plat/rockchip/common/bl31_plat_setup.c @@ -87,7 +87,7 @@ void bl31_platform_setup(void) /******************************************************************************* * Perform the very early platform specific architectural setup here. At the - * moment this is only intializes the mmu in a quick and dirty way. + * moment this is only initializes the mmu in a quick and dirty way. ******************************************************************************/ void bl31_plat_arch_setup(void) { diff --git a/plat/rockchip/common/drivers/pmu/pmu_com.h b/plat/rockchip/common/drivers/pmu/pmu_com.h index 5359f73b4..022bb024a 100644 --- a/plat/rockchip/common/drivers/pmu/pmu_com.h +++ b/plat/rockchip/common/drivers/pmu/pmu_com.h @@ -90,7 +90,7 @@ static int check_cpu_wfie(uint32_t cpu_id, uint32_t wfie_msk) /* * wfe/wfi tracking not possible, hopefully the host - * was sucessful in enabling wfe/wfi. + * was successful in enabling wfe/wfi. * We'll give a bit of additional time, like the kernel does. */ if ((cluster_id && clstb_cpu_wfe < 0) || diff --git a/plat/rockchip/common/sp_min_plat_setup.c b/plat/rockchip/common/sp_min_plat_setup.c index 0237b167f..8fb3f8ef1 100644 --- a/plat/rockchip/common/sp_min_plat_setup.c +++ b/plat/rockchip/common/sp_min_plat_setup.c @@ -82,7 +82,7 @@ void sp_min_platform_setup(void) /******************************************************************************* * Perform the very early platform specific architectural setup here. At the - * moment this is only intializes the mmu in a quick and dirty way. + * moment this is only initializes the mmu in a quick and dirty way. ******************************************************************************/ void sp_min_plat_arch_setup(void) { diff --git a/plat/rockchip/rk3288/drivers/pmu/pmu.c b/plat/rockchip/rk3288/drivers/pmu/pmu.c index d6d709887..085976c16 100644 --- a/plat/rockchip/rk3288/drivers/pmu/pmu.c +++ b/plat/rockchip/rk3288/drivers/pmu/pmu.c @@ -288,7 +288,7 @@ int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint) /* * We communicate with the bootrom to active the cpus other * than cpu0, after a blob of initialize code, they will - * stay at wfe state, once they are actived, they will check + * stay at wfe state, once they are activated, they will check * the mailbox: * sram_base_addr + 4: 0xdeadbeaf * sram_base_addr + 8: start address for pc diff --git a/plat/rockchip/rk3288/drivers/soc/soc.c b/plat/rockchip/rk3288/drivers/soc/soc.c index 36f410b1a..2316fbebe 100644 --- a/plat/rockchip/rk3288/drivers/soc/soc.c +++ b/plat/rockchip/rk3288/drivers/soc/soc.c @@ -216,7 +216,7 @@ void __dead2 rockchip_soc_soft_reset(void) /* * Maybe the HW needs some times to reset the system, - * so we do not hope the core to excute valid codes. + * so we do not hope the core to execute valid codes. */ while (1) ; diff --git a/plat/rockchip/rk3328/drivers/pmu/pmu.c b/plat/rockchip/rk3328/drivers/pmu/pmu.c index a17fef9e1..597db978f 100644 --- a/plat/rockchip/rk3328/drivers/pmu/pmu.c +++ b/plat/rockchip/rk3328/drivers/pmu/pmu.c @@ -202,7 +202,7 @@ void __dead2 rockchip_soc_soft_reset(void) dsb(); /* * Maybe the HW needs some times to reset the system, - * so we do not hope the core to excute valid codes. + * so we do not hope the core to execute valid codes. */ while (1) ; @@ -210,7 +210,7 @@ void __dead2 rockchip_soc_soft_reset(void) /* * For PMIC RK805, its sleep pin is connect with gpio2_d2 from rk3328. - * If the PMIC is configed for responding the sleep pin to power off it, + * If the PMIC is configured for responding the sleep pin to power off it, * once the pin is output high, it will get the pmic power off. */ void __dead2 rockchip_soc_system_off(void) @@ -462,7 +462,7 @@ static __sramfunc void sram_udelay(uint32_t us) /* * For PMIC RK805, its sleep pin is connect with gpio2_d2 from rk3328. - * If the PMIC is configed for responding the sleep pin + * If the PMIC is configured for responding the sleep pin * to get it into sleep mode, * once the pin is output high, it will get the pmic into sleep mode. */ diff --git a/plat/rockchip/rk3328/drivers/soc/soc.h b/plat/rockchip/rk3328/drivers/soc/soc.h index e8cbc09f6..e081f7171 100644 --- a/plat/rockchip/rk3328/drivers/soc/soc.h +++ b/plat/rockchip/rk3328/drivers/soc/soc.h @@ -27,7 +27,7 @@ enum plls_id { DPLL_ID, CPLL_ID, GPLL_ID, - REVERVE, + RESERVE, NPLL_ID, MAX_PLL, }; diff --git a/plat/rockchip/rk3368/drivers/soc/soc.c b/plat/rockchip/rk3368/drivers/soc/soc.c index 7d51bb8e8..9bb237f80 100644 --- a/plat/rockchip/rk3368/drivers/soc/soc.c +++ b/plat/rockchip/rk3368/drivers/soc/soc.c @@ -202,7 +202,7 @@ void __dead2 rockchip_soc_soft_reset(void) /* * Maybe the HW needs some times to reset the system, - * so we do not hope the core to excute valid codes. + * so we do not hope the core to execute valid codes. */ while (1) ; diff --git a/plat/rockchip/rk3399/drivers/dram/dfs.c b/plat/rockchip/rk3399/drivers/dram/dfs.c index 816372bfc..11b0373a7 100644 --- a/plat/rockchip/rk3399/drivers/dram/dfs.c +++ b/plat/rockchip/rk3399/drivers/dram/dfs.c @@ -1696,7 +1696,7 @@ static int to_get_clk_index(unsigned int mhz) pll_cnt = ARRAY_SIZE(dpll_rates_table); - /* Assumming rate_table is in descending order */ + /* Assuming rate_table is in descending order */ for (i = 0; i < pll_cnt; i++) { if (mhz >= dpll_rates_table[i].mhz) break; diff --git a/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h b/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h index 9cda22ca9..102ba789f 100644 --- a/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h +++ b/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h @@ -103,7 +103,7 @@ struct dram_timing_t { uint32_t tcksre; uint32_t tcksrx; uint32_t tdpd; - /* mode regiter timing */ + /* mode register timing */ uint32_t tmod; uint32_t tmrd; uint32_t tmrr; diff --git a/plat/rockchip/rk3399/drivers/dram/suspend.c b/plat/rockchip/rk3399/drivers/dram/suspend.c index a8b1c32d5..caa784c79 100644 --- a/plat/rockchip/rk3399/drivers/dram/suspend.c +++ b/plat/rockchip/rk3399/drivers/dram/suspend.c @@ -561,7 +561,7 @@ static __pmusramfunc int dram_switch_to_next_index( ch_count = sdram_params->num_channels; - /* LPDDR4 f2 cann't do training, all training will fail */ + /* LPDDR4 f2 can't do training, all training will fail */ for (ch = 0; ch < ch_count; ch++) { /* * Without this disabled for LPDDR4 we end up writing 0's diff --git a/plat/rockchip/rk3399/drivers/gpio/rk3399_gpio.c b/plat/rockchip/rk3399/drivers/gpio/rk3399_gpio.c index 724968f39..96b4753f3 100644 --- a/plat/rockchip/rk3399/drivers/gpio/rk3399_gpio.c +++ b/plat/rockchip/rk3399/drivers/gpio/rk3399_gpio.c @@ -376,7 +376,7 @@ void plat_rockchip_restore_gpio(void) mmio_write_32(base + SWPORTA_DDR, save->swporta_ddr); mmio_write_32(base + INTEN, save->inten); mmio_write_32(base + INTMASK, save->intmask); - mmio_write_32(base + INTTYPE_LEVEL, save->inttype_level), + mmio_write_32(base + INTTYPE_LEVEL, save->inttype_level); mmio_write_32(base + INT_POLARITY, save->int_polarity); mmio_write_32(base + DEBOUNCE, save->debounce); mmio_write_32(base + LS_SYNC, save->ls_sync); diff --git a/plat/rockchip/rk3399/drivers/m0/src/suspend.c b/plat/rockchip/rk3399/drivers/m0/src/suspend.c index 9ad2fa26a..8a0ea32ab 100644 --- a/plat/rockchip/rk3399/drivers/m0/src/suspend.c +++ b/plat/rockchip/rk3399/drivers/m0/src/suspend.c @@ -30,7 +30,7 @@ __attribute__((noreturn)) void m0_main(void) } /* - * FSM power secquence is .. -> ST_INPUT_CLAMP(step.17) -> .. -> + * FSM power sequence is .. -> ST_INPUT_CLAMP(step.17) -> .. -> * ST_WAKEUP_RESET -> ST_EXT_PWRUP-> ST_RELEASE_CLAMP -> * ST_24M_OSC_EN -> .. -> ST_WAKEUP_RESET_CLR(step.26) -> .., * INPUT_CLAMP and WAKEUP_RESET will hold the SOC not affect by diff --git a/plat/rockchip/rk3399/drivers/secure/secure.h b/plat/rockchip/rk3399/drivers/secure/secure.h index e31c999b7..79997b2f6 100644 --- a/plat/rockchip/rk3399/drivers/secure/secure.h +++ b/plat/rockchip/rk3399/drivers/secure/secure.h @@ -32,7 +32,7 @@ /* security config pmu slave ip */ /* All of slaves is ns */ #define SGRF_PMU_SLV_S_NS BIT_WITH_WMSK(0) -/* slaves secure attr is configed */ +/* slaves secure attr is configured */ #define SGRF_PMU_SLV_S_CFGED WMSK_BIT(0) #define SGRF_PMU_SLV_CRYPTO1_NS WMSK_BIT(1) diff --git a/plat/rockchip/rk3399/drivers/soc/soc.c b/plat/rockchip/rk3399/drivers/soc/soc.c index 98b5ad646..e2b2934b0 100644 --- a/plat/rockchip/rk3399/drivers/soc/soc.c +++ b/plat/rockchip/rk3399/drivers/soc/soc.c @@ -343,7 +343,7 @@ void __dead2 soc_global_soft_reset(void) /* * Maybe the HW needs some times to reset the system, - * so we do not hope the core to excute valid codes. + * so we do not hope the core to execute valid codes. */ while (1) ; diff --git a/plat/rpi/rpi4/rpi4_pci_svc.c b/plat/rpi/rpi4/rpi4_pci_svc.c index 7d1ca5c6e..e4ef5c1ae 100644 --- a/plat/rpi/rpi4/rpi4_pci_svc.c +++ b/plat/rpi/rpi4/rpi4_pci_svc.c @@ -11,7 +11,7 @@ * it. Given that it's not ECAM compliant yet reasonably simple, it makes for * an excellent example of the PCI SMCCC interface. * - * The PCI SMCCC interface is described in DEN0115 availabe from: + * The PCI SMCCC interface is described in DEN0115 available from: * https://developer.arm.com/documentation/den0115/latest */ diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk index 1d93983a8..55423aebb 100644 --- a/plat/st/stm32mp1/platform.mk +++ b/plat/st/stm32mp1/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -73,6 +73,9 @@ $(error "DECRYPTION_SUPPORT not supported on STM32MP15") endif endif +PKA_USE_NIST_P256 ?= 0 +PKA_USE_BRAINPOOL_P256T1 ?= 0 + ifeq ($(AARCH32_SP),sp_min) # Disable Neon support: sp_min runtime may conflict with non-secure world TF_CFLAGS += -mfloat-abi=soft @@ -158,7 +161,6 @@ $(eval $(call assert_booleans,\ $(sort \ PKA_USE_BRAINPOOL_P256T1 \ PKA_USE_NIST_P256 \ - PLAT_TBBR_IMG_DEF \ STM32MP_CRYPTO_ROM_LIB \ STM32MP_DDR_32BIT_INTERFACE \ STM32MP_DDR_DUAL_AXI_PORT \ diff --git a/plat/st/stm32mp1/stm32mp1_pm.c b/plat/st/stm32mp1/stm32mp1_pm.c index 74393811c..8e1c1cf99 100644 --- a/plat/st/stm32mp1/stm32mp1_pm.c +++ b/plat/st/stm32mp1/stm32mp1_pm.c @@ -42,7 +42,7 @@ static void stm32_cpu_standby(plat_local_state_t cpu_state) while (interrupt == GIC_SPURIOUS_INTERRUPT) { wfi(); - /* Acknoledge IT */ + /* Acknowledge IT */ interrupt = gicv2_acknowledge_interrupt(); /* If Interrupt == 1022 it will be acknowledged by non secure */ if ((interrupt != PENDING_G1_INTID) && diff --git a/plat/xilinx/common/plat_startup.c b/plat/xilinx/common/plat_startup.c index 6a83e9e3f..539aba2a9 100644 --- a/plat/xilinx/common/plat_startup.c +++ b/plat/xilinx/common/plat_startup.c @@ -135,7 +135,7 @@ static int32_t get_fsbl_estate(const struct xfsbl_partition *partition) * @bl33: BL33 image info structure * atf_handoff_addr: ATF handoff address * - * Process the handoff paramters from the FSBL and populate the BL32 and BL33 + * Process the handoff parameters from the FSBL and populate the BL32 and BL33 * image info structures accordingly. * * Return: Return the status of the handoff. The value will be from the diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c index fb7b00924..85e146448 100644 --- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c +++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c @@ -635,7 +635,7 @@ enum pm_ret_status pm_get_chipid(uint32_t *value) * pm_secure_rsaaes() - Load the secure images. * * This function provides access to the xilsecure library to load - * the authenticated, encrypted, and authenicated/encrypted images. + * the authenticated, encrypted, and authenticated/encrypted images. * * address_low: lower 32-bit Linear memory space address * diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c index c0c5d1497..7b1544391 100644 --- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c +++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c @@ -99,7 +99,7 @@ static void trigger_wdt_restart(void) * for warm restart. * * In presence of non-secure software layers (EL1/2) sets the interrupt - * at registered entrance in GIC and informs that PMU responsed or demands + * at registered entrance in GIC and informs that PMU responded or demands * action. */ static uint64_t ttc_fiq_handler(uint32_t id, uint32_t flags, void *handle, diff --git a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c index b51369a02..eaecb899e 100644 --- a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c +++ b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c @@ -43,7 +43,7 @@ void tsp_platform_setup(void) /******************************************************************************* * Perform the very early platform specific architectural setup here. At the - * moment this is only intializes the MMU + * moment this is only initializes the MMU ******************************************************************************/ void tsp_plat_arch_setup(void) { diff --git a/services/std_svc/drtm/drtm_measurements.c b/services/std_svc/drtm/drtm_measurements.c index a8f2b3267..8d514b77f 100644 --- a/services/std_svc/drtm/drtm_measurements.c +++ b/services/std_svc/drtm/drtm_measurements.c @@ -47,7 +47,7 @@ static int drtm_event_log_measure_and_record(uintptr_t data_base, metadata.pcr = pcr; /* - * Measure the payloads requested by D-CRTM and DCE commponents + * Measure the payloads requested by D-CRTM and DCE components * Hash algorithm decided by the Event Log driver at build-time */ rc = event_log_measure(data_base, data_size, hash_data); diff --git a/services/std_svc/errata_abi/cpu_errata_info.h b/services/std_svc/errata_abi/cpu_errata_info.h new file mode 100644 index 000000000..671a6949d --- /dev/null +++ b/services/std_svc/errata_abi/cpu_errata_info.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef ERRATA_CPUSPEC_H +#define ERRATA_CPUSPEC_H + +#include <stdint.h> +#include <arch_helpers.h> + +#if __aarch64__ +#include <cortex_a35.h> +#include <cortex_a510.h> +#include <cortex_a53.h> +#include <cortex_a57.h> +#include <cortex_a55.h> +#include <cortex_a710.h> +#include <cortex_a72.h> +#include <cortex_a73.h> +#include <cortex_a75.h> +#include <cortex_a76.h> +#include <cortex_a77.h> +#include <cortex_a78.h> +#include <cortex_a78_ae.h> +#include <cortex_a78c.h> +#include <cortex_makalu.h> +#include <cortex_x1.h> +#include <cortex_x2.h> +#include <neoverse_n1.h> +#include <neoverse_n2.h> +#include <neoverse_v1.h> +#include <neoverse_v2.h> +#else +#include <cortex_a15.h> +#include <cortex_a17.h> +#include <cortex_a57.h> +#include <cortex_a9.h> +#endif + +#define MAX_ERRATA_ENTRIES 16 + +#define ERRATA_LIST_END (MAX_ERRATA_ENTRIES - 1) + +/* Default values for unused memory in the array */ +#define UNDEF_ERRATA {UINT_MAX, UCHAR_MAX, UCHAR_MAX, false, false} + +#define EXTRACT_PARTNUM(x) ((x >> MIDR_PN_SHIFT) & MIDR_PN_MASK) + +#define RXPX_RANGE(x, y, z) (((x >= y) && (x <= z)) ? true : false) + +/* + * CPU specific values for errata handling + */ +struct em_cpu{ + unsigned int em_errata_id; + unsigned char em_rxpx_lo; /* lowest revision of errata applicable for the cpu */ + unsigned char em_rxpx_hi; /* highest revision of errata applicable for the cpu */ + bool errata_enabled; /* indicate if errata enabled */ + /* flag to indicate if errata query is based out of non-arm interconnect */ + bool non_arm_interconnect; +}; + +struct em_cpu_list{ + /* field to hold cpu specific part number defined in midr reg */ + unsigned long cpu_partnumber; + struct em_cpu cpu_errata_list[MAX_ERRATA_ENTRIES]; +}; + +int32_t verify_errata_implemented(uint32_t errata_id, uint32_t forward_flag); +#endif /* ERRATA_CPUSPEC_H */ diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c new file mode 100644 index 000000000..bf9409d06 --- /dev/null +++ b/services/std_svc/errata_abi/errata_abi_main.c @@ -0,0 +1,570 @@ +/* + * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include "cpu_errata_info.h" +#include <lib/smccc.h> +#include <lib/utils_def.h> +#include <services/errata_abi_svc.h> +#include <smccc_helpers.h> + +/* + * Global pointer that points to the specific + * structure based on the MIDR part number + */ +struct em_cpu_list *cpu_ptr; + +extern uint8_t cpu_get_rev_var(void); + +/* Structure array that holds CPU specific errata information */ +struct em_cpu_list cpu_list[] = { +#if CORTEX_A9_H_INC +{ + .cpu_partnumber = CORTEX_A9_MIDR, + .cpu_errata_list = { + [0] = {794073, 0x00, 0xFF, ERRATA_A9_794073}, + [1 ... ERRATA_LIST_END] = UNDEF_ERRATA, + } +}, +#endif /* CORTEX_A9_H_INC */ + +#if CORTEX_A15_H_INC +{ + .cpu_partnumber = CORTEX_A15_MIDR, + .cpu_errata_list = { + [0] = {816470, 0x30, 0xFF, ERRATA_A15_816470}, + [1] = {827671, 0x30, 0xFF, ERRATA_A15_827671}, + [2 ... ERRATA_LIST_END] = UNDEF_ERRATA, + } +}, +#endif /* CORTEX_A15_H_INC */ + +#if CORTEX_A17_H_INC +{ + .cpu_partnumber = CORTEX_A17_MIDR, + .cpu_errata_list = { + [0] = {852421, 0x00, 0x12, ERRATA_A17_852421}, + [1] = {852423, 0x00, 0x12, ERRATA_A17_852423}, + [2 ... ERRATA_LIST_END] = UNDEF_ERRATA, + } +}, +#endif /* CORTEX_A17_H_INC */ + +#if CORTEX_A35_H_INC +{ + .cpu_partnumber = CORTEX_A35_MIDR, + .cpu_errata_list = { + [0] = {855472, 0x00, 0x00, ERRATA_A35_855472}, + [1 ... ERRATA_LIST_END] = UNDEF_ERRATA, + } +}, +#endif /* CORTEX_A35_H_INC */ + +#if CORTEX_A53_H_INC +{ + .cpu_partnumber = CORTEX_A53_MIDR, + .cpu_errata_list = { + [0] = {819472, 0x00, 0x01, ERRATA_A53_819472}, + [1] = {824069, 0x00, 0x02, ERRATA_A53_824069}, + [2] = {826319, 0x00, 0x02, ERRATA_A53_826319}, + [3] = {827319, 0x00, 0x02, ERRATA_A53_827319}, + [4] = {835769, 0x00, 0x04, ERRATA_A53_835769}, + [5] = {836870, 0x00, 0x03, ERRATA_A53_836870}, + [6] = {843419, 0x00, 0x04, ERRATA_A53_843419}, + [7] = {855873, 0x03, 0xFF, ERRATA_A53_855873}, + [8] = {1530924, 0x00, 0xFF, ERRATA_A53_1530924}, + [9 ... ERRATA_LIST_END] = UNDEF_ERRATA, + } +}, +#endif /* CORTEX_A53_H_INC */ + +#if CORTEX_A55_H_INC +{ + .cpu_partnumber = CORTEX_A55_MIDR, + .cpu_errata_list = { + [0] = {768277, 0x00, 0x00, ERRATA_A55_768277}, + [1] = {778703, 0x00, 0x00, ERRATA_A55_778703}, + [2] = {798797, 0x00, 0x00, ERRATA_A55_798797}, + [3] = {846532, 0x00, 0x01, ERRATA_A55_846532}, + [4] = {903758, 0x00, 0x01, ERRATA_A55_903758}, + [5] = {1221012, 0x00, 0x10, ERRATA_A55_1221012}, + [6] = {1530923, 0x00, 0xFF, ERRATA_A55_1530923}, + [7 ... ERRATA_LIST_END] = UNDEF_ERRATA, + } +}, +#endif /* CORTEX_A55_H_INC */ + +#if CORTEX_A57_H_INC +{ + .cpu_partnumber = CORTEX_A57_MIDR, + .cpu_errata_list = { + [0] = {806969, 0x00, 0x00, ERRATA_A57_806969}, + [1] = {813419, 0x00, 0x00, ERRATA_A57_813419}, + [2] = {813420, 0x00, 0x00, ERRATA_A57_813420}, + [3] = {814670, 0x00, 0x00, ERRATA_A57_814670}, + [4] = {817169, 0x00, 0x01, ERRATA_A57_817169}, + [5] = {826974, 0x00, 0x11, ERRATA_A57_826974}, + [6] = {826977, 0x00, 0x11, ERRATA_A57_826977}, + [7] = {828024, 0x00, 0x11, ERRATA_A57_828024}, + [8] = {829520, 0x00, 0x12, ERRATA_A57_829520}, + [9] = {833471, 0x00, 0x12, ERRATA_A57_833471}, + [10] = {859972, 0x00, 0x13, ERRATA_A57_859972}, + [11] = {1319537, 0x00, 0xFF, ERRATA_A57_1319537}, + [12 ... ERRATA_LIST_END] = UNDEF_ERRATA, + } +}, +#endif /* CORTEX_A57_H_INC */ + +#if CORTEX_A72_H_INC +{ + .cpu_partnumber = CORTEX_A72_MIDR, + .cpu_errata_list = { + [0] = {859971, 0x00, 0x03, ERRATA_A72_859971}, + [1] = {1319367, 0x00, 0xFF, ERRATA_A72_1319367}, + [2 ... ERRATA_LIST_END] = UNDEF_ERRATA, + } +}, +#endif /* CORTEX_A72_H_INC */ + +#if CORTEX_A73_H_INC +{ + .cpu_partnumber = CORTEX_A73_MIDR, + .cpu_errata_list = { + [0] = {852427, 0x00, 0x00, ERRATA_A73_852427}, + [1] = {855423, 0x00, 0x01, ERRATA_A73_855423}, + [2 ... ERRATA_LIST_END] = UNDEF_ERRATA, + } +}, +#endif /* CORTEX_A73_H_INC */ + +#if CORTEX_A75_H_INC +{ + .cpu_partnumber = CORTEX_A75_MIDR, + .cpu_errata_list = { + [0] = {764081, 0x00, 0x00, ERRATA_A75_764081}, + [1] = {790748, 0x00, 0x00, ERRATA_A75_790748}, + [2 ... ERRATA_LIST_END] = UNDEF_ERRATA, + } +}, +#endif /* CORTEX_A75_H_INC */ + +#if CORTEX_A76_H_INC +{ + .cpu_partnumber = CORTEX_A76_MIDR, + .cpu_errata_list = { + [0] = {1073348, 0x00, 0x10, ERRATA_A76_1073348}, + [1] = {1130799, 0x00, 0x20, ERRATA_A76_1130799}, + [2] = {1165522, 0x00, 0xFF, ERRATA_A76_1165522}, + [3] = {1220197, 0x00, 0x20, ERRATA_A76_1220197}, + [4] = {1257314, 0x00, 0x30, ERRATA_A76_1257314}, + [5] = {1262606, 0x00, 0x30, ERRATA_A76_1262606}, + [6] = {1262888, 0x00, 0x30, ERRATA_A76_1262888}, + [7] = {1275112, 0x00, 0x30, ERRATA_A76_1275112}, + [8] = {1791580, 0x00, 0x40, ERRATA_A76_1791580}, + [9] = {1868343, 0x00, 0x40, ERRATA_A76_1868343}, + [10] = {1946160, 0x30, 0x41, ERRATA_A76_1946160}, + [11 ... ERRATA_LIST_END] = UNDEF_ERRATA, + } +}, +#endif /* CORTEX_A76_H_INC */ + +#if CORTEX_A77_H_INC +{ + .cpu_partnumber = CORTEX_A77_MIDR, + .cpu_errata_list = { + [0] = {1508412, 0x00, 0x10, ERRATA_A77_1508412}, + [1] = {1791578, 0x00, 0x11, ERRATA_A77_1791578}, + [2] = {1800714, 0x00, 0x11, ERRATA_A77_1800714}, + [3] = {1925769, 0x00, 0x11, ERRATA_A77_1925769}, + [4] = {1946167, 0x00, 0x11, ERRATA_A77_1946167}, + [5] = {2356587, 0x00, 0x11, ERRATA_A77_2356587}, + [6] = {2743100, 0x00, 0x11, ERRATA_A77_2743100}, + [7 ... ERRATA_LIST_END] = UNDEF_ERRATA, + } +}, +#endif /* CORTEX_A77_H_INC */ + +#if CORTEX_A78_H_INC +{ + .cpu_partnumber = CORTEX_A78_MIDR, + .cpu_errata_list = { + [0] = {1688305, 0x00, 0x10, ERRATA_A78_1688305}, + [1] = {1821534, 0x00, 0x10, ERRATA_A78_1821534}, + [2] = {1941498, 0x00, 0x11, ERRATA_A78_1941498}, + [3] = {1951500, 0x10, 0x11, ERRATA_A78_1951500}, + [4] = {1952683, 0x00, 0x00, ERRATA_A78_1952683}, + [5] = {2132060, 0x00, 0x12, ERRATA_A78_2132060}, + [6] = {2242635, 0x10, 0x12, ERRATA_A78_2242635}, + [7] = {2376745, 0x00, 0x12, ERRATA_A78_2376745}, + [8] = {2395406, 0x00, 0x12, ERRATA_A78_2395406}, + [9] = {2712571, 0x00, 0x12, ERRATA_A78_2712571, \ + ERRATA_NON_ARM_INTERCONNECT}, + [10] = {2742426, 0x00, 0x12, ERRATA_A78_2742426}, + [11] = {2772019, 0x00, 0x12, ERRATA_A78_2772019}, + [12] = {2779479, 0x00, 0x12, ERRATA_A78_2779479}, + [13 ... ERRATA_LIST_END] = UNDEF_ERRATA, + } +}, +#endif /* CORTEX_A78_H_INC */ + +#if CORTEX_A78_AE_H_INC +{ + .cpu_partnumber = CORTEX_A78_AE_MIDR, + .cpu_errata_list = { + [0] = {1941500, 0x00, 0x01, ERRATA_A78_AE_1941500}, + [1] = {1951502, 0x00, 0x01, ERRATA_A78_AE_1951502}, + [2] = {2376748, 0x00, 0x01, ERRATA_A78_AE_2376748}, + [3] = {2395408, 0x00, 0x01, ERRATA_A78_AE_2395408}, + [4] = {2712574, 0x00, 0x02, ERRATA_A78_AE_2712574, \ + ERRATA_NON_ARM_INTERCONNECT}, + [5 ... ERRATA_LIST_END] = UNDEF_ERRATA, + } +}, +#endif /* CORTEX_A78_AE_H_INC */ + +#if CORTEX_A78C_H_INC +{ + .cpu_partnumber = CORTEX_A78C_MIDR, + .cpu_errata_list = { + [0] = {2132064, 0x01, 0x02, ERRATA_A78C_2132064}, + [1] = {2242638, 0x01, 0x02, ERRATA_A78C_2242638}, + [2] = {2376749, 0x01, 0x02, ERRATA_A78C_2376749}, + [3] = {2395411, 0x01, 0x02, ERRATA_A78C_2395411}, + [4] = {2712575, 0x01, 0x02, ERRATA_A78C_2712575, \ + ERRATA_NON_ARM_INTERCONNECT}, + [5] = {2772121, 0x00, 0x02, ERRATA_A78C_2772121}, + [6] = {2779484, 0x01, 0x02, ERRATA_A78C_2779484}, + [7 ... ERRATA_LIST_END] = UNDEF_ERRATA, + } +}, +#endif /* CORTEX_A78C_H_INC */ + +#if CORTEX_X1_H_INC +{ + .cpu_partnumber = CORTEX_X1_MIDR, + .cpu_errata_list = { + [0] = {1688305, 0x00, 0x10, ERRATA_X1_1688305}, + [1] = {1821534, 0x00, 0x10, ERRATA_X1_1821534}, + [2] = {1827429, 0x00, 0x10, ERRATA_X1_1827429}, + [3 ... ERRATA_LIST_END] = UNDEF_ERRATA, + } +}, +#endif /* CORTEX_X1_H_INC */ + +#if NEOVERSE_N1_H_INC +{ + .cpu_partnumber = NEOVERSE_N1_MIDR, + .cpu_errata_list = { + [0] = {1073348, 0x00, 0x10, ERRATA_N1_1073348}, + [1] = {1130799, 0x00, 0x20, ERRATA_N1_1130799}, + [2] = {1165347, 0x00, 0x20, ERRATA_N1_1165347}, + [3] = {1207823, 0x00, 0x20, ERRATA_N1_1207823}, + [4] = {1220197, 0x00, 0x20, ERRATA_N1_1220197}, + [5] = {1257314, 0x00, 0x30, ERRATA_N1_1257314}, + [6] = {1262606, 0x00, 0x30, ERRATA_N1_1262606}, + [7] = {1262888, 0x00, 0x30, ERRATA_N1_1262888}, + [8] = {1275112, 0x00, 0x30, ERRATA_N1_1275112}, + [9] = {1315703, 0x00, 0x30, ERRATA_N1_1315703}, + [10] = {1542419, 0x30, 0x40, ERRATA_N1_1542419}, + [11] = {1868343, 0x00, 0x40, ERRATA_N1_1868343}, + [12] = {1946160, 0x30, 0x41, ERRATA_N1_1946160}, + [13] = {2743102, 0x00, 0x41, ERRATA_N1_2743102}, + [14 ... ERRATA_LIST_END] = UNDEF_ERRATA, + } +}, +#endif /* NEOVERSE_N1_H_INC */ + +#if NEOVERSE_V1_H_INC +{ + .cpu_partnumber = NEOVERSE_V1_MIDR, + .cpu_errata_list = { + [0] = {1618635, 0x00, 0x0F, ERRATA_V1_1618635}, + [1] = {1774420, 0x00, 0x10, ERRATA_V1_1774420}, + [2] = {1791573, 0x00, 0x10, ERRATA_V1_1791573}, + [3] = {1852267, 0x00, 0x10, ERRATA_V1_1852267}, + [4] = {1925756, 0x00, 0x11, ERRATA_V1_1925756}, + [5] = {1940577, 0x10, 0x11, ERRATA_V1_1940577}, + [6] = {1966096, 0x10, 0x11, ERRATA_V1_1966096}, + [7] = {2108267, 0x00, 0x11, ERRATA_V1_2108267}, + [8] = {2139242, 0x00, 0x11, ERRATA_V1_2139242}, + [9] = {2216392, 0x10, 0x11, ERRATA_V1_2216392}, + [10] = {2294912, 0x00, 0x11, ERRATA_V1_2294912}, + [11] = {2372203, 0x00, 0x11, ERRATA_V1_2372203}, + [12] = {2701953, 0x00, 0x11, ERRATA_V1_2701953, \ + ERRATA_NON_ARM_INTERCONNECT}, + [13] = {2743093, 0x00, 0x12, ERRATA_V1_2743093}, + [14] = {2779461, 0x00, 0x12, ERRATA_V1_2779461}, + [15 ... ERRATA_LIST_END] = UNDEF_ERRATA, + } +}, +#endif /* NEOVERSE_V1_H_INC */ + +#if CORTEX_A710_H_INC +{ + .cpu_partnumber = CORTEX_A710_MIDR, + .cpu_errata_list = { + [0] = {1987031, 0x00, 0x20, ERRATA_A710_1987031}, + [1] = {2008768, 0x00, 0x20, ERRATA_A710_2008768}, + [2] = {2017096, 0x00, 0x20, ERRATA_A710_2017096}, + [3] = {2055002, 0x10, 0x20, ERRATA_A710_2055002}, + [4] = {2058056, 0x00, 0x10, ERRATA_A710_2058056}, + [5] = {2081180, 0x00, 0x20, ERRATA_A710_2081180}, + [6] = {2083908, 0x20, 0x20, ERRATA_A710_2083908}, + [7] = {2136059, 0x00, 0x20, ERRATA_A710_2136059}, + [8] = {2147715, 0x20, 0x20, ERRATA_A710_2147715}, + [9] = {2216384, 0x00, 0x20, ERRATA_A710_2216384}, + [10] = {2267065, 0x00, 0x20, ERRATA_A710_2267065}, + [11] = {2282622, 0x00, 0x21, ERRATA_A710_2282622}, + [12] = {2291219, 0x00, 0x20, ERRATA_A710_2291219}, + [13] = {2371105, 0x00, 0x20, ERRATA_A710_2371105}, + [14] = {2701952, 0x00, 0x21, ERRATA_A710_2701952, \ + ERRATA_NON_ARM_INTERCONNECT}, + [15] = {2768515, 0x00, 0x21, ERRATA_A710_2768515} + } +}, +#endif /* CORTEX_A710_H_INC */ + +#if NEOVERSE_N2_H_INC +{ + .cpu_partnumber = NEOVERSE_N2_MIDR, + .cpu_errata_list = { + [0] = {2002655, 0x00, 0x00, ERRATA_N2_2002655}, + [1] = {2025414, 0x00, 0x00, ERRATA_N2_2025414}, + [2] = {2067956, 0x00, 0x00, ERRATA_N2_2067956}, + [3] = {2138953, 0x00, 0x00, ERRATA_N2_2138953}, + [4] = {2138956, 0x00, 0x00, ERRATA_N2_2138956}, + [5] = {2138958, 0x00, 0x00, ERRATA_N2_2138958}, + [6] = {2189731, 0x00, 0x00, ERRATA_N2_2189731}, + [7] = {2242400, 0x00, 0x00, ERRATA_N2_2242400}, + [8] = {2242415, 0x00, 0x00, ERRATA_N2_2242415}, + [9] = {2280757, 0x00, 0x00, ERRATA_N2_2280757}, + [10] = {2326639, 0x00, 0x00, ERRATA_N2_2326639}, + [11] = {2376738, 0x00, 0x00, ERRATA_N2_2376738}, + [12] = {2388450, 0x00, 0x00, ERRATA_N2_2388450}, + [13] = {2728475, 0x00, 0x02, ERRATA_N2_2728475, \ + ERRATA_NON_ARM_INTERCONNECT}, + [14] = {2743089, 0x00, 0x02, ERRATA_N2_2743089}, + [15 ... ERRATA_LIST_END] = UNDEF_ERRATA, + } +}, +#endif /* NEOVERSE_N2_H_INC */ + +#if CORTEX_X2_H_INC +{ + .cpu_partnumber = CORTEX_X2_MIDR, + .cpu_errata_list = { + [0] = {2002765, 0x00, 0x20, ERRATA_X2_2002765}, + [1] = {2017096, 0x00, 0x20, ERRATA_X2_2017096}, + [2] = {2058056, 0x00, 0x20, ERRATA_X2_2058056}, + [3] = {2081180, 0x00, 0x20, ERRATA_X2_2081180}, + [4] = {2083908, 0x00, 0x20, ERRATA_X2_2083908}, + [5] = {2147715, 0x20, 0x20, ERRATA_X2_2147715}, + [6] = {2216384, 0x00, 0x20, ERRATA_X2_2216384}, + [7] = {2282622, 0x00, 0x21, ERRATA_X2_2282622}, + [8] = {2371105, 0x00, 0x21, ERRATA_X2_2371105}, + [9] = {2701952, 0x00, 0x21, ERRATA_X2_2701952, \ + ERRATA_NON_ARM_INTERCONNECT}, + [10] = {2768515, 0x00, 0x21, ERRATA_X2_2768515}, + [11 ... ERRATA_LIST_END] = UNDEF_ERRATA, + } +}, +#endif /* CORTEX_X2_H_INC */ + +#if CORTEX_A510_H_INC +{ + .cpu_partnumber = CORTEX_A510_MIDR, + .cpu_errata_list = { + [0] = {1922240, 0x00, 0x00, ERRATA_A510_1922240}, + [1] = {2041909, 0x02, 0x02, ERRATA_A510_2041909}, + [2] = {2042739, 0x00, 0x02, ERRATA_A510_2042739}, + [3] = {2172148, 0x00, 0x10, ERRATA_A510_2172148}, + [4] = {2218950, 0x00, 0x10, ERRATA_A510_2218950}, + [5] = {2250311, 0x00, 0x10, ERRATA_A510_2250311}, + [6] = {2288014, 0x00, 0x10, ERRATA_A510_2288014}, + [7] = {2347730, 0x00, 0x11, ERRATA_A510_2347730}, + [8] = {2371937, 0x00, 0x11, ERRATA_A510_2371937}, + [9] = {2666669, 0x00, 0x11, ERRATA_A510_2666669}, + [10] = {2684597, 0x00, 0x12, ERRATA_A510_2684597}, + [11 ... ERRATA_LIST_END] = UNDEF_ERRATA, + } +}, +#endif /* CORTEX_A510_H_INC */ + +#if NEOVERSE_V2_H_INC +{ + .cpu_partnumber = NEOVERSE_V2_MIDR, + .cpu_errata_list = { + [0] = {2719103, 0x00, 0x01, ERRATA_V2_2719103, \ + ERRATA_NON_ARM_INTERCONNECT}, + [1 ... ERRATA_LIST_END] = UNDEF_ERRATA, + } +}, +#endif /* NEOVERSE_V2_H_INC */ + +#if CORTEX_A715_H_INC +{ + .cpu_partnumber = CORTEX_MAKALU_MIDR, + .cpu_errata_list = { + [0] = {2701951, 0x00, 0x11, ERRATA_A715_2701951, \ + ERRATA_NON_ARM_INTERCONNECT}, + [1 ... ERRATA_LIST_END] = UNDEF_ERRATA, + } +}, +#endif /* CORTEX_A715_H_INC */ +}; + +/* + * Function to do binary search and check for the specific errata ID + * in the array of structures specific to the cpu identified. + */ +int32_t binary_search(struct em_cpu_list *ptr, uint32_t erratum_id, uint8_t rxpx_val) +{ + int low_index = 0U, mid_index = 0U; + + int high_index = MAX_ERRATA_ENTRIES - 1; + + assert(ptr != NULL); + + /* + * Pointer to the errata list of the cpu that matches + * extracted partnumber in the cpu list + */ + struct em_cpu *erratum_ptr = NULL; + + while (low_index <= high_index) { + mid_index = (low_index + high_index) / 2; + + erratum_ptr = &ptr->cpu_errata_list[mid_index]; + assert(erratum_ptr != NULL); + + if (erratum_id < erratum_ptr->em_errata_id) { + high_index = mid_index - 1; + } else if (erratum_id > erratum_ptr->em_errata_id) { + low_index = mid_index + 1; + } else if (erratum_id == erratum_ptr->em_errata_id) { + if (RXPX_RANGE(rxpx_val, erratum_ptr->em_rxpx_lo, \ + erratum_ptr->em_rxpx_hi)) { + if ((erratum_ptr->errata_enabled) && \ + (!(erratum_ptr->non_arm_interconnect))) { + return EM_HIGHER_EL_MITIGATION; + } + return EM_AFFECTED; + } + return EM_NOT_AFFECTED; + } + } + /* no matching errata ID */ + return EM_UNKNOWN_ERRATUM; +} + +/* Function to check if the errata exists for the specific CPU and rxpx */ +int32_t verify_errata_implemented(uint32_t errata_id, uint32_t forward_flag) +{ + /* + * Read MIDR value and extract the revision, variant and partnumber + */ + static uint32_t midr_val, cpu_partnum; + static uint8_t cpu_rxpx_val; + int32_t ret_val = EM_UNKNOWN_ERRATUM; + + /* Determine the number of cpu listed in the cpu list */ + uint8_t size_cpulist = ARRAY_SIZE(cpu_list); + + /* Read the midr reg to extract cpu, revision and variant info */ + midr_val = read_midr(); + + /* Extract revision and variant from the MIDR register */ + cpu_rxpx_val = cpu_get_rev_var(); + + /* Extract the cpu partnumber and check if the cpu is in the cpu list */ + cpu_partnum = EXTRACT_PARTNUM(midr_val); + + for (uint8_t i = 0; i < size_cpulist; i++) { + cpu_ptr = &cpu_list[i]; + uint16_t partnum_extracted = EXTRACT_PARTNUM(cpu_ptr->cpu_partnumber); + + if (partnum_extracted == cpu_partnum) { + /* + * If the midr value is in the cpu list, binary search + * for the errata ID and specific revision in the list. + */ + ret_val = binary_search(cpu_ptr, errata_id, cpu_rxpx_val); + break; + } + } + return ret_val; +} + +/* Predicate indicating that a function id is part of EM_ABI */ +bool is_errata_fid(uint32_t smc_fid) +{ + return ((smc_fid == ARM_EM_VERSION) || + (smc_fid == ARM_EM_FEATURES) || + (smc_fid == ARM_EM_CPU_ERRATUM_FEATURES)); + +} + +bool validate_spsr_mode(void) +{ + /* In AArch64, if the caller is EL1, return true */ + + #if __aarch64__ + if (GET_EL(read_spsr_el3()) == MODE_EL1) { + return true; + } + return false; + #else + + /* In AArch32, if in system/svc mode, return true */ + uint8_t read_el_state = GET_M32(read_spsr()); + + if ((read_el_state == (MODE32_svc)) || (read_el_state == MODE32_sys)) { + return true; + } + return false; + #endif /* __aarch64__ */ +} + +uintptr_t errata_abi_smc_handler(uint32_t smc_fid, u_register_t x1, + u_register_t x2, u_register_t x3, u_register_t x4, + void *cookie, void *handle, u_register_t flags) +{ + int32_t ret_id = EM_UNKNOWN_ERRATUM; + + switch (smc_fid) { + case ARM_EM_VERSION: + SMC_RET1(handle, MAKE_SMCCC_VERSION( + EM_VERSION_MAJOR, EM_VERSION_MINOR + )); + break; /* unreachable */ + case ARM_EM_FEATURES: + if (is_errata_fid((uint32_t)x1)) { + SMC_RET1(handle, EM_SUCCESS); + } + + SMC_RET1(handle, EM_NOT_SUPPORTED); + break; /* unreachable */ + case ARM_EM_CPU_ERRATUM_FEATURES: + + /* + * If the forward flag is greater than zero and the calling EL + * is EL1 in AArch64 or in system mode or svc mode in case of AArch32, + * return Invalid Parameters. + */ + if (((uint32_t)x2 != 0) && (validate_spsr_mode())) { + SMC_RET1(handle, EM_INVALID_PARAMETERS); + } + ret_id = verify_errata_implemented((uint32_t)x1, (uint32_t)x2); + SMC_RET1(handle, ret_id); + break; /* unreachable */ + default: + { + WARN("Unimplemented Errata ABI Service Call: 0x%x\n", smc_fid); + SMC_RET1(handle, EM_UNKNOWN_ERRATUM); + break; /* unreachable */ + } + } +} diff --git a/services/std_svc/spm/el3_spmc/spmc_setup.c b/services/std_svc/spm/el3_spmc/spmc_setup.c index 8ebae2852..6de25f64b 100644 --- a/services/std_svc/spm/el3_spmc/spmc_setup.c +++ b/services/std_svc/spm/el3_spmc/spmc_setup.c @@ -90,7 +90,7 @@ static void spmc_create_boot_info(entry_point_info_t *ep_info, boot_header->offset_boot_info_desc); /* - * We must use the FF-A version coresponding to the version implemented + * We must use the FF-A version corresponding to the version implemented * by the SP. Currently this can only be v1.1. */ boot_header->version = sp->ffa_version; diff --git a/services/std_svc/spm/spm_mm/spm_mm_main.c b/services/std_svc/spm/spm_mm/spm_mm_main.c index 8525cd27c..1ff7bb77c 100644 --- a/services/std_svc/spm/spm_mm/spm_mm_main.c +++ b/services/std_svc/spm/spm_mm/spm_mm_main.c @@ -254,7 +254,7 @@ static uint64_t mm_communicate(uint32_t smc_fid, uint64_t mm_cookie, /* * The current secure partition design mandates * - at any point, only a single core can be - * executing in the secure partiton. + * executing in the secure partition. * - a core cannot be preempted by an interrupt * while executing in secure partition. * Raise the running priority of the core to the diff --git a/services/std_svc/std_svc_setup.c b/services/std_svc/std_svc_setup.c index 2884a3b9e..e782d09d2 100644 --- a/services/std_svc/std_svc_setup.c +++ b/services/std_svc/std_svc_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,6 +14,7 @@ #include <lib/psci/psci.h> #include <lib/runtime_instr.h> #include <services/drtm_svc.h> +#include <services/errata_abi_svc.h> #include <services/pci_svc.h> #include <services/rmmd_svc.h> #include <services/sdei.h> @@ -177,6 +178,13 @@ static uintptr_t std_svc_smc_handler(uint32_t smc_fid, } #endif /* TRNG_SUPPORT */ +#if ERRATA_ABI_SUPPORT + if (is_errata_fid(smc_fid)) { + return errata_abi_smc_handler(smc_fid, x1, x2, x3, x4, cookie, + handle, flags); + } +#endif /* ERRATA_ABI_SUPPORT */ + #if ENABLE_RME if (is_rmmd_el3_fid(smc_fid)) { diff --git a/tools/fiptool/win_posix.h b/tools/fiptool/win_posix.h index 6f0d8e6b6..13406408d 100644 --- a/tools/fiptool/win_posix.h +++ b/tools/fiptool/win_posix.h @@ -149,7 +149,7 @@ inline char *strdup(const char *s) * Windows does not have the getopt family of functions, as it normally * uses '/' instead of '-' as the command line option delimiter. * These functions provide a Windows version that uses '-', which precludes - * using '-' as the intial letter of a program argument. + * using '-' as the initial letter of a program argument. * This is not seen as a problem in the specific instance of fiptool, * and enables existing makefiles to work on a Windows build environment. */ diff --git a/tools/nxp/create_pbl/create_pbl.c b/tools/nxp/create_pbl/create_pbl.c index 792747f0e..c277e391a 100644 --- a/tools/nxp/create_pbl/create_pbl.c +++ b/tools/nxp/create_pbl/create_pbl.c @@ -912,7 +912,7 @@ int main(int argc, char **argv) while (word != 0x808f0000 && word != 0x80ff0000) { pbl_size++; /* 11th words in RCW has PBL length. Update it - * with new length. 2 comamnds get added + * with new length. 2 commands get added * Block copy + CCSR Write/CSF header write */ if (pbl_size == 11) { |